Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5639383	1			T1	3		T2	1		T3	6
all_levels[1]	1435414	1			T3	14		T4	2		T6	16958
all_levels[2]	268790	1			T3	1		T6	669		T8	72
all_levels[3]	241670	1			T6	35532		T8	83		T9	956
all_levels[4]	219708	1			T3	7		T6	272		T8	71
all_levels[5]	181032	1			T6	394		T8	66		T9	2
all_levels[6]	204733	1			T1	3		T6	386		T8	74
all_levels[7]	213290	1			T6	347		T8	84		T11	36
all_levels[8]	235174	1			T1	3		T3	2		T6	231
all_levels[9]	269217	1			T3	5		T6	214		T7	1
all_levels[10]	350235	1			T4	2		T6	352		T8	80
all_levels[11]	284386	1			T1	2		T6	362		T7	1
all_levels[12]	210007	1			T1	2		T6	224		T8	79
all_levels[13]	195970	1			T6	225		T8	80		T9	1
all_levels[14]	261204	1			T4	38		T6	233		T7	1
all_levels[15]	450902	1			T3	3		T6	233		T8	80
all_levels[16]	423313	1			T6	256		T8	86		T13	87
all_levels[17]	216466	1			T6	368		T8	76		T11	3
all_levels[18]	161287	1			T6	376		T8	85		T9	2
all_levels[19]	160835	1			T1	4		T6	325		T7	1
all_levels[20]	161119	1			T6	253		T7	1		T8	86
all_levels[21]	158168	1			T6	205		T7	2		T8	83
all_levels[22]	178161	1			T6	82		T8	74		T9	3
all_levels[23]	188806	1			T6	82		T7	3		T8	83
all_levels[24]	160647	1			T6	88		T8	85		T9	1
all_levels[25]	199961	1			T6	84		T8	90		T11	1
all_levels[26]	337806	1			T6	72		T8	85		T9	1
all_levels[27]	210182	1			T4	163		T6	48		T8	80
all_levels[28]	264352	1			T6	53		T8	82		T11	3
all_levels[29]	156832	1			T6	51		T8	72		T13	129
all_levels[30]	204685	1			T6	46		T8	69		T13	130
all_levels[31]	466672	1			T1	3		T6	52		T8	2242
all_levels[32]	11034389	1			T4	36		T6	4965		T7	33

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25340373

1

T1

17

T3

37

T4

256

auto[1]

4423

1

T1

3

T2

1

T3

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5636915	1			T1	3		T3	6		T4	16
all_levels[0]	auto[1]	2468	1			T2	1		T7	4		T9	3
all_levels[1]	auto[0]	1435072	1			T3	14		T4	2		T6	16958
all_levels[1]	auto[1]	342	1			T13	7		T16	6		T124	1
all_levels[2]	auto[0]	268757	1			T3	1		T6	669		T8	72
all_levels[2]	auto[1]	33	1			T143	1		T180	1		T302	1
all_levels[3]	auto[0]	241551	1			T6	35532		T8	83		T9	956
all_levels[3]	auto[1]	119	1			T27	2		T130	2		T236	1
all_levels[4]	auto[0]	219678	1			T3	7		T6	272		T8	71
all_levels[4]	auto[1]	30	1			T33	1		T188	1		T319	1
all_levels[5]	auto[0]	181005	1			T6	394		T8	66		T9	2
all_levels[5]	auto[1]	27	1			T35	3		T285	1		T263	2
all_levels[6]	auto[0]	204678	1			T1	3		T6	386		T8	74
all_levels[6]	auto[1]	55	1			T13	7		T263	4		T215	1
all_levels[7]	auto[0]	213179	1			T6	347		T8	84		T11	36
all_levels[7]	auto[1]	111	1			T24	3		T131	1		T26	1
all_levels[8]	auto[0]	235151	1			T1	3		T3	2		T6	231
all_levels[8]	auto[1]	23	1			T156	1		T186	2		T320	1
all_levels[9]	auto[0]	269194	1			T3	4		T6	214		T7	1
all_levels[9]	auto[1]	23	1			T3	1		T258	4		T34	1
all_levels[10]	auto[0]	350220	1			T4	2		T6	352		T8	80
all_levels[10]	auto[1]	15	1			T185	1		T181	1		T48	1
all_levels[11]	auto[0]	284362	1			T1	2		T6	362		T7	1
all_levels[11]	auto[1]	24	1			T32	1		T143	2		T129	2
all_levels[12]	auto[0]	209974	1			T1	2		T6	224		T8	79
all_levels[12]	auto[1]	33	1			T25	1		T218	1		T62	1
all_levels[13]	auto[0]	195952	1			T6	225		T8	80		T9	1
all_levels[13]	auto[1]	18	1			T26	1		T172	1		T102	1
all_levels[14]	auto[0]	261173	1			T4	38		T6	233		T7	1
all_levels[14]	auto[1]	31	1			T124	1		T145	1		T42	1
all_levels[15]	auto[0]	450704	1			T3	3		T6	233		T8	80
all_levels[15]	auto[1]	198	1			T16	11		T35	1		T194	1
all_levels[16]	auto[0]	423284	1			T6	256		T8	86		T13	87
all_levels[16]	auto[1]	29	1			T26	1		T180	2		T177	2
all_levels[17]	auto[0]	216442	1			T6	368		T8	76		T11	3
all_levels[17]	auto[1]	24	1			T215	2		T134	1		T175	3
all_levels[18]	auto[0]	161255	1			T6	376		T8	85		T9	2
all_levels[18]	auto[1]	32	1			T139	1		T186	4		T321	1
all_levels[19]	auto[0]	160813	1			T1	2		T6	325		T7	1
all_levels[19]	auto[1]	22	1			T1	2		T11	1		T133	1
all_levels[20]	auto[0]	161094	1			T6	253		T7	1		T8	86
all_levels[20]	auto[1]	25	1			T258	1		T131	2		T201	1
all_levels[21]	auto[0]	158155	1			T6	205		T7	2		T8	83
all_levels[21]	auto[1]	13	1			T322	1		T323	2		T324	1
all_levels[22]	auto[0]	178147	1			T6	82		T8	74		T9	3
all_levels[22]	auto[1]	14	1			T150	1		T223	2		T325	1
all_levels[23]	auto[0]	188790	1			T6	82		T7	2		T8	83
all_levels[23]	auto[1]	16	1			T7	1		T134	2		T129	1
all_levels[24]	auto[0]	160628	1			T6	88		T8	85		T9	1
all_levels[24]	auto[1]	19	1			T13	2		T276	1		T176	3
all_levels[25]	auto[0]	199946	1			T6	84		T8	90		T11	1
all_levels[25]	auto[1]	15	1			T218	1		T142	3		T324	1
all_levels[26]	auto[0]	337787	1			T6	72		T8	85		T9	1
all_levels[26]	auto[1]	19	1			T275	1		T193	3		T326	1
all_levels[27]	auto[0]	210166	1			T4	163		T6	48		T8	80
all_levels[27]	auto[1]	16	1			T62	1		T301	1		T327	1
all_levels[28]	auto[0]	264333	1			T6	53		T8	82		T11	3
all_levels[28]	auto[1]	19	1			T126	1		T134	1		T148	1
all_levels[29]	auto[0]	156814	1			T6	51		T8	72		T13	129
all_levels[29]	auto[1]	18	1			T302	1		T137	1		T232	1
all_levels[30]	auto[0]	204671	1			T6	46		T8	69		T13	130
all_levels[30]	auto[1]	14	1			T36	1		T134	2		T54	1
all_levels[31]	auto[0]	466656	1			T1	2		T6	52		T8	2242
all_levels[31]	auto[1]	16	1			T1	1		T281	1		T137	1
all_levels[32]	auto[0]	11033827	1			T4	35		T6	4965		T7	32
all_levels[32]	auto[1]	562	1			T4	1		T7	1		T8	1