Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	835	1			T9	7		T13	29		T14	4
all_values[1]	835	1			T9	7		T13	29		T14	4
all_values[2]	835	1			T9	7		T13	29		T14	4
all_values[3]	835	1			T9	7		T13	29		T14	4
all_values[4]	835	1			T9	7		T13	29		T14	4
all_values[5]	835	1			T9	7		T13	29		T14	4
all_values[6]	835	1			T9	7		T13	29		T14	4
all_values[7]	835	1			T9	7		T13	29		T14	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3453

1

T9

28

T13

136

T14

8

auto[1]

3227

1

T9

28

T13

96

T14

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2324

1

T9

18

T13

93

T14

12

auto[1]

4356

1

T9

38

T13

139

T14

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3872

1

T9

33

T13

140

T14

20

auto[1]

2808

1

T9

23

T13

92

T14

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	234	1			T9	1		T13	10		T84	2
all_values[0]	auto[0]	auto[1]	auto[1]	255	1			T9	4		T13	7		T14	3
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T13	6		T84	2		T27	1
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T9	2		T13	6		T14	1
all_values[1]	auto[0]	auto[0]	auto[0]	248	1			T9	1		T13	9		T84	1
all_values[1]	auto[0]	auto[1]	auto[0]	235	1			T9	4		T13	6		T14	4
all_values[1]	auto[1]	auto[0]	auto[1]	177	1			T9	2		T13	7		T84	1
all_values[1]	auto[1]	auto[1]	auto[1]	175	1			T13	7		T84	2		T26	3
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T9	2		T13	5		T84	2
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T9	1		T13	4		T14	1
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T9	1		T13	3		T14	1
all_values[2]	auto[0]	auto[1]	auto[1]	97	1			T13	2		T27	1		T121	3
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T9	1		T13	10		T14	1
all_values[2]	auto[1]	auto[1]	auto[1]	172	1			T9	2		T13	5		T14	1
all_values[3]	auto[0]	auto[0]	auto[0]	162	1			T13	5		T84	1		T26	1
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T14	1		T27	1		T121	3
all_values[3]	auto[0]	auto[1]	auto[0]	162	1			T13	7		T14	2		T84	1
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T9	1		T13	4		T84	2
all_values[3]	auto[1]	auto[0]	auto[1]	165	1			T9	4		T13	4		T14	1
all_values[3]	auto[1]	auto[1]	auto[1]	177	1			T9	2		T13	9		T84	1
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T9	1		T13	8		T84	1
all_values[4]	auto[0]	auto[0]	auto[1]	94	1			T9	1		T13	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T13	6		T14	1		T84	3
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T9	2		T13	5		T26	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T9	2		T13	5		T14	1
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T9	1		T13	4		T14	1
all_values[5]	auto[0]	auto[0]	auto[0]	170	1			T13	10		T84	1		T42	1
all_values[5]	auto[0]	auto[0]	auto[1]	84	1			T9	2		T13	1		T26	2
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T9	4		T13	6		T14	1
all_values[5]	auto[0]	auto[1]	auto[1]	96	1			T13	2		T14	1		T121	1
all_values[5]	auto[1]	auto[0]	auto[1]	187	1			T9	1		T13	8		T84	1
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T13	2		T14	2		T84	3
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T9	3		T13	10		T84	2
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T9	1		T13	2		T14	1
all_values[6]	auto[0]	auto[1]	auto[0]	119	1			T13	3		T42	2		T121	5
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T9	1		T13	4		T84	1
all_values[6]	auto[1]	auto[0]	auto[1]	183	1			T13	7		T14	1		T84	1
all_values[6]	auto[1]	auto[1]	auto[1]	173	1			T9	2		T13	3		T14	2
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T9	1		T13	13		T42	1
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T9	1		T13	2		T121	3
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T9	1		T13	2		T14	3
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T13	3		T84	2		T26	1
all_values[7]	auto[1]	auto[0]	auto[1]	181	1			T9	3		T13	9		T26	3
all_values[7]	auto[1]	auto[1]	auto[1]	164	1			T9	1		T14	1		T84	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal