Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1320
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T1259 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.537654918 May 05 02:43:49 PM PDT 24 May 05 02:43:50 PM PDT 24 32663174 ps
T1260 /workspace/coverage/cover_reg_top/13.uart_intr_test.2402901807 May 05 02:44:16 PM PDT 24 May 05 02:44:17 PM PDT 24 14421597 ps
T1261 /workspace/coverage/cover_reg_top/49.uart_intr_test.477552706 May 05 02:44:36 PM PDT 24 May 05 02:44:38 PM PDT 24 17878832 ps
T1262 /workspace/coverage/cover_reg_top/8.uart_tl_errors.623186266 May 05 02:44:17 PM PDT 24 May 05 02:44:20 PM PDT 24 146110580 ps
T1263 /workspace/coverage/cover_reg_top/2.uart_csr_rw.213128594 May 05 02:43:56 PM PDT 24 May 05 02:43:57 PM PDT 24 12639760 ps
T1264 /workspace/coverage/cover_reg_top/6.uart_intr_test.961673464 May 05 02:44:07 PM PDT 24 May 05 02:44:08 PM PDT 24 14308004 ps
T1265 /workspace/coverage/cover_reg_top/10.uart_intr_test.3322148555 May 05 02:44:18 PM PDT 24 May 05 02:44:19 PM PDT 24 32436294 ps
T89 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1490620330 May 05 02:44:04 PM PDT 24 May 05 02:44:06 PM PDT 24 98709083 ps
T1266 /workspace/coverage/cover_reg_top/40.uart_intr_test.2727057045 May 05 02:44:32 PM PDT 24 May 05 02:44:33 PM PDT 24 46053872 ps
T1267 /workspace/coverage/cover_reg_top/6.uart_csr_rw.4201504236 May 05 02:44:15 PM PDT 24 May 05 02:44:17 PM PDT 24 140062467 ps
T1268 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4208632791 May 05 02:43:58 PM PDT 24 May 05 02:44:01 PM PDT 24 1465210343 ps
T1269 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.368778042 May 05 02:43:57 PM PDT 24 May 05 02:43:58 PM PDT 24 14278163 ps
T1270 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1487407419 May 05 02:44:23 PM PDT 24 May 05 02:44:24 PM PDT 24 146317008 ps
T1271 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2949851534 May 05 02:43:56 PM PDT 24 May 05 02:43:58 PM PDT 24 154330094 ps
T1272 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2849422376 May 05 02:43:58 PM PDT 24 May 05 02:44:00 PM PDT 24 62909459 ps
T119 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2926123525 May 05 02:44:15 PM PDT 24 May 05 02:44:17 PM PDT 24 95267615 ps
T1273 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3958849897 May 05 02:43:49 PM PDT 24 May 05 02:43:50 PM PDT 24 45851900 ps
T1274 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1479665587 May 05 02:44:18 PM PDT 24 May 05 02:44:20 PM PDT 24 54749996 ps
T92 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3272715088 May 05 02:44:18 PM PDT 24 May 05 02:44:20 PM PDT 24 258038737 ps
T1275 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2194818160 May 05 02:44:23 PM PDT 24 May 05 02:44:24 PM PDT 24 48319404 ps
T1276 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1841822194 May 05 02:44:10 PM PDT 24 May 05 02:44:11 PM PDT 24 22866755 ps
T1277 /workspace/coverage/cover_reg_top/11.uart_intr_test.3350314248 May 05 02:44:20 PM PDT 24 May 05 02:44:21 PM PDT 24 12282297 ps
T117 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.690555113 May 05 02:43:58 PM PDT 24 May 05 02:44:00 PM PDT 24 107020722 ps
T1278 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3093373768 May 05 02:44:19 PM PDT 24 May 05 02:44:21 PM PDT 24 19920197 ps
T1279 /workspace/coverage/cover_reg_top/18.uart_tl_errors.894005728 May 05 02:44:26 PM PDT 24 May 05 02:44:28 PM PDT 24 90225272 ps
T1280 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1638082735 May 05 02:44:10 PM PDT 24 May 05 02:44:12 PM PDT 24 267455162 ps
T1281 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2772832112 May 05 02:44:18 PM PDT 24 May 05 02:44:20 PM PDT 24 60824595 ps
T1282 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3067653342 May 05 02:44:19 PM PDT 24 May 05 02:44:22 PM PDT 24 113904990 ps
T1283 /workspace/coverage/cover_reg_top/48.uart_intr_test.1910080821 May 05 02:44:37 PM PDT 24 May 05 02:44:38 PM PDT 24 25468125 ps
T1284 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3253514402 May 05 02:44:03 PM PDT 24 May 05 02:44:04 PM PDT 24 35261878 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_tl_errors.397267622 May 05 02:43:53 PM PDT 24 May 05 02:43:55 PM PDT 24 622380663 ps
T1286 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1180489123 May 05 02:44:19 PM PDT 24 May 05 02:44:22 PM PDT 24 351433386 ps
T1287 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.788862463 May 05 02:44:22 PM PDT 24 May 05 02:44:23 PM PDT 24 44873942 ps
T1288 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.601338973 May 05 02:44:27 PM PDT 24 May 05 02:44:28 PM PDT 24 33055132 ps
T1289 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1517060897 May 05 02:44:15 PM PDT 24 May 05 02:44:16 PM PDT 24 60765260 ps
T1290 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2268562245 May 05 02:44:23 PM PDT 24 May 05 02:44:24 PM PDT 24 177642751 ps
T1291 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4071222670 May 05 02:44:05 PM PDT 24 May 05 02:44:06 PM PDT 24 20991371 ps
T120 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3990316897 May 05 02:44:24 PM PDT 24 May 05 02:44:26 PM PDT 24 173342371 ps
T70 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3944394675 May 05 02:44:02 PM PDT 24 May 05 02:44:04 PM PDT 24 118009650 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_intr_test.4060316753 May 05 02:44:17 PM PDT 24 May 05 02:44:18 PM PDT 24 23512277 ps
T1293 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2225026425 May 05 02:44:28 PM PDT 24 May 05 02:44:30 PM PDT 24 48288920 ps
T1294 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3188376459 May 05 02:44:16 PM PDT 24 May 05 02:44:18 PM PDT 24 17217155 ps
T1295 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1207312770 May 05 02:43:50 PM PDT 24 May 05 02:43:51 PM PDT 24 103746104 ps
T1296 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3851752186 May 05 02:44:16 PM PDT 24 May 05 02:44:17 PM PDT 24 14566592 ps
T1297 /workspace/coverage/cover_reg_top/15.uart_intr_test.268276584 May 05 02:44:22 PM PDT 24 May 05 02:44:23 PM PDT 24 55648289 ps
T1298 /workspace/coverage/cover_reg_top/4.uart_tl_errors.130926721 May 05 02:44:15 PM PDT 24 May 05 02:44:17 PM PDT 24 144797282 ps
T1299 /workspace/coverage/cover_reg_top/29.uart_intr_test.888953177 May 05 02:44:31 PM PDT 24 May 05 02:44:32 PM PDT 24 24378417 ps
T118 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.112769762 May 05 02:44:28 PM PDT 24 May 05 02:44:29 PM PDT 24 149388649 ps
T1300 /workspace/coverage/cover_reg_top/44.uart_intr_test.738417877 May 05 02:44:34 PM PDT 24 May 05 02:44:35 PM PDT 24 13689923 ps
T1301 /workspace/coverage/cover_reg_top/43.uart_intr_test.3871408197 May 05 02:44:36 PM PDT 24 May 05 02:44:37 PM PDT 24 56924104 ps
T71 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2555084477 May 05 02:44:00 PM PDT 24 May 05 02:44:02 PM PDT 24 135313605 ps
T1302 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.344655965 May 05 02:44:24 PM PDT 24 May 05 02:44:25 PM PDT 24 106716569 ps
T1303 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.80124439 May 05 02:44:18 PM PDT 24 May 05 02:44:19 PM PDT 24 256123997 ps
T1304 /workspace/coverage/cover_reg_top/16.uart_intr_test.2484393716 May 05 02:44:23 PM PDT 24 May 05 02:44:24 PM PDT 24 13748821 ps
T1305 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2020459626 May 05 02:43:56 PM PDT 24 May 05 02:43:57 PM PDT 24 45585043 ps
T1306 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2433611207 May 05 02:44:18 PM PDT 24 May 05 02:44:19 PM PDT 24 35127105 ps
T1307 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1844615795 May 05 02:44:17 PM PDT 24 May 05 02:44:19 PM PDT 24 36970699 ps
T1308 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3422545246 May 05 02:44:22 PM PDT 24 May 05 02:44:25 PM PDT 24 137669679 ps
T1309 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3640187586 May 05 02:44:18 PM PDT 24 May 05 02:44:20 PM PDT 24 18026413 ps
T1310 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1994098359 May 05 02:43:57 PM PDT 24 May 05 02:43:58 PM PDT 24 52083455 ps
T1311 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2177300155 May 05 02:44:21 PM PDT 24 May 05 02:44:23 PM PDT 24 195170479 ps
T1312 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2089782015 May 05 02:44:17 PM PDT 24 May 05 02:44:18 PM PDT 24 51047778 ps
T1313 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2487537178 May 05 02:44:25 PM PDT 24 May 05 02:44:26 PM PDT 24 16780536 ps
T1314 /workspace/coverage/cover_reg_top/3.uart_intr_test.1775777204 May 05 02:43:57 PM PDT 24 May 05 02:43:58 PM PDT 24 35863229 ps
T1315 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3113239297 May 05 02:43:55 PM PDT 24 May 05 02:43:56 PM PDT 24 93842610 ps
T1316 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1519440051 May 05 02:44:23 PM PDT 24 May 05 02:44:24 PM PDT 24 120172836 ps
T1317 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2940366651 May 05 02:43:49 PM PDT 24 May 05 02:43:51 PM PDT 24 91131111 ps
T1318 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3242603671 May 05 02:44:17 PM PDT 24 May 05 02:44:19 PM PDT 24 442580203 ps
T1319 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1786239458 May 05 02:44:06 PM PDT 24 May 05 02:44:07 PM PDT 24 62246434 ps
T1320 /workspace/coverage/cover_reg_top/25.uart_intr_test.3925522534 May 05 02:44:31 PM PDT 24 May 05 02:44:32 PM PDT 24 27880525 ps

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1269947840
Short name T9
Test name
Test status
Simulation time 115870391036 ps
CPU time 320.97 seconds
Started May 05 01:34:33 PM PDT 24
Finished May 05 01:39:55 PM PDT 24
Peak memory 225192 kb
Host smart-dcdf1530-5f64-4177-ab57-f5822d85ecae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269947840 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1269947840
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2593290419
Short name T25
Test name
Test status
Simulation time 677175120800 ps
CPU time 728.07 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:48:41 PM PDT 24
Peak memory 225248 kb
Host smart-f33f41a2-486c-420c-b856-7645da400e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593290419 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2593290419
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.611138200
Short name T8
Test name
Test status
Simulation time 175683031186 ps
CPU time 582.97 seconds
Started May 05 01:34:54 PM PDT 24
Finished May 05 01:44:38 PM PDT 24
Peak memory 200308 kb
Host smart-5f9ad38e-4bf6-428b-8446-85bc02deed43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611138200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.611138200
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2083850766
Short name T45
Test name
Test status
Simulation time 524065718269 ps
CPU time 1536.97 seconds
Started May 05 01:35:05 PM PDT 24
Finished May 05 02:00:43 PM PDT 24
Peak memory 227948 kb
Host smart-f162cf4b-ae45-4e71-9235-44c8d2a6f90f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083850766 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2083850766
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.3938564504
Short name T115
Test name
Test status
Simulation time 200587769147 ps
CPU time 574.19 seconds
Started May 05 01:36:06 PM PDT 24
Finished May 05 01:45:40 PM PDT 24
Peak memory 200300 kb
Host smart-7b3ac3c8-0d0b-43c9-b588-ae8c00756fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938564504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3938564504
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.592533467
Short name T277
Test name
Test status
Simulation time 379089980238 ps
CPU time 1266.24 seconds
Started May 05 01:36:51 PM PDT 24
Finished May 05 01:57:58 PM PDT 24
Peak memory 227880 kb
Host smart-f80639ff-ee87-4991-8f8d-02d478c16d66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592533467 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.592533467
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1092758151
Short name T6
Test name
Test status
Simulation time 29773717610 ps
CPU time 241.07 seconds
Started May 05 01:36:48 PM PDT 24
Finished May 05 01:40:50 PM PDT 24
Peak memory 202624 kb
Host smart-f81124df-e4c9-47d5-a2f3-fea1fa4b28d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092758151 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1092758151
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2827910302
Short name T36
Test name
Test status
Simulation time 200455018280 ps
CPU time 357.57 seconds
Started May 05 01:36:56 PM PDT 24
Finished May 05 01:42:54 PM PDT 24
Peak memory 200332 kb
Host smart-066cab31-d607-443b-a1d8-c37e4ecb6dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827910302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2827910302
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1367329438
Short name T21
Test name
Test status
Simulation time 57220850 ps
CPU time 0.83 seconds
Started May 05 01:29:57 PM PDT 24
Finished May 05 01:29:58 PM PDT 24
Peak memory 218732 kb
Host smart-ea3f5efe-27b3-4332-9295-de9db1f4042a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367329438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1367329438
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2613576740
Short name T13
Test name
Test status
Simulation time 82393797081 ps
CPU time 451.04 seconds
Started May 05 01:33:23 PM PDT 24
Finished May 05 01:40:54 PM PDT 24
Peak memory 226680 kb
Host smart-5e1f9c59-b86d-40da-bb7d-dec55ed2eb15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613576740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2613576740
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3721218436
Short name T57
Test name
Test status
Simulation time 84570229397 ps
CPU time 1034.18 seconds
Started May 05 01:34:01 PM PDT 24
Finished May 05 01:51:16 PM PDT 24
Peak memory 216860 kb
Host smart-3046093d-c0db-455e-a922-dfa91320630f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721218436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3721218436
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.1660968881
Short name T137
Test name
Test status
Simulation time 505904333625 ps
CPU time 225.82 seconds
Started May 05 01:34:34 PM PDT 24
Finished May 05 01:38:21 PM PDT 24
Peak memory 200560 kb
Host smart-7d9fb29d-09a9-4271-ae7a-e3be0e439abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660968881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1660968881
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3579411964
Short name T260
Test name
Test status
Simulation time 199729175951 ps
CPU time 371.72 seconds
Started May 05 01:34:18 PM PDT 24
Finished May 05 01:40:30 PM PDT 24
Peak memory 200280 kb
Host smart-d544fa91-3853-4276-bdfd-b3d570721e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579411964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3579411964
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1127467841
Short name T107
Test name
Test status
Simulation time 125243319452 ps
CPU time 381.33 seconds
Started May 05 01:37:21 PM PDT 24
Finished May 05 01:43:42 PM PDT 24
Peak memory 225224 kb
Host smart-752f4ee3-1b18-406f-aa19-6467c711ea0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127467841 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1127467841
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.4285639884
Short name T7
Test name
Test status
Simulation time 22690863967 ps
CPU time 72.01 seconds
Started May 05 01:37:07 PM PDT 24
Finished May 05 01:38:19 PM PDT 24
Peak memory 200352 kb
Host smart-63d33f59-7ca9-4e8d-b509-50a5822c2fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285639884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4285639884
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all.917070360
Short name T145
Test name
Test status
Simulation time 384466025217 ps
CPU time 181.05 seconds
Started May 05 01:30:38 PM PDT 24
Finished May 05 01:33:40 PM PDT 24
Peak memory 216868 kb
Host smart-ca4c3aa2-7acb-438b-9739-88b75530bbc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917070360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.917070360
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.41728719
Short name T88
Test name
Test status
Simulation time 260190653 ps
CPU time 1.19 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 199528 kb
Host smart-c34fcb24-e039-43c5-9e2f-3143bc020cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41728719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.41728719
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1024973425
Short name T123
Test name
Test status
Simulation time 170904732567 ps
CPU time 79.84 seconds
Started May 05 01:35:42 PM PDT 24
Finished May 05 01:37:02 PM PDT 24
Peak memory 208688 kb
Host smart-4f66b68e-7585-4449-aa86-040e31090fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024973425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1024973425
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_alert_test.1377925195
Short name T411
Test name
Test status
Simulation time 32472996 ps
CPU time 0.53 seconds
Started May 05 01:29:58 PM PDT 24
Finished May 05 01:29:59 PM PDT 24
Peak memory 195796 kb
Host smart-86d3070b-4af6-436c-bcc3-68fec024fa04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377925195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1377925195
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2510988779
Short name T175
Test name
Test status
Simulation time 27398974497 ps
CPU time 25.3 seconds
Started May 05 01:31:35 PM PDT 24
Finished May 05 01:32:01 PM PDT 24
Peak memory 200440 kb
Host smart-287da281-c2d6-4bae-8da6-61035a1f2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510988779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2510988779
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4055931881
Short name T126
Test name
Test status
Simulation time 307512891355 ps
CPU time 219.59 seconds
Started May 05 01:31:48 PM PDT 24
Finished May 05 01:35:27 PM PDT 24
Peak memory 200392 kb
Host smart-20281d54-be7c-4f2a-8053-33c18fb31db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055931881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4055931881
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4222265543
Short name T131
Test name
Test status
Simulation time 204075945072 ps
CPU time 167.13 seconds
Started May 05 01:38:22 PM PDT 24
Finished May 05 01:41:09 PM PDT 24
Peak memory 200304 kb
Host smart-da505ed7-2f6a-4551-b488-435fb1435898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222265543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4222265543
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4242556580
Short name T125
Test name
Test status
Simulation time 122244733758 ps
CPU time 57.42 seconds
Started May 05 01:32:14 PM PDT 24
Finished May 05 01:33:12 PM PDT 24
Peak memory 200340 kb
Host smart-e1ed17d9-f6e4-440b-b83c-097d1f456c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242556580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4242556580
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3691824526
Short name T69
Test name
Test status
Simulation time 43900259 ps
CPU time 0.56 seconds
Started May 05 02:43:47 PM PDT 24
Finished May 05 02:43:48 PM PDT 24
Peak memory 195696 kb
Host smart-f7f0c56d-ca8c-4e80-9a59-1c33a7c1658a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691824526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3691824526
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1552083899
Short name T82
Test name
Test status
Simulation time 40585647 ps
CPU time 0.62 seconds
Started May 05 02:43:52 PM PDT 24
Finished May 05 02:43:53 PM PDT 24
Peak memory 195700 kb
Host smart-caaf7fbb-5b3b-4439-8b64-f4df06482fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552083899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1552083899
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1291200418
Short name T275
Test name
Test status
Simulation time 221716995593 ps
CPU time 859.35 seconds
Started May 05 01:38:19 PM PDT 24
Finished May 05 01:52:38 PM PDT 24
Peak memory 200408 kb
Host smart-c9af934d-8552-4da8-b098-7408777989d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291200418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1291200418
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3897851884
Short name T24
Test name
Test status
Simulation time 178307147947 ps
CPU time 463.05 seconds
Started May 05 01:31:38 PM PDT 24
Finished May 05 01:39:21 PM PDT 24
Peak memory 212136 kb
Host smart-d9c88645-fe63-4de6-826d-375a7e0fcbe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897851884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3897851884
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2881159824
Short name T109
Test name
Test status
Simulation time 98665201000 ps
CPU time 612.15 seconds
Started May 05 01:36:58 PM PDT 24
Finished May 05 01:47:10 PM PDT 24
Peak memory 217052 kb
Host smart-3406cb9e-0143-402b-84bc-b913a9caae9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881159824 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2881159824
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4163116986
Short name T62
Test name
Test status
Simulation time 122234272289 ps
CPU time 71.52 seconds
Started May 05 01:38:22 PM PDT 24
Finished May 05 01:39:34 PM PDT 24
Peak memory 200392 kb
Host smart-0f5dbaf5-0b43-4abc-9882-1e16da8d2cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163116986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4163116986
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.432832881
Short name T218
Test name
Test status
Simulation time 37089722089 ps
CPU time 69.72 seconds
Started May 05 01:38:29 PM PDT 24
Finished May 05 01:39:39 PM PDT 24
Peak memory 200360 kb
Host smart-95d238ab-4d5f-45fe-a556-cb4664d13325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432832881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.432832881
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1443222093
Short name T156
Test name
Test status
Simulation time 37530094293 ps
CPU time 64.17 seconds
Started May 05 01:38:48 PM PDT 24
Finished May 05 01:39:52 PM PDT 24
Peak memory 200064 kb
Host smart-5a797f05-6710-40b8-8894-70336c0bb97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443222093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1443222093
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.926909644
Short name T258
Test name
Test status
Simulation time 99348922101 ps
CPU time 90.6 seconds
Started May 05 01:38:43 PM PDT 24
Finished May 05 01:40:14 PM PDT 24
Peak memory 200364 kb
Host smart-cb5525c8-9172-4b1d-9d5d-2ba59a3a8d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926909644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.926909644
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.963926270
Short name T35
Test name
Test status
Simulation time 80249979636 ps
CPU time 112.62 seconds
Started May 05 01:39:24 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 200416 kb
Host smart-9cc08e3a-76a9-4029-85aa-4c302b9e22d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963926270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.963926270
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3990316897
Short name T120
Test name
Test status
Simulation time 173342371 ps
CPU time 1.26 seconds
Started May 05 02:44:24 PM PDT 24
Finished May 05 02:44:26 PM PDT 24
Peak memory 199800 kb
Host smart-e7519627-a795-4264-9a02-606a0bd26b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990316897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3990316897
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1012641768
Short name T171
Test name
Test status
Simulation time 162699884591 ps
CPU time 1287.06 seconds
Started May 05 01:32:11 PM PDT 24
Finished May 05 01:53:39 PM PDT 24
Peak memory 216048 kb
Host smart-3a1657c7-03bb-4d53-9606-95abc5830cbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012641768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1012641768
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2878242267
Short name T146
Test name
Test status
Simulation time 52884096846 ps
CPU time 58.85 seconds
Started May 05 01:38:32 PM PDT 24
Finished May 05 01:39:32 PM PDT 24
Peak memory 200304 kb
Host smart-aff114df-5dba-442d-9007-61f41aab5e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878242267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2878242267
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.3973458871
Short name T232
Test name
Test status
Simulation time 108584142596 ps
CPU time 666.54 seconds
Started May 05 01:35:21 PM PDT 24
Finished May 05 01:46:28 PM PDT 24
Peak memory 200412 kb
Host smart-2da17ac5-0cbb-4fc8-b6d3-4c31c50d4c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973458871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3973458871
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1988955232
Short name T185
Test name
Test status
Simulation time 106506405573 ps
CPU time 273.76 seconds
Started May 05 01:38:29 PM PDT 24
Finished May 05 01:43:03 PM PDT 24
Peak memory 200340 kb
Host smart-ba6e8808-7381-4c31-9113-6dc64742394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988955232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1988955232
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.3866375874
Short name T469
Test name
Test status
Simulation time 187990021898 ps
CPU time 1080.35 seconds
Started May 05 01:32:43 PM PDT 24
Finished May 05 01:50:43 PM PDT 24
Peak memory 200408 kb
Host smart-10c3d4c3-ed4f-455d-8c53-9025b5fc7725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866375874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3866375874
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3189159102
Short name T59
Test name
Test status
Simulation time 344414871063 ps
CPU time 175.63 seconds
Started May 05 01:30:10 PM PDT 24
Finished May 05 01:33:06 PM PDT 24
Peak memory 200116 kb
Host smart-ca17526d-1086-4153-aa06-5a8edd4857da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189159102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3189159102
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.287383026
Short name T192
Test name
Test status
Simulation time 21517909619 ps
CPU time 32.77 seconds
Started May 05 01:36:43 PM PDT 24
Finished May 05 01:37:16 PM PDT 24
Peak memory 200312 kb
Host smart-fb9db2f9-04fe-4638-8ec5-a140b2c429f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287383026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.287383026
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.4280792320
Short name T209
Test name
Test status
Simulation time 53895832130 ps
CPU time 128.26 seconds
Started May 05 01:38:03 PM PDT 24
Finished May 05 01:40:12 PM PDT 24
Peak memory 200252 kb
Host smart-6b6bf0f6-1fe5-4565-806c-17aaebe5e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280792320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4280792320
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.991043987
Short name T200
Test name
Test status
Simulation time 123486901970 ps
CPU time 285.54 seconds
Started May 05 01:32:18 PM PDT 24
Finished May 05 01:37:04 PM PDT 24
Peak memory 216456 kb
Host smart-a869656a-4d58-4367-86f6-8861c23aac95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991043987 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.991043987
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3372078106
Short name T159
Test name
Test status
Simulation time 28165055375 ps
CPU time 13.8 seconds
Started May 05 01:30:02 PM PDT 24
Finished May 05 01:30:16 PM PDT 24
Peak memory 200416 kb
Host smart-85d09d36-f5bb-46f4-9430-b37559fb5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372078106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3372078106
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3747974097
Short name T166
Test name
Test status
Simulation time 186143858369 ps
CPU time 86.95 seconds
Started May 05 01:32:37 PM PDT 24
Finished May 05 01:34:04 PM PDT 24
Peak memory 200404 kb
Host smart-baac16c7-4dd6-41f2-b8cc-0f3b3f7062d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747974097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3747974097
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.4272185049
Short name T223
Test name
Test status
Simulation time 140029619313 ps
CPU time 48.82 seconds
Started May 05 01:38:45 PM PDT 24
Finished May 05 01:39:34 PM PDT 24
Peak memory 200400 kb
Host smart-de4b90e6-607c-463a-8d07-eda1ab0910ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272185049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.4272185049
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1888805328
Short name T160
Test name
Test status
Simulation time 11604538731 ps
CPU time 12.06 seconds
Started May 05 01:39:13 PM PDT 24
Finished May 05 01:39:25 PM PDT 24
Peak memory 200200 kb
Host smart-62541c05-b4c7-4217-ac2a-e92f2b63ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888805328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1888805328
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3224274398
Short name T133
Test name
Test status
Simulation time 5561909601 ps
CPU time 10.67 seconds
Started May 05 01:39:12 PM PDT 24
Finished May 05 01:39:23 PM PDT 24
Peak memory 199960 kb
Host smart-372c1c74-8a22-4b00-aae5-7532cc4d2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224274398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3224274398
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1375235115
Short name T219
Test name
Test status
Simulation time 52248239350 ps
CPU time 31.56 seconds
Started May 05 01:39:16 PM PDT 24
Finished May 05 01:39:48 PM PDT 24
Peak memory 200292 kb
Host smart-cc59f3ea-dd6b-4483-ac17-9eb5227947d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375235115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1375235115
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1948850482
Short name T162
Test name
Test status
Simulation time 179489114642 ps
CPU time 19.17 seconds
Started May 05 01:31:03 PM PDT 24
Finished May 05 01:31:22 PM PDT 24
Peak memory 200332 kb
Host smart-2c7b904d-7639-492d-b8ad-c490c73e7f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948850482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1948850482
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.4129788269
Short name T248
Test name
Test status
Simulation time 102699879366 ps
CPU time 60.08 seconds
Started May 05 01:37:35 PM PDT 24
Finished May 05 01:38:35 PM PDT 24
Peak memory 200356 kb
Host smart-29a8fa60-7ceb-4723-bae6-10704b885f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129788269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4129788269
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4123930441
Short name T182
Test name
Test status
Simulation time 66797154835 ps
CPU time 110.93 seconds
Started May 05 01:37:35 PM PDT 24
Finished May 05 01:39:26 PM PDT 24
Peak memory 200408 kb
Host smart-106e2db3-6949-46ff-bb62-32d0621a7086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123930441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4123930441
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3580652653
Short name T130
Test name
Test status
Simulation time 77843933555 ps
CPU time 19.65 seconds
Started May 05 01:37:46 PM PDT 24
Finished May 05 01:38:06 PM PDT 24
Peak memory 200404 kb
Host smart-6c16bd04-a15e-483f-8bcb-4ce070759597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580652653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3580652653
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1899605733
Short name T251
Test name
Test status
Simulation time 27269291354 ps
CPU time 55 seconds
Started May 05 01:33:14 PM PDT 24
Finished May 05 01:34:10 PM PDT 24
Peak memory 200364 kb
Host smart-459c7643-cd10-4a51-8ea9-34ccc770c9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899605733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1899605733
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3878496891
Short name T1143
Test name
Test status
Simulation time 86728501825 ps
CPU time 85.79 seconds
Started May 05 01:39:07 PM PDT 24
Finished May 05 01:40:33 PM PDT 24
Peak memory 200412 kb
Host smart-a05205cf-efd4-468a-a467-2e5a2e8f5273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878496891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3878496891
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3224015720
Short name T302
Test name
Test status
Simulation time 44241094957 ps
CPU time 34.72 seconds
Started May 05 01:36:33 PM PDT 24
Finished May 05 01:37:08 PM PDT 24
Peak memory 200340 kb
Host smart-64bd3608-0d7a-4f97-9dab-3c128cde4959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224015720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3224015720
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2940366651
Short name T1317
Test name
Test status
Simulation time 91131111 ps
CPU time 1.31 seconds
Started May 05 02:43:49 PM PDT 24
Finished May 05 02:43:51 PM PDT 24
Peak memory 199596 kb
Host smart-d07c6cd7-829d-4e10-991b-227597520b96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940366651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2940366651
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2021731279
Short name T134
Test name
Test status
Simulation time 18184600017 ps
CPU time 27.35 seconds
Started May 05 01:37:26 PM PDT 24
Finished May 05 01:37:54 PM PDT 24
Peak memory 200092 kb
Host smart-32c79765-dd2f-4262-b2c9-85f57e945500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021731279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2021731279
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3238555588
Short name T238
Test name
Test status
Simulation time 17487949649 ps
CPU time 28.04 seconds
Started May 05 01:37:30 PM PDT 24
Finished May 05 01:37:58 PM PDT 24
Peak memory 200392 kb
Host smart-a40864a6-2e92-4ece-aefc-a866d0cf00a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238555588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3238555588
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.264938982
Short name T128
Test name
Test status
Simulation time 50857494926 ps
CPU time 79.04 seconds
Started May 05 01:30:58 PM PDT 24
Finished May 05 01:32:18 PM PDT 24
Peak memory 200328 kb
Host smart-2bc13ec0-7ad1-43a3-a0b3-dd005aef5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264938982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.264938982
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.505449199
Short name T239
Test name
Test status
Simulation time 52697653939 ps
CPU time 86.74 seconds
Started May 05 01:37:59 PM PDT 24
Finished May 05 01:39:26 PM PDT 24
Peak memory 200344 kb
Host smart-3e17301b-8d43-41d0-801f-f3cecab9e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505449199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.505449199
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3064200242
Short name T310
Test name
Test status
Simulation time 125200155256 ps
CPU time 415.74 seconds
Started May 05 01:31:42 PM PDT 24
Finished May 05 01:38:39 PM PDT 24
Peak memory 216832 kb
Host smart-01e2a561-a5a2-49e0-91e0-6a896743b1d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064200242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3064200242
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3863515026
Short name T197
Test name
Test status
Simulation time 135143695909 ps
CPU time 38.14 seconds
Started May 05 01:38:03 PM PDT 24
Finished May 05 01:38:41 PM PDT 24
Peak memory 200384 kb
Host smart-3f22b350-3649-4605-9fa3-36e48e7c5c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863515026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3863515026
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.612726745
Short name T207
Test name
Test status
Simulation time 88721804989 ps
CPU time 11.39 seconds
Started May 05 01:38:13 PM PDT 24
Finished May 05 01:38:24 PM PDT 24
Peak memory 200244 kb
Host smart-bb9ad9d1-2ed0-4651-bef1-bfd0aaec5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612726745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.612726745
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2755491250
Short name T243
Test name
Test status
Simulation time 46446409724 ps
CPU time 18.09 seconds
Started May 05 01:38:13 PM PDT 24
Finished May 05 01:38:32 PM PDT 24
Peak memory 200212 kb
Host smart-558127ae-b5fd-4546-bb07-1d135dd3f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755491250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2755491250
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1778279837
Short name T229
Test name
Test status
Simulation time 174935162774 ps
CPU time 290.01 seconds
Started May 05 01:38:29 PM PDT 24
Finished May 05 01:43:20 PM PDT 24
Peak memory 200348 kb
Host smart-6aa9a0fa-dbf4-4108-9830-d18d1bc1e189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778279837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1778279837
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1942598126
Short name T99
Test name
Test status
Simulation time 53381953430 ps
CPU time 22.81 seconds
Started May 05 01:38:27 PM PDT 24
Finished May 05 01:38:50 PM PDT 24
Peak memory 200272 kb
Host smart-ef86388e-2a8b-46f6-9aa2-c9aca675b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942598126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1942598126
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4028380445
Short name T129
Test name
Test status
Simulation time 87079484376 ps
CPU time 83.18 seconds
Started May 05 01:32:22 PM PDT 24
Finished May 05 01:33:45 PM PDT 24
Peak memory 200320 kb
Host smart-3030045d-0b0a-471e-89b1-7b51b633fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028380445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4028380445
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2611598053
Short name T247
Test name
Test status
Simulation time 16399415672 ps
CPU time 25.22 seconds
Started May 05 01:38:37 PM PDT 24
Finished May 05 01:39:03 PM PDT 24
Peak memory 200320 kb
Host smart-865806ea-106f-453c-9057-14a78713eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611598053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2611598053
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1385847260
Short name T56
Test name
Test status
Simulation time 127544639875 ps
CPU time 147.12 seconds
Started May 05 01:38:49 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 200420 kb
Host smart-35773b6c-5b14-466a-b361-3ab8640d73e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385847260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1385847260
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4251653595
Short name T222
Test name
Test status
Simulation time 180144054405 ps
CPU time 392.18 seconds
Started May 05 01:38:56 PM PDT 24
Finished May 05 01:45:28 PM PDT 24
Peak memory 200336 kb
Host smart-2120726d-8980-46fb-b87c-8e953db0f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251653595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4251653595
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2804433445
Short name T241
Test name
Test status
Simulation time 155596546239 ps
CPU time 20.14 seconds
Started May 05 01:38:57 PM PDT 24
Finished May 05 01:39:18 PM PDT 24
Peak memory 200324 kb
Host smart-c951d366-4de6-4c04-809a-f2a54ed227d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804433445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2804433445
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3142539089
Short name T142
Test name
Test status
Simulation time 88234228361 ps
CPU time 150.57 seconds
Started May 05 01:38:59 PM PDT 24
Finished May 05 01:41:30 PM PDT 24
Peak memory 200360 kb
Host smart-49aa5564-941d-493a-8200-2eb7d7785436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142539089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3142539089
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3202851822
Short name T233
Test name
Test status
Simulation time 39554251532 ps
CPU time 97.51 seconds
Started May 05 01:33:21 PM PDT 24
Finished May 05 01:34:59 PM PDT 24
Peak memory 200380 kb
Host smart-f37c605b-8fd4-41af-bdcc-11f2591115ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202851822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3202851822
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.305867865
Short name T152
Test name
Test status
Simulation time 100365354216 ps
CPU time 171.79 seconds
Started May 05 01:36:24 PM PDT 24
Finished May 05 01:39:16 PM PDT 24
Peak memory 200320 kb
Host smart-ec10456d-496d-44d1-a8cf-0915bab8e1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305867865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.305867865
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.626316242
Short name T228
Test name
Test status
Simulation time 37180097718 ps
CPU time 46.66 seconds
Started May 05 01:36:56 PM PDT 24
Finished May 05 01:37:43 PM PDT 24
Peak memory 200588 kb
Host smart-ac576339-0144-40b2-bd91-edd00c208f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626316242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.626316242
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2917151133
Short name T244
Test name
Test status
Simulation time 100036360660 ps
CPU time 50.15 seconds
Started May 05 01:37:19 PM PDT 24
Finished May 05 01:38:09 PM PDT 24
Peak memory 200364 kb
Host smart-e63b6668-4925-4b85-b17e-b5c3e913067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917151133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2917151133
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4057191277
Short name T1205
Test name
Test status
Simulation time 114564360 ps
CPU time 0.78 seconds
Started May 05 02:43:47 PM PDT 24
Finished May 05 02:43:49 PM PDT 24
Peak memory 196752 kb
Host smart-466025e6-5528-4487-af50-af4d49509a39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057191277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4057191277
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4208632791
Short name T1268
Test name
Test status
Simulation time 1465210343 ps
CPU time 2.48 seconds
Started May 05 02:43:58 PM PDT 24
Finished May 05 02:44:01 PM PDT 24
Peak memory 198160 kb
Host smart-ef8fb959-bce5-48cf-9a37-fd188205f868
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208632791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4208632791
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.537654918
Short name T1259
Test name
Test status
Simulation time 32663174 ps
CPU time 0.8 seconds
Started May 05 02:43:49 PM PDT 24
Finished May 05 02:43:50 PM PDT 24
Peak memory 199552 kb
Host smart-13ffb8b3-e611-4303-8476-522917e87eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537654918 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.537654918
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3958849897
Short name T1273
Test name
Test status
Simulation time 45851900 ps
CPU time 0.58 seconds
Started May 05 02:43:49 PM PDT 24
Finished May 05 02:43:50 PM PDT 24
Peak memory 195716 kb
Host smart-21e21589-f8d7-4acb-83f3-f63c1fa620a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958849897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3958849897
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2918525799
Short name T1193
Test name
Test status
Simulation time 41180445 ps
CPU time 0.57 seconds
Started May 05 02:43:50 PM PDT 24
Finished May 05 02:43:51 PM PDT 24
Peak memory 194648 kb
Host smart-1c27f3e9-9bfe-4503-aea7-6c6a3bee8729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918525799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2918525799
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1207312770
Short name T1295
Test name
Test status
Simulation time 103746104 ps
CPU time 0.76 seconds
Started May 05 02:43:50 PM PDT 24
Finished May 05 02:43:51 PM PDT 24
Peak memory 196364 kb
Host smart-246d029f-763f-48da-9072-b13838114e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207312770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1207312770
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2849422376
Short name T1272
Test name
Test status
Simulation time 62909459 ps
CPU time 1.55 seconds
Started May 05 02:43:58 PM PDT 24
Finished May 05 02:44:00 PM PDT 24
Peak memory 200288 kb
Host smart-7caf47a8-bf3f-4569-8d41-bb7909a0936b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849422376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2849422376
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2913309134
Short name T1216
Test name
Test status
Simulation time 17982947 ps
CPU time 0.78 seconds
Started May 05 02:43:53 PM PDT 24
Finished May 05 02:43:55 PM PDT 24
Peak memory 196728 kb
Host smart-491cfe6a-5429-497d-8c09-61f749db11ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913309134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2913309134
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.974911859
Short name T68
Test name
Test status
Simulation time 1548473496 ps
CPU time 2.54 seconds
Started May 05 02:43:53 PM PDT 24
Finished May 05 02:43:56 PM PDT 24
Peak memory 198284 kb
Host smart-7706ec30-c1b6-46af-b9ca-87e7a5d8df1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974911859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.974911859
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1840232526
Short name T1196
Test name
Test status
Simulation time 15897054 ps
CPU time 0.56 seconds
Started May 05 02:43:57 PM PDT 24
Finished May 05 02:43:58 PM PDT 24
Peak memory 195680 kb
Host smart-f829b412-87d3-4651-9431-4b45cee61d4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840232526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1840232526
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1678684728
Short name T1228
Test name
Test status
Simulation time 312318188 ps
CPU time 0.74 seconds
Started May 05 02:43:53 PM PDT 24
Finished May 05 02:43:55 PM PDT 24
Peak memory 198484 kb
Host smart-720d7232-37b8-4133-9089-c840070edec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678684728 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1678684728
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3246088696
Short name T1248
Test name
Test status
Simulation time 56404517 ps
CPU time 0.59 seconds
Started May 05 02:43:56 PM PDT 24
Finished May 05 02:43:57 PM PDT 24
Peak memory 194652 kb
Host smart-cb414edd-c0cb-409e-9e27-ccc12d54071e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246088696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3246088696
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1694650175
Short name T1238
Test name
Test status
Simulation time 92345593 ps
CPU time 0.74 seconds
Started May 05 02:43:52 PM PDT 24
Finished May 05 02:43:53 PM PDT 24
Peak memory 197404 kb
Host smart-2485ede2-f7e3-4e61-85db-f39848c6a7a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694650175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1694650175
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.397267622
Short name T1285
Test name
Test status
Simulation time 622380663 ps
CPU time 1.63 seconds
Started May 05 02:43:53 PM PDT 24
Finished May 05 02:43:55 PM PDT 24
Peak memory 200300 kb
Host smart-4af4917d-87c5-49e1-9b94-85d0d5b6686a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397267622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.397267622
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4139188687
Short name T85
Test name
Test status
Simulation time 128680221 ps
CPU time 0.91 seconds
Started May 05 02:43:54 PM PDT 24
Finished May 05 02:43:56 PM PDT 24
Peak memory 199224 kb
Host smart-76a1a182-e2e9-4d4e-99f1-c063b395be77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139188687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4139188687
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3640187586
Short name T1309
Test name
Test status
Simulation time 18026413 ps
CPU time 0.66 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 197832 kb
Host smart-6c5db2df-3ec3-4212-a570-623c5133b822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640187586 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3640187586
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3188376459
Short name T1294
Test name
Test status
Simulation time 17217155 ps
CPU time 0.59 seconds
Started May 05 02:44:16 PM PDT 24
Finished May 05 02:44:18 PM PDT 24
Peak memory 195692 kb
Host smart-ff009b86-0269-430a-84e7-5baf6429f14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188376459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3188376459
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3322148555
Short name T1265
Test name
Test status
Simulation time 32436294 ps
CPU time 0.53 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 194636 kb
Host smart-5566d3ab-242f-43d3-86c9-6f65ceb4d21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322148555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3322148555
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3696879684
Short name T75
Test name
Test status
Simulation time 18595432 ps
CPU time 0.62 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:16 PM PDT 24
Peak memory 195920 kb
Host smart-e3fa9a37-5416-4bcb-b433-708c0acf49a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696879684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3696879684
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2772832112
Short name T1281
Test name
Test status
Simulation time 60824595 ps
CPU time 1.47 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 200240 kb
Host smart-0fb4abc4-0dd2-4175-bce0-00cb8fdb71bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772832112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2772832112
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.80124439
Short name T1303
Test name
Test status
Simulation time 256123997 ps
CPU time 1.28 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 199648 kb
Host smart-25c004d5-f049-4c82-938a-ee088e2b93fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80124439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.80124439
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3989939253
Short name T1244
Test name
Test status
Simulation time 22914209 ps
CPU time 0.72 seconds
Started May 05 02:44:16 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 199280 kb
Host smart-8ae8a7dd-a043-4207-99f2-629d875c4ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989939253 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3989939253
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3414839670
Short name T81
Test name
Test status
Simulation time 14777980 ps
CPU time 0.62 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:18 PM PDT 24
Peak memory 195740 kb
Host smart-56282f70-0809-4503-9bb4-9e67780796c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414839670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3414839670
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3350314248
Short name T1277
Test name
Test status
Simulation time 12282297 ps
CPU time 0.57 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 194644 kb
Host smart-4f018c0f-876c-4fdc-9ffd-a8b0e442d73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350314248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3350314248
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1844615795
Short name T1307
Test name
Test status
Simulation time 36970699 ps
CPU time 0.59 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 195764 kb
Host smart-72397ece-9135-4c01-af3e-78216bf80a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844615795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1844615795
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3067033016
Short name T1246
Test name
Test status
Simulation time 91695211 ps
CPU time 1.2 seconds
Started May 05 02:44:19 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 200380 kb
Host smart-766207d7-7d61-41eb-80ad-8b9c47909fef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067033016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3067033016
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3044547243
Short name T1253
Test name
Test status
Simulation time 69700056 ps
CPU time 1.02 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 200240 kb
Host smart-ea2f2a94-a904-47a0-8b12-b1c5a616f945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044547243 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3044547243
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3851752186
Short name T1296
Test name
Test status
Simulation time 14566592 ps
CPU time 0.58 seconds
Started May 05 02:44:16 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 195640 kb
Host smart-cfcd74c0-a7df-4dd9-a7e6-739bfbe39227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851752186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3851752186
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.362887726
Short name T1233
Test name
Test status
Simulation time 44196363 ps
CPU time 0.57 seconds
Started May 05 02:44:19 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 194668 kb
Host smart-72044f55-0fc0-4dd8-8add-91514c72a533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362887726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.362887726
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1799411395
Short name T1257
Test name
Test status
Simulation time 76872721 ps
CPU time 0.63 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 195788 kb
Host smart-87836107-abba-46e2-8760-5b18e834d0f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799411395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1799411395
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1180489123
Short name T1286
Test name
Test status
Simulation time 351433386 ps
CPU time 1.96 seconds
Started May 05 02:44:19 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 200384 kb
Host smart-3fed228b-58ca-4570-80c8-6296655ad704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180489123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1180489123
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3114586615
Short name T86
Test name
Test status
Simulation time 124354221 ps
CPU time 0.93 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 199256 kb
Host smart-755109b5-53bc-46d6-8b48-06a52ead4787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114586615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3114586615
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1487407419
Short name T1270
Test name
Test status
Simulation time 146317008 ps
CPU time 0.86 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 200200 kb
Host smart-c435b6a3-f920-4e7e-9108-21eae20a1ae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487407419 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1487407419
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.952264249
Short name T78
Test name
Test status
Simulation time 17942309 ps
CPU time 0.61 seconds
Started May 05 02:44:22 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 195708 kb
Host smart-e8ce0055-4a75-4b9c-9e37-65d9e1da6ae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952264249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.952264249
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2402901807
Short name T1260
Test name
Test status
Simulation time 14421597 ps
CPU time 0.6 seconds
Started May 05 02:44:16 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 194664 kb
Host smart-a00d5ef9-0b91-4891-ad0c-fa66e5ba3e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402901807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2402901807
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.344655965
Short name T1302
Test name
Test status
Simulation time 106716569 ps
CPU time 0.77 seconds
Started May 05 02:44:24 PM PDT 24
Finished May 05 02:44:25 PM PDT 24
Peak memory 197284 kb
Host smart-4aad0f8e-adfe-4f95-80a5-6475eaa38f58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344655965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.344655965
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3067653342
Short name T1282
Test name
Test status
Simulation time 113904990 ps
CPU time 1.57 seconds
Started May 05 02:44:19 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 200248 kb
Host smart-497f434f-77ff-404f-994f-092ac1f6e8ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067653342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3067653342
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3242603671
Short name T1318
Test name
Test status
Simulation time 442580203 ps
CPU time 1.4 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 199404 kb
Host smart-eeec6996-52d9-41e5-80cc-a977472f396a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242603671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3242603671
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1090756678
Short name T1230
Test name
Test status
Simulation time 30903671 ps
CPU time 0.91 seconds
Started May 05 02:44:21 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 200212 kb
Host smart-114d6fee-c963-4f98-ad2d-8679f2139bda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090756678 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1090756678
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3732854548
Short name T1225
Test name
Test status
Simulation time 36826865 ps
CPU time 0.59 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 195676 kb
Host smart-409cf067-1964-4c9c-9296-918b0b5a5565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732854548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3732854548
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1469656562
Short name T1211
Test name
Test status
Simulation time 40511505 ps
CPU time 0.57 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 194668 kb
Host smart-7720494d-545a-4ca1-8e8f-7567fbce2368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469656562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1469656562
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1519440051
Short name T1316
Test name
Test status
Simulation time 120172836 ps
CPU time 0.72 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 197408 kb
Host smart-979fe837-96f8-41be-bc85-de5994ce3403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519440051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1519440051
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3422545246
Short name T1308
Test name
Test status
Simulation time 137669679 ps
CPU time 2.29 seconds
Started May 05 02:44:22 PM PDT 24
Finished May 05 02:44:25 PM PDT 24
Peak memory 200276 kb
Host smart-b2d727e1-ba74-4c93-b1c6-ca2f5d82d09e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422545246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3422545246
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2268562245
Short name T1290
Test name
Test status
Simulation time 177642751 ps
CPU time 1.02 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 199272 kb
Host smart-61a55e01-9eb5-43f4-8cdd-20f6ae99fa82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268562245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2268562245
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1915344300
Short name T1189
Test name
Test status
Simulation time 18381610 ps
CPU time 0.75 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 199752 kb
Host smart-bcb1cfd2-2738-44f9-ba38-529dffb14925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915344300 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1915344300
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2194818160
Short name T1275
Test name
Test status
Simulation time 48319404 ps
CPU time 0.58 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 195700 kb
Host smart-607c24e5-d080-4ce0-bb35-e097799dda01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194818160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2194818160
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.268276584
Short name T1297
Test name
Test status
Simulation time 55648289 ps
CPU time 0.59 seconds
Started May 05 02:44:22 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 194644 kb
Host smart-b18b3ad7-032d-44b0-ab98-2415509c9730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268276584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.268276584
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.788862463
Short name T1287
Test name
Test status
Simulation time 44873942 ps
CPU time 0.66 seconds
Started May 05 02:44:22 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 196892 kb
Host smart-b18aa364-098f-499d-8bbe-a7e9612fbc17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788862463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.788862463
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.975114062
Short name T1254
Test name
Test status
Simulation time 144948662 ps
CPU time 1.48 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 200360 kb
Host smart-b209bde3-55b9-457b-9508-0bd341c7c9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975114062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.975114062
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1389097524
Short name T87
Test name
Test status
Simulation time 52407755 ps
CPU time 1.03 seconds
Started May 05 02:44:22 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 199336 kb
Host smart-9c8d4e62-9167-4757-826a-36bc48bd6462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389097524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1389097524
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.601338973
Short name T1288
Test name
Test status
Simulation time 33055132 ps
CPU time 0.84 seconds
Started May 05 02:44:27 PM PDT 24
Finished May 05 02:44:28 PM PDT 24
Peak memory 200092 kb
Host smart-a9da93e4-2ee2-47d1-ba33-6920af2f3a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601338973 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.601338973
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2122973121
Short name T1214
Test name
Test status
Simulation time 24571705 ps
CPU time 0.63 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 195712 kb
Host smart-914a5a40-918c-4b29-844d-8baee11ea2b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122973121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2122973121
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2484393716
Short name T1304
Test name
Test status
Simulation time 13748821 ps
CPU time 0.54 seconds
Started May 05 02:44:23 PM PDT 24
Finished May 05 02:44:24 PM PDT 24
Peak memory 194576 kb
Host smart-a2784179-2073-4c5c-9189-cd2fc5516db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484393716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2484393716
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3891351839
Short name T73
Test name
Test status
Simulation time 18573804 ps
CPU time 0.77 seconds
Started May 05 02:44:26 PM PDT 24
Finished May 05 02:44:27 PM PDT 24
Peak memory 197432 kb
Host smart-805b0aec-be95-429c-a3ba-3deac5a1d1e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891351839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3891351839
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3112798518
Short name T1227
Test name
Test status
Simulation time 26071670 ps
CPU time 1.19 seconds
Started May 05 02:44:21 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 200372 kb
Host smart-e35aad23-6c6c-4d59-995c-0dff55c68a10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112798518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3112798518
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2177300155
Short name T1311
Test name
Test status
Simulation time 195170479 ps
CPU time 1.25 seconds
Started May 05 02:44:21 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 199424 kb
Host smart-a313d4fd-c4d3-4750-8aa8-24b93a714b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177300155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2177300155
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3474037068
Short name T1249
Test name
Test status
Simulation time 18616522 ps
CPU time 0.88 seconds
Started May 05 02:44:25 PM PDT 24
Finished May 05 02:44:26 PM PDT 24
Peak memory 200248 kb
Host smart-0b6a342d-db72-4c4a-bf5b-5a2f05d2d0e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474037068 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3474037068
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.605091089
Short name T1251
Test name
Test status
Simulation time 12790395 ps
CPU time 0.59 seconds
Started May 05 02:44:25 PM PDT 24
Finished May 05 02:44:26 PM PDT 24
Peak memory 195712 kb
Host smart-4d607679-7f19-46ad-97c0-c0598a3d5983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605091089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.605091089
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2453258326
Short name T1187
Test name
Test status
Simulation time 50337146 ps
CPU time 0.55 seconds
Started May 05 02:44:24 PM PDT 24
Finished May 05 02:44:25 PM PDT 24
Peak memory 194748 kb
Host smart-b65ee847-776b-450f-8992-c5274a0234c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453258326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2453258326
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3777463551
Short name T1231
Test name
Test status
Simulation time 17493766 ps
CPU time 0.71 seconds
Started May 05 02:44:25 PM PDT 24
Finished May 05 02:44:26 PM PDT 24
Peak memory 197240 kb
Host smart-64d88953-caa8-423a-84d4-0141a5e1e7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777463551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3777463551
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3836894367
Short name T1235
Test name
Test status
Simulation time 751054850 ps
CPU time 1.81 seconds
Started May 05 02:44:26 PM PDT 24
Finished May 05 02:44:28 PM PDT 24
Peak memory 200356 kb
Host smart-b8af76d4-00fa-49c1-83d2-84e0715c1cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836894367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3836894367
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2272545412
Short name T93
Test name
Test status
Simulation time 95364783 ps
CPU time 1.32 seconds
Started May 05 02:44:28 PM PDT 24
Finished May 05 02:44:30 PM PDT 24
Peak memory 199620 kb
Host smart-e031700d-c433-48f8-9841-319d87bd1365
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272545412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2272545412
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3983809573
Short name T1195
Test name
Test status
Simulation time 43079013 ps
CPU time 0.71 seconds
Started May 05 02:44:25 PM PDT 24
Finished May 05 02:44:27 PM PDT 24
Peak memory 199364 kb
Host smart-f6db620b-e913-48fa-bbcf-14d68fb0a025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983809573 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3983809573
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3945657573
Short name T1223
Test name
Test status
Simulation time 144419104 ps
CPU time 0.58 seconds
Started May 05 02:44:27 PM PDT 24
Finished May 05 02:44:28 PM PDT 24
Peak memory 195648 kb
Host smart-a085cdf8-43c0-45f9-aa82-5eb56b45634a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945657573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3945657573
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3125248568
Short name T1200
Test name
Test status
Simulation time 14394450 ps
CPU time 0.61 seconds
Started May 05 02:44:27 PM PDT 24
Finished May 05 02:44:28 PM PDT 24
Peak memory 194664 kb
Host smart-abb335f1-0196-4079-a338-b277a2a21ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125248568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3125248568
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2487537178
Short name T1313
Test name
Test status
Simulation time 16780536 ps
CPU time 0.62 seconds
Started May 05 02:44:25 PM PDT 24
Finished May 05 02:44:26 PM PDT 24
Peak memory 195776 kb
Host smart-6ba4e461-f475-4414-bc67-73a061f64d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487537178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2487537178
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.894005728
Short name T1279
Test name
Test status
Simulation time 90225272 ps
CPU time 1.23 seconds
Started May 05 02:44:26 PM PDT 24
Finished May 05 02:44:28 PM PDT 24
Peak memory 200308 kb
Host smart-756ee7b1-d746-4d6d-9521-21e73d454aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894005728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.894005728
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2346890916
Short name T1241
Test name
Test status
Simulation time 54751830 ps
CPU time 0.65 seconds
Started May 05 02:44:33 PM PDT 24
Finished May 05 02:44:34 PM PDT 24
Peak memory 198004 kb
Host smart-93983ad4-1966-4fb2-86a7-0892d5e465f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346890916 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2346890916
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2149848610
Short name T67
Test name
Test status
Simulation time 11984517 ps
CPU time 0.58 seconds
Started May 05 02:44:33 PM PDT 24
Finished May 05 02:44:34 PM PDT 24
Peak memory 195608 kb
Host smart-3e0afea1-1435-4422-b13b-58d73bb05c2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149848610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2149848610
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3228930220
Short name T1221
Test name
Test status
Simulation time 52533228 ps
CPU time 0.55 seconds
Started May 05 02:44:26 PM PDT 24
Finished May 05 02:44:27 PM PDT 24
Peak memory 194632 kb
Host smart-fca80152-07f3-40a9-8bb7-60793a9382a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228930220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3228930220
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3604119580
Short name T74
Test name
Test status
Simulation time 46566286 ps
CPU time 0.63 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:33 PM PDT 24
Peak memory 196796 kb
Host smart-53536bf4-88fd-4bbf-84d1-f99da82bef46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604119580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3604119580
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2225026425
Short name T1293
Test name
Test status
Simulation time 48288920 ps
CPU time 1.58 seconds
Started May 05 02:44:28 PM PDT 24
Finished May 05 02:44:30 PM PDT 24
Peak memory 200320 kb
Host smart-635a20ed-4792-4ad8-a994-9bee3b8cbaeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225026425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2225026425
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.112769762
Short name T118
Test name
Test status
Simulation time 149388649 ps
CPU time 1.38 seconds
Started May 05 02:44:28 PM PDT 24
Finished May 05 02:44:29 PM PDT 24
Peak memory 199520 kb
Host smart-7f0db130-e0f9-4a73-94af-9bddf09f851f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112769762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.112769762
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.4232254191
Short name T1190
Test name
Test status
Simulation time 51473579 ps
CPU time 0.67 seconds
Started May 05 02:43:56 PM PDT 24
Finished May 05 02:43:57 PM PDT 24
Peak memory 195800 kb
Host smart-2206af0f-dd0b-438b-aaf3-83f2b6d8c06f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232254191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.4232254191
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2555084477
Short name T71
Test name
Test status
Simulation time 135313605 ps
CPU time 1.63 seconds
Started May 05 02:44:00 PM PDT 24
Finished May 05 02:44:02 PM PDT 24
Peak memory 198288 kb
Host smart-13251aff-91d6-4738-a563-19692868ce5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555084477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2555084477
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.368778042
Short name T1269
Test name
Test status
Simulation time 14278163 ps
CPU time 0.58 seconds
Started May 05 02:43:57 PM PDT 24
Finished May 05 02:43:58 PM PDT 24
Peak memory 195712 kb
Host smart-c4960f2e-93b0-4889-9739-d5c7876e9da0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368778042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.368778042
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3496944768
Short name T1258
Test name
Test status
Simulation time 35088067 ps
CPU time 0.86 seconds
Started May 05 02:43:58 PM PDT 24
Finished May 05 02:43:59 PM PDT 24
Peak memory 200088 kb
Host smart-c256543e-19e4-44f4-965d-d1101d049ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496944768 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3496944768
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.213128594
Short name T1263
Test name
Test status
Simulation time 12639760 ps
CPU time 0.57 seconds
Started May 05 02:43:56 PM PDT 24
Finished May 05 02:43:57 PM PDT 24
Peak memory 195712 kb
Host smart-a787f61c-dc1f-4deb-befb-1066839f8c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213128594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.213128594
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4275830504
Short name T1207
Test name
Test status
Simulation time 14368740 ps
CPU time 0.59 seconds
Started May 05 02:43:51 PM PDT 24
Finished May 05 02:43:52 PM PDT 24
Peak memory 194648 kb
Host smart-097224c0-4254-4011-a519-2363a7d70514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275830504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4275830504
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1994098359
Short name T1310
Test name
Test status
Simulation time 52083455 ps
CPU time 0.73 seconds
Started May 05 02:43:57 PM PDT 24
Finished May 05 02:43:58 PM PDT 24
Peak memory 196436 kb
Host smart-fb17fd1e-9507-41a7-9345-f2c0715ff310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994098359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1994098359
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2949851534
Short name T1271
Test name
Test status
Simulation time 154330094 ps
CPU time 1.71 seconds
Started May 05 02:43:56 PM PDT 24
Finished May 05 02:43:58 PM PDT 24
Peak memory 200340 kb
Host smart-fb119b07-35a5-4933-b8e8-13f16c7e3d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949851534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2949851534
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.690555113
Short name T117
Test name
Test status
Simulation time 107020722 ps
CPU time 1.24 seconds
Started May 05 02:43:58 PM PDT 24
Finished May 05 02:44:00 PM PDT 24
Peak memory 199404 kb
Host smart-5fdbaf75-11d7-42c4-a78d-309e5383b285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690555113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.690555113
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3488375681
Short name T1240
Test name
Test status
Simulation time 18107497 ps
CPU time 0.57 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194904 kb
Host smart-a6130105-4c51-4ee3-a1ac-8bc757ebf020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488375681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3488375681
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1716685399
Short name T1219
Test name
Test status
Simulation time 11589113 ps
CPU time 0.59 seconds
Started May 05 02:44:29 PM PDT 24
Finished May 05 02:44:30 PM PDT 24
Peak memory 194668 kb
Host smart-dc91751c-421d-43ef-b491-b409cb45e946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716685399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1716685399
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3136454842
Short name T1204
Test name
Test status
Simulation time 115186924 ps
CPU time 0.59 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:33 PM PDT 24
Peak memory 194632 kb
Host smart-40e0181a-52f0-4948-ae68-79cbaeb7dadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136454842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3136454842
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2806472707
Short name T1250
Test name
Test status
Simulation time 38769821 ps
CPU time 0.54 seconds
Started May 05 02:44:29 PM PDT 24
Finished May 05 02:44:30 PM PDT 24
Peak memory 194644 kb
Host smart-942bd27c-9732-43e4-8754-c5550b09513a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806472707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2806472707
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2801303273
Short name T1192
Test name
Test status
Simulation time 34676901 ps
CPU time 0.56 seconds
Started May 05 02:44:29 PM PDT 24
Finished May 05 02:44:30 PM PDT 24
Peak memory 194656 kb
Host smart-0ae6b101-4057-4542-b736-67775e130a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801303273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2801303273
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3925522534
Short name T1320
Test name
Test status
Simulation time 27880525 ps
CPU time 0.57 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194680 kb
Host smart-d497249c-e2c6-4891-b05d-147237117a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925522534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3925522534
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1621172747
Short name T1215
Test name
Test status
Simulation time 14847151 ps
CPU time 0.57 seconds
Started May 05 02:44:30 PM PDT 24
Finished May 05 02:44:31 PM PDT 24
Peak memory 194588 kb
Host smart-bfdecc22-6e4c-473f-a6dc-0a0844e69727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621172747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1621172747
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1783951325
Short name T1218
Test name
Test status
Simulation time 18249033 ps
CPU time 0.59 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:34 PM PDT 24
Peak memory 194700 kb
Host smart-f2a49dc7-c7f3-4c5e-915a-15735ca787c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783951325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1783951325
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2692922352
Short name T1226
Test name
Test status
Simulation time 13052058 ps
CPU time 0.59 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194692 kb
Host smart-334df68b-9682-45c6-9ae3-08c63a295c65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692922352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2692922352
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.888953177
Short name T1299
Test name
Test status
Simulation time 24378417 ps
CPU time 0.58 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194712 kb
Host smart-b3c90042-f213-4f4b-898d-17906e4acba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888953177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.888953177
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1905776780
Short name T1212
Test name
Test status
Simulation time 15016761 ps
CPU time 0.65 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:16 PM PDT 24
Peak memory 195252 kb
Host smart-e9e305ff-1edb-437b-8ec3-36e299fbc4e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905776780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1905776780
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2061791132
Short name T66
Test name
Test status
Simulation time 61001351 ps
CPU time 2.27 seconds
Started May 05 02:43:56 PM PDT 24
Finished May 05 02:43:59 PM PDT 24
Peak memory 197956 kb
Host smart-ab0cd0de-3727-467e-b5d1-5604717fa12f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061791132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2061791132
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.892713058
Short name T1243
Test name
Test status
Simulation time 38590608 ps
CPU time 0.6 seconds
Started May 05 02:44:03 PM PDT 24
Finished May 05 02:44:04 PM PDT 24
Peak memory 195696 kb
Host smart-447cd010-97b0-4846-bec2-48ee6e73eacb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892713058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.892713058
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1517060897
Short name T1289
Test name
Test status
Simulation time 60765260 ps
CPU time 0.66 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:16 PM PDT 24
Peak memory 197656 kb
Host smart-6e295baa-06e6-4732-8967-ca65dd60c436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517060897 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1517060897
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2020459626
Short name T1305
Test name
Test status
Simulation time 45585043 ps
CPU time 0.62 seconds
Started May 05 02:43:56 PM PDT 24
Finished May 05 02:43:57 PM PDT 24
Peak memory 195732 kb
Host smart-05d1639d-993d-4bc0-8090-0ca54a6ba1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020459626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2020459626
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1775777204
Short name T1314
Test name
Test status
Simulation time 35863229 ps
CPU time 0.57 seconds
Started May 05 02:43:57 PM PDT 24
Finished May 05 02:43:58 PM PDT 24
Peak memory 194716 kb
Host smart-5a27df47-607f-4a09-b0c0-427bf4ec809f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775777204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1775777204
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2276493217
Short name T80
Test name
Test status
Simulation time 72170982 ps
CPU time 0.67 seconds
Started May 05 02:44:03 PM PDT 24
Finished May 05 02:44:04 PM PDT 24
Peak memory 196852 kb
Host smart-a34d60a0-5557-40a7-af0d-0c45f7af12c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276493217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2276493217
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3716751819
Short name T1224
Test name
Test status
Simulation time 48425593 ps
CPU time 2.28 seconds
Started May 05 02:43:57 PM PDT 24
Finished May 05 02:43:59 PM PDT 24
Peak memory 200380 kb
Host smart-ab628c0d-36b4-413a-ad11-a7ac02e9dc91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716751819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3716751819
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3113239297
Short name T1315
Test name
Test status
Simulation time 93842610 ps
CPU time 0.95 seconds
Started May 05 02:43:55 PM PDT 24
Finished May 05 02:43:56 PM PDT 24
Peak memory 199360 kb
Host smart-520c2376-3c03-473f-954b-f745e60fab17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113239297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3113239297
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.82444343
Short name T1232
Test name
Test status
Simulation time 15701705 ps
CPU time 0.56 seconds
Started May 05 02:44:33 PM PDT 24
Finished May 05 02:44:34 PM PDT 24
Peak memory 194652 kb
Host smart-3038302a-7e26-4197-bf67-c4f10f0495aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82444343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.82444343
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2799210649
Short name T1203
Test name
Test status
Simulation time 22284654 ps
CPU time 0.55 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:33 PM PDT 24
Peak memory 194696 kb
Host smart-084681be-7b9e-4581-872a-a2426a064b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799210649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2799210649
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1603552002
Short name T1188
Test name
Test status
Simulation time 17055892 ps
CPU time 0.61 seconds
Started May 05 02:44:33 PM PDT 24
Finished May 05 02:44:34 PM PDT 24
Peak memory 194716 kb
Host smart-f3c378f0-2f81-4e89-8ebd-68a77a3b3d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603552002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1603552002
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.218548889
Short name T1239
Test name
Test status
Simulation time 34152585 ps
CPU time 0.62 seconds
Started May 05 02:44:30 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194744 kb
Host smart-cfa1cb16-28e0-485c-916a-6d48e1220865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218548889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.218548889
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.290259638
Short name T1197
Test name
Test status
Simulation time 59485653 ps
CPU time 0.59 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:33 PM PDT 24
Peak memory 194668 kb
Host smart-a4594d31-9606-4ffe-a778-e9dd14f46beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290259638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.290259638
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2953239099
Short name T1213
Test name
Test status
Simulation time 11163999 ps
CPU time 0.55 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194648 kb
Host smart-834f7c18-f125-48c6-b372-ec7fd4aff70c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953239099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2953239099
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3476576364
Short name T1191
Test name
Test status
Simulation time 13876238 ps
CPU time 0.57 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194684 kb
Host smart-b81bf7d2-1658-43e5-b499-45c7df5528a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476576364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3476576364
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1353279137
Short name T1220
Test name
Test status
Simulation time 24498449 ps
CPU time 0.57 seconds
Started May 05 02:44:34 PM PDT 24
Finished May 05 02:44:35 PM PDT 24
Peak memory 194724 kb
Host smart-390f3a34-39fa-4903-957f-8b593f02655d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353279137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1353279137
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.779261884
Short name T1229
Test name
Test status
Simulation time 14567971 ps
CPU time 0.58 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:33 PM PDT 24
Peak memory 194632 kb
Host smart-8d5429aa-da9c-4bf1-b808-3fd0a561f2c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779261884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.779261884
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2737806651
Short name T1199
Test name
Test status
Simulation time 15712237 ps
CPU time 0.56 seconds
Started May 05 02:44:30 PM PDT 24
Finished May 05 02:44:31 PM PDT 24
Peak memory 194688 kb
Host smart-6d821575-bc34-4d39-b7d2-3afff953d81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737806651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2737806651
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.437187373
Short name T1255
Test name
Test status
Simulation time 13031731 ps
CPU time 0.66 seconds
Started May 05 02:44:06 PM PDT 24
Finished May 05 02:44:07 PM PDT 24
Peak memory 195164 kb
Host smart-eb15b749-d8a7-430d-9ed8-c3dc843b3027
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437187373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.437187373
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3944394675
Short name T70
Test name
Test status
Simulation time 118009650 ps
CPU time 1.42 seconds
Started May 05 02:44:02 PM PDT 24
Finished May 05 02:44:04 PM PDT 24
Peak memory 198112 kb
Host smart-4fa8e220-1a3c-45a2-aafd-1ddc43c7662a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944394675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3944394675
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3919413109
Short name T72
Test name
Test status
Simulation time 49236144 ps
CPU time 0.6 seconds
Started May 05 02:44:02 PM PDT 24
Finished May 05 02:44:04 PM PDT 24
Peak memory 195672 kb
Host smart-dd64ffb3-fea9-4f30-abee-1f2a0256f92c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919413109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3919413109
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.942962696
Short name T1186
Test name
Test status
Simulation time 44719053 ps
CPU time 0.74 seconds
Started May 05 02:44:10 PM PDT 24
Finished May 05 02:44:11 PM PDT 24
Peak memory 199028 kb
Host smart-fd65e956-a4ef-4679-ac98-d131804cf0ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942962696 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.942962696
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3253514402
Short name T1284
Test name
Test status
Simulation time 35261878 ps
CPU time 0.59 seconds
Started May 05 02:44:03 PM PDT 24
Finished May 05 02:44:04 PM PDT 24
Peak memory 195716 kb
Host smart-932b3c7d-5743-4174-8625-b754fa986031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253514402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3253514402
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2159124314
Short name T1252
Test name
Test status
Simulation time 147061125 ps
CPU time 0.56 seconds
Started May 05 02:44:03 PM PDT 24
Finished May 05 02:44:04 PM PDT 24
Peak memory 194724 kb
Host smart-d9f50537-5b1a-41e7-acd4-1b22e1e4ce19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159124314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2159124314
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1090253996
Short name T79
Test name
Test status
Simulation time 71143285 ps
CPU time 0.64 seconds
Started May 05 02:44:06 PM PDT 24
Finished May 05 02:44:07 PM PDT 24
Peak memory 196060 kb
Host smart-cf12e324-5e96-4b7c-bc22-332946786d7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090253996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1090253996
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.130926721
Short name T1298
Test name
Test status
Simulation time 144797282 ps
CPU time 1.33 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 200376 kb
Host smart-23996a46-1b10-4d8d-bfdf-cec7af247a27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130926721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.130926721
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2926123525
Short name T119
Test name
Test status
Simulation time 95267615 ps
CPU time 1.31 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 199632 kb
Host smart-6280b545-f2f4-40b2-853b-b0c31b0b13c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926123525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2926123525
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2727057045
Short name T1266
Test name
Test status
Simulation time 46053872 ps
CPU time 0.57 seconds
Started May 05 02:44:32 PM PDT 24
Finished May 05 02:44:33 PM PDT 24
Peak memory 194632 kb
Host smart-4fc9f20c-5386-4cac-8c7f-c5fa6932bc5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727057045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2727057045
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2218312111
Short name T1201
Test name
Test status
Simulation time 31772467 ps
CPU time 0.56 seconds
Started May 05 02:44:31 PM PDT 24
Finished May 05 02:44:32 PM PDT 24
Peak memory 194648 kb
Host smart-28b28760-d5db-4af4-bd1f-d3aed77359a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218312111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2218312111
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.261324764
Short name T1247
Test name
Test status
Simulation time 13110279 ps
CPU time 0.57 seconds
Started May 05 02:44:36 PM PDT 24
Finished May 05 02:44:37 PM PDT 24
Peak memory 194648 kb
Host smart-d619f40d-6a2f-495a-b889-caf5cf3b281d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261324764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.261324764
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3871408197
Short name T1301
Test name
Test status
Simulation time 56924104 ps
CPU time 0.58 seconds
Started May 05 02:44:36 PM PDT 24
Finished May 05 02:44:37 PM PDT 24
Peak memory 194644 kb
Host smart-0f8d2098-de9f-411d-8481-4c33fe8f89b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871408197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3871408197
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.738417877
Short name T1300
Test name
Test status
Simulation time 13689923 ps
CPU time 0.58 seconds
Started May 05 02:44:34 PM PDT 24
Finished May 05 02:44:35 PM PDT 24
Peak memory 194680 kb
Host smart-ebe2debe-ed5a-4ea1-b7d8-af5d13f3343b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738417877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.738417877
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1009669177
Short name T1222
Test name
Test status
Simulation time 36128286 ps
CPU time 0.65 seconds
Started May 05 02:44:35 PM PDT 24
Finished May 05 02:44:36 PM PDT 24
Peak memory 194752 kb
Host smart-b5fa6de4-38f6-495d-9cf0-baa79c58d97e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009669177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1009669177
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1234011040
Short name T1194
Test name
Test status
Simulation time 19931763 ps
CPU time 0.57 seconds
Started May 05 02:44:36 PM PDT 24
Finished May 05 02:44:37 PM PDT 24
Peak memory 194660 kb
Host smart-22c26767-6048-4d67-85cf-1513479574ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234011040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1234011040
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.4192572820
Short name T1217
Test name
Test status
Simulation time 46118294 ps
CPU time 0.59 seconds
Started May 05 02:44:36 PM PDT 24
Finished May 05 02:44:37 PM PDT 24
Peak memory 194744 kb
Host smart-f633e419-7f18-4ac6-adf6-3ac25175c997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192572820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4192572820
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1910080821
Short name T1283
Test name
Test status
Simulation time 25468125 ps
CPU time 0.57 seconds
Started May 05 02:44:37 PM PDT 24
Finished May 05 02:44:38 PM PDT 24
Peak memory 194652 kb
Host smart-e3dbe195-d97c-45e9-bd9a-6ebee59f5dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910080821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1910080821
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.477552706
Short name T1261
Test name
Test status
Simulation time 17878832 ps
CPU time 0.56 seconds
Started May 05 02:44:36 PM PDT 24
Finished May 05 02:44:38 PM PDT 24
Peak memory 194636 kb
Host smart-c4b0ea75-f7ca-45aa-94f6-7efbbd39936b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477552706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.477552706
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3944106351
Short name T1242
Test name
Test status
Simulation time 72698766 ps
CPU time 0.73 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 198344 kb
Host smart-a70fcafa-ea33-4207-9f51-3a6c5162c295
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944106351 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3944106351
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1786239458
Short name T1319
Test name
Test status
Simulation time 62246434 ps
CPU time 0.62 seconds
Started May 05 02:44:06 PM PDT 24
Finished May 05 02:44:07 PM PDT 24
Peak memory 195804 kb
Host smart-1fb27611-72e6-480f-bfb3-3d8ec4563c22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786239458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1786239458
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3724503663
Short name T1245
Test name
Test status
Simulation time 25857650 ps
CPU time 0.58 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 194660 kb
Host smart-0db08aee-d0de-4253-89f1-9e50310f927a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724503663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3724503663
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4071222670
Short name T1291
Test name
Test status
Simulation time 20991371 ps
CPU time 0.64 seconds
Started May 05 02:44:05 PM PDT 24
Finished May 05 02:44:06 PM PDT 24
Peak memory 196228 kb
Host smart-3039f9ec-622e-4358-aa23-6825927de90c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071222670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4071222670
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4293337109
Short name T1236
Test name
Test status
Simulation time 474315854 ps
CPU time 1.95 seconds
Started May 05 02:44:06 PM PDT 24
Finished May 05 02:44:08 PM PDT 24
Peak memory 200360 kb
Host smart-d326a276-4e40-4217-a707-a08b1402d9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293337109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4293337109
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.444239260
Short name T91
Test name
Test status
Simulation time 37218097 ps
CPU time 1.04 seconds
Started May 05 02:44:08 PM PDT 24
Finished May 05 02:44:09 PM PDT 24
Peak memory 199336 kb
Host smart-0c475c92-87a2-4f1a-a609-2e7e4260459e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444239260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.444239260
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2387181171
Short name T1208
Test name
Test status
Simulation time 50349795 ps
CPU time 0.79 seconds
Started May 05 02:44:09 PM PDT 24
Finished May 05 02:44:11 PM PDT 24
Peak memory 200160 kb
Host smart-e7d1aaa8-20c5-4aa6-8ecf-120b9832966a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387181171 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2387181171
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4201504236
Short name T1267
Test name
Test status
Simulation time 140062467 ps
CPU time 0.62 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 195800 kb
Host smart-45bea322-1402-4bb3-b831-cea0753458b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201504236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4201504236
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.961673464
Short name T1264
Test name
Test status
Simulation time 14308004 ps
CPU time 0.58 seconds
Started May 05 02:44:07 PM PDT 24
Finished May 05 02:44:08 PM PDT 24
Peak memory 194632 kb
Host smart-0f9aea1b-8741-41a1-bd69-d56cd91fb97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961673464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.961673464
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.117048144
Short name T76
Test name
Test status
Simulation time 38688401 ps
CPU time 0.74 seconds
Started May 05 02:44:15 PM PDT 24
Finished May 05 02:44:17 PM PDT 24
Peak memory 196120 kb
Host smart-0d302a50-a387-4b56-b0c6-87c658331d23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117048144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.117048144
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3982667038
Short name T1210
Test name
Test status
Simulation time 170348637 ps
CPU time 1.69 seconds
Started May 05 02:44:10 PM PDT 24
Finished May 05 02:44:12 PM PDT 24
Peak memory 200280 kb
Host smart-3f41106a-ab27-4bbd-8234-a48f66494da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982667038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3982667038
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1638082735
Short name T1280
Test name
Test status
Simulation time 267455162 ps
CPU time 0.92 seconds
Started May 05 02:44:10 PM PDT 24
Finished May 05 02:44:12 PM PDT 24
Peak memory 199404 kb
Host smart-5d8f4b6b-ef22-4e2d-8db6-61b62b626b11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638082735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1638082735
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1394351847
Short name T1206
Test name
Test status
Simulation time 50258900 ps
CPU time 0.8 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 200348 kb
Host smart-7e04cbed-de9f-4146-a262-b72176871ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394351847 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1394351847
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1554442365
Short name T77
Test name
Test status
Simulation time 42449196 ps
CPU time 0.57 seconds
Started May 05 02:44:21 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 195684 kb
Host smart-8280316b-dfe9-4a29-a785-8ce4f62f7a52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554442365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1554442365
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2551993114
Short name T1234
Test name
Test status
Simulation time 15137700 ps
CPU time 0.57 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 194644 kb
Host smart-cd2e0702-3846-4a65-b78d-78aca6bc4d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551993114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2551993114
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.386614777
Short name T1256
Test name
Test status
Simulation time 25302904 ps
CPU time 0.69 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 196224 kb
Host smart-15329b6c-f55e-416c-8f14-98c8f69c1606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386614777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.386614777
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1841822194
Short name T1276
Test name
Test status
Simulation time 22866755 ps
CPU time 1.01 seconds
Started May 05 02:44:10 PM PDT 24
Finished May 05 02:44:11 PM PDT 24
Peak memory 200164 kb
Host smart-043ac0dc-319e-486f-9663-be4b22b7a389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841822194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1841822194
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1490620330
Short name T89
Test name
Test status
Simulation time 98709083 ps
CPU time 1.29 seconds
Started May 05 02:44:04 PM PDT 24
Finished May 05 02:44:06 PM PDT 24
Peak memory 199632 kb
Host smart-839d4b78-dcbf-4c56-a090-113ae0c2e4a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490620330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1490620330
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1294817226
Short name T1198
Test name
Test status
Simulation time 17382801 ps
CPU time 0.67 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 198008 kb
Host smart-4285797b-56d4-471e-8d1b-1bc7aee3caa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294817226 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1294817226
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2089782015
Short name T1312
Test name
Test status
Simulation time 51047778 ps
CPU time 0.59 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:18 PM PDT 24
Peak memory 195788 kb
Host smart-6c827fcc-168c-41bd-b332-c696eafc651f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089782015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2089782015
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4060316753
Short name T1292
Test name
Test status
Simulation time 23512277 ps
CPU time 0.58 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:18 PM PDT 24
Peak memory 194676 kb
Host smart-f9b9585a-1579-4a3d-8a54-d531d1a4f4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060316753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4060316753
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3065964050
Short name T1237
Test name
Test status
Simulation time 24419871 ps
CPU time 0.64 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:18 PM PDT 24
Peak memory 195916 kb
Host smart-01db220f-32d8-479d-b00b-edb3536778a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065964050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3065964050
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.623186266
Short name T1262
Test name
Test status
Simulation time 146110580 ps
CPU time 1.85 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 200332 kb
Host smart-5c4a5152-c3b4-43a7-88ce-ca8ac33baa7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623186266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.623186266
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1604029534
Short name T90
Test name
Test status
Simulation time 822534910 ps
CPU time 1.3 seconds
Started May 05 02:44:17 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 199560 kb
Host smart-9b7ad13a-8ae1-409c-bec9-b2dad7232e60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604029534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1604029534
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3093373768
Short name T1278
Test name
Test status
Simulation time 19920197 ps
CPU time 0.86 seconds
Started May 05 02:44:19 PM PDT 24
Finished May 05 02:44:21 PM PDT 24
Peak memory 200136 kb
Host smart-2274b9bc-ed69-4613-9b17-ee9e599d2c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093373768 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3093373768
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1479665587
Short name T1274
Test name
Test status
Simulation time 54749996 ps
CPU time 0.6 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 195632 kb
Host smart-2ae0d788-73e5-4b1a-8e49-a26ec31fbc1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479665587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1479665587
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.927862587
Short name T1209
Test name
Test status
Simulation time 91818746 ps
CPU time 0.56 seconds
Started May 05 02:44:21 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 194664 kb
Host smart-c646e8cc-6c9d-46e7-9333-0ee361e91963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927862587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.927862587
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2433611207
Short name T1306
Test name
Test status
Simulation time 35127105 ps
CPU time 0.62 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:19 PM PDT 24
Peak memory 195820 kb
Host smart-1d0a6d66-6375-43e3-9ecf-68e48dd172f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433611207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2433611207
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2794388299
Short name T1202
Test name
Test status
Simulation time 372113340 ps
CPU time 1.13 seconds
Started May 05 02:44:20 PM PDT 24
Finished May 05 02:44:22 PM PDT 24
Peak memory 200320 kb
Host smart-1387d1c4-d9a8-4a5b-9c9b-87d062bfcacc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794388299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2794388299
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3272715088
Short name T92
Test name
Test status
Simulation time 258038737 ps
CPU time 1.27 seconds
Started May 05 02:44:18 PM PDT 24
Finished May 05 02:44:20 PM PDT 24
Peak memory 199680 kb
Host smart-6170fec9-b5c1-4f0b-b5d3-9f39600a28fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272715088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3272715088
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.287967072
Short name T1151
Test name
Test status
Simulation time 82540955172 ps
CPU time 16.36 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:30:10 PM PDT 24
Peak memory 200320 kb
Host smart-cd630a13-46f1-409f-869b-1dd9076a6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287967072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.287967072
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.956367634
Short name T819
Test name
Test status
Simulation time 13970476180 ps
CPU time 22.17 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:30:15 PM PDT 24
Peak memory 200352 kb
Host smart-499385a2-ca73-49ac-a4a7-dd2914a29ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956367634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.956367634
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3275028421
Short name T540
Test name
Test status
Simulation time 34034047896 ps
CPU time 17.62 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:30:11 PM PDT 24
Peak memory 200384 kb
Host smart-b3a0113f-2961-4824-9ce7-710cbfd29f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275028421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3275028421
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2059976202
Short name T1024
Test name
Test status
Simulation time 33119168352 ps
CPU time 49.56 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:30:43 PM PDT 24
Peak memory 200368 kb
Host smart-5d24b6ca-f19e-4afd-ac6d-b04e9db2627f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059976202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2059976202
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3656321002
Short name T1060
Test name
Test status
Simulation time 198437019295 ps
CPU time 131.71 seconds
Started May 05 01:30:00 PM PDT 24
Finished May 05 01:32:12 PM PDT 24
Peak memory 200352 kb
Host smart-6be919e4-55ce-49fa-b753-3a86127ac9da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656321002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3656321002
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2629802881
Short name T789
Test name
Test status
Simulation time 4659484064 ps
CPU time 5.69 seconds
Started May 05 01:29:52 PM PDT 24
Finished May 05 01:29:58 PM PDT 24
Peak memory 199416 kb
Host smart-164f9920-2e47-4a8a-b2af-ad0ba4d5b0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629802881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2629802881
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1551409245
Short name T613
Test name
Test status
Simulation time 30484996242 ps
CPU time 26.16 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:30:19 PM PDT 24
Peak memory 200352 kb
Host smart-115894a0-d972-456c-9249-21ce980c56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551409245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1551409245
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.4231463565
Short name T703
Test name
Test status
Simulation time 19903741930 ps
CPU time 116.15 seconds
Started May 05 01:29:52 PM PDT 24
Finished May 05 01:31:48 PM PDT 24
Peak memory 200376 kb
Host smart-ac075978-a304-453b-86b0-4c4d3bf03eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231463565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4231463565
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2571961504
Short name T985
Test name
Test status
Simulation time 7127288471 ps
CPU time 65.57 seconds
Started May 05 01:29:52 PM PDT 24
Finished May 05 01:30:58 PM PDT 24
Peak memory 198724 kb
Host smart-2a5e7b43-b96f-4cd8-a6d5-05db754dc934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571961504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2571961504
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2993008812
Short name T785
Test name
Test status
Simulation time 210470507478 ps
CPU time 42.6 seconds
Started May 05 01:29:54 PM PDT 24
Finished May 05 01:30:37 PM PDT 24
Peak memory 200392 kb
Host smart-4b9ec340-7ad6-4504-9b23-2b41f03b4717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993008812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2993008812
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2945274628
Short name T375
Test name
Test status
Simulation time 1670404809 ps
CPU time 2.03 seconds
Started May 05 01:29:51 PM PDT 24
Finished May 05 01:29:54 PM PDT 24
Peak memory 195988 kb
Host smart-dc9e0396-a089-4129-b7b8-a32b0732eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945274628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2945274628
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2423404077
Short name T354
Test name
Test status
Simulation time 856601657 ps
CPU time 2.36 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:29:56 PM PDT 24
Peak memory 200192 kb
Host smart-ecd566c2-c141-40f2-803d-64b9aac2f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423404077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2423404077
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1952813134
Short name T673
Test name
Test status
Simulation time 233058520182 ps
CPU time 406.06 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:36:47 PM PDT 24
Peak memory 200224 kb
Host smart-13619679-3534-40e7-8732-cc1148b614a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952813134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1952813134
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3723500089
Short name T652
Test name
Test status
Simulation time 211793592826 ps
CPU time 487.73 seconds
Started May 05 01:29:59 PM PDT 24
Finished May 05 01:38:07 PM PDT 24
Peak memory 211892 kb
Host smart-441c7861-d74a-44d5-b841-7081eb56fee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723500089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3723500089
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.4046625990
Short name T855
Test name
Test status
Simulation time 1029596703 ps
CPU time 1.78 seconds
Started May 05 01:29:53 PM PDT 24
Finished May 05 01:29:55 PM PDT 24
Peak memory 198868 kb
Host smart-95f67d85-817f-4c90-83c9-175a153b11f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046625990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4046625990
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.220489776
Short name T877
Test name
Test status
Simulation time 33340798460 ps
CPU time 46.12 seconds
Started May 05 01:29:51 PM PDT 24
Finished May 05 01:30:38 PM PDT 24
Peak memory 200340 kb
Host smart-554eee37-57e5-461f-9a8c-cd2a66f73ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220489776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.220489776
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3263810001
Short name T748
Test name
Test status
Simulation time 19501623 ps
CPU time 0.58 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:30:02 PM PDT 24
Peak memory 195768 kb
Host smart-607666a3-c4dd-446e-a862-f2580552e8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263810001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3263810001
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3521858319
Short name T1157
Test name
Test status
Simulation time 127483561757 ps
CPU time 236.65 seconds
Started May 05 01:29:57 PM PDT 24
Finished May 05 01:33:54 PM PDT 24
Peak memory 200308 kb
Host smart-bf5614e2-8955-4176-a632-a1843069f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521858319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3521858319
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1273530794
Short name T816
Test name
Test status
Simulation time 19357630276 ps
CPU time 34.72 seconds
Started May 05 01:29:58 PM PDT 24
Finished May 05 01:30:33 PM PDT 24
Peak memory 200352 kb
Host smart-24c74f3a-66c3-468f-8466-3014c68ed767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273530794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1273530794
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.965068339
Short name T939
Test name
Test status
Simulation time 108763357800 ps
CPU time 141.09 seconds
Started May 05 01:29:57 PM PDT 24
Finished May 05 01:32:19 PM PDT 24
Peak memory 200412 kb
Host smart-2767917b-32ce-4438-91c6-f89109c003ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965068339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.965068339
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.62882009
Short name T510
Test name
Test status
Simulation time 29858595221 ps
CPU time 12.57 seconds
Started May 05 01:29:58 PM PDT 24
Finished May 05 01:30:11 PM PDT 24
Peak memory 199908 kb
Host smart-e234f041-23a6-409a-a6a3-083006458434
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62882009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.62882009
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3301221053
Short name T1003
Test name
Test status
Simulation time 70436225708 ps
CPU time 120.24 seconds
Started May 05 01:30:00 PM PDT 24
Finished May 05 01:32:01 PM PDT 24
Peak memory 200576 kb
Host smart-b2816f50-c891-450c-9359-fd0796cbf5d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301221053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3301221053
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2735474780
Short name T515
Test name
Test status
Simulation time 8310672877 ps
CPU time 31.66 seconds
Started May 05 01:30:04 PM PDT 24
Finished May 05 01:30:36 PM PDT 24
Peak memory 200184 kb
Host smart-8e38ae82-ac76-4098-a7ab-d2c8b4782c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735474780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2735474780
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1827266329
Short name T859
Test name
Test status
Simulation time 38652720764 ps
CPU time 25.85 seconds
Started May 05 01:29:59 PM PDT 24
Finished May 05 01:30:25 PM PDT 24
Peak memory 200464 kb
Host smart-7b565d90-2920-4838-a93f-f226705f6835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827266329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1827266329
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.59831050
Short name T688
Test name
Test status
Simulation time 33440569150 ps
CPU time 206.32 seconds
Started May 05 01:30:02 PM PDT 24
Finished May 05 01:33:28 PM PDT 24
Peak memory 200360 kb
Host smart-72b96557-cc0a-4e09-9166-65e3776314f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59831050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.59831050
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3439304733
Short name T399
Test name
Test status
Simulation time 6163354610 ps
CPU time 13.22 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:30:14 PM PDT 24
Peak memory 199472 kb
Host smart-4797d3f2-9a52-479a-800c-3cca06fd4601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439304733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3439304733
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.171465536
Short name T1078
Test name
Test status
Simulation time 109754749606 ps
CPU time 142.48 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:32:24 PM PDT 24
Peak memory 200288 kb
Host smart-29b63518-561c-4638-99ad-741f7e34dc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171465536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.171465536
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.511766686
Short name T674
Test name
Test status
Simulation time 5983327825 ps
CPU time 5.42 seconds
Started May 05 01:29:58 PM PDT 24
Finished May 05 01:30:04 PM PDT 24
Peak memory 196384 kb
Host smart-ffc8b779-84f9-44a4-8b8d-e81d686c3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511766686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.511766686
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1551463218
Short name T22
Test name
Test status
Simulation time 107149371 ps
CPU time 0.78 seconds
Started May 05 01:30:03 PM PDT 24
Finished May 05 01:30:04 PM PDT 24
Peak memory 218552 kb
Host smart-39a90d9e-c034-4c69-89ef-a27b8a8b4516
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551463218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1551463218
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2369603362
Short name T820
Test name
Test status
Simulation time 5466479634 ps
CPU time 13.39 seconds
Started May 05 01:29:59 PM PDT 24
Finished May 05 01:30:12 PM PDT 24
Peak memory 200124 kb
Host smart-607c3910-2d90-453c-b5d5-0c293992610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369603362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2369603362
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1686250368
Short name T1079
Test name
Test status
Simulation time 135300697872 ps
CPU time 245.81 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:34:07 PM PDT 24
Peak memory 200308 kb
Host smart-c6fb8bfe-d8a6-41c7-b242-89e070d8637c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686250368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1686250368
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1195863197
Short name T315
Test name
Test status
Simulation time 30099181221 ps
CPU time 353.22 seconds
Started May 05 01:30:02 PM PDT 24
Finished May 05 01:35:56 PM PDT 24
Peak memory 216804 kb
Host smart-eb0cbeee-5fcd-44b4-b6e4-103d87ffb45f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195863197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1195863197
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2315125647
Short name T577
Test name
Test status
Simulation time 824480485 ps
CPU time 2.51 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:30:04 PM PDT 24
Peak memory 200240 kb
Host smart-49c50576-0166-479c-8760-e00ce77737cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315125647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2315125647
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3351879928
Short name T993
Test name
Test status
Simulation time 152593674082 ps
CPU time 152.32 seconds
Started May 05 01:29:57 PM PDT 24
Finished May 05 01:32:30 PM PDT 24
Peak memory 200300 kb
Host smart-22b93cf2-deea-476a-8e98-84a8a569262d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351879928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3351879928
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3566355300
Short name T900
Test name
Test status
Simulation time 33417657 ps
CPU time 0.55 seconds
Started May 05 01:31:04 PM PDT 24
Finished May 05 01:31:05 PM PDT 24
Peak memory 195740 kb
Host smart-1d2b9362-9e09-4fad-a272-b0260ddb6157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566355300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3566355300
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3152878060
Short name T169
Test name
Test status
Simulation time 305816771423 ps
CPU time 38.49 seconds
Started May 05 01:30:56 PM PDT 24
Finished May 05 01:31:35 PM PDT 24
Peak memory 200340 kb
Host smart-283fe9ae-085e-4622-859c-b7477f332de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152878060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3152878060
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3056275633
Short name T917
Test name
Test status
Simulation time 49973073839 ps
CPU time 42.42 seconds
Started May 05 01:30:57 PM PDT 24
Finished May 05 01:31:40 PM PDT 24
Peak memory 200324 kb
Host smart-a8246764-9525-4e4f-8d20-df436806b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056275633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3056275633
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3799899622
Short name T882
Test name
Test status
Simulation time 69343583222 ps
CPU time 36.97 seconds
Started May 05 01:30:56 PM PDT 24
Finished May 05 01:31:34 PM PDT 24
Peak memory 200376 kb
Host smart-4b0fff54-99b1-4065-b89c-3cac3cb737a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799899622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3799899622
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3043495081
Short name T317
Test name
Test status
Simulation time 21382222770 ps
CPU time 10.46 seconds
Started May 05 01:30:58 PM PDT 24
Finished May 05 01:31:09 PM PDT 24
Peak memory 200396 kb
Host smart-24bfca9d-b16e-418f-a6cd-56e20b1eb39b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043495081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3043495081
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.35751054
Short name T1141
Test name
Test status
Simulation time 304691419799 ps
CPU time 408.67 seconds
Started May 05 01:31:00 PM PDT 24
Finished May 05 01:37:49 PM PDT 24
Peak memory 200404 kb
Host smart-1f6c1de0-be18-4c7e-8aee-e7e1ca325d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35751054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.35751054
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2238716142
Short name T1139
Test name
Test status
Simulation time 1624614050 ps
CPU time 2.14 seconds
Started May 05 01:31:02 PM PDT 24
Finished May 05 01:31:04 PM PDT 24
Peak memory 197372 kb
Host smart-52e0354f-ec55-47e4-ba6a-853716171148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238716142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2238716142
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2818352569
Short name T1116
Test name
Test status
Simulation time 116558031532 ps
CPU time 46.34 seconds
Started May 05 01:30:57 PM PDT 24
Finished May 05 01:31:43 PM PDT 24
Peak memory 198876 kb
Host smart-c816675a-7313-4b3a-aa96-61fc6ae87315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818352569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2818352569
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4200561703
Short name T628
Test name
Test status
Simulation time 17863659331 ps
CPU time 627.99 seconds
Started May 05 01:31:00 PM PDT 24
Finished May 05 01:41:29 PM PDT 24
Peak memory 200392 kb
Host smart-1506c301-408d-43a6-a0ed-be01bc493d65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200561703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4200561703
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.978383231
Short name T346
Test name
Test status
Simulation time 5248624194 ps
CPU time 43.08 seconds
Started May 05 01:30:56 PM PDT 24
Finished May 05 01:31:39 PM PDT 24
Peak memory 199580 kb
Host smart-dcf333fb-87b9-4b96-842c-f2a74ca233c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978383231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.978383231
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2759187030
Short name T1051
Test name
Test status
Simulation time 27204967118 ps
CPU time 39.24 seconds
Started May 05 01:30:56 PM PDT 24
Finished May 05 01:31:36 PM PDT 24
Peak memory 200384 kb
Host smart-89d9c9a1-ff0c-4104-be93-b58821e7b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759187030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2759187030
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1114801814
Short name T348
Test name
Test status
Simulation time 724810643 ps
CPU time 0.86 seconds
Started May 05 01:30:57 PM PDT 24
Finished May 05 01:30:58 PM PDT 24
Peak memory 195752 kb
Host smart-4c451fd0-a86e-4b82-a84f-6b31879cdf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114801814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1114801814
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3767982359
Short name T735
Test name
Test status
Simulation time 504116955 ps
CPU time 2.3 seconds
Started May 05 01:30:51 PM PDT 24
Finished May 05 01:30:54 PM PDT 24
Peak memory 199120 kb
Host smart-ee928ac6-69f9-4e7e-9df0-4e85ab85b438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767982359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3767982359
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3549566753
Short name T690
Test name
Test status
Simulation time 275092130460 ps
CPU time 123.37 seconds
Started May 05 01:31:03 PM PDT 24
Finished May 05 01:33:07 PM PDT 24
Peak memory 200312 kb
Host smart-83a99e8c-e41b-4276-ac3c-2a8c05d6a3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549566753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3549566753
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.782801119
Short name T116
Test name
Test status
Simulation time 74006325220 ps
CPU time 852.3 seconds
Started May 05 01:31:01 PM PDT 24
Finished May 05 01:45:14 PM PDT 24
Peak memory 225196 kb
Host smart-18762bf6-d102-487a-b66c-af95d729ca37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782801119 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.782801119
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2195454062
Short name T448
Test name
Test status
Simulation time 2205355608 ps
CPU time 2.08 seconds
Started May 05 01:31:01 PM PDT 24
Finished May 05 01:31:03 PM PDT 24
Peak memory 199344 kb
Host smart-afaf6c41-9a68-4d29-802c-5fed61212f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195454062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2195454062
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2305022881
Short name T663
Test name
Test status
Simulation time 18489296687 ps
CPU time 17.17 seconds
Started May 05 01:30:54 PM PDT 24
Finished May 05 01:31:12 PM PDT 24
Peak memory 200400 kb
Host smart-00f4f842-7722-4cff-b529-b1fe8ab60587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305022881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2305022881
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2113084235
Short name T447
Test name
Test status
Simulation time 27212145657 ps
CPU time 36.9 seconds
Started May 05 01:37:21 PM PDT 24
Finished May 05 01:37:58 PM PDT 24
Peak memory 200304 kb
Host smart-9a9c4059-e612-4914-bbf4-fdb5c7e174b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113084235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2113084235
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3544251647
Short name T176
Test name
Test status
Simulation time 181972570857 ps
CPU time 74.02 seconds
Started May 05 01:37:28 PM PDT 24
Finished May 05 01:38:42 PM PDT 24
Peak memory 200204 kb
Host smart-d6d3dacd-78c7-4d00-a805-4c1073169f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544251647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3544251647
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3759043578
Short name T578
Test name
Test status
Simulation time 23808609235 ps
CPU time 66.92 seconds
Started May 05 01:37:28 PM PDT 24
Finished May 05 01:38:35 PM PDT 24
Peak memory 200252 kb
Host smart-ae248400-a757-46b8-99a8-255f97a0e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759043578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3759043578
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2317768444
Short name T1177
Test name
Test status
Simulation time 188848118719 ps
CPU time 155.31 seconds
Started May 05 01:37:27 PM PDT 24
Finished May 05 01:40:03 PM PDT 24
Peak memory 200392 kb
Host smart-9274b8de-1840-4b58-b1bb-d1a319f4d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317768444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2317768444
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2938369622
Short name T202
Test name
Test status
Simulation time 46916950478 ps
CPU time 20.87 seconds
Started May 05 01:37:25 PM PDT 24
Finished May 05 01:37:46 PM PDT 24
Peak memory 200340 kb
Host smart-82ec9676-292d-4bb6-a0b0-ad14492cd5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938369622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2938369622
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.481571615
Short name T189
Test name
Test status
Simulation time 97452761532 ps
CPU time 34.53 seconds
Started May 05 01:37:25 PM PDT 24
Finished May 05 01:38:00 PM PDT 24
Peak memory 200400 kb
Host smart-786edc8f-766e-41f4-8a58-c1a522fced0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481571615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.481571615
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2539611407
Short name T476
Test name
Test status
Simulation time 66313988507 ps
CPU time 53.11 seconds
Started May 05 01:37:32 PM PDT 24
Finished May 05 01:38:25 PM PDT 24
Peak memory 200396 kb
Host smart-49557df5-c64f-4c58-ad5e-fa0d571d6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539611407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2539611407
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.528983482
Short name T139
Test name
Test status
Simulation time 100550734602 ps
CPU time 159.57 seconds
Started May 05 01:37:30 PM PDT 24
Finished May 05 01:40:10 PM PDT 24
Peak memory 200360 kb
Host smart-89a93c1b-51fd-4251-a5a8-347ab3bb8a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528983482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.528983482
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1942926791
Short name T587
Test name
Test status
Simulation time 40699690 ps
CPU time 0.53 seconds
Started May 05 01:31:12 PM PDT 24
Finished May 05 01:31:13 PM PDT 24
Peak memory 195812 kb
Host smart-8baf2fa8-e13b-4f15-982d-4965d94114a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942926791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1942926791
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.80248673
Short name T773
Test name
Test status
Simulation time 103599907776 ps
CPU time 574.14 seconds
Started May 05 01:31:04 PM PDT 24
Finished May 05 01:40:39 PM PDT 24
Peak memory 200320 kb
Host smart-05dd4fa0-2156-44e3-a3c7-97e2b505a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80248673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.80248673
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.1926180962
Short name T98
Test name
Test status
Simulation time 12132657173 ps
CPU time 19.31 seconds
Started May 05 01:30:59 PM PDT 24
Finished May 05 01:31:19 PM PDT 24
Peak memory 197060 kb
Host smart-aa18df73-886e-446e-8b0c-5b12c258b348
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926180962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1926180962
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1612252053
Short name T903
Test name
Test status
Simulation time 190351597163 ps
CPU time 319.67 seconds
Started May 05 01:31:04 PM PDT 24
Finished May 05 01:36:24 PM PDT 24
Peak memory 200392 kb
Host smart-e11f5a34-8b4c-4015-a461-b8bbd3130a55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612252053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1612252053
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4154313905
Short name T841
Test name
Test status
Simulation time 6046822579 ps
CPU time 13.83 seconds
Started May 05 01:31:14 PM PDT 24
Finished May 05 01:31:28 PM PDT 24
Peak memory 198808 kb
Host smart-6e9a704d-c739-4dee-b7c5-af40c45b7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154313905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4154313905
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2844094155
Short name T568
Test name
Test status
Simulation time 137230045875 ps
CPU time 93.57 seconds
Started May 05 01:31:04 PM PDT 24
Finished May 05 01:32:38 PM PDT 24
Peak memory 208692 kb
Host smart-73b6b9b8-fd58-4744-a4bb-2ae410df604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844094155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2844094155
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2542110418
Short name T266
Test name
Test status
Simulation time 11629590792 ps
CPU time 309.62 seconds
Started May 05 01:31:05 PM PDT 24
Finished May 05 01:36:15 PM PDT 24
Peak memory 200336 kb
Host smart-1e3c8168-9693-4d0e-9aa0-c6599a949a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542110418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2542110418
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3142234173
Short name T947
Test name
Test status
Simulation time 6982893443 ps
CPU time 16.67 seconds
Started May 05 01:31:03 PM PDT 24
Finished May 05 01:31:20 PM PDT 24
Peak memory 198520 kb
Host smart-580f0698-a43f-4588-ae68-31c9a733394c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142234173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3142234173
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3141569615
Short name T1153
Test name
Test status
Simulation time 20994903083 ps
CPU time 34.55 seconds
Started May 05 01:31:02 PM PDT 24
Finished May 05 01:31:37 PM PDT 24
Peak memory 200280 kb
Host smart-701d1a79-d954-4506-9dbc-769959cb17ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141569615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3141569615
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2279201821
Short name T306
Test name
Test status
Simulation time 4198058380 ps
CPU time 7.29 seconds
Started May 05 01:31:00 PM PDT 24
Finished May 05 01:31:08 PM PDT 24
Peak memory 196388 kb
Host smart-fc8378e7-66b7-4092-a11f-8da9c20c0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279201821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2279201821
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2677804103
Short name T980
Test name
Test status
Simulation time 858371533 ps
CPU time 1.79 seconds
Started May 05 01:31:00 PM PDT 24
Finished May 05 01:31:03 PM PDT 24
Peak memory 199644 kb
Host smart-1cdb7567-4af8-4000-a057-5e0f29f6f8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677804103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2677804103
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1169948813
Short name T893
Test name
Test status
Simulation time 114294336111 ps
CPU time 227.97 seconds
Started May 05 01:31:11 PM PDT 24
Finished May 05 01:34:59 PM PDT 24
Peak memory 200420 kb
Host smart-1811a333-daa1-4380-bf01-0eefdb360d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169948813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1169948813
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.249406818
Short name T1162
Test name
Test status
Simulation time 345214140180 ps
CPU time 745.6 seconds
Started May 05 01:31:12 PM PDT 24
Finished May 05 01:43:38 PM PDT 24
Peak memory 225172 kb
Host smart-aba58ca0-4a63-4044-964e-0ff5262a0ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249406818 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.249406818
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.446128367
Short name T359
Test name
Test status
Simulation time 1611952705 ps
CPU time 1.86 seconds
Started May 05 01:31:03 PM PDT 24
Finished May 05 01:31:05 PM PDT 24
Peak memory 198636 kb
Host smart-a6444443-5b22-4cef-8d5a-700b59ecb22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446128367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.446128367
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.220643180
Short name T400
Test name
Test status
Simulation time 52226875523 ps
CPU time 84.74 seconds
Started May 05 01:31:02 PM PDT 24
Finished May 05 01:32:27 PM PDT 24
Peak memory 200372 kb
Host smart-c8d5bdcd-6ce8-4453-8add-859c1635644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220643180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.220643180
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4069900424
Short name T394
Test name
Test status
Simulation time 13173532382 ps
CPU time 19.43 seconds
Started May 05 01:37:30 PM PDT 24
Finished May 05 01:37:49 PM PDT 24
Peak memory 200376 kb
Host smart-755acb34-7766-4f74-9cea-0049ade39d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069900424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4069900424
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1867018947
Short name T616
Test name
Test status
Simulation time 224226446127 ps
CPU time 114.72 seconds
Started May 05 01:37:35 PM PDT 24
Finished May 05 01:39:30 PM PDT 24
Peak memory 200340 kb
Host smart-9b20f89a-dbbd-426a-96e2-c373c6718d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867018947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1867018947
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1959532832
Short name T325
Test name
Test status
Simulation time 30184970506 ps
CPU time 39.33 seconds
Started May 05 01:37:37 PM PDT 24
Finished May 05 01:38:17 PM PDT 24
Peak memory 200400 kb
Host smart-dc6392f5-5b05-4a8b-9f9f-ad177649013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959532832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1959532832
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.44255404
Short name T863
Test name
Test status
Simulation time 11044202808 ps
CPU time 25.26 seconds
Started May 05 01:37:36 PM PDT 24
Finished May 05 01:38:01 PM PDT 24
Peak memory 200372 kb
Host smart-a9d21e3f-d000-4f62-93f6-ffb3c4fa4086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44255404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.44255404
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3242374046
Short name T1090
Test name
Test status
Simulation time 72443476700 ps
CPU time 19.89 seconds
Started May 05 01:37:35 PM PDT 24
Finished May 05 01:37:55 PM PDT 24
Peak memory 200396 kb
Host smart-3af8fed3-809a-4e4b-82c1-b1a831939aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242374046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3242374046
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1819029504
Short name T693
Test name
Test status
Simulation time 218465737143 ps
CPU time 115.93 seconds
Started May 05 01:37:36 PM PDT 24
Finished May 05 01:39:32 PM PDT 24
Peak memory 200356 kb
Host smart-4d35d62e-9e48-416e-b4c2-eed6affa0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819029504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1819029504
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1208679094
Short name T184
Test name
Test status
Simulation time 25251575229 ps
CPU time 41.79 seconds
Started May 05 01:37:35 PM PDT 24
Finished May 05 01:38:17 PM PDT 24
Peak memory 200352 kb
Host smart-49720297-9038-48ab-8eb3-8a972e2cea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208679094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1208679094
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3878818370
Short name T327
Test name
Test status
Simulation time 215957066905 ps
CPU time 186.16 seconds
Started May 05 01:37:42 PM PDT 24
Finished May 05 01:40:49 PM PDT 24
Peak memory 200280 kb
Host smart-004f975f-6e58-403d-9859-f429583810f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878818370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3878818370
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1070849783
Short name T449
Test name
Test status
Simulation time 16679290 ps
CPU time 0.55 seconds
Started May 05 01:31:23 PM PDT 24
Finished May 05 01:31:24 PM PDT 24
Peak memory 195708 kb
Host smart-d34cafbb-c044-4eee-9a70-26ca397ae0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070849783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1070849783
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3948752725
Short name T694
Test name
Test status
Simulation time 59505338278 ps
CPU time 12.41 seconds
Started May 05 01:31:13 PM PDT 24
Finished May 05 01:31:26 PM PDT 24
Peak memory 200368 kb
Host smart-416ba606-9e76-492c-bc2d-2ec52aa029d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948752725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3948752725
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1921773689
Short name T836
Test name
Test status
Simulation time 30549363142 ps
CPU time 45.74 seconds
Started May 05 01:31:10 PM PDT 24
Finished May 05 01:31:56 PM PDT 24
Peak memory 200340 kb
Host smart-c48bbff7-600b-493b-b4e1-a504d3b0d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921773689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1921773689
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2598483653
Short name T114
Test name
Test status
Simulation time 52373447145 ps
CPU time 41.18 seconds
Started May 05 01:31:13 PM PDT 24
Finished May 05 01:31:54 PM PDT 24
Peak memory 200340 kb
Host smart-2bd0462a-5854-4d87-a299-6e09ba24f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598483653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2598483653
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3883528758
Short name T39
Test name
Test status
Simulation time 12500782556 ps
CPU time 6.17 seconds
Started May 05 01:31:13 PM PDT 24
Finished May 05 01:31:19 PM PDT 24
Peak memory 196508 kb
Host smart-9d26f7ed-4a6f-4b49-bd87-a056792b211c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883528758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3883528758
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1206856076
Short name T873
Test name
Test status
Simulation time 147040058430 ps
CPU time 1032.86 seconds
Started May 05 01:31:16 PM PDT 24
Finished May 05 01:48:30 PM PDT 24
Peak memory 200324 kb
Host smart-d439f3f3-656f-444d-afba-be4a762ad93a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206856076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1206856076
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1956395719
Short name T335
Test name
Test status
Simulation time 5864257927 ps
CPU time 4.95 seconds
Started May 05 01:31:16 PM PDT 24
Finished May 05 01:31:21 PM PDT 24
Peak memory 199956 kb
Host smart-6c5d1206-d4b8-4afa-9a7e-6be8a9806235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956395719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1956395719
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2726037898
Short name T655
Test name
Test status
Simulation time 690749197 ps
CPU time 0.88 seconds
Started May 05 01:31:12 PM PDT 24
Finished May 05 01:31:13 PM PDT 24
Peak memory 194900 kb
Host smart-926fa8af-d50f-4f9b-b350-7404cccbee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726037898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2726037898
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.317474751
Short name T523
Test name
Test status
Simulation time 17450410520 ps
CPU time 177.39 seconds
Started May 05 01:31:20 PM PDT 24
Finished May 05 01:34:18 PM PDT 24
Peak memory 200296 kb
Host smart-b10cccfe-c07c-4f49-94ea-e9ce0523006c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317474751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.317474751
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3823621904
Short name T638
Test name
Test status
Simulation time 7341766623 ps
CPU time 5.69 seconds
Started May 05 01:31:12 PM PDT 24
Finished May 05 01:31:18 PM PDT 24
Peak memory 199512 kb
Host smart-895b1252-65aa-40a5-87ee-2f9ef1676818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823621904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3823621904
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1147126777
Short name T1057
Test name
Test status
Simulation time 71105723551 ps
CPU time 63.77 seconds
Started May 05 01:31:13 PM PDT 24
Finished May 05 01:32:17 PM PDT 24
Peak memory 200268 kb
Host smart-90a3fee0-4de9-4b2b-81ca-f478df418d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147126777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1147126777
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3435016863
Short name T289
Test name
Test status
Simulation time 2684610388 ps
CPU time 1.61 seconds
Started May 05 01:31:11 PM PDT 24
Finished May 05 01:31:13 PM PDT 24
Peak memory 196108 kb
Host smart-05d03d38-ffc4-4050-96f1-6b624b223e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435016863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3435016863
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1578612806
Short name T1120
Test name
Test status
Simulation time 101027671 ps
CPU time 0.85 seconds
Started May 05 01:31:06 PM PDT 24
Finished May 05 01:31:08 PM PDT 24
Peak memory 197144 kb
Host smart-9b9e4483-7dbe-4487-a475-396a6a1d5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578612806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1578612806
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3519751656
Short name T1054
Test name
Test status
Simulation time 812443368488 ps
CPU time 833.32 seconds
Started May 05 01:31:21 PM PDT 24
Finished May 05 01:45:14 PM PDT 24
Peak memory 200412 kb
Host smart-047f5d52-74e8-47dc-b097-336b40d86700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519751656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3519751656
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1634436172
Short name T181
Test name
Test status
Simulation time 182363760685 ps
CPU time 772.74 seconds
Started May 05 01:31:17 PM PDT 24
Finished May 05 01:44:10 PM PDT 24
Peak memory 216868 kb
Host smart-3145082a-44f7-4486-b786-ca99a4d571fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634436172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1634436172
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3745924292
Short name T945
Test name
Test status
Simulation time 1630788566 ps
CPU time 1.86 seconds
Started May 05 01:31:15 PM PDT 24
Finished May 05 01:31:17 PM PDT 24
Peak memory 199460 kb
Host smart-e2d82654-7765-408e-91ee-b247099e978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745924292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3745924292
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.560422020
Short name T507
Test name
Test status
Simulation time 62172415928 ps
CPU time 107.96 seconds
Started May 05 01:31:04 PM PDT 24
Finished May 05 01:32:52 PM PDT 24
Peak memory 200360 kb
Host smart-cd9e523d-c47f-4571-903e-e6abe64d8696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560422020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.560422020
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.807639503
Short name T909
Test name
Test status
Simulation time 35651094386 ps
CPU time 15.23 seconds
Started May 05 01:37:41 PM PDT 24
Finished May 05 01:37:56 PM PDT 24
Peak memory 200320 kb
Host smart-8d0198ba-89ee-479a-b4eb-ad473cc2ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807639503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.807639503
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.105629594
Short name T225
Test name
Test status
Simulation time 68798773797 ps
CPU time 154.64 seconds
Started May 05 01:37:43 PM PDT 24
Finished May 05 01:40:18 PM PDT 24
Peak memory 200340 kb
Host smart-e4b5a746-bb14-4640-a573-4869c72cbcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105629594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.105629594
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2302188480
Short name T960
Test name
Test status
Simulation time 29726641897 ps
CPU time 13.01 seconds
Started May 05 01:37:40 PM PDT 24
Finished May 05 01:37:53 PM PDT 24
Peak memory 200220 kb
Host smart-24399f83-fd5a-47ef-81b1-f85a21d62bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302188480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2302188480
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3994985326
Short name T124
Test name
Test status
Simulation time 64342184037 ps
CPU time 50.86 seconds
Started May 05 01:37:42 PM PDT 24
Finished May 05 01:38:33 PM PDT 24
Peak memory 200332 kb
Host smart-86743f1a-dc07-4d9f-aae7-0d1363af9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994985326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3994985326
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.923145173
Short name T750
Test name
Test status
Simulation time 25817298744 ps
CPU time 27.1 seconds
Started May 05 01:37:41 PM PDT 24
Finished May 05 01:38:08 PM PDT 24
Peak memory 200400 kb
Host smart-36c6dbde-f247-4aff-9c28-54bf08b59248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923145173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.923145173
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2114760417
Short name T728
Test name
Test status
Simulation time 69100360820 ps
CPU time 113.68 seconds
Started May 05 01:37:46 PM PDT 24
Finished May 05 01:39:40 PM PDT 24
Peak memory 200332 kb
Host smart-ad056569-3177-433c-9795-2a6e61cc952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114760417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2114760417
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2836571219
Short name T203
Test name
Test status
Simulation time 119822406351 ps
CPU time 19.9 seconds
Started May 05 01:37:48 PM PDT 24
Finished May 05 01:38:08 PM PDT 24
Peak memory 200352 kb
Host smart-111e73a9-62d6-46a4-a249-eb35cadb8242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836571219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2836571219
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1403371537
Short name T851
Test name
Test status
Simulation time 171791217955 ps
CPU time 79.92 seconds
Started May 05 01:37:46 PM PDT 24
Finished May 05 01:39:06 PM PDT 24
Peak memory 200300 kb
Host smart-bb852e5e-33d9-4869-8add-ab48f438b1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403371537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1403371537
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3558728981
Short name T666
Test name
Test status
Simulation time 19354328539 ps
CPU time 9.75 seconds
Started May 05 01:37:47 PM PDT 24
Finished May 05 01:37:57 PM PDT 24
Peak memory 200132 kb
Host smart-35569515-6334-47fc-a6ef-1a30fe1853d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558728981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3558728981
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2668985017
Short name T1146
Test name
Test status
Simulation time 38228978597 ps
CPU time 31.14 seconds
Started May 05 01:37:47 PM PDT 24
Finished May 05 01:38:19 PM PDT 24
Peak memory 200548 kb
Host smart-e88211e9-3c10-4117-b93a-ad1d2f2c99dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668985017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2668985017
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3776155259
Short name T475
Test name
Test status
Simulation time 43585271 ps
CPU time 0.52 seconds
Started May 05 01:31:24 PM PDT 24
Finished May 05 01:31:25 PM PDT 24
Peak memory 195772 kb
Host smart-31c01387-d970-45ee-afa5-c41d5a8b16be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776155259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3776155259
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.4124572447
Short name T550
Test name
Test status
Simulation time 136349810318 ps
CPU time 30.47 seconds
Started May 05 01:31:21 PM PDT 24
Finished May 05 01:31:52 PM PDT 24
Peak memory 200416 kb
Host smart-d1f98520-b403-44fd-8ab0-1bdcb39761ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124572447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.4124572447
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.222535259
Short name T972
Test name
Test status
Simulation time 9221618390 ps
CPU time 14.73 seconds
Started May 05 01:31:23 PM PDT 24
Finished May 05 01:31:38 PM PDT 24
Peak memory 200300 kb
Host smart-24e7b591-ad35-4653-b1be-8e91342188c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222535259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.222535259
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3994685194
Short name T585
Test name
Test status
Simulation time 194305387037 ps
CPU time 73.35 seconds
Started May 05 01:31:22 PM PDT 24
Finished May 05 01:32:35 PM PDT 24
Peak memory 200384 kb
Host smart-eb972721-7579-4289-a65d-b35f971f50d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994685194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3994685194
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3862299529
Short name T1145
Test name
Test status
Simulation time 278978474015 ps
CPU time 223.01 seconds
Started May 05 01:31:21 PM PDT 24
Finished May 05 01:35:04 PM PDT 24
Peak memory 198500 kb
Host smart-b49730e1-6c77-4f87-a652-244746a1ec2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862299529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3862299529
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3296659494
Short name T692
Test name
Test status
Simulation time 79169516820 ps
CPU time 554.94 seconds
Started May 05 01:31:26 PM PDT 24
Finished May 05 01:40:41 PM PDT 24
Peak memory 200328 kb
Host smart-85a146d0-6f58-47ee-b7f1-fb69be5f3166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296659494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3296659494
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2024686280
Short name T1138
Test name
Test status
Simulation time 988651296 ps
CPU time 2.33 seconds
Started May 05 01:31:26 PM PDT 24
Finished May 05 01:31:28 PM PDT 24
Peak memory 196420 kb
Host smart-e86937da-0a7d-4937-8ec9-9835e13fb086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024686280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2024686280
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.271798869
Short name T336
Test name
Test status
Simulation time 28067249490 ps
CPU time 45.17 seconds
Started May 05 01:31:22 PM PDT 24
Finished May 05 01:32:08 PM PDT 24
Peak memory 198756 kb
Host smart-924f5a16-4eb7-4c41-b88f-bf2a267215bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271798869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.271798869
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.411102971
Short name T1159
Test name
Test status
Simulation time 5945501949 ps
CPU time 305.76 seconds
Started May 05 01:31:25 PM PDT 24
Finished May 05 01:36:32 PM PDT 24
Peak memory 200392 kb
Host smart-3cdadea8-d7de-4541-a1d1-588eeeea44f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411102971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.411102971
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3133674385
Short name T948
Test name
Test status
Simulation time 5164742988 ps
CPU time 11.33 seconds
Started May 05 01:31:23 PM PDT 24
Finished May 05 01:31:34 PM PDT 24
Peak memory 199188 kb
Host smart-6fc5ea7a-bab7-430e-98fa-4c06cd3a1de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133674385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3133674385
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3384544821
Short name T3
Test name
Test status
Simulation time 77814800390 ps
CPU time 25.78 seconds
Started May 05 01:31:22 PM PDT 24
Finished May 05 01:31:48 PM PDT 24
Peak memory 200264 kb
Host smart-34f20de2-0bae-42eb-84c9-b6f9ada3b813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384544821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3384544821
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3497026042
Short name T43
Test name
Test status
Simulation time 2616608345 ps
CPU time 5.2 seconds
Started May 05 01:31:22 PM PDT 24
Finished May 05 01:31:28 PM PDT 24
Peak memory 196076 kb
Host smart-805d5719-9ce8-45e9-8423-91e3d8bc4a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497026042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3497026042
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3862945158
Short name T769
Test name
Test status
Simulation time 5995744432 ps
CPU time 20.46 seconds
Started May 05 01:31:21 PM PDT 24
Finished May 05 01:31:42 PM PDT 24
Peak memory 199468 kb
Host smart-316d224c-39d2-4fc5-82de-3e0d2697ee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862945158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3862945158
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.866625689
Short name T1124
Test name
Test status
Simulation time 880264394029 ps
CPU time 374.09 seconds
Started May 05 01:31:28 PM PDT 24
Finished May 05 01:37:42 PM PDT 24
Peak memory 200340 kb
Host smart-1b19ed73-931f-46c3-b60f-e1ecec9832af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866625689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.866625689
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2259895444
Short name T519
Test name
Test status
Simulation time 72398890026 ps
CPU time 856.44 seconds
Started May 05 01:31:26 PM PDT 24
Finished May 05 01:45:43 PM PDT 24
Peak memory 216812 kb
Host smart-2de2f824-b867-43db-be61-41bedff2153e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259895444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2259895444
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1913934347
Short name T763
Test name
Test status
Simulation time 1076631996 ps
CPU time 3.49 seconds
Started May 05 01:31:23 PM PDT 24
Finished May 05 01:31:26 PM PDT 24
Peak memory 198836 kb
Host smart-cf58dcd7-45c4-429a-95ef-65d257367572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913934347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1913934347
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1350924903
Short name T644
Test name
Test status
Simulation time 25307078340 ps
CPU time 49.1 seconds
Started May 05 01:31:20 PM PDT 24
Finished May 05 01:32:09 PM PDT 24
Peak memory 200372 kb
Host smart-1a4b475b-b1f3-4d14-bb18-ac735c490554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350924903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1350924903
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1518083122
Short name T236
Test name
Test status
Simulation time 152483469086 ps
CPU time 22.08 seconds
Started May 05 01:37:46 PM PDT 24
Finished May 05 01:38:09 PM PDT 24
Peak memory 200440 kb
Host smart-260b30c0-80cb-462f-b7af-ed510b8764b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518083122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1518083122
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3227831205
Short name T301
Test name
Test status
Simulation time 32234745513 ps
CPU time 55.86 seconds
Started May 05 01:37:48 PM PDT 24
Finished May 05 01:38:44 PM PDT 24
Peak memory 200424 kb
Host smart-2cfdd6a1-67db-4c77-a38a-c6027d71dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227831205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3227831205
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1184000969
Short name T872
Test name
Test status
Simulation time 13300290500 ps
CPU time 21.85 seconds
Started May 05 01:37:47 PM PDT 24
Finished May 05 01:38:09 PM PDT 24
Peak memory 200408 kb
Host smart-ee99a512-be22-4a4e-bab6-2f32dfa2fa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184000969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1184000969
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1374295754
Short name T564
Test name
Test status
Simulation time 28426079103 ps
CPU time 27.21 seconds
Started May 05 01:37:46 PM PDT 24
Finished May 05 01:38:14 PM PDT 24
Peak memory 200328 kb
Host smart-20da38e1-b094-4a9e-87db-9c8aeb923687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374295754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1374295754
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4115560977
Short name T646
Test name
Test status
Simulation time 11372974811 ps
CPU time 4.6 seconds
Started May 05 01:37:47 PM PDT 24
Finished May 05 01:37:52 PM PDT 24
Peak memory 197560 kb
Host smart-9c308e4b-3d93-4fab-9ac9-ffc586da05f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115560977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4115560977
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4008527355
Short name T968
Test name
Test status
Simulation time 127297428575 ps
CPU time 107.87 seconds
Started May 05 01:37:51 PM PDT 24
Finished May 05 01:39:39 PM PDT 24
Peak memory 200340 kb
Host smart-0d689e29-5930-4822-8f07-0328ad6826f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008527355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4008527355
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.919779639
Short name T1055
Test name
Test status
Simulation time 13756142707 ps
CPU time 22.31 seconds
Started May 05 01:37:52 PM PDT 24
Finished May 05 01:38:14 PM PDT 24
Peak memory 200412 kb
Host smart-5071c602-9405-4c72-a314-02ba74f2f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919779639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.919779639
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3987033777
Short name T444
Test name
Test status
Simulation time 15999762638 ps
CPU time 7.9 seconds
Started May 05 01:37:53 PM PDT 24
Finished May 05 01:38:02 PM PDT 24
Peak memory 199084 kb
Host smart-5c67d058-2613-4cee-8bfa-22e80b8af219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987033777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3987033777
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.682015449
Short name T931
Test name
Test status
Simulation time 166375796720 ps
CPU time 87.48 seconds
Started May 05 01:37:54 PM PDT 24
Finished May 05 01:39:22 PM PDT 24
Peak memory 200400 kb
Host smart-3a0e1510-23ac-4f11-ac0b-0b9b74818630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682015449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.682015449
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3089739119
Short name T20
Test name
Test status
Simulation time 22774757 ps
CPU time 0.54 seconds
Started May 05 01:31:35 PM PDT 24
Finished May 05 01:31:36 PM PDT 24
Peak memory 195764 kb
Host smart-6050b175-2caf-440d-ac9e-7daae65ab063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089739119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3089739119
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3027789055
Short name T603
Test name
Test status
Simulation time 106324789011 ps
CPU time 30.49 seconds
Started May 05 01:31:31 PM PDT 24
Finished May 05 01:32:02 PM PDT 24
Peak memory 200348 kb
Host smart-05ec483b-d78a-4d14-bc17-762b9d01b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027789055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3027789055
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2000446490
Short name T664
Test name
Test status
Simulation time 57512070526 ps
CPU time 48.34 seconds
Started May 05 01:31:36 PM PDT 24
Finished May 05 01:32:25 PM PDT 24
Peak memory 200388 kb
Host smart-24f9dce4-7c30-44b8-bffe-429356050c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000446490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2000446490
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.2787583252
Short name T840
Test name
Test status
Simulation time 19887959706 ps
CPU time 34.41 seconds
Started May 05 01:31:31 PM PDT 24
Finished May 05 01:32:05 PM PDT 24
Peak memory 200332 kb
Host smart-975bcf91-1ab0-4773-9b42-695fca5c4c11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787583252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2787583252
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.479893286
Short name T867
Test name
Test status
Simulation time 32665948704 ps
CPU time 59.88 seconds
Started May 05 01:31:31 PM PDT 24
Finished May 05 01:32:31 PM PDT 24
Peak memory 200292 kb
Host smart-a573dbb6-7dc8-4074-af7b-6e50e970ed61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479893286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.479893286
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3045385632
Short name T1122
Test name
Test status
Simulation time 1347285623 ps
CPU time 2.68 seconds
Started May 05 01:31:36 PM PDT 24
Finished May 05 01:31:39 PM PDT 24
Peak memory 200308 kb
Host smart-466b561e-afbd-403a-88c4-d6710665815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045385632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3045385632
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.596563775
Short name T1106
Test name
Test status
Simulation time 91513294836 ps
CPU time 33.67 seconds
Started May 05 01:31:30 PM PDT 24
Finished May 05 01:32:04 PM PDT 24
Peak memory 200576 kb
Host smart-d15789a0-6dd7-46b3-b558-6e96063baaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596563775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.596563775
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1524094509
Short name T496
Test name
Test status
Simulation time 14357689912 ps
CPU time 398.69 seconds
Started May 05 01:31:30 PM PDT 24
Finished May 05 01:38:09 PM PDT 24
Peak memory 200348 kb
Host smart-195c6935-2660-4ec9-bd78-21ac3248e2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524094509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1524094509
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2675788375
Short name T609
Test name
Test status
Simulation time 3160512098 ps
CPU time 5.48 seconds
Started May 05 01:31:31 PM PDT 24
Finished May 05 01:31:37 PM PDT 24
Peak memory 199628 kb
Host smart-9504dbeb-e7e1-4e8a-bc68-12cc464c0913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675788375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2675788375
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1316691188
Short name T549
Test name
Test status
Simulation time 82645939460 ps
CPU time 156.1 seconds
Started May 05 01:31:30 PM PDT 24
Finished May 05 01:34:06 PM PDT 24
Peak memory 200400 kb
Host smart-8b3b1e3d-943b-4102-b5d3-d7494131ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316691188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1316691188
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1816931455
Short name T739
Test name
Test status
Simulation time 2440925633 ps
CPU time 5.06 seconds
Started May 05 01:31:32 PM PDT 24
Finished May 05 01:31:37 PM PDT 24
Peak memory 196296 kb
Host smart-0e7dc6c2-0817-4165-b0e1-9c50fb1650dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816931455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1816931455
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1043646559
Short name T259
Test name
Test status
Simulation time 91571563 ps
CPU time 0.97 seconds
Started May 05 01:31:28 PM PDT 24
Finished May 05 01:31:29 PM PDT 24
Peak memory 200008 kb
Host smart-e7aab09f-fd04-4287-aa45-a1194585931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043646559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1043646559
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1141124332
Short name T1062
Test name
Test status
Simulation time 434487733695 ps
CPU time 69.46 seconds
Started May 05 01:31:36 PM PDT 24
Finished May 05 01:32:46 PM PDT 24
Peak memory 200384 kb
Host smart-644eedd0-f715-42e1-8542-74e565d80e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141124332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1141124332
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1483108181
Short name T511
Test name
Test status
Simulation time 3500561992 ps
CPU time 2.23 seconds
Started May 05 01:31:31 PM PDT 24
Finished May 05 01:31:34 PM PDT 24
Peak memory 200288 kb
Host smart-f01eafd6-b6e4-4944-95ec-71488895fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483108181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1483108181
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3916485514
Short name T37
Test name
Test status
Simulation time 1096856463 ps
CPU time 0.71 seconds
Started May 05 01:31:33 PM PDT 24
Finished May 05 01:31:34 PM PDT 24
Peak memory 196952 kb
Host smart-1a930656-2a4d-4c82-b732-a6d6fdfcb6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916485514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3916485514
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2911770609
Short name T297
Test name
Test status
Simulation time 144887001792 ps
CPU time 207.77 seconds
Started May 05 01:37:51 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 200424 kb
Host smart-c6464770-d479-46c5-a9f0-ec2d388fca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911770609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2911770609
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.566506512
Short name T740
Test name
Test status
Simulation time 55121137479 ps
CPU time 29.39 seconds
Started May 05 01:37:52 PM PDT 24
Finished May 05 01:38:21 PM PDT 24
Peak memory 200372 kb
Host smart-dc415ea2-3a38-4f82-91f4-073517445cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566506512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.566506512
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1841591541
Short name T528
Test name
Test status
Simulation time 277431542270 ps
CPU time 34.08 seconds
Started May 05 01:37:51 PM PDT 24
Finished May 05 01:38:25 PM PDT 24
Peak memory 200312 kb
Host smart-78b32c7e-4a31-48e8-9e04-c3fdee26c412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841591541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1841591541
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3181775410
Short name T1086
Test name
Test status
Simulation time 78215459454 ps
CPU time 139.37 seconds
Started May 05 01:37:57 PM PDT 24
Finished May 05 01:40:16 PM PDT 24
Peak memory 200224 kb
Host smart-8e09fa2c-bd69-423d-a956-dcb35226f688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181775410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3181775410
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2180527738
Short name T191
Test name
Test status
Simulation time 36483959190 ps
CPU time 19.23 seconds
Started May 05 01:38:03 PM PDT 24
Finished May 05 01:38:23 PM PDT 24
Peak memory 200212 kb
Host smart-2a7ec353-1cf6-4600-948a-c3c8600e8d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180527738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2180527738
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.314243580
Short name T551
Test name
Test status
Simulation time 217150877642 ps
CPU time 70.46 seconds
Started May 05 01:37:56 PM PDT 24
Finished May 05 01:39:07 PM PDT 24
Peak memory 200332 kb
Host smart-663b4288-abac-4aa9-b31e-e96ef1123cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314243580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.314243580
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2289960644
Short name T1049
Test name
Test status
Simulation time 119058114961 ps
CPU time 55.87 seconds
Started May 05 01:38:03 PM PDT 24
Finished May 05 01:39:00 PM PDT 24
Peak memory 200280 kb
Host smart-53cd81bb-b762-4507-a6c5-0d6f9a896b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289960644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2289960644
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2956922942
Short name T562
Test name
Test status
Simulation time 6726198202 ps
CPU time 15.5 seconds
Started May 05 01:37:58 PM PDT 24
Finished May 05 01:38:14 PM PDT 24
Peak memory 200328 kb
Host smart-ebe41526-5df3-46e5-8707-20af3bdfd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956922942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2956922942
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1302283067
Short name T1019
Test name
Test status
Simulation time 27652899 ps
CPU time 0.55 seconds
Started May 05 01:31:47 PM PDT 24
Finished May 05 01:31:48 PM PDT 24
Peak memory 195124 kb
Host smart-2f34fa03-501d-4248-96c9-ddd6860fe773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302283067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1302283067
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.276824866
Short name T1034
Test name
Test status
Simulation time 179813092563 ps
CPU time 107.71 seconds
Started May 05 01:31:37 PM PDT 24
Finished May 05 01:33:25 PM PDT 24
Peak memory 200276 kb
Host smart-e8a525a0-9c84-4460-a197-d9bafb8cd626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276824866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.276824866
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3374734206
Short name T1001
Test name
Test status
Simulation time 128581630296 ps
CPU time 346.25 seconds
Started May 05 01:31:36 PM PDT 24
Finished May 05 01:37:23 PM PDT 24
Peak memory 200300 kb
Host smart-ba5a60dd-abfa-40fc-9a12-3259b33bb024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374734206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3374734206
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3517089862
Short name T650
Test name
Test status
Simulation time 33094740772 ps
CPU time 55.37 seconds
Started May 05 01:31:35 PM PDT 24
Finished May 05 01:32:30 PM PDT 24
Peak memory 200408 kb
Host smart-cc099e87-eac3-443f-8951-19623b4f2530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517089862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3517089862
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.640121635
Short name T368
Test name
Test status
Simulation time 20619469640 ps
CPU time 16.65 seconds
Started May 05 01:31:40 PM PDT 24
Finished May 05 01:31:57 PM PDT 24
Peak memory 197504 kb
Host smart-b06e4066-ebc9-4c14-b71a-a239de015677
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640121635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.640121635
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3911597884
Short name T365
Test name
Test status
Simulation time 35940796020 ps
CPU time 199.46 seconds
Started May 05 01:31:43 PM PDT 24
Finished May 05 01:35:03 PM PDT 24
Peak memory 200412 kb
Host smart-f68da49f-9446-49a0-ad79-5fdb54ac0e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911597884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3911597884
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2802232757
Short name T1100
Test name
Test status
Simulation time 1382991886 ps
CPU time 1.93 seconds
Started May 05 01:31:42 PM PDT 24
Finished May 05 01:31:44 PM PDT 24
Peak memory 196488 kb
Host smart-e8b05372-1b94-4d27-9ce1-757539adb6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802232757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2802232757
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3771747981
Short name T452
Test name
Test status
Simulation time 83540949611 ps
CPU time 42.97 seconds
Started May 05 01:31:40 PM PDT 24
Finished May 05 01:32:23 PM PDT 24
Peak memory 199600 kb
Host smart-feae54f2-ee0b-43f4-ae7b-06a6e885847c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771747981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3771747981
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3146620056
Short name T803
Test name
Test status
Simulation time 31239841114 ps
CPU time 872.62 seconds
Started May 05 01:31:41 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 200352 kb
Host smart-6f72af10-27d4-4399-8355-6e33b146e1b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146620056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3146620056
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1323073842
Short name T797
Test name
Test status
Simulation time 3811568734 ps
CPU time 6.86 seconds
Started May 05 01:31:36 PM PDT 24
Finished May 05 01:31:43 PM PDT 24
Peak memory 198792 kb
Host smart-f3308501-8ea0-4c53-b0b5-0658bb4b5b1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323073842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1323073842
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.942524680
Short name T583
Test name
Test status
Simulation time 26882950217 ps
CPU time 25.14 seconds
Started May 05 01:31:40 PM PDT 24
Finished May 05 01:32:06 PM PDT 24
Peak memory 200296 kb
Host smart-da10c76c-afd0-4095-8cb7-9c9ea06d1ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942524680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.942524680
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2402493219
Short name T731
Test name
Test status
Simulation time 49341704018 ps
CPU time 68.14 seconds
Started May 05 01:31:39 PM PDT 24
Finished May 05 01:32:48 PM PDT 24
Peak memory 196356 kb
Host smart-a0512ca9-be12-47fb-80a1-203151597420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402493219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2402493219
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.513339294
Short name T361
Test name
Test status
Simulation time 5910786920 ps
CPU time 34.75 seconds
Started May 05 01:31:35 PM PDT 24
Finished May 05 01:32:10 PM PDT 24
Peak memory 200156 kb
Host smart-41cd6830-b172-4c0f-b2c2-aea0a4fc8be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513339294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.513339294
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2839250939
Short name T84
Test name
Test status
Simulation time 193452338344 ps
CPU time 831.46 seconds
Started May 05 01:31:42 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 200300 kb
Host smart-cae92894-7b9d-4dea-a23b-4be68bcefdd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839250939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2839250939
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1392064977
Short name T1095
Test name
Test status
Simulation time 1007317415 ps
CPU time 1.93 seconds
Started May 05 01:31:40 PM PDT 24
Finished May 05 01:31:43 PM PDT 24
Peak memory 199120 kb
Host smart-ff8a4389-3230-47bd-9b4b-1923b3e0832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392064977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1392064977
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2324230639
Short name T1185
Test name
Test status
Simulation time 57254458136 ps
CPU time 105.61 seconds
Started May 05 01:31:34 PM PDT 24
Finished May 05 01:33:20 PM PDT 24
Peak memory 200376 kb
Host smart-5c53c86b-4ee3-4d82-a0f7-075c27e23926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324230639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2324230639
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1788978035
Short name T60
Test name
Test status
Simulation time 108979839002 ps
CPU time 95.25 seconds
Started May 05 01:37:56 PM PDT 24
Finished May 05 01:39:31 PM PDT 24
Peak memory 200256 kb
Host smart-a0291198-90ad-4ff7-bfbd-2961a9af65cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788978035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1788978035
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3402507093
Short name T263
Test name
Test status
Simulation time 15350374957 ps
CPU time 33.65 seconds
Started May 05 01:37:56 PM PDT 24
Finished May 05 01:38:30 PM PDT 24
Peak memory 200332 kb
Host smart-5e993b51-6b21-460a-917b-9dae56f2dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402507093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3402507093
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1427215072
Short name T390
Test name
Test status
Simulation time 80322517886 ps
CPU time 32.05 seconds
Started May 05 01:37:56 PM PDT 24
Finished May 05 01:38:28 PM PDT 24
Peak memory 200336 kb
Host smart-89973d6c-d804-4c01-a0f4-9515f903cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427215072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1427215072
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1918372116
Short name T590
Test name
Test status
Simulation time 175131979389 ps
CPU time 145.79 seconds
Started May 05 01:38:03 PM PDT 24
Finished May 05 01:40:29 PM PDT 24
Peak memory 200400 kb
Host smart-1d23fdb5-240c-4dff-9a20-9a960f904a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918372116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1918372116
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1769982573
Short name T1098
Test name
Test status
Simulation time 10786361627 ps
CPU time 5.4 seconds
Started May 05 01:37:54 PM PDT 24
Finished May 05 01:38:00 PM PDT 24
Peak memory 200264 kb
Host smart-a0cf7432-1ca0-4a7b-a156-b1e90d405758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769982573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1769982573
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3789122388
Short name T557
Test name
Test status
Simulation time 55526126001 ps
CPU time 54.04 seconds
Started May 05 01:37:55 PM PDT 24
Finished May 05 01:38:49 PM PDT 24
Peak memory 200312 kb
Host smart-cd0116c4-0caa-4cdf-8113-eff9d4d108e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789122388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3789122388
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.84560711
Short name T1009
Test name
Test status
Simulation time 58598679207 ps
CPU time 47.2 seconds
Started May 05 01:37:55 PM PDT 24
Finished May 05 01:38:42 PM PDT 24
Peak memory 200332 kb
Host smart-ce4ad3cc-0cab-4993-940c-f5e97cc4e57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84560711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.84560711
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2214379760
Short name T1005
Test name
Test status
Simulation time 30668652030 ps
CPU time 86.98 seconds
Started May 05 01:38:03 PM PDT 24
Finished May 05 01:39:30 PM PDT 24
Peak memory 200336 kb
Host smart-29daff32-0d3e-492c-8a03-205fadf5d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214379760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2214379760
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1378224562
Short name T1068
Test name
Test status
Simulation time 181519715168 ps
CPU time 85.89 seconds
Started May 05 01:38:02 PM PDT 24
Finished May 05 01:39:28 PM PDT 24
Peak memory 200416 kb
Host smart-8d616591-0020-44cf-a1de-328925d232cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378224562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1378224562
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1410304963
Short name T97
Test name
Test status
Simulation time 43793995813 ps
CPU time 40.09 seconds
Started May 05 01:38:02 PM PDT 24
Finished May 05 01:38:42 PM PDT 24
Peak memory 200296 kb
Host smart-632cfd3a-678b-4615-8c0b-a4163d9ed199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410304963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1410304963
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.311105022
Short name T989
Test name
Test status
Simulation time 23173270 ps
CPU time 0.57 seconds
Started May 05 01:31:52 PM PDT 24
Finished May 05 01:31:53 PM PDT 24
Peak memory 195776 kb
Host smart-6496e6c1-f2bb-403f-937e-22a188aa5ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311105022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.311105022
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2677702251
Short name T429
Test name
Test status
Simulation time 101309143317 ps
CPU time 43.97 seconds
Started May 05 01:31:45 PM PDT 24
Finished May 05 01:32:30 PM PDT 24
Peak memory 200376 kb
Host smart-520b34f4-4bef-4d6a-862a-175e1c29153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677702251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2677702251
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2460003916
Short name T1142
Test name
Test status
Simulation time 61999073245 ps
CPU time 81.61 seconds
Started May 05 01:31:45 PM PDT 24
Finished May 05 01:33:08 PM PDT 24
Peak memory 200336 kb
Host smart-ccd1d40a-f208-4782-9d05-a29dc76420bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460003916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2460003916
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3448465316
Short name T1102
Test name
Test status
Simulation time 228502215826 ps
CPU time 179.01 seconds
Started May 05 01:31:46 PM PDT 24
Finished May 05 01:34:45 PM PDT 24
Peak memory 198832 kb
Host smart-06225188-172a-4a97-8736-cd519ba02eb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448465316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3448465316
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1590102017
Short name T930
Test name
Test status
Simulation time 116551622094 ps
CPU time 228.29 seconds
Started May 05 01:31:50 PM PDT 24
Finished May 05 01:35:39 PM PDT 24
Peak memory 200356 kb
Host smart-d57403f4-7e47-4f63-9fe1-8aee393c508e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590102017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1590102017
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1089305914
Short name T1013
Test name
Test status
Simulation time 2086546177 ps
CPU time 2.04 seconds
Started May 05 01:31:51 PM PDT 24
Finished May 05 01:31:53 PM PDT 24
Peak memory 198756 kb
Host smart-87b98d46-8b77-4ed9-afe8-1e8e5921258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089305914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1089305914
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1090015232
Short name T1041
Test name
Test status
Simulation time 113226186272 ps
CPU time 193.57 seconds
Started May 05 01:31:51 PM PDT 24
Finished May 05 01:35:05 PM PDT 24
Peak memory 208760 kb
Host smart-dd0c1d5a-f2b2-4e95-81d2-a19338d0f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090015232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1090015232
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1148307016
Short name T554
Test name
Test status
Simulation time 8691570619 ps
CPU time 230.3 seconds
Started May 05 01:31:52 PM PDT 24
Finished May 05 01:35:42 PM PDT 24
Peak memory 200276 kb
Host smart-4f41092f-194f-4032-a727-39e4487b3c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148307016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1148307016
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3255399790
Short name T643
Test name
Test status
Simulation time 4423127101 ps
CPU time 36.61 seconds
Started May 05 01:31:46 PM PDT 24
Finished May 05 01:32:23 PM PDT 24
Peak memory 199128 kb
Host smart-48e8c8e9-3da6-41c7-95f9-f43f17faded5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255399790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3255399790
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4063080143
Short name T262
Test name
Test status
Simulation time 34061583431 ps
CPU time 18.46 seconds
Started May 05 01:31:52 PM PDT 24
Finished May 05 01:32:11 PM PDT 24
Peak memory 200072 kb
Host smart-d592e3b2-1a6f-44db-af61-00d419418df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063080143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4063080143
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4027043078
Short name T38
Test name
Test status
Simulation time 3334388639 ps
CPU time 2.14 seconds
Started May 05 01:31:52 PM PDT 24
Finished May 05 01:31:54 PM PDT 24
Peak memory 196360 kb
Host smart-639dee19-5e2e-46b0-8417-74e5fbf21c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027043078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4027043078
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1249993515
Short name T744
Test name
Test status
Simulation time 533806453 ps
CPU time 0.99 seconds
Started May 05 01:31:48 PM PDT 24
Finished May 05 01:31:49 PM PDT 24
Peak memory 199764 kb
Host smart-c99e1ee1-3818-4216-89b6-69f38d9f812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249993515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1249993515
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1586557742
Short name T401
Test name
Test status
Simulation time 48047338967 ps
CPU time 16.17 seconds
Started May 05 01:31:50 PM PDT 24
Finished May 05 01:32:07 PM PDT 24
Peak memory 200388 kb
Host smart-2776b1ea-587e-45cd-855d-6687d0787d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586557742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1586557742
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1374200664
Short name T1087
Test name
Test status
Simulation time 38245907708 ps
CPU time 393.03 seconds
Started May 05 01:31:54 PM PDT 24
Finished May 05 01:38:27 PM PDT 24
Peak memory 216752 kb
Host smart-8f78bdcb-e2f6-406e-875a-2e0e72802e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374200664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1374200664
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1564680637
Short name T470
Test name
Test status
Simulation time 432098016 ps
CPU time 2.12 seconds
Started May 05 01:31:52 PM PDT 24
Finished May 05 01:31:54 PM PDT 24
Peak memory 200248 kb
Host smart-9743eff9-f374-426c-874b-a5de854740a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564680637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1564680637
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3739728386
Short name T988
Test name
Test status
Simulation time 101688432463 ps
CPU time 56.76 seconds
Started May 05 01:31:45 PM PDT 24
Finished May 05 01:32:43 PM PDT 24
Peak memory 200404 kb
Host smart-46de240d-08b2-4c14-b0e6-271510f53a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739728386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3739728386
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.756571807
Short name T172
Test name
Test status
Simulation time 90474897268 ps
CPU time 330.48 seconds
Started May 05 01:38:00 PM PDT 24
Finished May 05 01:43:31 PM PDT 24
Peak memory 200368 kb
Host smart-dd13a29a-3a42-407c-a74a-8c07b365a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756571807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.756571807
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2894124758
Short name T1018
Test name
Test status
Simulation time 74594294055 ps
CPU time 135.22 seconds
Started May 05 01:38:00 PM PDT 24
Finished May 05 01:40:16 PM PDT 24
Peak memory 200340 kb
Host smart-28d569e7-c4a8-4595-b04a-602c569728fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894124758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2894124758
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3465249199
Short name T559
Test name
Test status
Simulation time 197376705999 ps
CPU time 16.03 seconds
Started May 05 01:38:01 PM PDT 24
Finished May 05 01:38:17 PM PDT 24
Peak memory 200152 kb
Host smart-2534bc11-fa37-45d3-a619-afb0b7df291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465249199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3465249199
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2696578404
Short name T323
Test name
Test status
Simulation time 176558303936 ps
CPU time 187.66 seconds
Started May 05 01:38:04 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 200368 kb
Host smart-62dd79d3-a7d4-4f3f-adeb-32db570ca17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696578404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2696578404
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.754053567
Short name T522
Test name
Test status
Simulation time 110650509400 ps
CPU time 40.83 seconds
Started May 05 01:38:12 PM PDT 24
Finished May 05 01:38:53 PM PDT 24
Peak memory 200396 kb
Host smart-af94709e-da38-4242-8586-8c58a7a7a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754053567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.754053567
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2218613521
Short name T837
Test name
Test status
Simulation time 80101404583 ps
CPU time 220.81 seconds
Started May 05 01:38:14 PM PDT 24
Finished May 05 01:41:55 PM PDT 24
Peak memory 200376 kb
Host smart-caebe9d2-5995-473e-a624-9e703eb377ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218613521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2218613521
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2547759518
Short name T853
Test name
Test status
Simulation time 45949630239 ps
CPU time 35.58 seconds
Started May 05 01:38:12 PM PDT 24
Finished May 05 01:38:48 PM PDT 24
Peak memory 200352 kb
Host smart-d803540e-5cd4-4e18-96ac-6b19120966d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547759518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2547759518
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2001684677
Short name T136
Test name
Test status
Simulation time 120634753060 ps
CPU time 22.56 seconds
Started May 05 01:38:05 PM PDT 24
Finished May 05 01:38:28 PM PDT 24
Peak memory 200344 kb
Host smart-68304175-5e5a-4ee1-9d6b-9f5008226acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001684677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2001684677
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3552713731
Short name T351
Test name
Test status
Simulation time 13155943 ps
CPU time 0.6 seconds
Started May 05 01:32:06 PM PDT 24
Finished May 05 01:32:07 PM PDT 24
Peak memory 195804 kb
Host smart-ca250422-21f0-4935-82c9-9bac3e8576cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552713731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3552713731
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.596572076
Short name T1182
Test name
Test status
Simulation time 29934304411 ps
CPU time 45.14 seconds
Started May 05 01:31:51 PM PDT 24
Finished May 05 01:32:36 PM PDT 24
Peak memory 200224 kb
Host smart-d72a1368-ec40-4cae-bd0a-acef3861ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596572076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.596572076
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1343347716
Short name T804
Test name
Test status
Simulation time 37547067096 ps
CPU time 14.95 seconds
Started May 05 01:31:51 PM PDT 24
Finished May 05 01:32:06 PM PDT 24
Peak memory 200348 kb
Host smart-53d3eaa1-0204-45ed-a4a2-856dbbb9e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343347716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1343347716
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1334044452
Short name T708
Test name
Test status
Simulation time 129390765219 ps
CPU time 26.82 seconds
Started May 05 01:31:54 PM PDT 24
Finished May 05 01:32:22 PM PDT 24
Peak memory 200336 kb
Host smart-d66c03ae-61e7-4883-bf8e-00f8fa12ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334044452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1334044452
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.248765192
Short name T560
Test name
Test status
Simulation time 52103632760 ps
CPU time 21.31 seconds
Started May 05 01:31:57 PM PDT 24
Finished May 05 01:32:18 PM PDT 24
Peak memory 200336 kb
Host smart-4464ad25-d466-402c-996c-482005b3f852
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248765192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.248765192
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.689988702
Short name T762
Test name
Test status
Simulation time 64631981999 ps
CPU time 264.74 seconds
Started May 05 01:32:02 PM PDT 24
Finished May 05 01:36:27 PM PDT 24
Peak memory 200328 kb
Host smart-2ae41239-8451-4852-94a5-dae22029b00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689988702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.689988702
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2623934942
Short name T1118
Test name
Test status
Simulation time 4768108955 ps
CPU time 10.49 seconds
Started May 05 01:32:02 PM PDT 24
Finished May 05 01:32:13 PM PDT 24
Peak memory 200036 kb
Host smart-7c37d90b-c304-44cd-ab46-d55aa7c396a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623934942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2623934942
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3891108742
Short name T268
Test name
Test status
Simulation time 15559778127 ps
CPU time 10.42 seconds
Started May 05 01:31:56 PM PDT 24
Finished May 05 01:32:07 PM PDT 24
Peak memory 200336 kb
Host smart-1c5ca8d7-73be-4426-93ba-ce6355c75e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891108742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3891108742
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2138485613
Short name T668
Test name
Test status
Simulation time 13339217471 ps
CPU time 733.46 seconds
Started May 05 01:32:02 PM PDT 24
Finished May 05 01:44:16 PM PDT 24
Peak memory 200312 kb
Host smart-f6c6417d-102a-425c-8e7a-1e2441ca5f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138485613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2138485613
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4279569065
Short name T385
Test name
Test status
Simulation time 1802797285 ps
CPU time 9.44 seconds
Started May 05 01:31:55 PM PDT 24
Finished May 05 01:32:05 PM PDT 24
Peak memory 198240 kb
Host smart-f33e527b-70b6-40a8-b936-6d1aa90a5261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279569065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4279569065
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3970231103
Short name T955
Test name
Test status
Simulation time 20158224922 ps
CPU time 31.2 seconds
Started May 05 01:32:01 PM PDT 24
Finished May 05 01:32:33 PM PDT 24
Peak memory 200332 kb
Host smart-ecb935c8-c333-4609-b83b-1ca48b52909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970231103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3970231103
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1156177457
Short name T751
Test name
Test status
Simulation time 41155259026 ps
CPU time 51.45 seconds
Started May 05 01:32:01 PM PDT 24
Finished May 05 01:32:53 PM PDT 24
Peak memory 196068 kb
Host smart-1b90a731-afc0-4daa-9731-0bd0a6dc71b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156177457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1156177457
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.958563573
Short name T391
Test name
Test status
Simulation time 534827944 ps
CPU time 1.22 seconds
Started May 05 01:31:51 PM PDT 24
Finished May 05 01:31:52 PM PDT 24
Peak memory 198668 kb
Host smart-d67547cf-c23a-4edf-8b1b-debeb5ecf1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958563573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.958563573
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.539303561
Short name T727
Test name
Test status
Simulation time 363392161859 ps
CPU time 252.35 seconds
Started May 05 01:32:03 PM PDT 24
Finished May 05 01:36:15 PM PDT 24
Peak memory 208712 kb
Host smart-bb012ebf-9abd-4799-9964-d56c763c5167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539303561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.539303561
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2077095450
Short name T1152
Test name
Test status
Simulation time 58819090830 ps
CPU time 460.75 seconds
Started May 05 01:32:03 PM PDT 24
Finished May 05 01:39:44 PM PDT 24
Peak memory 226336 kb
Host smart-681bda87-0b6b-436c-8000-198822518b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077095450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2077095450
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2134363673
Short name T5
Test name
Test status
Simulation time 1030248774 ps
CPU time 3.15 seconds
Started May 05 01:32:03 PM PDT 24
Finished May 05 01:32:06 PM PDT 24
Peak memory 199024 kb
Host smart-5d1bf23a-6b77-4571-bf42-31a6068a48be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134363673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2134363673
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.722319194
Short name T958
Test name
Test status
Simulation time 94226244035 ps
CPU time 199.59 seconds
Started May 05 01:31:52 PM PDT 24
Finished May 05 01:35:12 PM PDT 24
Peak memory 200308 kb
Host smart-e1a092f0-941b-414b-b135-4dac2f4f6417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722319194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.722319194
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3983088670
Short name T194
Test name
Test status
Simulation time 85099460650 ps
CPU time 176.47 seconds
Started May 05 01:38:06 PM PDT 24
Finished May 05 01:41:02 PM PDT 24
Peak memory 200360 kb
Host smart-bea0e9d4-6e72-4466-b15a-6e094097d3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983088670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3983088670
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3729823645
Short name T661
Test name
Test status
Simulation time 116692044275 ps
CPU time 257.15 seconds
Started May 05 01:38:11 PM PDT 24
Finished May 05 01:42:28 PM PDT 24
Peak memory 200396 kb
Host smart-478f46ec-3b83-4851-a58b-aaee38f0513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729823645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3729823645
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2803194181
Short name T1164
Test name
Test status
Simulation time 143611281486 ps
CPU time 347.46 seconds
Started May 05 01:38:12 PM PDT 24
Finished May 05 01:44:00 PM PDT 24
Peak memory 200432 kb
Host smart-015631f0-1466-46be-b21c-711932c66b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803194181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2803194181
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.325370280
Short name T1123
Test name
Test status
Simulation time 66204326128 ps
CPU time 27.14 seconds
Started May 05 01:38:13 PM PDT 24
Finished May 05 01:38:40 PM PDT 24
Peak memory 200216 kb
Host smart-7f0fcf31-f34a-4ebc-b3ea-dff79840f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325370280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.325370280
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4201221935
Short name T210
Test name
Test status
Simulation time 107060311678 ps
CPU time 199.91 seconds
Started May 05 01:38:12 PM PDT 24
Finished May 05 01:41:32 PM PDT 24
Peak memory 200328 kb
Host smart-bf92af05-2c22-47ad-89b4-c6c57a4846d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201221935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4201221935
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3088113498
Short name T1031
Test name
Test status
Simulation time 34361348952 ps
CPU time 33.78 seconds
Started May 05 01:38:12 PM PDT 24
Finished May 05 01:38:46 PM PDT 24
Peak memory 200448 kb
Host smart-4342f86d-e576-4bab-8883-007b6a55f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088113498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3088113498
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2893546349
Short name T822
Test name
Test status
Simulation time 25174629102 ps
CPU time 53.38 seconds
Started May 05 01:38:11 PM PDT 24
Finished May 05 01:39:05 PM PDT 24
Peak memory 200344 kb
Host smart-1589326a-bbc4-4041-889c-0d4c22b3f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893546349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2893546349
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4017842211
Short name T869
Test name
Test status
Simulation time 99778848589 ps
CPU time 204.52 seconds
Started May 05 01:38:13 PM PDT 24
Finished May 05 01:41:38 PM PDT 24
Peak memory 200232 kb
Host smart-4bfe0c32-db9f-4262-88d2-5f6539762936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017842211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4017842211
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1742507065
Short name T647
Test name
Test status
Simulation time 30058994900 ps
CPU time 13.61 seconds
Started May 05 01:38:18 PM PDT 24
Finished May 05 01:38:32 PM PDT 24
Peak memory 200344 kb
Host smart-65aa62ff-1f14-4048-a568-abb0db9f11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742507065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1742507065
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3328379473
Short name T671
Test name
Test status
Simulation time 15982171 ps
CPU time 0.57 seconds
Started May 05 01:32:11 PM PDT 24
Finished May 05 01:32:11 PM PDT 24
Peak memory 195780 kb
Host smart-6897c2fa-482e-4a64-98fe-40226ab82831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328379473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3328379473
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3096618374
Short name T637
Test name
Test status
Simulation time 42266960511 ps
CPU time 38.76 seconds
Started May 05 01:32:06 PM PDT 24
Finished May 05 01:32:45 PM PDT 24
Peak memory 200424 kb
Host smart-7b5482a2-c845-4188-9f36-3e45d4ba8600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096618374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3096618374
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2428590845
Short name T883
Test name
Test status
Simulation time 167653880420 ps
CPU time 25.52 seconds
Started May 05 01:32:06 PM PDT 24
Finished May 05 01:32:32 PM PDT 24
Peak memory 200044 kb
Host smart-8ab22188-3d0f-40a0-b666-8b1325fd8768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428590845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2428590845
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3412158551
Short name T1015
Test name
Test status
Simulation time 17145540452 ps
CPU time 14.13 seconds
Started May 05 01:32:07 PM PDT 24
Finished May 05 01:32:21 PM PDT 24
Peak memory 200400 kb
Host smart-3758feb6-dfc1-44ab-8dbd-88a217d4c4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412158551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3412158551
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1446100448
Short name T596
Test name
Test status
Simulation time 12877460391 ps
CPU time 18.44 seconds
Started May 05 01:32:07 PM PDT 24
Finished May 05 01:32:26 PM PDT 24
Peak memory 200304 kb
Host smart-8682e004-1cae-4c55-8886-0acfad556c9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446100448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1446100448
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4093669978
Short name T458
Test name
Test status
Simulation time 57654078832 ps
CPU time 463.34 seconds
Started May 05 01:32:14 PM PDT 24
Finished May 05 01:39:58 PM PDT 24
Peak memory 200328 kb
Host smart-844b9680-e79f-4f0c-808d-8e57bfd6a41d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093669978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4093669978
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1900605667
Short name T765
Test name
Test status
Simulation time 12070020666 ps
CPU time 23.82 seconds
Started May 05 01:32:12 PM PDT 24
Finished May 05 01:32:36 PM PDT 24
Peak memory 200332 kb
Host smart-edb03b4f-3d4f-4a38-aebf-469f3b2c3147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900605667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1900605667
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1221686475
Short name T1006
Test name
Test status
Simulation time 6594905941 ps
CPU time 12.95 seconds
Started May 05 01:32:07 PM PDT 24
Finished May 05 01:32:20 PM PDT 24
Peak memory 198976 kb
Host smart-b80858b1-c33a-4611-8ee1-61c2641ce3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221686475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1221686475
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.400176767
Short name T827
Test name
Test status
Simulation time 12000292957 ps
CPU time 35.82 seconds
Started May 05 01:32:12 PM PDT 24
Finished May 05 01:32:48 PM PDT 24
Peak memory 200364 kb
Host smart-56ebc8db-7a9e-4c04-8ecd-39b0c1d28709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400176767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.400176767
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2903606558
Short name T332
Test name
Test status
Simulation time 4368892509 ps
CPU time 7.78 seconds
Started May 05 01:32:06 PM PDT 24
Finished May 05 01:32:14 PM PDT 24
Peak memory 199212 kb
Host smart-4b5ed5cd-7378-4333-9bce-7690ecb695d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903606558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2903606558
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2393661445
Short name T270
Test name
Test status
Simulation time 88526788089 ps
CPU time 138.4 seconds
Started May 05 01:32:13 PM PDT 24
Finished May 05 01:34:32 PM PDT 24
Peak memory 200324 kb
Host smart-a8b93b6c-664d-4c42-942c-26454e33cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393661445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2393661445
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.921655804
Short name T437
Test name
Test status
Simulation time 2397201190 ps
CPU time 4.38 seconds
Started May 05 01:32:06 PM PDT 24
Finished May 05 01:32:11 PM PDT 24
Peak memory 196392 kb
Host smart-107d1ebb-b9a1-4499-9bb1-71f236fabb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921655804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.921655804
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2302941709
Short name T662
Test name
Test status
Simulation time 918500286 ps
CPU time 2.03 seconds
Started May 05 01:32:07 PM PDT 24
Finished May 05 01:32:09 PM PDT 24
Peak memory 198648 kb
Host smart-ab61bdfb-37a5-4da1-883b-cd6b7e3618c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302941709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2302941709
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.628156426
Short name T1022
Test name
Test status
Simulation time 99515282322 ps
CPU time 82.95 seconds
Started May 05 01:32:12 PM PDT 24
Finished May 05 01:33:35 PM PDT 24
Peak memory 200588 kb
Host smart-6b4e1cf2-7b0c-4718-a446-575298495395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628156426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.628156426
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3447263135
Short name T856
Test name
Test status
Simulation time 1389655344 ps
CPU time 1.65 seconds
Started May 05 01:32:12 PM PDT 24
Finished May 05 01:32:14 PM PDT 24
Peak memory 199204 kb
Host smart-69d46800-718f-40c1-90d9-d5b31fa80873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447263135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3447263135
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3509536942
Short name T278
Test name
Test status
Simulation time 76870386389 ps
CPU time 70.01 seconds
Started May 05 01:32:07 PM PDT 24
Finished May 05 01:33:17 PM PDT 24
Peak memory 200328 kb
Host smart-4a8db781-cbf0-4163-a301-f9136076def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509536942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3509536942
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2914091174
Short name T576
Test name
Test status
Simulation time 43640721406 ps
CPU time 62.27 seconds
Started May 05 01:38:17 PM PDT 24
Finished May 05 01:39:19 PM PDT 24
Peak memory 199904 kb
Host smart-5ea4939a-847b-432a-9f39-e6b11b7779be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914091174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2914091174
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1078195831
Short name T212
Test name
Test status
Simulation time 35832730070 ps
CPU time 31.11 seconds
Started May 05 01:38:19 PM PDT 24
Finished May 05 01:38:50 PM PDT 24
Peak memory 200376 kb
Host smart-a6baba31-bf15-48bf-ac64-d517ec887ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078195831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1078195831
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.31592007
Short name T220
Test name
Test status
Simulation time 34767034481 ps
CPU time 60.97 seconds
Started May 05 01:38:17 PM PDT 24
Finished May 05 01:39:18 PM PDT 24
Peak memory 200356 kb
Host smart-1adcd027-7dbe-429b-8690-e3db0a150ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31592007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.31592007
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1652982731
Short name T1091
Test name
Test status
Simulation time 15979559060 ps
CPU time 27.69 seconds
Started May 05 01:38:16 PM PDT 24
Finished May 05 01:38:44 PM PDT 24
Peak memory 200324 kb
Host smart-6959f7dd-1959-4c61-b755-59d0dcf5630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652982731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1652982731
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2844085700
Short name T915
Test name
Test status
Simulation time 64743201050 ps
CPU time 94.69 seconds
Started May 05 01:38:16 PM PDT 24
Finished May 05 01:39:51 PM PDT 24
Peak memory 200096 kb
Host smart-6e809b90-4056-4359-a16c-e715abd7ca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844085700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2844085700
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3664622954
Short name T651
Test name
Test status
Simulation time 65737412633 ps
CPU time 8.78 seconds
Started May 05 01:38:18 PM PDT 24
Finished May 05 01:38:27 PM PDT 24
Peak memory 200328 kb
Host smart-06918155-573b-4a4c-88f7-0e2ca85063fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664622954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3664622954
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.684685752
Short name T1081
Test name
Test status
Simulation time 47875486782 ps
CPU time 26.89 seconds
Started May 05 01:38:22 PM PDT 24
Finished May 05 01:38:49 PM PDT 24
Peak memory 200328 kb
Host smart-1e6c6ad7-feb7-47db-bd15-8d29987959af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684685752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.684685752
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3214883969
Short name T885
Test name
Test status
Simulation time 93475392264 ps
CPU time 146.49 seconds
Started May 05 01:38:22 PM PDT 24
Finished May 05 01:40:49 PM PDT 24
Peak memory 200340 kb
Host smart-ade064ee-2c30-4f96-99c6-ae958cc5806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214883969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3214883969
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.228438938
Short name T582
Test name
Test status
Simulation time 35331291 ps
CPU time 0.55 seconds
Started May 05 01:32:20 PM PDT 24
Finished May 05 01:32:20 PM PDT 24
Peak memory 195748 kb
Host smart-7896374c-4a73-45f0-a8ce-f8e3544368cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228438938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.228438938
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1646642814
Short name T151
Test name
Test status
Simulation time 13767385254 ps
CPU time 22 seconds
Started May 05 01:32:13 PM PDT 24
Finished May 05 01:32:36 PM PDT 24
Peak memory 200392 kb
Host smart-7b4d1da5-0702-404d-aa4b-15bec6ff7ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646642814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1646642814
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1269334865
Short name T715
Test name
Test status
Simulation time 16565543691 ps
CPU time 26.41 seconds
Started May 05 01:32:11 PM PDT 24
Finished May 05 01:32:38 PM PDT 24
Peak memory 200336 kb
Host smart-cbbfebfc-2f9c-42f0-bdbf-8a6f77fbac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269334865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1269334865
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1838953755
Short name T304
Test name
Test status
Simulation time 67994741130 ps
CPU time 132.88 seconds
Started May 05 01:32:14 PM PDT 24
Finished May 05 01:34:27 PM PDT 24
Peak memory 200292 kb
Host smart-8d03b6f7-c1de-4fb3-a869-1fae0006eb18
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838953755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1838953755
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3674633907
Short name T642
Test name
Test status
Simulation time 119479802059 ps
CPU time 317.66 seconds
Started May 05 01:32:16 PM PDT 24
Finished May 05 01:37:34 PM PDT 24
Peak memory 200328 kb
Host smart-ff99ec1d-18bd-4343-9649-a382a02337ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674633907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3674633907
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1056318623
Short name T561
Test name
Test status
Simulation time 8461144711 ps
CPU time 4.56 seconds
Started May 05 01:32:17 PM PDT 24
Finished May 05 01:32:22 PM PDT 24
Peak memory 198736 kb
Host smart-42bdeb35-2ea5-4846-a064-c034eed02d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056318623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1056318623
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1672839796
Short name T571
Test name
Test status
Simulation time 147732794686 ps
CPU time 56.58 seconds
Started May 05 01:32:12 PM PDT 24
Finished May 05 01:33:09 PM PDT 24
Peak memory 200660 kb
Host smart-c09f8972-62d6-41a9-9c54-91d624987abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672839796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1672839796
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.136230381
Short name T404
Test name
Test status
Simulation time 14465331054 ps
CPU time 45.17 seconds
Started May 05 01:32:16 PM PDT 24
Finished May 05 01:33:02 PM PDT 24
Peak memory 200392 kb
Host smart-c02ac697-7db9-4baf-b762-2a9b560df369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136230381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.136230381
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3522684186
Short name T800
Test name
Test status
Simulation time 3033177040 ps
CPU time 21.85 seconds
Started May 05 01:32:11 PM PDT 24
Finished May 05 01:32:33 PM PDT 24
Peak memory 199448 kb
Host smart-067b7af4-83e0-4553-81b1-42521e450762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522684186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3522684186
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2463585393
Short name T1114
Test name
Test status
Simulation time 173259142517 ps
CPU time 73.52 seconds
Started May 05 01:32:16 PM PDT 24
Finished May 05 01:33:30 PM PDT 24
Peak memory 200092 kb
Host smart-c62fd843-2b59-4ae0-bf96-796f10d5d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463585393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2463585393
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4294215657
Short name T487
Test name
Test status
Simulation time 1076106498 ps
CPU time 1.5 seconds
Started May 05 01:32:16 PM PDT 24
Finished May 05 01:32:18 PM PDT 24
Peak memory 195480 kb
Host smart-3be0f581-30b4-47a1-b347-45afe62d7d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294215657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4294215657
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2697135637
Short name T358
Test name
Test status
Simulation time 690976720 ps
CPU time 1.62 seconds
Started May 05 01:32:11 PM PDT 24
Finished May 05 01:32:13 PM PDT 24
Peak memory 200144 kb
Host smart-1b382ace-9aa8-49de-8af3-9830c81f70e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697135637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2697135637
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4100126238
Short name T977
Test name
Test status
Simulation time 237354649985 ps
CPU time 58.42 seconds
Started May 05 01:32:18 PM PDT 24
Finished May 05 01:33:17 PM PDT 24
Peak memory 200056 kb
Host smart-eed65d3e-4ac2-4b9a-84d8-cff4240b2619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100126238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4100126238
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2677696319
Short name T15
Test name
Test status
Simulation time 779670940 ps
CPU time 2.26 seconds
Started May 05 01:32:15 PM PDT 24
Finished May 05 01:32:18 PM PDT 24
Peak memory 198940 kb
Host smart-ecad1801-e622-4dd2-8ef8-1244117ec922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677696319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2677696319
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.183587983
Short name T1176
Test name
Test status
Simulation time 16895828147 ps
CPU time 15.45 seconds
Started May 05 01:32:12 PM PDT 24
Finished May 05 01:32:27 PM PDT 24
Peak memory 200052 kb
Host smart-3cb32952-21d2-47b5-951c-a1de5a1b7810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183587983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.183587983
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.765996260
Short name T180
Test name
Test status
Simulation time 62776811264 ps
CPU time 83.12 seconds
Started May 05 01:38:23 PM PDT 24
Finished May 05 01:39:46 PM PDT 24
Peak memory 200420 kb
Host smart-3d9ef35e-dee6-4edc-85dc-54449e38dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765996260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.765996260
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3049266565
Short name T406
Test name
Test status
Simulation time 149079099297 ps
CPU time 264.39 seconds
Started May 05 01:38:21 PM PDT 24
Finished May 05 01:42:46 PM PDT 24
Peak memory 200604 kb
Host smart-2bdcf378-ce9b-44fa-8d62-c61ed8f8bfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049266565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3049266565
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1707602752
Short name T887
Test name
Test status
Simulation time 219729300872 ps
CPU time 54.07 seconds
Started May 05 01:38:22 PM PDT 24
Finished May 05 01:39:17 PM PDT 24
Peak memory 200360 kb
Host smart-870851fb-8b25-4588-ba06-9699542de679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707602752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1707602752
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.649010407
Short name T1040
Test name
Test status
Simulation time 21343346525 ps
CPU time 36.15 seconds
Started May 05 01:38:22 PM PDT 24
Finished May 05 01:38:59 PM PDT 24
Peak memory 200348 kb
Host smart-c7ae0cc5-0aab-40fb-9504-2b0dddbcd84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649010407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.649010407
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3954702322
Short name T138
Test name
Test status
Simulation time 32458413082 ps
CPU time 22.2 seconds
Started May 05 01:38:30 PM PDT 24
Finished May 05 01:38:52 PM PDT 24
Peak memory 200308 kb
Host smart-ae908c8b-4c0e-4b90-b0e9-ad0ef3116d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954702322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3954702322
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.163104557
Short name T422
Test name
Test status
Simulation time 89039715182 ps
CPU time 75.05 seconds
Started May 05 01:38:31 PM PDT 24
Finished May 05 01:39:46 PM PDT 24
Peak memory 200248 kb
Host smart-a23b41e6-8f97-4c5a-a6c7-a4041d7b52e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163104557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.163104557
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2676985885
Short name T1044
Test name
Test status
Simulation time 43753894991 ps
CPU time 15.45 seconds
Started May 05 01:38:28 PM PDT 24
Finished May 05 01:38:44 PM PDT 24
Peak memory 199708 kb
Host smart-5eb2e5fb-0128-4546-a272-8006a1e50c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676985885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2676985885
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.548649777
Short name T508
Test name
Test status
Simulation time 101744852 ps
CPU time 0.56 seconds
Started May 05 01:30:08 PM PDT 24
Finished May 05 01:30:09 PM PDT 24
Peak memory 195768 kb
Host smart-2eaa00dc-6ecd-48ac-918e-31e5e6d459f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548649777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.548649777
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.657819149
Short name T264
Test name
Test status
Simulation time 157134270790 ps
CPU time 241.89 seconds
Started May 05 01:30:01 PM PDT 24
Finished May 05 01:34:04 PM PDT 24
Peak memory 200312 kb
Host smart-c5334864-5fdd-4f76-9071-ebe1959271c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657819149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.657819149
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.4260241487
Short name T755
Test name
Test status
Simulation time 95751904949 ps
CPU time 222.11 seconds
Started May 05 01:30:03 PM PDT 24
Finished May 05 01:33:46 PM PDT 24
Peak memory 200332 kb
Host smart-947f7167-cc03-4842-9784-65e275957cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260241487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4260241487
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.1504381910
Short name T479
Test name
Test status
Simulation time 36338063113 ps
CPU time 64.25 seconds
Started May 05 01:30:12 PM PDT 24
Finished May 05 01:31:16 PM PDT 24
Peak memory 200316 kb
Host smart-774d5e13-6287-44aa-bc57-a7bd87c5e71e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504381910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1504381910
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2641154500
Short name T353
Test name
Test status
Simulation time 86399670159 ps
CPU time 109.99 seconds
Started May 05 01:30:12 PM PDT 24
Finished May 05 01:32:02 PM PDT 24
Peak memory 200296 kb
Host smart-371c8c49-041f-43a3-a474-6a523c4fe355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641154500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2641154500
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.4179859241
Short name T699
Test name
Test status
Simulation time 8969280129 ps
CPU time 4.61 seconds
Started May 05 01:30:12 PM PDT 24
Finished May 05 01:30:17 PM PDT 24
Peak memory 199308 kb
Host smart-e28d9659-3cd5-44bb-8170-bbbbfd8e3566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179859241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4179859241
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1889878349
Short name T780
Test name
Test status
Simulation time 110950270956 ps
CPU time 103.16 seconds
Started May 05 01:30:11 PM PDT 24
Finished May 05 01:31:54 PM PDT 24
Peak memory 200360 kb
Host smart-0e6b52b1-ee25-4046-93f9-757e4a8176f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889878349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1889878349
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4231482155
Short name T987
Test name
Test status
Simulation time 7477420979 ps
CPU time 86.48 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:31:40 PM PDT 24
Peak memory 200404 kb
Host smart-7d8bb9e7-9b31-43d7-9293-48e0273e0b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231482155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4231482155
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2815359165
Short name T842
Test name
Test status
Simulation time 5882238414 ps
CPU time 12.56 seconds
Started May 05 01:30:03 PM PDT 24
Finished May 05 01:30:16 PM PDT 24
Peak memory 198416 kb
Host smart-8b662e5a-5cad-4518-850c-53b0549d20d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815359165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2815359165
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.176788957
Short name T113
Test name
Test status
Simulation time 53610170640 ps
CPU time 45.38 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:30:59 PM PDT 24
Peak memory 200280 kb
Host smart-c28e7d68-2cfd-41a2-b843-3286988147ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176788957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.176788957
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.507949016
Short name T623
Test name
Test status
Simulation time 619732131 ps
CPU time 0.89 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:30:15 PM PDT 24
Peak memory 195748 kb
Host smart-3ae6d0a8-83cb-45b8-b030-b643e216cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507949016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.507949016
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.943980559
Short name T95
Test name
Test status
Simulation time 40332261 ps
CPU time 0.76 seconds
Started May 05 01:30:09 PM PDT 24
Finished May 05 01:30:10 PM PDT 24
Peak memory 218512 kb
Host smart-9296a7da-ccdb-4a33-8f07-213b5a282906
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943980559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.943980559
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2797185301
Short name T1072
Test name
Test status
Simulation time 5903607715 ps
CPU time 8.47 seconds
Started May 05 01:30:04 PM PDT 24
Finished May 05 01:30:13 PM PDT 24
Peak memory 200052 kb
Host smart-01da8cc2-b590-4137-9325-b133be94bd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797185301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2797185301
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3913229340
Short name T546
Test name
Test status
Simulation time 284758780872 ps
CPU time 309.06 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:35:23 PM PDT 24
Peak memory 208880 kb
Host smart-5e19647a-a7e0-4af0-b470-5b7fc9640e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913229340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3913229340
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2579339647
Short name T619
Test name
Test status
Simulation time 317818907765 ps
CPU time 241.11 seconds
Started May 05 01:30:08 PM PDT 24
Finished May 05 01:34:10 PM PDT 24
Peak memory 209292 kb
Host smart-72a8f6d4-5612-4df9-9ff1-82896e6e28b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579339647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2579339647
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1673125245
Short name T274
Test name
Test status
Simulation time 695500594 ps
CPU time 2.87 seconds
Started May 05 01:30:08 PM PDT 24
Finished May 05 01:30:12 PM PDT 24
Peak memory 198812 kb
Host smart-8fe7ff1d-f9fb-49a3-b274-e02724c131c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673125245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1673125245
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3342557760
Short name T614
Test name
Test status
Simulation time 118168083878 ps
CPU time 46.94 seconds
Started May 05 01:30:04 PM PDT 24
Finished May 05 01:30:51 PM PDT 24
Peak memory 200400 kb
Host smart-0e211c0f-5afb-43bd-a36d-5c490545375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342557760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3342557760
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2530366741
Short name T680
Test name
Test status
Simulation time 30935459 ps
CPU time 0.54 seconds
Started May 05 01:32:28 PM PDT 24
Finished May 05 01:32:29 PM PDT 24
Peak memory 195156 kb
Host smart-75334e41-a577-40dd-9878-8150f8fd78a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530366741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2530366741
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.754823782
Short name T513
Test name
Test status
Simulation time 35182151583 ps
CPU time 52.86 seconds
Started May 05 01:32:23 PM PDT 24
Finished May 05 01:33:16 PM PDT 24
Peak memory 200328 kb
Host smart-bc635807-0ead-4d29-8ad6-d34b92559dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754823782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.754823782
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2687699156
Short name T686
Test name
Test status
Simulation time 6538495786 ps
CPU time 11.2 seconds
Started May 05 01:32:21 PM PDT 24
Finished May 05 01:32:33 PM PDT 24
Peak memory 200096 kb
Host smart-a382fdd7-c03c-4432-a238-4654ad5ca2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687699156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2687699156
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.4239408086
Short name T902
Test name
Test status
Simulation time 28698425863 ps
CPU time 45.48 seconds
Started May 05 01:32:21 PM PDT 24
Finished May 05 01:33:07 PM PDT 24
Peak memory 198236 kb
Host smart-14a616cf-d4a7-441a-8215-081c1e5b0437
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239408086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4239408086
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.906941637
Short name T700
Test name
Test status
Simulation time 74191420131 ps
CPU time 490.98 seconds
Started May 05 01:32:27 PM PDT 24
Finished May 05 01:40:38 PM PDT 24
Peak memory 200364 kb
Host smart-5f6ebc27-28fc-4666-8b88-ce38cb4a28d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906941637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.906941637
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.4189343273
Short name T339
Test name
Test status
Simulation time 8106926509 ps
CPU time 3.34 seconds
Started May 05 01:32:27 PM PDT 24
Finished May 05 01:32:31 PM PDT 24
Peak memory 200304 kb
Host smart-e3087574-c7fe-4d23-a919-87061ceef9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189343273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4189343273
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.105247141
Short name T1092
Test name
Test status
Simulation time 13049146010 ps
CPU time 26.65 seconds
Started May 05 01:32:21 PM PDT 24
Finished May 05 01:32:48 PM PDT 24
Peak memory 199616 kb
Host smart-7c3a954f-2c30-4bf9-bcd8-65ba371dc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105247141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.105247141
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3767446598
Short name T709
Test name
Test status
Simulation time 11310085892 ps
CPU time 346.77 seconds
Started May 05 01:32:28 PM PDT 24
Finished May 05 01:38:16 PM PDT 24
Peak memory 200320 kb
Host smart-377efb2b-4d4c-41e9-a49b-9b1a7d445f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767446598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3767446598
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.398838972
Short name T1002
Test name
Test status
Simulation time 1290346915 ps
CPU time 1.08 seconds
Started May 05 01:32:21 PM PDT 24
Finished May 05 01:32:22 PM PDT 24
Peak memory 195964 kb
Host smart-e4134fcc-1ddb-44e8-9418-5d6d4345b305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398838972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.398838972
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.478242175
Short name T173
Test name
Test status
Simulation time 186978534660 ps
CPU time 88.45 seconds
Started May 05 01:32:22 PM PDT 24
Finished May 05 01:33:51 PM PDT 24
Peak memory 200384 kb
Host smart-7bb293ea-df8e-47b9-a09e-c2e0f5844095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478242175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.478242175
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3823286784
Short name T622
Test name
Test status
Simulation time 3323589232 ps
CPU time 4.68 seconds
Started May 05 01:32:22 PM PDT 24
Finished May 05 01:32:27 PM PDT 24
Peak memory 196672 kb
Host smart-b2947127-af98-40e5-b5fd-2fb44d67f982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823286784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3823286784
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1828913035
Short name T450
Test name
Test status
Simulation time 501127740 ps
CPU time 2.01 seconds
Started May 05 01:32:19 PM PDT 24
Finished May 05 01:32:21 PM PDT 24
Peak memory 199368 kb
Host smart-df94e33a-f377-41e8-8632-b27a4e61bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828913035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1828913035
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.566029726
Short name T1161
Test name
Test status
Simulation time 229691668933 ps
CPU time 529.27 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:41:21 PM PDT 24
Peak memory 200396 kb
Host smart-5b76fa71-2c9a-4131-8599-73995b3bc71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566029726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.566029726
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1633173094
Short name T1036
Test name
Test status
Simulation time 33970586858 ps
CPU time 453.65 seconds
Started May 05 01:32:27 PM PDT 24
Finished May 05 01:40:01 PM PDT 24
Peak memory 216804 kb
Host smart-8cfad8d8-9bcc-4015-84fa-20f1b802f056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633173094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1633173094
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.60276458
Short name T1154
Test name
Test status
Simulation time 7076589235 ps
CPU time 15.99 seconds
Started May 05 01:32:22 PM PDT 24
Finished May 05 01:32:38 PM PDT 24
Peak memory 199640 kb
Host smart-17954caf-53e5-4945-9e95-d26e47795a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60276458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.60276458
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2305195354
Short name T1064
Test name
Test status
Simulation time 112816746911 ps
CPU time 131.72 seconds
Started May 05 01:32:19 PM PDT 24
Finished May 05 01:34:31 PM PDT 24
Peak memory 200404 kb
Host smart-724a56ff-298a-4c89-92d7-a7a70c163ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305195354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2305195354
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3180497023
Short name T398
Test name
Test status
Simulation time 8282118096 ps
CPU time 13.49 seconds
Started May 05 01:38:27 PM PDT 24
Finished May 05 01:38:41 PM PDT 24
Peak memory 199432 kb
Host smart-afc14715-30d8-4d6b-ac12-94177f3dd499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180497023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3180497023
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3949259451
Short name T1032
Test name
Test status
Simulation time 251197043482 ps
CPU time 313.56 seconds
Started May 05 01:38:30 PM PDT 24
Finished May 05 01:43:44 PM PDT 24
Peak memory 200404 kb
Host smart-a4ca6282-50dc-4126-a32f-15fe9cd5c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949259451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3949259451
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2020753360
Short name T211
Test name
Test status
Simulation time 8885748630 ps
CPU time 9.89 seconds
Started May 05 01:38:28 PM PDT 24
Finished May 05 01:38:38 PM PDT 24
Peak memory 198712 kb
Host smart-097bba43-4eae-4665-9da1-0ac8df6ad716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020753360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2020753360
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2734659178
Short name T764
Test name
Test status
Simulation time 28533265258 ps
CPU time 12.25 seconds
Started May 05 01:38:36 PM PDT 24
Finished May 05 01:38:48 PM PDT 24
Peak memory 200312 kb
Host smart-e3e92ba4-cbaa-42c7-ad6b-ed0f48d4e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734659178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2734659178
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.340153832
Short name T206
Test name
Test status
Simulation time 22614723951 ps
CPU time 50.74 seconds
Started May 05 01:38:34 PM PDT 24
Finished May 05 01:39:25 PM PDT 24
Peak memory 200420 kb
Host smart-50af2d06-48e3-434d-8643-a20efaa5dd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340153832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.340153832
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1296790329
Short name T818
Test name
Test status
Simulation time 7429054775 ps
CPU time 15.14 seconds
Started May 05 01:38:32 PM PDT 24
Finished May 05 01:38:48 PM PDT 24
Peak memory 200420 kb
Host smart-dc1e9e88-11bc-479e-b068-67d573b73d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296790329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1296790329
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2531065968
Short name T809
Test name
Test status
Simulation time 30121622872 ps
CPU time 14.15 seconds
Started May 05 01:38:36 PM PDT 24
Finished May 05 01:38:50 PM PDT 24
Peak memory 200168 kb
Host smart-4e1f44ce-cb3c-460c-bf4d-b6138e9d1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531065968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2531065968
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3720899160
Short name T494
Test name
Test status
Simulation time 12443536 ps
CPU time 0.54 seconds
Started May 05 01:32:35 PM PDT 24
Finished May 05 01:32:36 PM PDT 24
Peak memory 195784 kb
Host smart-57da5242-a4a2-4911-a132-f927cd7b56a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720899160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3720899160
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3355077310
Short name T706
Test name
Test status
Simulation time 573176252935 ps
CPU time 159.06 seconds
Started May 05 01:32:26 PM PDT 24
Finished May 05 01:35:06 PM PDT 24
Peak memory 200364 kb
Host smart-03226203-4343-4a81-9d71-0513e0ba6ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355077310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3355077310
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.542946569
Short name T144
Test name
Test status
Simulation time 60217067035 ps
CPU time 34.96 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:33:06 PM PDT 24
Peak memory 200344 kb
Host smart-62bcf037-4a63-4c14-84be-2f28ea69ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542946569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.542946569
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3940588893
Short name T216
Test name
Test status
Simulation time 23055862339 ps
CPU time 36.49 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:33:08 PM PDT 24
Peak memory 200324 kb
Host smart-abfc8c33-dbe0-4b5d-bc0c-2706f24c3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940588893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3940588893
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.4032185625
Short name T717
Test name
Test status
Simulation time 83667433061 ps
CPU time 60.04 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:33:31 PM PDT 24
Peak memory 196304 kb
Host smart-053f654e-4076-4b02-a009-0127e37df03d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032185625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4032185625
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.26616939
Short name T283
Test name
Test status
Simulation time 49497259912 ps
CPU time 428.48 seconds
Started May 05 01:32:36 PM PDT 24
Finished May 05 01:39:45 PM PDT 24
Peak memory 200416 kb
Host smart-92a7dcc2-9f2f-4566-83f4-a6ebd2416dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26616939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.26616939
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3370190313
Short name T691
Test name
Test status
Simulation time 7969856228 ps
CPU time 14.74 seconds
Started May 05 01:32:30 PM PDT 24
Finished May 05 01:32:45 PM PDT 24
Peak memory 200312 kb
Host smart-9e65c40a-c473-4fe5-b7cd-9c1e6dbc73ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370190313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3370190313
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.884557099
Short name T11
Test name
Test status
Simulation time 75253513909 ps
CPU time 62.82 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:33:34 PM PDT 24
Peak memory 200572 kb
Host smart-58995cac-7141-464c-8532-141d4e69a9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884557099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.884557099
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.836368847
Short name T279
Test name
Test status
Simulation time 10690384812 ps
CPU time 329.02 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:38:01 PM PDT 24
Peak memory 200348 kb
Host smart-b218a6db-38a7-4570-a8c4-dd669ca235fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836368847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.836368847
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2060842200
Short name T329
Test name
Test status
Simulation time 5284277851 ps
CPU time 12.48 seconds
Started May 05 01:32:29 PM PDT 24
Finished May 05 01:32:41 PM PDT 24
Peak memory 198568 kb
Host smart-d1648412-1f13-44b7-bea5-f2816a0c888a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060842200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2060842200
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.546449699
Short name T403
Test name
Test status
Simulation time 21912073361 ps
CPU time 33.65 seconds
Started May 05 01:32:32 PM PDT 24
Finished May 05 01:33:06 PM PDT 24
Peak memory 200208 kb
Host smart-de40c0b8-570f-4ad3-8822-221bfef507a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546449699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.546449699
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3839463798
Short name T629
Test name
Test status
Simulation time 3315379899 ps
CPU time 1.82 seconds
Started May 05 01:32:31 PM PDT 24
Finished May 05 01:32:33 PM PDT 24
Peak memory 196636 kb
Host smart-8506ced1-4fd7-4583-9b12-8b8ab65b720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839463798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3839463798
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2328733377
Short name T356
Test name
Test status
Simulation time 5897589581 ps
CPU time 8.33 seconds
Started May 05 01:32:25 PM PDT 24
Finished May 05 01:32:34 PM PDT 24
Peak memory 200268 kb
Host smart-f74e97a4-6c62-4762-a6b9-e8326fe08a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328733377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2328733377
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2697970751
Short name T782
Test name
Test status
Simulation time 250763314098 ps
CPU time 684.51 seconds
Started May 05 01:32:37 PM PDT 24
Finished May 05 01:44:02 PM PDT 24
Peak memory 208648 kb
Host smart-1dc82b1a-1030-4d21-a3e9-e8ab14365811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697970751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2697970751
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.835910236
Short name T110
Test name
Test status
Simulation time 69652087806 ps
CPU time 182.11 seconds
Started May 05 01:32:37 PM PDT 24
Finished May 05 01:35:39 PM PDT 24
Peak memory 217028 kb
Host smart-eb047f5e-5122-44ca-bb95-cd336402ea85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835910236 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.835910236
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3781661620
Short name T843
Test name
Test status
Simulation time 7991015156 ps
CPU time 10.97 seconds
Started May 05 01:32:32 PM PDT 24
Finished May 05 01:32:43 PM PDT 24
Peak memory 200160 kb
Host smart-ab509e1f-3eaa-4015-a025-7728c214750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781661620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3781661620
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2358366570
Short name T54
Test name
Test status
Simulation time 15923174023 ps
CPU time 14.61 seconds
Started May 05 01:32:29 PM PDT 24
Finished May 05 01:32:44 PM PDT 24
Peak memory 198820 kb
Host smart-947d81d2-a0aa-4abc-8324-bc818802bf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358366570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2358366570
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1891497010
Short name T779
Test name
Test status
Simulation time 4672642165 ps
CPU time 10.33 seconds
Started May 05 01:38:36 PM PDT 24
Finished May 05 01:38:47 PM PDT 24
Peak memory 200372 kb
Host smart-2f225ad2-e25a-40de-99c7-4b5fcbd315f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891497010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1891497010
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1796109895
Short name T612
Test name
Test status
Simulation time 45439708288 ps
CPU time 20.03 seconds
Started May 05 01:38:32 PM PDT 24
Finished May 05 01:38:53 PM PDT 24
Peak memory 200312 kb
Host smart-36d55a11-61d5-4ab4-a8bc-edd714eb5130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796109895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1796109895
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.517530972
Short name T881
Test name
Test status
Simulation time 42413334325 ps
CPU time 20.97 seconds
Started May 05 01:38:35 PM PDT 24
Finished May 05 01:38:57 PM PDT 24
Peak memory 200304 kb
Host smart-a68d13fb-fa07-4581-8914-ef5b42080f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517530972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.517530972
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.256214350
Short name T321
Test name
Test status
Simulation time 21283151804 ps
CPU time 41.8 seconds
Started May 05 01:38:33 PM PDT 24
Finished May 05 01:39:15 PM PDT 24
Peak memory 200264 kb
Host smart-8cd4f626-6574-4edb-a9e1-e5fdaf64b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256214350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.256214350
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3417019046
Short name T1043
Test name
Test status
Simulation time 119698808491 ps
CPU time 56.47 seconds
Started May 05 01:38:33 PM PDT 24
Finished May 05 01:39:30 PM PDT 24
Peak memory 200592 kb
Host smart-0e6e7c84-5ee5-4bed-8bff-42797b6962ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417019046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3417019046
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3017167316
Short name T813
Test name
Test status
Simulation time 44508567337 ps
CPU time 19.67 seconds
Started May 05 01:38:37 PM PDT 24
Finished May 05 01:38:57 PM PDT 24
Peak memory 200276 kb
Host smart-c9ce8877-4238-4b9c-9d76-d1a5d88b577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017167316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3017167316
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3337897455
Short name T541
Test name
Test status
Simulation time 35322428989 ps
CPU time 97.59 seconds
Started May 05 01:38:32 PM PDT 24
Finished May 05 01:40:10 PM PDT 24
Peak memory 200380 kb
Host smart-e50fc5c2-c798-44b7-bb79-fa7618748593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337897455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3337897455
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3347864554
Short name T186
Test name
Test status
Simulation time 74919942836 ps
CPU time 212.3 seconds
Started May 05 01:38:33 PM PDT 24
Finished May 05 01:42:06 PM PDT 24
Peak memory 200380 kb
Host smart-ffc25dd4-ba70-4114-9fec-79d46303a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347864554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3347864554
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2740717414
Short name T34
Test name
Test status
Simulation time 205392030161 ps
CPU time 91.82 seconds
Started May 05 01:38:33 PM PDT 24
Finished May 05 01:40:06 PM PDT 24
Peak memory 200316 kb
Host smart-681d75ab-bd69-452e-bb4e-6d912d8d8177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740717414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2740717414
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2483149264
Short name T865
Test name
Test status
Simulation time 12015508 ps
CPU time 0.54 seconds
Started May 05 01:32:40 PM PDT 24
Finished May 05 01:32:41 PM PDT 24
Peak memory 195784 kb
Host smart-d4385698-337e-494b-9935-765139e26aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483149264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2483149264
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2157980453
Short name T527
Test name
Test status
Simulation time 67275598897 ps
CPU time 28.94 seconds
Started May 05 01:32:38 PM PDT 24
Finished May 05 01:33:07 PM PDT 24
Peak memory 200176 kb
Host smart-5ed1981a-d96e-43df-b81b-c4f2127c071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157980453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2157980453
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2003920363
Short name T768
Test name
Test status
Simulation time 21448093791 ps
CPU time 36.2 seconds
Started May 05 01:32:37 PM PDT 24
Finished May 05 01:33:13 PM PDT 24
Peak memory 200376 kb
Host smart-5a22c393-5418-441e-80f7-f00297ca6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003920363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2003920363
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.609859755
Short name T943
Test name
Test status
Simulation time 265471276705 ps
CPU time 113.55 seconds
Started May 05 01:32:36 PM PDT 24
Finished May 05 01:34:30 PM PDT 24
Peak memory 200356 kb
Host smart-286a50eb-438e-48e1-88f6-7d072dd7c8b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609859755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.609859755
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.848394263
Short name T801
Test name
Test status
Simulation time 83501708303 ps
CPU time 279.66 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:37:21 PM PDT 24
Peak memory 200308 kb
Host smart-6bdbe6c2-cfe7-4a4c-ad46-39fba42f5552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848394263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.848394263
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1427290482
Short name T1108
Test name
Test status
Simulation time 6089331899 ps
CPU time 12.92 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:32:54 PM PDT 24
Peak memory 200084 kb
Host smart-2dd4085c-237a-4789-8ee5-2f1dd612d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427290482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1427290482
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.845231826
Short name T4
Test name
Test status
Simulation time 38291356187 ps
CPU time 28.49 seconds
Started May 05 01:32:36 PM PDT 24
Finished May 05 01:33:05 PM PDT 24
Peak memory 200604 kb
Host smart-56088fd2-ac48-46b7-afd2-2d9cae050222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845231826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.845231826
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2934121595
Short name T657
Test name
Test status
Simulation time 15651489286 ps
CPU time 682.1 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:44:03 PM PDT 24
Peak memory 200400 kb
Host smart-3e5aa330-cbfb-4cde-9f33-cdf9049dc247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934121595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2934121595
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2511479533
Short name T916
Test name
Test status
Simulation time 1405643510 ps
CPU time 1.21 seconds
Started May 05 01:32:39 PM PDT 24
Finished May 05 01:32:40 PM PDT 24
Peak memory 195812 kb
Host smart-a6dbe8f7-c4d0-40aa-8ef6-3ed791869494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511479533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2511479533
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2815270576
Short name T1071
Test name
Test status
Simulation time 52175304822 ps
CPU time 91.56 seconds
Started May 05 01:32:40 PM PDT 24
Finished May 05 01:34:12 PM PDT 24
Peak memory 200408 kb
Host smart-fb5f464e-b832-47a6-af96-3be7bde90562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815270576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2815270576
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2048713971
Short name T924
Test name
Test status
Simulation time 5163313823 ps
CPU time 4.9 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:32:46 PM PDT 24
Peak memory 196672 kb
Host smart-f07ab2dd-3466-483c-978a-16556a0cebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048713971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2048713971
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2772273292
Short name T730
Test name
Test status
Simulation time 308941668 ps
CPU time 0.98 seconds
Started May 05 01:32:37 PM PDT 24
Finished May 05 01:32:39 PM PDT 24
Peak memory 198952 kb
Host smart-a2449350-c895-4d93-8127-d19af58a79e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772273292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2772273292
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3408993267
Short name T1158
Test name
Test status
Simulation time 120877839565 ps
CPU time 434.49 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:39:56 PM PDT 24
Peak memory 217072 kb
Host smart-bf459498-eeea-4ddd-ba11-a4879f0fc4d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408993267 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3408993267
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.644502422
Short name T754
Test name
Test status
Simulation time 6865277207 ps
CPU time 19.72 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:33:01 PM PDT 24
Peak memory 200324 kb
Host smart-2bed7648-97b2-4c8a-9da9-8dcdd15c688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644502422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.644502422
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1098500797
Short name T446
Test name
Test status
Simulation time 127785350625 ps
CPU time 85.37 seconds
Started May 05 01:32:36 PM PDT 24
Finished May 05 01:34:02 PM PDT 24
Peak memory 200356 kb
Host smart-506767fe-f20f-4f64-9781-dd26fdfe5ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098500797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1098500797
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3526190677
Short name T962
Test name
Test status
Simulation time 106739572460 ps
CPU time 196.33 seconds
Started May 05 01:38:32 PM PDT 24
Finished May 05 01:41:49 PM PDT 24
Peak memory 200240 kb
Host smart-36aaab48-35d2-4be5-93ca-8c4ef1369d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526190677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3526190677
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.4230659819
Short name T1107
Test name
Test status
Simulation time 17621658973 ps
CPU time 8.08 seconds
Started May 05 01:38:38 PM PDT 24
Finished May 05 01:38:47 PM PDT 24
Peak memory 200136 kb
Host smart-4ed00ae3-d4b4-40e2-ba71-88ba48fef186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230659819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4230659819
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3221980558
Short name T599
Test name
Test status
Simulation time 175384124736 ps
CPU time 132.33 seconds
Started May 05 01:38:40 PM PDT 24
Finished May 05 01:40:53 PM PDT 24
Peak memory 200300 kb
Host smart-0c7faccc-816a-475a-911a-7027cd5ccf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221980558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3221980558
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3322305582
Short name T1070
Test name
Test status
Simulation time 172967814112 ps
CPU time 153.5 seconds
Started May 05 01:38:37 PM PDT 24
Finished May 05 01:41:11 PM PDT 24
Peak memory 200300 kb
Host smart-d1ab32f9-6554-441b-b649-22d2a6c28d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322305582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3322305582
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1892642611
Short name T96
Test name
Test status
Simulation time 50022344858 ps
CPU time 76.93 seconds
Started May 05 01:38:38 PM PDT 24
Finished May 05 01:39:56 PM PDT 24
Peak memory 200288 kb
Host smart-b7d7b5f5-81ac-4903-99d4-646b5e36a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892642611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1892642611
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2822564206
Short name T802
Test name
Test status
Simulation time 109812787918 ps
CPU time 231.94 seconds
Started May 05 01:38:39 PM PDT 24
Finished May 05 01:42:31 PM PDT 24
Peak memory 200336 kb
Host smart-26672d78-4904-41a1-ae6c-6850ca94d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822564206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2822564206
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2952057455
Short name T44
Test name
Test status
Simulation time 29763142386 ps
CPU time 33.45 seconds
Started May 05 01:38:38 PM PDT 24
Finished May 05 01:39:12 PM PDT 24
Peak memory 200372 kb
Host smart-a444a9d3-152f-4d69-892e-11763a211966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952057455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2952057455
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3679597551
Short name T431
Test name
Test status
Simulation time 110621087777 ps
CPU time 49.16 seconds
Started May 05 01:38:45 PM PDT 24
Finished May 05 01:39:35 PM PDT 24
Peak memory 200276 kb
Host smart-5f126ac6-385c-435b-84b2-521d41cbb658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679597551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3679597551
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4282949656
Short name T370
Test name
Test status
Simulation time 113580573647 ps
CPU time 153.71 seconds
Started May 05 01:38:42 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 200196 kb
Host smart-16e00c45-1592-4cc6-805b-cc9863e8048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282949656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4282949656
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2664272346
Short name T602
Test name
Test status
Simulation time 19266612 ps
CPU time 0.51 seconds
Started May 05 01:32:51 PM PDT 24
Finished May 05 01:32:52 PM PDT 24
Peak memory 195756 kb
Host smart-cae4906a-48a3-462c-95ac-3c2ab8bc42f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664272346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2664272346
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.4027469016
Short name T595
Test name
Test status
Simulation time 142846943491 ps
CPU time 758.54 seconds
Started May 05 01:32:41 PM PDT 24
Finished May 05 01:45:20 PM PDT 24
Peak memory 200280 kb
Host smart-ed401d01-5949-4d35-a26d-b2c5c98ed91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027469016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.4027469016
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1802533816
Short name T952
Test name
Test status
Simulation time 32341616829 ps
CPU time 57.1 seconds
Started May 05 01:32:48 PM PDT 24
Finished May 05 01:33:45 PM PDT 24
Peak memory 200320 kb
Host smart-6adfc8f8-ba0c-4510-8c38-fa1020840e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802533816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1802533816
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4246515155
Short name T143
Test name
Test status
Simulation time 58329439373 ps
CPU time 91.8 seconds
Started May 05 01:32:46 PM PDT 24
Finished May 05 01:34:18 PM PDT 24
Peak memory 200236 kb
Host smart-2d8975d8-0f2d-4a79-8f0c-4a3bd07068af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246515155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4246515155
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.564805929
Short name T490
Test name
Test status
Simulation time 3967180862 ps
CPU time 1.84 seconds
Started May 05 01:32:46 PM PDT 24
Finished May 05 01:32:48 PM PDT 24
Peak memory 196388 kb
Host smart-299a0a16-3326-4eae-9739-d379731b9cb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564805929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.564805929
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2012591111
Short name T412
Test name
Test status
Simulation time 92290634730 ps
CPU time 761.53 seconds
Started May 05 01:32:51 PM PDT 24
Finished May 05 01:45:33 PM PDT 24
Peak memory 200412 kb
Host smart-db3d6bf0-f9c9-448b-b6a7-32c54c82e11f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012591111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2012591111
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1218614165
Short name T535
Test name
Test status
Simulation time 1289508483 ps
CPU time 2.86 seconds
Started May 05 01:32:53 PM PDT 24
Finished May 05 01:32:57 PM PDT 24
Peak memory 199012 kb
Host smart-80be08b3-3f83-4316-aa90-50c8506f9fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218614165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1218614165
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2963882299
Short name T414
Test name
Test status
Simulation time 62845200612 ps
CPU time 97.29 seconds
Started May 05 01:32:46 PM PDT 24
Finished May 05 01:34:24 PM PDT 24
Peak memory 200452 kb
Host smart-0bf299ca-8698-4799-9b06-9b7e47b76cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963882299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2963882299
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.332280189
Short name T1093
Test name
Test status
Simulation time 5722254976 ps
CPU time 247.16 seconds
Started May 05 01:32:50 PM PDT 24
Finished May 05 01:36:57 PM PDT 24
Peak memory 200340 kb
Host smart-7cfcc31c-31fb-434f-aee0-ca3f0e65bf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332280189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.332280189
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3721406219
Short name T760
Test name
Test status
Simulation time 2243920445 ps
CPU time 3.64 seconds
Started May 05 01:32:46 PM PDT 24
Finished May 05 01:32:50 PM PDT 24
Peak memory 198560 kb
Host smart-a1cd86f1-87c3-4240-85ba-85f6ff55a322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721406219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3721406219
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3683419562
Short name T291
Test name
Test status
Simulation time 78823959820 ps
CPU time 42.97 seconds
Started May 05 01:32:47 PM PDT 24
Finished May 05 01:33:30 PM PDT 24
Peak memory 200320 kb
Host smart-76cbfb47-4648-44db-a3bf-494c895ef37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683419562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3683419562
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3584537477
Short name T514
Test name
Test status
Simulation time 720059873 ps
CPU time 0.87 seconds
Started May 05 01:32:45 PM PDT 24
Finished May 05 01:32:46 PM PDT 24
Peak memory 195792 kb
Host smart-b2b0f424-8689-45e9-ad81-2f7218c09bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584537477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3584537477
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1252603148
Short name T1065
Test name
Test status
Simulation time 475222598 ps
CPU time 2.43 seconds
Started May 05 01:32:40 PM PDT 24
Finished May 05 01:32:43 PM PDT 24
Peak memory 198588 kb
Host smart-a234fca4-7f0c-482a-87ef-47509145a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252603148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1252603148
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.441602243
Short name T436
Test name
Test status
Simulation time 69834234610 ps
CPU time 104.25 seconds
Started May 05 01:32:51 PM PDT 24
Finished May 05 01:34:35 PM PDT 24
Peak memory 200408 kb
Host smart-a26b8f9b-7ad4-4c19-942f-e7f4ae1fe56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441602243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.441602243
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1746831289
Short name T53
Test name
Test status
Simulation time 180665846554 ps
CPU time 410.02 seconds
Started May 05 01:32:51 PM PDT 24
Finished May 05 01:39:41 PM PDT 24
Peak memory 225240 kb
Host smart-0568a628-c725-47c7-bf27-192c19971afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746831289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1746831289
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1429358871
Short name T1075
Test name
Test status
Simulation time 2101358473 ps
CPU time 2.17 seconds
Started May 05 01:32:51 PM PDT 24
Finished May 05 01:32:53 PM PDT 24
Peak memory 198936 kb
Host smart-20cf21af-7c6d-4a27-b884-0ad090a0111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429358871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1429358871
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.668479762
Short name T677
Test name
Test status
Simulation time 33418088924 ps
CPU time 10.11 seconds
Started May 05 01:32:42 PM PDT 24
Finished May 05 01:32:53 PM PDT 24
Peak memory 200332 kb
Host smart-92229916-3b7d-40c9-ba1e-abecebc0759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668479762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.668479762
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.155659443
Short name T556
Test name
Test status
Simulation time 23371464843 ps
CPU time 38.33 seconds
Started May 05 01:38:45 PM PDT 24
Finished May 05 01:39:24 PM PDT 24
Peak memory 200348 kb
Host smart-5f251760-6dab-420f-9e52-d8884486b17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155659443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.155659443
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4203601675
Short name T58
Test name
Test status
Simulation time 94471846153 ps
CPU time 71.14 seconds
Started May 05 01:38:46 PM PDT 24
Finished May 05 01:39:57 PM PDT 24
Peak memory 200044 kb
Host smart-3c6bb073-2e70-43aa-860d-058550256b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203601675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4203601675
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3629668455
Short name T217
Test name
Test status
Simulation time 87216715348 ps
CPU time 149.38 seconds
Started May 05 01:38:46 PM PDT 24
Finished May 05 01:41:15 PM PDT 24
Peak memory 200356 kb
Host smart-873a31df-e874-4997-9c63-43cfea78c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629668455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3629668455
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3230978673
Short name T555
Test name
Test status
Simulation time 104580835125 ps
CPU time 44.48 seconds
Started May 05 01:38:43 PM PDT 24
Finished May 05 01:39:27 PM PDT 24
Peak memory 200408 kb
Host smart-a0fb3273-4429-429e-b80d-dd1c1974fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230978673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3230978673
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2633508992
Short name T1
Test name
Test status
Simulation time 131864416235 ps
CPU time 128.23 seconds
Started May 05 01:38:43 PM PDT 24
Finished May 05 01:40:51 PM PDT 24
Peak memory 200388 kb
Host smart-ef7603e6-59c0-4fe3-a5cd-db8abad71364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633508992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2633508992
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1203993628
Short name T386
Test name
Test status
Simulation time 63571875831 ps
CPU time 17.99 seconds
Started May 05 01:38:45 PM PDT 24
Finished May 05 01:39:03 PM PDT 24
Peak memory 200344 kb
Host smart-18b59998-9c02-4575-8d4b-e9999b646b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203993628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1203993628
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2865116121
Short name T545
Test name
Test status
Simulation time 218630360068 ps
CPU time 138.85 seconds
Started May 05 01:38:45 PM PDT 24
Finished May 05 01:41:04 PM PDT 24
Peak memory 200336 kb
Host smart-b5ff990b-2559-4022-8d06-17941cc7f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865116121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2865116121
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1985323236
Short name T442
Test name
Test status
Simulation time 107782002178 ps
CPU time 95.47 seconds
Started May 05 01:38:46 PM PDT 24
Finished May 05 01:40:22 PM PDT 24
Peak memory 200036 kb
Host smart-384232af-66a7-4c54-969a-675adc898988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985323236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1985323236
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2925054510
Short name T747
Test name
Test status
Simulation time 36616918638 ps
CPU time 19.15 seconds
Started May 05 01:38:42 PM PDT 24
Finished May 05 01:39:01 PM PDT 24
Peak memory 200412 kb
Host smart-44691210-8a0e-4e0a-9c32-076c52654d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925054510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2925054510
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.760584068
Short name T488
Test name
Test status
Simulation time 37245098 ps
CPU time 0.56 seconds
Started May 05 01:32:56 PM PDT 24
Finished May 05 01:32:57 PM PDT 24
Peak memory 194760 kb
Host smart-2c0e7e7f-f835-459a-815a-3b9a2f78f4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760584068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.760584068
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1266990928
Short name T696
Test name
Test status
Simulation time 235745338247 ps
CPU time 553.51 seconds
Started May 05 01:32:50 PM PDT 24
Finished May 05 01:42:04 PM PDT 24
Peak memory 200356 kb
Host smart-14530a24-849e-44ab-9c8e-78494a1b5a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266990928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1266990928
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2608071844
Short name T995
Test name
Test status
Simulation time 129830725225 ps
CPU time 48.64 seconds
Started May 05 01:32:53 PM PDT 24
Finished May 05 01:33:42 PM PDT 24
Peak memory 200340 kb
Host smart-8100d066-6bb0-4e77-98ba-22ca8e98a73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608071844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2608071844
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2266955065
Short name T1136
Test name
Test status
Simulation time 99713641374 ps
CPU time 99.25 seconds
Started May 05 01:32:56 PM PDT 24
Finished May 05 01:34:36 PM PDT 24
Peak memory 200380 kb
Host smart-a190a8df-d82b-43fc-b011-5850b1d01feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266955065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2266955065
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.61360698
Short name T517
Test name
Test status
Simulation time 47555799997 ps
CPU time 15.84 seconds
Started May 05 01:32:56 PM PDT 24
Finished May 05 01:33:12 PM PDT 24
Peak memory 200400 kb
Host smart-fe72bdfb-f2a6-40f4-a32c-d86a007dc5b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61360698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.61360698
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3495282783
Short name T104
Test name
Test status
Simulation time 126243939941 ps
CPU time 405.23 seconds
Started May 05 01:32:58 PM PDT 24
Finished May 05 01:39:44 PM PDT 24
Peak memory 200396 kb
Host smart-df53fb3a-6575-4303-86c8-50ef4c4cfa4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495282783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3495282783
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.259494592
Short name T857
Test name
Test status
Simulation time 6854170749 ps
CPU time 2.79 seconds
Started May 05 01:32:55 PM PDT 24
Finished May 05 01:32:58 PM PDT 24
Peak memory 198444 kb
Host smart-3a78d608-7792-4fce-bd94-3a9eea7cb783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259494592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.259494592
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2840830915
Short name T854
Test name
Test status
Simulation time 9468691135 ps
CPU time 15.04 seconds
Started May 05 01:32:55 PM PDT 24
Finished May 05 01:33:10 PM PDT 24
Peak memory 200504 kb
Host smart-942d1ae5-79af-4c1d-a3c3-a297155cf20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840830915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2840830915
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.919158729
Short name T405
Test name
Test status
Simulation time 5691172951 ps
CPU time 33.13 seconds
Started May 05 01:32:55 PM PDT 24
Finished May 05 01:33:29 PM PDT 24
Peak memory 200292 kb
Host smart-730e8df4-88ed-4653-bc44-5f60eb09335d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919158729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.919158729
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1723612891
Short name T937
Test name
Test status
Simulation time 7364801006 ps
CPU time 32.64 seconds
Started May 05 01:32:56 PM PDT 24
Finished May 05 01:33:30 PM PDT 24
Peak memory 200300 kb
Host smart-15f5e628-5848-4efc-9506-b08e9d1210e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723612891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1723612891
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3178684985
Short name T927
Test name
Test status
Simulation time 202501876908 ps
CPU time 337.29 seconds
Started May 05 01:32:55 PM PDT 24
Finished May 05 01:38:33 PM PDT 24
Peak memory 200380 kb
Host smart-3b12b22e-7ae5-4c74-b917-6b9dc1fc6c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178684985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3178684985
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3434916392
Short name T891
Test name
Test status
Simulation time 6445812444 ps
CPU time 5.92 seconds
Started May 05 01:32:57 PM PDT 24
Finished May 05 01:33:03 PM PDT 24
Peak memory 196416 kb
Host smart-0268f698-7d2d-4051-86f1-28f9ef7104c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434916392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3434916392
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2474635133
Short name T421
Test name
Test status
Simulation time 940445543 ps
CPU time 4.19 seconds
Started May 05 01:32:50 PM PDT 24
Finished May 05 01:32:54 PM PDT 24
Peak memory 199848 kb
Host smart-a4ab9c9d-9ed6-4000-8577-852eaa7e64e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474635133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2474635133
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.4206885043
Short name T473
Test name
Test status
Simulation time 194815393069 ps
CPU time 1197.81 seconds
Started May 05 01:32:55 PM PDT 24
Finished May 05 01:52:54 PM PDT 24
Peak memory 200296 kb
Host smart-bed0da51-f124-426f-8d42-41d4519cdf47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206885043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4206885043
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3665515874
Short name T430
Test name
Test status
Simulation time 239137292219 ps
CPU time 429.86 seconds
Started May 05 01:32:54 PM PDT 24
Finished May 05 01:40:04 PM PDT 24
Peak memory 217012 kb
Host smart-c8e2f0d9-c6b0-4fc9-936d-d3f44a284fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665515874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3665515874
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1250911917
Short name T953
Test name
Test status
Simulation time 6503819154 ps
CPU time 21 seconds
Started May 05 01:32:56 PM PDT 24
Finished May 05 01:33:18 PM PDT 24
Peak memory 200236 kb
Host smart-8d7d9ba2-5b58-4d44-8210-b7d9143fc435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250911917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1250911917
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4174667888
Short name T597
Test name
Test status
Simulation time 31674440167 ps
CPU time 31.61 seconds
Started May 05 01:32:50 PM PDT 24
Finished May 05 01:33:22 PM PDT 24
Peak memory 200340 kb
Host smart-860f9d98-7352-4b58-a7ab-e779c69fbcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174667888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4174667888
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.4097012599
Short name T322
Test name
Test status
Simulation time 11431161232 ps
CPU time 5.62 seconds
Started May 05 01:38:45 PM PDT 24
Finished May 05 01:38:52 PM PDT 24
Peak memory 200240 kb
Host smart-650d5b01-89f6-4364-92a2-75d08ac18d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097012599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4097012599
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1448759478
Short name T224
Test name
Test status
Simulation time 141723845414 ps
CPU time 194.57 seconds
Started May 05 01:38:49 PM PDT 24
Finished May 05 01:42:04 PM PDT 24
Peak memory 200336 kb
Host smart-acc4206f-7cde-406d-a00a-fbfd422544c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448759478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1448759478
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3896430274
Short name T969
Test name
Test status
Simulation time 193254219447 ps
CPU time 32.21 seconds
Started May 05 01:38:48 PM PDT 24
Finished May 05 01:39:20 PM PDT 24
Peak memory 200344 kb
Host smart-cde0d486-679b-4034-972d-09e97365d5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896430274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3896430274
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3828431136
Short name T195
Test name
Test status
Simulation time 55814909753 ps
CPU time 38.12 seconds
Started May 05 01:38:47 PM PDT 24
Finished May 05 01:39:26 PM PDT 24
Peak memory 200192 kb
Host smart-7c1a196d-11e9-479b-b647-7a3e43cb52bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828431136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3828431136
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.824641046
Short name T1172
Test name
Test status
Simulation time 28184603917 ps
CPU time 27.21 seconds
Started May 05 01:38:46 PM PDT 24
Finished May 05 01:39:14 PM PDT 24
Peak memory 200388 kb
Host smart-9d0cbc2c-3788-40b7-b8b8-17d0c918465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824641046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.824641046
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1395306983
Short name T1175
Test name
Test status
Simulation time 124638193558 ps
CPU time 198.6 seconds
Started May 05 01:38:47 PM PDT 24
Finished May 05 01:42:06 PM PDT 24
Peak memory 200336 kb
Host smart-f32427b3-3f41-4865-ac7c-28d6c952805d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395306983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1395306983
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1496168706
Short name T153
Test name
Test status
Simulation time 63255386314 ps
CPU time 28.58 seconds
Started May 05 01:38:47 PM PDT 24
Finished May 05 01:39:16 PM PDT 24
Peak memory 200356 kb
Host smart-85bc5957-f14a-4eff-9551-3c94ca4ea259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496168706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1496168706
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4075938142
Short name T911
Test name
Test status
Simulation time 44483896074 ps
CPU time 50.05 seconds
Started May 05 01:38:49 PM PDT 24
Finished May 05 01:39:39 PM PDT 24
Peak memory 200304 kb
Host smart-914848b4-c551-4da9-a16c-de10ba9ae3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075938142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4075938142
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.823314250
Short name T435
Test name
Test status
Simulation time 43472217564 ps
CPU time 69.37 seconds
Started May 05 01:38:48 PM PDT 24
Finished May 05 01:39:58 PM PDT 24
Peak memory 200380 kb
Host smart-224147ca-78d0-420e-9f3b-20fc647d4aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823314250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.823314250
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1488584379
Short name T957
Test name
Test status
Simulation time 23491969 ps
CPU time 0.55 seconds
Started May 05 01:33:05 PM PDT 24
Finished May 05 01:33:06 PM PDT 24
Peak memory 195720 kb
Host smart-fccef159-dc4f-4615-af8f-fe5c566f67f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488584379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1488584379
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.344147604
Short name T810
Test name
Test status
Simulation time 72594868676 ps
CPU time 284.47 seconds
Started May 05 01:33:02 PM PDT 24
Finished May 05 01:37:47 PM PDT 24
Peak memory 200340 kb
Host smart-83723b02-ca96-4077-a969-599709744fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344147604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.344147604
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.112630212
Short name T774
Test name
Test status
Simulation time 144858492714 ps
CPU time 128.51 seconds
Started May 05 01:33:00 PM PDT 24
Finished May 05 01:35:09 PM PDT 24
Peak memory 200360 kb
Host smart-9609f884-7efb-47fe-ac9a-68be43d8af7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112630212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.112630212
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1773392024
Short name T1085
Test name
Test status
Simulation time 102003554206 ps
CPU time 47.5 seconds
Started May 05 01:33:02 PM PDT 24
Finished May 05 01:33:50 PM PDT 24
Peak memory 200332 kb
Host smart-351d2753-2a44-43d7-b61a-23c11d2baf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773392024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1773392024
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.438012963
Short name T341
Test name
Test status
Simulation time 30164560012 ps
CPU time 37.48 seconds
Started May 05 01:33:02 PM PDT 24
Finished May 05 01:33:40 PM PDT 24
Peak memory 200404 kb
Host smart-62133ac8-f2dc-4187-a379-cbc17cf20ccc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438012963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.438012963
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.537961438
Short name T794
Test name
Test status
Simulation time 129909292339 ps
CPU time 974.24 seconds
Started May 05 01:33:06 PM PDT 24
Finished May 05 01:49:21 PM PDT 24
Peak memory 200324 kb
Host smart-6efe4ab8-a850-4996-83d8-f16f7a4ea703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537961438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.537961438
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.4281633919
Short name T620
Test name
Test status
Simulation time 7924702755 ps
CPU time 10.65 seconds
Started May 05 01:33:04 PM PDT 24
Finished May 05 01:33:15 PM PDT 24
Peak memory 200344 kb
Host smart-ce28d8f1-a636-4596-a4fc-975c42345ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281633919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4281633919
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2084283766
Short name T874
Test name
Test status
Simulation time 5739486058 ps
CPU time 2.93 seconds
Started May 05 01:33:01 PM PDT 24
Finished May 05 01:33:04 PM PDT 24
Peak memory 200304 kb
Host smart-845c66ad-11ca-4ec0-9fad-bb9fdc50e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084283766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2084283766
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3867284263
Short name T899
Test name
Test status
Simulation time 13202006826 ps
CPU time 227.31 seconds
Started May 05 01:33:05 PM PDT 24
Finished May 05 01:36:53 PM PDT 24
Peak memory 200384 kb
Host smart-12f3702e-c586-4f5b-8ad2-d7aebd630b0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867284263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3867284263
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.165652148
Short name T682
Test name
Test status
Simulation time 6111104663 ps
CPU time 6.95 seconds
Started May 05 01:33:01 PM PDT 24
Finished May 05 01:33:08 PM PDT 24
Peak memory 199620 kb
Host smart-03c0d238-b7fd-4700-93fd-0c86d105d754
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165652148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.165652148
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2481623918
Short name T698
Test name
Test status
Simulation time 59359476599 ps
CPU time 53.89 seconds
Started May 05 01:33:06 PM PDT 24
Finished May 05 01:34:01 PM PDT 24
Peak memory 200348 kb
Host smart-ff14eb89-d122-49a5-b118-6f5641cf5633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481623918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2481623918
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1234913722
Short name T298
Test name
Test status
Simulation time 30477721074 ps
CPU time 25.43 seconds
Started May 05 01:33:00 PM PDT 24
Finished May 05 01:33:26 PM PDT 24
Peak memory 196332 kb
Host smart-9823812d-efca-4f9a-a7c0-f440968838b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234913722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1234913722
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1379607227
Short name T825
Test name
Test status
Simulation time 484590887 ps
CPU time 1.46 seconds
Started May 05 01:33:00 PM PDT 24
Finished May 05 01:33:02 PM PDT 24
Peak memory 200212 kb
Host smart-e1a7c993-02c0-470e-83da-c49d2314f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379607227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1379607227
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3136154872
Short name T269
Test name
Test status
Simulation time 214736117105 ps
CPU time 579 seconds
Started May 05 01:33:07 PM PDT 24
Finished May 05 01:42:47 PM PDT 24
Peak memory 200404 kb
Host smart-38e71874-4c50-44d6-bae3-fd20c7a88463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136154872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3136154872
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3920525341
Short name T50
Test name
Test status
Simulation time 78856722910 ps
CPU time 1031.02 seconds
Started May 05 01:33:04 PM PDT 24
Finished May 05 01:50:15 PM PDT 24
Peak memory 216832 kb
Host smart-1a4f7a45-1e25-42f6-baf0-587a106d7e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920525341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3920525341
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1214025694
Short name T388
Test name
Test status
Simulation time 1141604792 ps
CPU time 3.59 seconds
Started May 05 01:33:06 PM PDT 24
Finished May 05 01:33:10 PM PDT 24
Peak memory 198780 kb
Host smart-185eead1-626b-4405-9984-4759056b1b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214025694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1214025694
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.686897288
Short name T548
Test name
Test status
Simulation time 67338339362 ps
CPU time 114.6 seconds
Started May 05 01:33:02 PM PDT 24
Finished May 05 01:34:57 PM PDT 24
Peak memory 200544 kb
Host smart-548eb620-20c4-4fa8-a3f5-42f8ee4e885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686897288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.686897288
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4197578616
Short name T360
Test name
Test status
Simulation time 110209750664 ps
CPU time 179.72 seconds
Started May 05 01:38:48 PM PDT 24
Finished May 05 01:41:48 PM PDT 24
Peak memory 200344 kb
Host smart-bf64ed36-f7ca-4233-9bb2-56beb035acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197578616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4197578616
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3161496987
Short name T950
Test name
Test status
Simulation time 92940972424 ps
CPU time 75.74 seconds
Started May 05 01:38:57 PM PDT 24
Finished May 05 01:40:14 PM PDT 24
Peak memory 200440 kb
Host smart-b7ca27cf-d81c-4e17-8eb8-cc1b49faae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161496987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3161496987
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1931271612
Short name T1131
Test name
Test status
Simulation time 82792660308 ps
CPU time 82.07 seconds
Started May 05 01:38:54 PM PDT 24
Finished May 05 01:40:16 PM PDT 24
Peak memory 200404 kb
Host smart-0cb06332-917f-42a2-96de-d22aaa71e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931271612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1931271612
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.381057680
Short name T771
Test name
Test status
Simulation time 84161932145 ps
CPU time 35.31 seconds
Started May 05 01:38:54 PM PDT 24
Finished May 05 01:39:30 PM PDT 24
Peak memory 200364 kb
Host smart-a1d0f9af-5454-4141-af22-4a823df792a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381057680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.381057680
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1656537888
Short name T154
Test name
Test status
Simulation time 28260221566 ps
CPU time 45.94 seconds
Started May 05 01:38:53 PM PDT 24
Finished May 05 01:39:39 PM PDT 24
Peak memory 200344 kb
Host smart-3e9231dc-a021-48d0-b7e5-cad692759d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656537888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1656537888
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2702960040
Short name T1046
Test name
Test status
Simulation time 136905936348 ps
CPU time 50.96 seconds
Started May 05 01:38:54 PM PDT 24
Finished May 05 01:39:46 PM PDT 24
Peak memory 200332 kb
Host smart-227c320c-de1a-4279-84dc-8c50b7a79fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702960040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2702960040
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1899179422
Short name T831
Test name
Test status
Simulation time 41010051290 ps
CPU time 15.09 seconds
Started May 05 01:38:53 PM PDT 24
Finished May 05 01:39:09 PM PDT 24
Peak memory 200376 kb
Host smart-4c5d8156-1cf1-4d92-b8d4-e343b0b34255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899179422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1899179422
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3536657718
Short name T413
Test name
Test status
Simulation time 11939787180 ps
CPU time 21.76 seconds
Started May 05 01:38:53 PM PDT 24
Finished May 05 01:39:15 PM PDT 24
Peak memory 200424 kb
Host smart-b66cafb9-d8d2-4f3d-b153-7517c03c8252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536657718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3536657718
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3077597425
Short name T456
Test name
Test status
Simulation time 47239281 ps
CPU time 0.51 seconds
Started May 05 01:33:15 PM PDT 24
Finished May 05 01:33:16 PM PDT 24
Peak memory 194932 kb
Host smart-0cf2a87e-2018-44da-9652-7935b9d8203b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077597425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3077597425
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.855222003
Short name T168
Test name
Test status
Simulation time 95112109093 ps
CPU time 82.78 seconds
Started May 05 01:33:05 PM PDT 24
Finished May 05 01:34:29 PM PDT 24
Peak memory 200332 kb
Host smart-6d56d6eb-804f-4f1c-988e-1ec0fc62556b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855222003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.855222003
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1194875128
Short name T929
Test name
Test status
Simulation time 195635509679 ps
CPU time 288.45 seconds
Started May 05 01:33:06 PM PDT 24
Finished May 05 01:37:55 PM PDT 24
Peak memory 200320 kb
Host smart-741c2cea-1260-4b49-a263-9d7aae2e9987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194875128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1194875128
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.4018980360
Short name T199
Test name
Test status
Simulation time 39473336189 ps
CPU time 96.11 seconds
Started May 05 01:33:05 PM PDT 24
Finished May 05 01:34:42 PM PDT 24
Peak memory 200340 kb
Host smart-7e51d76c-c8fa-42de-acea-5107e1b5065d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018980360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4018980360
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.624200333
Short name T379
Test name
Test status
Simulation time 22003277352 ps
CPU time 18.44 seconds
Started May 05 01:33:11 PM PDT 24
Finished May 05 01:33:29 PM PDT 24
Peak memory 197368 kb
Host smart-6009d0d1-f8cc-4d6c-b944-df7cc374c254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624200333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.624200333
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1572144324
Short name T255
Test name
Test status
Simulation time 95392935389 ps
CPU time 969.35 seconds
Started May 05 01:33:16 PM PDT 24
Finished May 05 01:49:26 PM PDT 24
Peak memory 200400 kb
Host smart-e06fc263-763e-48be-bc6f-5d3bfaeb0ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572144324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1572144324
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3896980078
Short name T1052
Test name
Test status
Simulation time 4495753916 ps
CPU time 5.13 seconds
Started May 05 01:33:11 PM PDT 24
Finished May 05 01:33:16 PM PDT 24
Peak memory 199456 kb
Host smart-3d0b95fb-0a35-4ffd-920e-ff8a4447c411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896980078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3896980078
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3795908001
Short name T518
Test name
Test status
Simulation time 115513738188 ps
CPU time 175.52 seconds
Started May 05 01:33:11 PM PDT 24
Finished May 05 01:36:07 PM PDT 24
Peak memory 200308 kb
Host smart-a069f405-a104-45bf-83c4-61f5a99d5a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795908001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3795908001
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1046852399
Short name T1042
Test name
Test status
Simulation time 19590347624 ps
CPU time 291.67 seconds
Started May 05 01:33:12 PM PDT 24
Finished May 05 01:38:04 PM PDT 24
Peak memory 200588 kb
Host smart-5ec349cf-65b3-48c5-b65e-9747bdf4f3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046852399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1046852399
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1069526773
Short name T600
Test name
Test status
Simulation time 2446124771 ps
CPU time 8.65 seconds
Started May 05 01:33:10 PM PDT 24
Finished May 05 01:33:19 PM PDT 24
Peak memory 198516 kb
Host smart-d6b97b4b-652c-46bc-b238-ea9679fae5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069526773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1069526773
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1700367739
Short name T938
Test name
Test status
Simulation time 367485792332 ps
CPU time 52.13 seconds
Started May 05 01:33:09 PM PDT 24
Finished May 05 01:34:02 PM PDT 24
Peak memory 200344 kb
Host smart-8b100cc5-6fcd-451e-a38f-78db92b9a27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700367739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1700367739
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.39719869
Short name T416
Test name
Test status
Simulation time 4286133048 ps
CPU time 4.39 seconds
Started May 05 01:33:10 PM PDT 24
Finished May 05 01:33:15 PM PDT 24
Peak memory 196668 kb
Host smart-4ef9fc79-48b0-40c5-ad42-39830e46490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39719869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.39719869
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2638975277
Short name T1038
Test name
Test status
Simulation time 11073471041 ps
CPU time 14.6 seconds
Started May 05 01:33:06 PM PDT 24
Finished May 05 01:33:21 PM PDT 24
Peak memory 200292 kb
Host smart-59f854bb-a9ba-4616-a79f-012436eab22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638975277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2638975277
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3032112091
Short name T732
Test name
Test status
Simulation time 137256254181 ps
CPU time 110 seconds
Started May 05 01:33:10 PM PDT 24
Finished May 05 01:35:01 PM PDT 24
Peak memory 208796 kb
Host smart-cfe0f85d-6a89-4a6e-a2f4-083cb273048a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032112091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3032112091
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2999793901
Short name T991
Test name
Test status
Simulation time 135827993473 ps
CPU time 388.1 seconds
Started May 05 01:33:11 PM PDT 24
Finished May 05 01:39:40 PM PDT 24
Peak memory 211092 kb
Host smart-e7f87bf5-7f9b-4953-bbb2-943a77d6bd60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999793901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2999793901
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3022651664
Short name T772
Test name
Test status
Simulation time 1709975616 ps
CPU time 2.23 seconds
Started May 05 01:33:12 PM PDT 24
Finished May 05 01:33:14 PM PDT 24
Peak memory 198816 kb
Host smart-246f94a7-3ae6-40cd-958e-6a278b0c77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022651664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3022651664
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3840685695
Short name T563
Test name
Test status
Simulation time 12362234765 ps
CPU time 14.64 seconds
Started May 05 01:33:06 PM PDT 24
Finished May 05 01:33:21 PM PDT 24
Peak memory 200408 kb
Host smart-a80c00ba-58cf-4397-8e8d-629daaf57887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840685695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3840685695
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.6729999
Short name T997
Test name
Test status
Simulation time 283186194342 ps
CPU time 75.62 seconds
Started May 05 01:38:54 PM PDT 24
Finished May 05 01:40:10 PM PDT 24
Peak memory 200368 kb
Host smart-cbfa1807-0362-4982-abf2-0c963c9c601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6729999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.6729999
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1741957729
Short name T1048
Test name
Test status
Simulation time 72812778096 ps
CPU time 33.35 seconds
Started May 05 01:38:57 PM PDT 24
Finished May 05 01:39:31 PM PDT 24
Peak memory 200328 kb
Host smart-badc6f38-5929-443d-b7f0-8e0baa0f267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741957729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1741957729
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.207508647
Short name T770
Test name
Test status
Simulation time 58772969368 ps
CPU time 44.75 seconds
Started May 05 01:39:00 PM PDT 24
Finished May 05 01:39:45 PM PDT 24
Peak memory 200380 kb
Host smart-458286ba-363d-47c6-9137-608b80e6300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207508647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.207508647
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3846231694
Short name T871
Test name
Test status
Simulation time 70797936101 ps
CPU time 146.85 seconds
Started May 05 01:38:59 PM PDT 24
Finished May 05 01:41:26 PM PDT 24
Peak memory 200348 kb
Host smart-0e779951-bd3e-404c-8774-4fe8f2598042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846231694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3846231694
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3654450698
Short name T1035
Test name
Test status
Simulation time 97788195090 ps
CPU time 47.21 seconds
Started May 05 01:38:58 PM PDT 24
Finished May 05 01:39:46 PM PDT 24
Peak memory 200344 kb
Host smart-48f2e9b9-7547-43be-8fc9-3a63aa55ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654450698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3654450698
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2959554372
Short name T201
Test name
Test status
Simulation time 36110762222 ps
CPU time 49.83 seconds
Started May 05 01:38:57 PM PDT 24
Finished May 05 01:39:48 PM PDT 24
Peak memory 200356 kb
Host smart-3f39df1b-6c8c-4e1d-bee0-4bf96812559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959554372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2959554372
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3824325550
Short name T188
Test name
Test status
Simulation time 22788097672 ps
CPU time 37.23 seconds
Started May 05 01:38:57 PM PDT 24
Finished May 05 01:39:35 PM PDT 24
Peak memory 200400 kb
Host smart-5b5b48e1-386d-4374-aaf8-1a26441ba081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824325550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3824325550
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3384004853
Short name T875
Test name
Test status
Simulation time 125410693235 ps
CPU time 77.2 seconds
Started May 05 01:38:59 PM PDT 24
Finished May 05 01:40:16 PM PDT 24
Peak memory 200368 kb
Host smart-6a137839-0317-451d-adac-49d1fbf8841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384004853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3384004853
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.73667428
Short name T18
Test name
Test status
Simulation time 11359310 ps
CPU time 0.54 seconds
Started May 05 01:33:21 PM PDT 24
Finished May 05 01:33:22 PM PDT 24
Peak memory 195752 kb
Host smart-77286c16-9a57-4b58-85b6-0aae9be42bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73667428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.73667428
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1689645519
Short name T669
Test name
Test status
Simulation time 69815950227 ps
CPU time 36.85 seconds
Started May 05 01:33:14 PM PDT 24
Finished May 05 01:33:52 PM PDT 24
Peak memory 200360 kb
Host smart-778e204b-4523-41e2-9787-81a73c127416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689645519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1689645519
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.275269108
Short name T362
Test name
Test status
Simulation time 153752390996 ps
CPU time 240.09 seconds
Started May 05 01:33:19 PM PDT 24
Finished May 05 01:37:19 PM PDT 24
Peak memory 200384 kb
Host smart-0fbfb240-18f6-4cc9-9685-c7c6c01d3536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275269108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.275269108
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.150915385
Short name T879
Test name
Test status
Simulation time 60639427799 ps
CPU time 89.77 seconds
Started May 05 01:33:19 PM PDT 24
Finished May 05 01:34:49 PM PDT 24
Peak memory 200288 kb
Host smart-50f50e5b-9ba9-4505-a008-db14f9951ea3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150915385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.150915385
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4217322576
Short name T617
Test name
Test status
Simulation time 109884451461 ps
CPU time 283.49 seconds
Started May 05 01:33:22 PM PDT 24
Finished May 05 01:38:06 PM PDT 24
Peak memory 200380 kb
Host smart-2e8c0c35-23d2-4608-8b40-a3b67485fc33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217322576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4217322576
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1043515865
Short name T423
Test name
Test status
Simulation time 4016390387 ps
CPU time 2.94 seconds
Started May 05 01:33:22 PM PDT 24
Finished May 05 01:33:26 PM PDT 24
Peak memory 199420 kb
Host smart-29542d65-2de0-43ce-ac05-d66bf89b7cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043515865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1043515865
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.376082063
Short name T665
Test name
Test status
Simulation time 187287407078 ps
CPU time 120.11 seconds
Started May 05 01:33:15 PM PDT 24
Finished May 05 01:35:15 PM PDT 24
Peak memory 208764 kb
Host smart-1b32b457-2322-4431-86da-a1f3404d0ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376082063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.376082063
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2351881951
Short name T253
Test name
Test status
Simulation time 15317878005 ps
CPU time 450.24 seconds
Started May 05 01:33:22 PM PDT 24
Finished May 05 01:40:52 PM PDT 24
Peak memory 200304 kb
Host smart-8ebd142b-da75-4412-a5eb-81fe34f989fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351881951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2351881951
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1586205132
Short name T328
Test name
Test status
Simulation time 6536906228 ps
CPU time 15.23 seconds
Started May 05 01:33:19 PM PDT 24
Finished May 05 01:33:34 PM PDT 24
Peak memory 199196 kb
Host smart-c9c00d70-3093-44f0-a4dc-7bb2fe66a3b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586205132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1586205132
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2004972936
Short name T625
Test name
Test status
Simulation time 64780659114 ps
CPU time 107.1 seconds
Started May 05 01:33:15 PM PDT 24
Finished May 05 01:35:03 PM PDT 24
Peak memory 200364 kb
Host smart-570c10b5-8c2a-4a9b-9be3-487977566efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004972936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2004972936
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.649422279
Short name T697
Test name
Test status
Simulation time 82208712755 ps
CPU time 21.56 seconds
Started May 05 01:33:14 PM PDT 24
Finished May 05 01:33:36 PM PDT 24
Peak memory 196368 kb
Host smart-b4a84912-294a-4d97-a00e-a9bdda616710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649422279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.649422279
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.189846656
Short name T949
Test name
Test status
Simulation time 5705021553 ps
CPU time 3.41 seconds
Started May 05 01:33:16 PM PDT 24
Finished May 05 01:33:20 PM PDT 24
Peak memory 200148 kb
Host smart-a72f5721-cca4-4909-bbd4-c5c74d48e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189846656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.189846656
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.355399813
Short name T1056
Test name
Test status
Simulation time 100450515529 ps
CPU time 929.71 seconds
Started May 05 01:33:21 PM PDT 24
Finished May 05 01:48:51 PM PDT 24
Peak memory 200356 kb
Host smart-098ea0fe-378c-461b-b42f-d64c06d65037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355399813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.355399813
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2188096462
Short name T705
Test name
Test status
Simulation time 369662612 ps
CPU time 1.8 seconds
Started May 05 01:33:16 PM PDT 24
Finished May 05 01:33:18 PM PDT 24
Peak memory 199296 kb
Host smart-eef872f8-6307-401f-848e-1c98d26e23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188096462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2188096462
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.580859747
Short name T805
Test name
Test status
Simulation time 53825049870 ps
CPU time 39.97 seconds
Started May 05 01:33:16 PM PDT 24
Finished May 05 01:33:56 PM PDT 24
Peak memory 200280 kb
Host smart-e9ef7feb-6cdf-4218-b818-d585cbfa7380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580859747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.580859747
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1584159449
Short name T716
Test name
Test status
Simulation time 7285490732 ps
CPU time 14.25 seconds
Started May 05 01:39:02 PM PDT 24
Finished May 05 01:39:17 PM PDT 24
Peak memory 200360 kb
Host smart-1ddcd027-fa4b-4e18-b2c9-ca95a34d8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584159449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1584159449
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1533139371
Short name T497
Test name
Test status
Simulation time 48757432322 ps
CPU time 70.29 seconds
Started May 05 01:39:04 PM PDT 24
Finished May 05 01:40:14 PM PDT 24
Peak memory 200144 kb
Host smart-f6749a2b-8182-4959-a1a3-d3db4024ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533139371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1533139371
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3913860163
Short name T542
Test name
Test status
Simulation time 19778486783 ps
CPU time 32.1 seconds
Started May 05 01:39:03 PM PDT 24
Finished May 05 01:39:36 PM PDT 24
Peak memory 200376 kb
Host smart-5306aaa2-bfd2-4b52-9353-9d3f5d84dc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913860163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3913860163
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1952658874
Short name T786
Test name
Test status
Simulation time 9173166008 ps
CPU time 13.63 seconds
Started May 05 01:39:04 PM PDT 24
Finished May 05 01:39:18 PM PDT 24
Peak memory 200388 kb
Host smart-8b022fed-c705-4af7-bd82-c2ed60099187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952658874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1952658874
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3793910417
Short name T1011
Test name
Test status
Simulation time 143999427589 ps
CPU time 152.01 seconds
Started May 05 01:39:02 PM PDT 24
Finished May 05 01:41:35 PM PDT 24
Peak memory 200404 kb
Host smart-790fd59b-871e-4edb-bf0a-f154705e5222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793910417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3793910417
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3133646257
Short name T894
Test name
Test status
Simulation time 15658242273 ps
CPU time 26.12 seconds
Started May 05 01:39:03 PM PDT 24
Finished May 05 01:39:29 PM PDT 24
Peak memory 200368 kb
Host smart-e01cedd0-16b5-4c12-ace3-9944435bde3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133646257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3133646257
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3714136820
Short name T374
Test name
Test status
Simulation time 32008189545 ps
CPU time 57.59 seconds
Started May 05 01:39:03 PM PDT 24
Finished May 05 01:40:01 PM PDT 24
Peak memory 200384 kb
Host smart-54145e62-8223-498e-bc79-ed2457dfb1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714136820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3714136820
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2153997397
Short name T976
Test name
Test status
Simulation time 54661211703 ps
CPU time 50.62 seconds
Started May 05 01:39:08 PM PDT 24
Finished May 05 01:39:59 PM PDT 24
Peak memory 200332 kb
Host smart-d4cfe3f2-7205-47a9-bba2-863ea13269e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153997397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2153997397
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.973557636
Short name T455
Test name
Test status
Simulation time 94859160714 ps
CPU time 41.33 seconds
Started May 05 01:39:08 PM PDT 24
Finished May 05 01:39:50 PM PDT 24
Peak memory 200348 kb
Host smart-cf342a36-91ff-46ea-95b2-c15f99b4b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973557636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.973557636
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3573524429
Short name T381
Test name
Test status
Simulation time 143074239 ps
CPU time 0.54 seconds
Started May 05 01:33:32 PM PDT 24
Finished May 05 01:33:33 PM PDT 24
Peak memory 195744 kb
Host smart-caef7fa2-c205-4bdd-8a7c-c214390acb0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573524429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3573524429
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.546510800
Short name T775
Test name
Test status
Simulation time 155581983678 ps
CPU time 598.86 seconds
Started May 05 01:33:22 PM PDT 24
Finished May 05 01:43:21 PM PDT 24
Peak memory 200356 kb
Host smart-9b9e6126-1ef4-4619-864c-4f5bc2602f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546510800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.546510800
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2073744143
Short name T1101
Test name
Test status
Simulation time 76632187314 ps
CPU time 31.67 seconds
Started May 05 01:33:22 PM PDT 24
Finished May 05 01:33:54 PM PDT 24
Peak memory 200116 kb
Host smart-75227ee9-98f9-42c4-b717-5e02fc4f1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073744143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2073744143
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.2438041779
Short name T308
Test name
Test status
Simulation time 10600095697 ps
CPU time 3.21 seconds
Started May 05 01:33:25 PM PDT 24
Finished May 05 01:33:29 PM PDT 24
Peak memory 198048 kb
Host smart-9383fcaa-91b6-428d-a5fa-7af24d8c397b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438041779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2438041779
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.641728857
Short name T387
Test name
Test status
Simulation time 85431685026 ps
CPU time 853.96 seconds
Started May 05 01:33:26 PM PDT 24
Finished May 05 01:47:40 PM PDT 24
Peak memory 200332 kb
Host smart-988b9532-de44-49ea-abdd-d40b09724df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641728857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.641728857
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1802667289
Short name T1025
Test name
Test status
Simulation time 6502933664 ps
CPU time 6.67 seconds
Started May 05 01:33:25 PM PDT 24
Finished May 05 01:33:32 PM PDT 24
Peak memory 199648 kb
Host smart-308720ac-8566-42af-a838-69fa65ec4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802667289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1802667289
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.817890208
Short name T1163
Test name
Test status
Simulation time 55203313295 ps
CPU time 90.15 seconds
Started May 05 01:33:26 PM PDT 24
Finished May 05 01:34:56 PM PDT 24
Peak memory 208764 kb
Host smart-2cfeff1a-8e94-4c36-8614-c743513f95b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817890208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.817890208
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.127366559
Short name T481
Test name
Test status
Simulation time 13975886741 ps
CPU time 180.12 seconds
Started May 05 01:33:26 PM PDT 24
Finished May 05 01:36:26 PM PDT 24
Peak memory 200412 kb
Host smart-0d3ad8be-a5f1-4177-b6df-e074f8514a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127366559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.127366559
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1439113394
Short name T2
Test name
Test status
Simulation time 7357865999 ps
CPU time 59.58 seconds
Started May 05 01:33:26 PM PDT 24
Finished May 05 01:34:26 PM PDT 24
Peak memory 199040 kb
Host smart-5009e61b-a1ba-421f-bc1e-75b6fce69a84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439113394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1439113394
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.133782426
Short name T158
Test name
Test status
Simulation time 55236365897 ps
CPU time 30.31 seconds
Started May 05 01:33:25 PM PDT 24
Finished May 05 01:33:56 PM PDT 24
Peak memory 200284 kb
Host smart-adb97364-eaec-4684-94a1-75cdb95ea375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133782426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.133782426
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.601083370
Short name T845
Test name
Test status
Simulation time 2758516060 ps
CPU time 4.71 seconds
Started May 05 01:33:26 PM PDT 24
Finished May 05 01:33:31 PM PDT 24
Peak memory 196068 kb
Host smart-4b767e42-2d11-447d-bd3e-26951f571d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601083370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.601083370
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2262991434
Short name T428
Test name
Test status
Simulation time 11649290947 ps
CPU time 8.22 seconds
Started May 05 01:33:22 PM PDT 24
Finished May 05 01:33:30 PM PDT 24
Peak memory 200304 kb
Host smart-1504c4a7-3d53-4038-8a9b-f69d263cf3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262991434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2262991434
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3062197189
Short name T978
Test name
Test status
Simulation time 174805556512 ps
CPU time 533.2 seconds
Started May 05 01:33:25 PM PDT 24
Finished May 05 01:42:19 PM PDT 24
Peak memory 216132 kb
Host smart-96ae8200-6ece-46ea-9a8c-c4e597dda617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062197189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3062197189
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.785143235
Short name T505
Test name
Test status
Simulation time 148625330782 ps
CPU time 497.4 seconds
Started May 05 01:33:25 PM PDT 24
Finished May 05 01:41:43 PM PDT 24
Peak memory 216836 kb
Host smart-2fbb6ab9-bb96-42ab-88c7-c27c8a950108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785143235 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.785143235
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3547654800
Short name T282
Test name
Test status
Simulation time 643473592 ps
CPU time 2.31 seconds
Started May 05 01:33:25 PM PDT 24
Finished May 05 01:33:28 PM PDT 24
Peak memory 198968 kb
Host smart-ab509343-d1cc-45b6-9639-c7e56c692232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547654800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3547654800
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1574475375
Short name T1066
Test name
Test status
Simulation time 166813640724 ps
CPU time 28.51 seconds
Started May 05 01:33:21 PM PDT 24
Finished May 05 01:33:50 PM PDT 24
Peak memory 200412 kb
Host smart-caed8f77-8fc5-4ef7-bda5-9a1791ed6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574475375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1574475375
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2216181859
Short name T1135
Test name
Test status
Simulation time 110741992472 ps
CPU time 131.6 seconds
Started May 05 01:39:06 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 200336 kb
Host smart-71332486-474f-420e-9d63-dee556ebb09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216181859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2216181859
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.923228839
Short name T1045
Test name
Test status
Simulation time 74000065573 ps
CPU time 108.87 seconds
Started May 05 01:39:08 PM PDT 24
Finished May 05 01:40:57 PM PDT 24
Peak memory 200280 kb
Host smart-a6cf6621-d04e-48fb-aced-bd211b6f00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923228839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.923228839
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1571494453
Short name T177
Test name
Test status
Simulation time 204980829551 ps
CPU time 172 seconds
Started May 05 01:39:12 PM PDT 24
Finished May 05 01:42:05 PM PDT 24
Peak memory 200420 kb
Host smart-afe88028-b564-449c-a07f-5d7f8d7db0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571494453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1571494453
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2673498760
Short name T340
Test name
Test status
Simulation time 103063732738 ps
CPU time 146.54 seconds
Started May 05 01:39:09 PM PDT 24
Finished May 05 01:41:36 PM PDT 24
Peak memory 200276 kb
Host smart-46b3c9f5-c6e6-4cd7-92c1-01d3d03cf193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673498760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2673498760
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.644596056
Short name T846
Test name
Test status
Simulation time 82695758183 ps
CPU time 104.12 seconds
Started May 05 01:39:12 PM PDT 24
Finished May 05 01:40:57 PM PDT 24
Peak memory 200448 kb
Host smart-81e528c1-6ef0-439c-9128-e4fa8cb1f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644596056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.644596056
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1428658577
Short name T198
Test name
Test status
Simulation time 75655484920 ps
CPU time 58.26 seconds
Started May 05 01:39:15 PM PDT 24
Finished May 05 01:40:14 PM PDT 24
Peak memory 200296 kb
Host smart-c247fa47-43ea-4464-9ddb-40d5c0351b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428658577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1428658577
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3364431520
Short name T504
Test name
Test status
Simulation time 26079359487 ps
CPU time 29.31 seconds
Started May 05 01:39:12 PM PDT 24
Finished May 05 01:39:42 PM PDT 24
Peak memory 200360 kb
Host smart-9cf3825e-27f0-41b7-9ffa-420262cc9a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364431520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3364431520
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3877432382
Short name T942
Test name
Test status
Simulation time 79959809770 ps
CPU time 99.1 seconds
Started May 05 01:39:12 PM PDT 24
Finished May 05 01:40:51 PM PDT 24
Peak memory 200416 kb
Host smart-b8543df0-6219-43ff-93c6-e44250a679f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877432382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3877432382
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4034638444
Short name T736
Test name
Test status
Simulation time 14690829 ps
CPU time 0.57 seconds
Started May 05 01:33:39 PM PDT 24
Finished May 05 01:33:40 PM PDT 24
Peak memory 195760 kb
Host smart-a2d4e613-210f-4029-9305-9fe43150a3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034638444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4034638444
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3801007013
Short name T1130
Test name
Test status
Simulation time 108427413880 ps
CPU time 258.78 seconds
Started May 05 01:33:30 PM PDT 24
Finished May 05 01:37:49 PM PDT 24
Peak memory 200280 kb
Host smart-13948785-7af0-4a66-8a78-285931daf778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801007013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3801007013
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3417247828
Short name T974
Test name
Test status
Simulation time 168446060522 ps
CPU time 250.04 seconds
Started May 05 01:33:30 PM PDT 24
Finished May 05 01:37:40 PM PDT 24
Peak memory 200292 kb
Host smart-95f03d1d-d73c-428f-a7a9-46de1534a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417247828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3417247828
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.4034581676
Short name T1008
Test name
Test status
Simulation time 38750360298 ps
CPU time 128.29 seconds
Started May 05 01:33:36 PM PDT 24
Finished May 05 01:35:45 PM PDT 24
Peak memory 200356 kb
Host smart-837cb6b0-f341-41fd-b542-1276b1e68f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034581676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4034581676
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3737348396
Short name T537
Test name
Test status
Simulation time 12784507674 ps
CPU time 14.41 seconds
Started May 05 01:33:35 PM PDT 24
Finished May 05 01:33:50 PM PDT 24
Peak memory 197396 kb
Host smart-9fb6c7eb-360d-45f9-884b-2b9bc971aee3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737348396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3737348396
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.5892147
Short name T484
Test name
Test status
Simulation time 99622353732 ps
CPU time 836.32 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:47:37 PM PDT 24
Peak memory 200400 kb
Host smart-071d48a6-ac32-4ac5-8832-5eaca8eecbfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5892147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.5892147
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.572628991
Short name T759
Test name
Test status
Simulation time 7411136096 ps
CPU time 7.79 seconds
Started May 05 01:33:35 PM PDT 24
Finished May 05 01:33:43 PM PDT 24
Peak memory 199040 kb
Host smart-96fa4c14-a445-47ec-887a-612bad96e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572628991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.572628991
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.507654986
Short name T389
Test name
Test status
Simulation time 46226529898 ps
CPU time 79.41 seconds
Started May 05 01:33:36 PM PDT 24
Finished May 05 01:34:56 PM PDT 24
Peak memory 200628 kb
Host smart-0a49447f-165c-404d-9573-0b3a76011c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507654986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.507654986
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3012177791
Short name T254
Test name
Test status
Simulation time 11410918521 ps
CPU time 267.7 seconds
Started May 05 01:33:40 PM PDT 24
Finished May 05 01:38:08 PM PDT 24
Peak memory 200384 kb
Host smart-0feb9cb2-7208-4912-823d-a08e644c7ab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012177791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3012177791
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2759999706
Short name T848
Test name
Test status
Simulation time 2123789072 ps
CPU time 13.46 seconds
Started May 05 01:33:36 PM PDT 24
Finished May 05 01:33:50 PM PDT 24
Peak memory 198988 kb
Host smart-1c6ddbb0-7cc8-4de3-ba69-74f20a93c750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759999706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2759999706
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2355984637
Short name T864
Test name
Test status
Simulation time 130588322489 ps
CPU time 61.31 seconds
Started May 05 01:33:35 PM PDT 24
Finished May 05 01:34:37 PM PDT 24
Peak memory 200384 kb
Host smart-e3165fdc-1d40-4c16-ac1d-caa2987ee16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355984637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2355984637
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1856046208
Short name T1156
Test name
Test status
Simulation time 3504589371 ps
CPU time 1.55 seconds
Started May 05 01:33:36 PM PDT 24
Finished May 05 01:33:38 PM PDT 24
Peak memory 196372 kb
Host smart-77bfabb8-4595-417a-971b-c492c955743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856046208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1856046208
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3644209134
Short name T1149
Test name
Test status
Simulation time 5817124390 ps
CPU time 15.6 seconds
Started May 05 01:33:29 PM PDT 24
Finished May 05 01:33:45 PM PDT 24
Peak memory 200092 kb
Host smart-3fe924c9-51ef-4008-89cd-10aa75352e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644209134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3644209134
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.766249027
Short name T438
Test name
Test status
Simulation time 343108734985 ps
CPU time 667 seconds
Started May 05 01:33:45 PM PDT 24
Finished May 05 01:44:53 PM PDT 24
Peak memory 200308 kb
Host smart-46175185-8ba9-4e2a-9b5e-960ee33cf1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766249027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.766249027
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1547192453
Short name T925
Test name
Test status
Simulation time 74050418273 ps
CPU time 177.2 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:36:38 PM PDT 24
Peak memory 215868 kb
Host smart-843c74fb-5538-4c53-8322-c95d2dc90075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547192453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1547192453
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2033344206
Short name T280
Test name
Test status
Simulation time 617718449 ps
CPU time 1.67 seconds
Started May 05 01:33:36 PM PDT 24
Finished May 05 01:33:38 PM PDT 24
Peak memory 199600 kb
Host smart-9f4177fc-1618-495e-9ced-39ffc3fc295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033344206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2033344206
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1763621542
Short name T425
Test name
Test status
Simulation time 20769056923 ps
CPU time 13.49 seconds
Started May 05 01:33:31 PM PDT 24
Finished May 05 01:33:44 PM PDT 24
Peak memory 200416 kb
Host smart-27f2390c-e5c4-41f6-8363-8ebe38b07b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763621542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1763621542
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.552343961
Short name T178
Test name
Test status
Simulation time 196500035767 ps
CPU time 84.95 seconds
Started May 05 01:39:19 PM PDT 24
Finished May 05 01:40:44 PM PDT 24
Peak memory 200332 kb
Host smart-ec6bd64f-a34b-4258-970f-5c62a78834e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552343961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.552343961
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1053876318
Short name T141
Test name
Test status
Simulation time 84320026903 ps
CPU time 38.38 seconds
Started May 05 01:39:17 PM PDT 24
Finished May 05 01:39:55 PM PDT 24
Peak memory 200364 kb
Host smart-88a2512d-0f46-477a-9f34-33e121e6857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053876318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1053876318
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2280498870
Short name T645
Test name
Test status
Simulation time 53323541222 ps
CPU time 114.21 seconds
Started May 05 01:39:16 PM PDT 24
Finished May 05 01:41:11 PM PDT 24
Peak memory 200304 kb
Host smart-133b7fac-a19e-4e80-aa55-3326e4359468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280498870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2280498870
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2310807468
Short name T895
Test name
Test status
Simulation time 21925635432 ps
CPU time 58.15 seconds
Started May 05 01:39:16 PM PDT 24
Finished May 05 01:40:15 PM PDT 24
Peak memory 200364 kb
Host smart-bb9a1c97-ce1c-4209-9a79-d8abd98b22df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310807468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2310807468
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2404981668
Short name T187
Test name
Test status
Simulation time 43130745920 ps
CPU time 17.16 seconds
Started May 05 01:39:18 PM PDT 24
Finished May 05 01:39:35 PM PDT 24
Peak memory 200344 kb
Host smart-1c2efcf8-b15e-456c-9830-4f0113dcfa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404981668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2404981668
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4128804151
Short name T477
Test name
Test status
Simulation time 26736409932 ps
CPU time 12.6 seconds
Started May 05 01:39:16 PM PDT 24
Finished May 05 01:39:29 PM PDT 24
Peak memory 200364 kb
Host smart-1d8c1712-0fe2-4693-b98f-4d7e834be9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128804151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4128804151
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3078291781
Short name T724
Test name
Test status
Simulation time 119933672954 ps
CPU time 50.91 seconds
Started May 05 01:39:17 PM PDT 24
Finished May 05 01:40:08 PM PDT 24
Peak memory 200324 kb
Host smart-72cc5681-6a23-4c1b-b71e-115bc577c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078291781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3078291781
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1444881055
Short name T594
Test name
Test status
Simulation time 85249160007 ps
CPU time 29.66 seconds
Started May 05 01:39:17 PM PDT 24
Finished May 05 01:39:47 PM PDT 24
Peak memory 200408 kb
Host smart-f0051533-9e0c-47f0-80e3-66f6d6e53ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444881055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1444881055
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3302532935
Short name T1119
Test name
Test status
Simulation time 14750552 ps
CPU time 0.56 seconds
Started May 05 01:30:14 PM PDT 24
Finished May 05 01:30:15 PM PDT 24
Peak memory 195764 kb
Host smart-bf3efe3f-0e50-47fd-897d-a803cfb2d6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302532935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3302532935
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.859721438
Short name T499
Test name
Test status
Simulation time 138304474717 ps
CPU time 68.65 seconds
Started May 05 01:30:06 PM PDT 24
Finished May 05 01:31:15 PM PDT 24
Peak memory 200400 kb
Host smart-4e84bd02-86b0-4fd0-9364-61a6b3150488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859721438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.859721438
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3819225151
Short name T392
Test name
Test status
Simulation time 9899013750 ps
CPU time 18.65 seconds
Started May 05 01:30:08 PM PDT 24
Finished May 05 01:30:27 PM PDT 24
Peak memory 200248 kb
Host smart-c70f4537-976b-4167-9a3e-704af7ca4d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819225151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3819225151
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1647764758
Short name T970
Test name
Test status
Simulation time 10762741433 ps
CPU time 17.73 seconds
Started May 05 01:30:09 PM PDT 24
Finished May 05 01:30:27 PM PDT 24
Peak memory 197084 kb
Host smart-60d1ddad-b3ae-4558-b36c-0cfb20ee0621
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647764758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1647764758
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1943231488
Short name T685
Test name
Test status
Simulation time 191542317230 ps
CPU time 502.25 seconds
Started May 05 01:30:14 PM PDT 24
Finished May 05 01:38:37 PM PDT 24
Peak memory 200380 kb
Host smart-997374a7-4687-4f03-a284-f505df44b8bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943231488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1943231488
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.44603498
Short name T1088
Test name
Test status
Simulation time 12283416543 ps
CPU time 13.42 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:30:31 PM PDT 24
Peak memory 200340 kb
Host smart-a30a62bc-7074-4502-8243-fbb48579d182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44603498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.44603498
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.737811525
Short name T847
Test name
Test status
Simulation time 151360733522 ps
CPU time 76.45 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:31:30 PM PDT 24
Peak memory 208740 kb
Host smart-2b87aa64-b82a-4bd9-b38a-84021494bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737811525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.737811525
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1248678973
Short name T419
Test name
Test status
Simulation time 12931928201 ps
CPU time 147.83 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:32:41 PM PDT 24
Peak memory 200376 kb
Host smart-8804967f-15bd-4653-b7cb-e587e918cc26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248678973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1248678973
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2445080338
Short name T672
Test name
Test status
Simulation time 4737891564 ps
CPU time 9.66 seconds
Started May 05 01:30:10 PM PDT 24
Finished May 05 01:30:20 PM PDT 24
Peak memory 199068 kb
Host smart-67dc29a8-1d59-4106-b591-1aaa9daf7fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445080338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2445080338
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2203148139
Short name T40
Test name
Test status
Simulation time 76525973863 ps
CPU time 20.54 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:30:34 PM PDT 24
Peak memory 200184 kb
Host smart-3c97af58-c883-4875-ab38-6a8611802206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203148139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2203148139
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1919832447
Short name T584
Test name
Test status
Simulation time 4735834160 ps
CPU time 7.8 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:30:25 PM PDT 24
Peak memory 196384 kb
Host smart-fe533131-ee3c-4aee-b402-3cf156dda8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919832447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1919832447
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.118450463
Short name T23
Test name
Test status
Simulation time 41152784 ps
CPU time 0.76 seconds
Started May 05 01:30:14 PM PDT 24
Finished May 05 01:30:15 PM PDT 24
Peak memory 218564 kb
Host smart-a467a135-6c0c-48a5-a10c-17478ff88975
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118450463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.118450463
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2848038513
Short name T252
Test name
Test status
Simulation time 6252386808 ps
CPU time 10.63 seconds
Started May 05 01:30:08 PM PDT 24
Finished May 05 01:30:19 PM PDT 24
Peak memory 200320 kb
Host smart-bc3e1c4d-8178-4b30-98f7-124caf7b47e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848038513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2848038513
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1504282265
Short name T16
Test name
Test status
Simulation time 92273994338 ps
CPU time 80.17 seconds
Started May 05 01:30:16 PM PDT 24
Finished May 05 01:31:36 PM PDT 24
Peak memory 200360 kb
Host smart-7e99a813-5880-46eb-bf9d-e976628d9d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504282265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1504282265
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2503296725
Short name T314
Test name
Test status
Simulation time 49846688630 ps
CPU time 538.61 seconds
Started May 05 01:30:12 PM PDT 24
Finished May 05 01:39:11 PM PDT 24
Peak memory 225140 kb
Host smart-78f8b6eb-b489-4aa9-9583-3a31056f8ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503296725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2503296725
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1853629273
Short name T713
Test name
Test status
Simulation time 1263571833 ps
CPU time 2.29 seconds
Started May 05 01:30:13 PM PDT 24
Finished May 05 01:30:15 PM PDT 24
Peak memory 198852 kb
Host smart-c0d3ea47-2409-4bc2-9f53-2f68edac04bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853629273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1853629273
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3422018236
Short name T319
Test name
Test status
Simulation time 14083941962 ps
CPU time 23.53 seconds
Started May 05 01:30:12 PM PDT 24
Finished May 05 01:30:36 PM PDT 24
Peak memory 200376 kb
Host smart-ca4e22fb-9ca3-4d14-a3c3-58d70cb60766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422018236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3422018236
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4122999942
Short name T409
Test name
Test status
Simulation time 32004654 ps
CPU time 0.54 seconds
Started May 05 01:33:49 PM PDT 24
Finished May 05 01:33:50 PM PDT 24
Peak memory 195748 kb
Host smart-5dbc3e92-addb-4c3d-b7ba-b801a2386c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122999942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4122999942
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.987421649
Short name T538
Test name
Test status
Simulation time 149919582021 ps
CPU time 56.19 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:34:38 PM PDT 24
Peak memory 200360 kb
Host smart-0403b03d-8920-40d6-8ff4-af63d10a0331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987421649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.987421649
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2263569119
Short name T1148
Test name
Test status
Simulation time 162794353737 ps
CPU time 14.19 seconds
Started May 05 01:33:42 PM PDT 24
Finished May 05 01:33:56 PM PDT 24
Peak memory 200296 kb
Host smart-28d14361-24ff-40b9-badd-a16effd0dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263569119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2263569119
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1068246704
Short name T781
Test name
Test status
Simulation time 54684249048 ps
CPU time 76.2 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:34:57 PM PDT 24
Peak memory 200356 kb
Host smart-c83cc622-e0e1-4237-8a32-e892dfd555e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068246704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1068246704
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2331639263
Short name T1061
Test name
Test status
Simulation time 51368711044 ps
CPU time 31.15 seconds
Started May 05 01:33:40 PM PDT 24
Finished May 05 01:34:12 PM PDT 24
Peak memory 200332 kb
Host smart-ff34b873-f2f7-4e10-b63f-0d6f38c2fe38
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331639263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2331639263
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2535452186
Short name T418
Test name
Test status
Simulation time 67439088356 ps
CPU time 248.14 seconds
Started May 05 01:33:49 PM PDT 24
Finished May 05 01:37:57 PM PDT 24
Peak memory 200316 kb
Host smart-fcc11cbd-8428-4a18-886d-501e31394fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2535452186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2535452186
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3303343093
Short name T912
Test name
Test status
Simulation time 6238689630 ps
CPU time 4.94 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:33:47 PM PDT 24
Peak memory 200332 kb
Host smart-d03c73ab-dae5-4b78-a6ba-65e420eb8e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303343093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3303343093
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2491193289
Short name T32
Test name
Test status
Simulation time 148753759241 ps
CPU time 60.15 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:34:42 PM PDT 24
Peak memory 199256 kb
Host smart-737f000f-db78-44c4-9ba4-e5e9b78ed837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491193289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2491193289
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3621776301
Short name T834
Test name
Test status
Simulation time 15080685224 ps
CPU time 863.52 seconds
Started May 05 01:33:45 PM PDT 24
Finished May 05 01:48:09 PM PDT 24
Peak memory 200380 kb
Host smart-4e1a727c-a248-49b9-9928-c04923eda2a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621776301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3621776301
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2297573121
Short name T1096
Test name
Test status
Simulation time 3359383944 ps
CPU time 7.27 seconds
Started May 05 01:33:38 PM PDT 24
Finished May 05 01:33:46 PM PDT 24
Peak memory 198516 kb
Host smart-bb7faccb-ccdb-4c7b-8a6f-4d027345f9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297573121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2297573121
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.126016500
Short name T478
Test name
Test status
Simulation time 22324735241 ps
CPU time 17.68 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:33:59 PM PDT 24
Peak memory 199992 kb
Host smart-77a64314-0a55-4ec5-849d-a4c5d6271fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126016500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.126016500
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2510201515
Short name T1016
Test name
Test status
Simulation time 3634956794 ps
CPU time 1.81 seconds
Started May 05 01:33:39 PM PDT 24
Finished May 05 01:33:41 PM PDT 24
Peak memory 196344 kb
Host smart-01ee2b9e-693b-4446-9612-a80d67d87ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510201515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2510201515
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2957452100
Short name T896
Test name
Test status
Simulation time 5694459112 ps
CPU time 10.38 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:33:52 PM PDT 24
Peak memory 200344 kb
Host smart-65fe04a6-f88f-42e9-b84b-697a3470f4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957452100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2957452100
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.4127050160
Short name T567
Test name
Test status
Simulation time 152475187092 ps
CPU time 282.8 seconds
Started May 05 01:33:44 PM PDT 24
Finished May 05 01:38:27 PM PDT 24
Peak memory 216228 kb
Host smart-ea1088bf-e0eb-4883-8352-379baaed6b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127050160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4127050160
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2571180198
Short name T292
Test name
Test status
Simulation time 211409535917 ps
CPU time 648.15 seconds
Started May 05 01:33:49 PM PDT 24
Finished May 05 01:44:38 PM PDT 24
Peak memory 213508 kb
Host smart-4e0b3e22-80e7-42f9-b373-1e280a45a66d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571180198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2571180198
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2611617201
Short name T396
Test name
Test status
Simulation time 1094982921 ps
CPU time 3.4 seconds
Started May 05 01:33:42 PM PDT 24
Finished May 05 01:33:45 PM PDT 24
Peak memory 199976 kb
Host smart-badcd140-214d-4dd2-9278-e2df7e2746ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611617201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2611617201
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1251974619
Short name T852
Test name
Test status
Simulation time 10910027154 ps
CPU time 19.52 seconds
Started May 05 01:33:41 PM PDT 24
Finished May 05 01:34:01 PM PDT 24
Peak memory 200296 kb
Host smart-7bb0c4b4-b8a0-4e5c-babc-4f94cb11d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251974619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1251974619
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.668861375
Short name T858
Test name
Test status
Simulation time 34740597 ps
CPU time 0.53 seconds
Started May 05 01:33:57 PM PDT 24
Finished May 05 01:33:58 PM PDT 24
Peak memory 195760 kb
Host smart-0ccdb80c-2559-47b1-b2e7-ad2091df4714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668861375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.668861375
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2841455076
Short name T326
Test name
Test status
Simulation time 32356278083 ps
CPU time 20.1 seconds
Started May 05 01:33:49 PM PDT 24
Finished May 05 01:34:09 PM PDT 24
Peak memory 200356 kb
Host smart-3bf9d914-a7fb-4875-9fcf-c819cbb5e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841455076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2841455076
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3691047069
Short name T366
Test name
Test status
Simulation time 43027129638 ps
CPU time 34.47 seconds
Started May 05 01:33:48 PM PDT 24
Finished May 05 01:34:23 PM PDT 24
Peak memory 200272 kb
Host smart-3cec6dbd-fea8-4f4c-81bf-30b30977da75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691047069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3691047069
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1500090402
Short name T630
Test name
Test status
Simulation time 158221760211 ps
CPU time 60.29 seconds
Started May 05 01:33:51 PM PDT 24
Finished May 05 01:34:52 PM PDT 24
Peak memory 200336 kb
Host smart-7a5560d8-51d5-479b-a811-58eafd5c9d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500090402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1500090402
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2972782326
Short name T529
Test name
Test status
Simulation time 36467655025 ps
CPU time 66.49 seconds
Started May 05 01:33:51 PM PDT 24
Finished May 05 01:34:58 PM PDT 24
Peak memory 200392 kb
Host smart-cefd43cf-0c88-4696-8437-9db761654456
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972782326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2972782326
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4202929748
Short name T1180
Test name
Test status
Simulation time 95977386050 ps
CPU time 767.66 seconds
Started May 05 01:33:54 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 200328 kb
Host smart-5d388dea-188a-4986-8407-7e4bf67e720f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202929748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4202929748
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3500387883
Short name T971
Test name
Test status
Simulation time 8126277474 ps
CPU time 4.63 seconds
Started May 05 01:33:50 PM PDT 24
Finished May 05 01:33:55 PM PDT 24
Peak memory 200368 kb
Host smart-bfe5852e-30e3-4fb7-b60e-0dcd84d19d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500387883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3500387883
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1770024012
Short name T287
Test name
Test status
Simulation time 70268346130 ps
CPU time 36.9 seconds
Started May 05 01:33:51 PM PDT 24
Finished May 05 01:34:28 PM PDT 24
Peak memory 198744 kb
Host smart-771a4ebb-6d46-414e-91ab-354b69de78cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770024012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1770024012
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4102930318
Short name T570
Test name
Test status
Simulation time 11164158668 ps
CPU time 319.59 seconds
Started May 05 01:33:57 PM PDT 24
Finished May 05 01:39:17 PM PDT 24
Peak memory 200384 kb
Host smart-a783ed9e-7a7a-4508-b247-e397543ba947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102930318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4102930318
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.846183002
Short name T984
Test name
Test status
Simulation time 3551887187 ps
CPU time 26.6 seconds
Started May 05 01:33:51 PM PDT 24
Finished May 05 01:34:18 PM PDT 24
Peak memory 198652 kb
Host smart-57df6f4f-4249-45ae-a010-53db34f48afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846183002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.846183002
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1518967426
Short name T777
Test name
Test status
Simulation time 21962159700 ps
CPU time 23.74 seconds
Started May 05 01:33:51 PM PDT 24
Finished May 05 01:34:15 PM PDT 24
Peak memory 200304 kb
Host smart-82b3f546-08c2-471c-baf5-23653f891fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518967426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1518967426
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.999280346
Short name T498
Test name
Test status
Simulation time 2945403612 ps
CPU time 1.73 seconds
Started May 05 01:33:50 PM PDT 24
Finished May 05 01:33:52 PM PDT 24
Peak memory 196368 kb
Host smart-7747bda2-c3b1-49ee-895b-1f5f83a21ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999280346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.999280346
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1869786966
Short name T520
Test name
Test status
Simulation time 698916491 ps
CPU time 1.56 seconds
Started May 05 01:33:44 PM PDT 24
Finished May 05 01:33:46 PM PDT 24
Peak memory 200176 kb
Host smart-13ff62ca-77d5-4a23-a864-7d6763616c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869786966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1869786966
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1592740787
Short name T439
Test name
Test status
Simulation time 156566330656 ps
CPU time 533.53 seconds
Started May 05 01:33:54 PM PDT 24
Finished May 05 01:42:48 PM PDT 24
Peak memory 200332 kb
Host smart-119d9c76-cd1a-44cf-a97f-ed834f1e95ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592740787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1592740787
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.181364318
Short name T170
Test name
Test status
Simulation time 1070105058869 ps
CPU time 1380.63 seconds
Started May 05 01:33:54 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 224980 kb
Host smart-05974714-d770-403b-b175-acdf19f0e16e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181364318 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.181364318
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.441270713
Short name T369
Test name
Test status
Simulation time 6484463941 ps
CPU time 23 seconds
Started May 05 01:33:50 PM PDT 24
Finished May 05 01:34:14 PM PDT 24
Peak memory 200308 kb
Host smart-853d8d55-f1bd-4308-b259-0828cf70f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441270713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.441270713
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1053096121
Short name T483
Test name
Test status
Simulation time 108847545635 ps
CPU time 43.05 seconds
Started May 05 01:33:44 PM PDT 24
Finished May 05 01:34:28 PM PDT 24
Peak memory 200296 kb
Host smart-9f8c2919-1143-4052-b3d9-ea410437085c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053096121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1053096121
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2889363789
Short name T573
Test name
Test status
Simulation time 13499973 ps
CPU time 0.55 seconds
Started May 05 01:33:59 PM PDT 24
Finished May 05 01:34:00 PM PDT 24
Peak memory 195776 kb
Host smart-8317be29-6212-4173-b4e6-137ae89c9e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889363789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2889363789
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3361070722
Short name T635
Test name
Test status
Simulation time 86190685504 ps
CPU time 47.27 seconds
Started May 05 01:33:57 PM PDT 24
Finished May 05 01:34:45 PM PDT 24
Peak memory 200332 kb
Host smart-0cdec91a-e4cc-4fda-b4ec-1f6d86f8ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361070722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3361070722
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3662618697
Short name T433
Test name
Test status
Simulation time 72145702421 ps
CPU time 34.01 seconds
Started May 05 01:33:55 PM PDT 24
Finished May 05 01:34:30 PM PDT 24
Peak memory 200352 kb
Host smart-cb53fcac-a2a6-4d8a-94c6-2fa11c369f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662618697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3662618697
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.495179421
Short name T758
Test name
Test status
Simulation time 72624133228 ps
CPU time 66.01 seconds
Started May 05 01:33:55 PM PDT 24
Finished May 05 01:35:01 PM PDT 24
Peak memory 200308 kb
Host smart-a079a2e3-5ef3-4f60-9a3d-573dfe7c9bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495179421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.495179421
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1517530715
Short name T539
Test name
Test status
Simulation time 31761567319 ps
CPU time 60.46 seconds
Started May 05 01:33:59 PM PDT 24
Finished May 05 01:35:00 PM PDT 24
Peak memory 200396 kb
Host smart-985e46d2-4e27-4a60-aebb-c65dccdd5efb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517530715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1517530715
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3526607116
Short name T407
Test name
Test status
Simulation time 175340150568 ps
CPU time 337.45 seconds
Started May 05 01:33:58 PM PDT 24
Finished May 05 01:39:36 PM PDT 24
Peak memory 200392 kb
Host smart-dfbc4f83-0df4-4165-81d8-e15a51493f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526607116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3526607116
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1444093620
Short name T951
Test name
Test status
Simulation time 5232522333 ps
CPU time 5.22 seconds
Started May 05 01:34:01 PM PDT 24
Finished May 05 01:34:06 PM PDT 24
Peak memory 199504 kb
Host smart-b104040e-d61c-4244-84b9-95b610449a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444093620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1444093620
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3091274354
Short name T588
Test name
Test status
Simulation time 43096710559 ps
CPU time 68.63 seconds
Started May 05 01:34:00 PM PDT 24
Finished May 05 01:35:09 PM PDT 24
Peak memory 200568 kb
Host smart-0dff569c-6b7b-445b-87db-2c1fc0b34952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091274354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3091274354
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1989398683
Short name T936
Test name
Test status
Simulation time 4136269212 ps
CPU time 40.16 seconds
Started May 05 01:33:59 PM PDT 24
Finished May 05 01:34:39 PM PDT 24
Peak memory 200356 kb
Host smart-37323ecc-7aa1-48ae-88fb-480d63accecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989398683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1989398683
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1953705123
Short name T1020
Test name
Test status
Simulation time 3681052929 ps
CPU time 31.55 seconds
Started May 05 01:33:56 PM PDT 24
Finished May 05 01:34:28 PM PDT 24
Peak memory 198548 kb
Host smart-66751140-62a8-4d59-ac6a-6560df662fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953705123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1953705123
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3533746505
Short name T12
Test name
Test status
Simulation time 40682843489 ps
CPU time 34.06 seconds
Started May 05 01:34:00 PM PDT 24
Finished May 05 01:34:35 PM PDT 24
Peak memory 200112 kb
Host smart-ae411187-963f-43c7-802b-bf14b2e67104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533746505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3533746505
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2161604221
Short name T382
Test name
Test status
Simulation time 4772511463 ps
CPU time 2.06 seconds
Started May 05 01:34:00 PM PDT 24
Finished May 05 01:34:02 PM PDT 24
Peak memory 196380 kb
Host smart-b23a87db-26a0-4075-b132-1363c3c88dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161604221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2161604221
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.754538995
Short name T501
Test name
Test status
Simulation time 316092106 ps
CPU time 1.36 seconds
Started May 05 01:33:56 PM PDT 24
Finished May 05 01:33:58 PM PDT 24
Peak memory 198764 kb
Host smart-0dab1838-5ae4-4bfd-82a2-eeb99ae966d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754538995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.754538995
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.210209690
Short name T667
Test name
Test status
Simulation time 96614410528 ps
CPU time 584.67 seconds
Started May 05 01:34:02 PM PDT 24
Finished May 05 01:43:47 PM PDT 24
Peak memory 200340 kb
Host smart-786371ec-891a-463b-bde2-7329636a8032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210209690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.210209690
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.829895038
Short name T445
Test name
Test status
Simulation time 1321915506 ps
CPU time 2.71 seconds
Started May 05 01:34:00 PM PDT 24
Finished May 05 01:34:03 PM PDT 24
Peak memory 198920 kb
Host smart-b8ad79ea-db82-4793-9cac-7bcf045c4d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829895038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.829895038
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1562199140
Short name T593
Test name
Test status
Simulation time 26712199584 ps
CPU time 54.5 seconds
Started May 05 01:33:54 PM PDT 24
Finished May 05 01:34:49 PM PDT 24
Peak memory 200608 kb
Host smart-e1545fdb-458b-4ab7-b7a4-45606bd7ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562199140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1562199140
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.830234155
Short name T812
Test name
Test status
Simulation time 11976637 ps
CPU time 0.61 seconds
Started May 05 01:34:11 PM PDT 24
Finished May 05 01:34:12 PM PDT 24
Peak memory 195740 kb
Host smart-2c57fcfe-d860-4ba5-9f48-2fb3ba5db0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830234155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.830234155
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3464060205
Short name T127
Test name
Test status
Simulation time 166769114239 ps
CPU time 257.88 seconds
Started May 05 01:34:03 PM PDT 24
Finished May 05 01:38:21 PM PDT 24
Peak memory 200360 kb
Host smart-c109ff82-8770-4b4b-a358-1c39929158ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464060205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3464060205
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4016807321
Short name T788
Test name
Test status
Simulation time 124763004724 ps
CPU time 54.74 seconds
Started May 05 01:34:05 PM PDT 24
Finished May 05 01:35:00 PM PDT 24
Peak memory 200300 kb
Host smart-7f0c2753-4913-4aa1-bafd-6d5877e1ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016807321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4016807321
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2117674191
Short name T607
Test name
Test status
Simulation time 214057566797 ps
CPU time 432.21 seconds
Started May 05 01:34:04 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 200320 kb
Host smart-7bcb9ca1-541d-4891-b119-04bd5848a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117674191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2117674191
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3494495965
Short name T434
Test name
Test status
Simulation time 53972437502 ps
CPU time 91.23 seconds
Started May 05 01:34:04 PM PDT 24
Finished May 05 01:35:36 PM PDT 24
Peak memory 200400 kb
Host smart-50ea78ab-d4f8-4656-aab9-de860cb706bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494495965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3494495965
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.499057485
Short name T605
Test name
Test status
Simulation time 81606643950 ps
CPU time 435.87 seconds
Started May 05 01:34:11 PM PDT 24
Finished May 05 01:41:27 PM PDT 24
Peak memory 200320 kb
Host smart-e5817d00-323f-441f-98cf-e41df75f3b5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499057485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.499057485
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2867818556
Short name T334
Test name
Test status
Simulation time 2207919013 ps
CPU time 2.34 seconds
Started May 05 01:34:06 PM PDT 24
Finished May 05 01:34:09 PM PDT 24
Peak memory 198704 kb
Host smart-a788b92f-d864-4ad8-9677-7b6af8651271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867818556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2867818556
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3910527722
Short name T653
Test name
Test status
Simulation time 7837606943 ps
CPU time 14.8 seconds
Started May 05 01:34:05 PM PDT 24
Finished May 05 01:34:20 PM PDT 24
Peak memory 195524 kb
Host smart-f3a65b2c-bc8f-4d62-b8d8-6a416532aa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910527722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3910527722
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.966499036
Short name T719
Test name
Test status
Simulation time 20621276403 ps
CPU time 109.51 seconds
Started May 05 01:34:04 PM PDT 24
Finished May 05 01:35:54 PM PDT 24
Peak memory 200348 kb
Host smart-19e5ed42-9afa-4062-9c65-222b8ee6a6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966499036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.966499036
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1564957530
Short name T316
Test name
Test status
Simulation time 4291712812 ps
CPU time 17.54 seconds
Started May 05 01:34:06 PM PDT 24
Finished May 05 01:34:24 PM PDT 24
Peak memory 199600 kb
Host smart-112c8aa5-d9f1-473c-b4da-2cea7bdc817c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564957530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1564957530
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1999307529
Short name T525
Test name
Test status
Simulation time 133767591534 ps
CPU time 86.26 seconds
Started May 05 01:34:05 PM PDT 24
Finished May 05 01:35:31 PM PDT 24
Peak memory 200328 kb
Host smart-7b5c83ae-d1b0-4741-af2d-629f9cd0d135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999307529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1999307529
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1810097418
Short name T532
Test name
Test status
Simulation time 1773389475 ps
CPU time 1.38 seconds
Started May 05 01:34:05 PM PDT 24
Finished May 05 01:34:06 PM PDT 24
Peak memory 195660 kb
Host smart-84693349-46c7-44ee-b3f5-435efe759c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810097418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1810097418
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3076646521
Short name T454
Test name
Test status
Simulation time 5766959769 ps
CPU time 8.39 seconds
Started May 05 01:34:01 PM PDT 24
Finished May 05 01:34:09 PM PDT 24
Peak memory 200268 kb
Host smart-e400baad-0198-43f2-ac57-f382f3745bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076646521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3076646521
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2170819821
Short name T1030
Test name
Test status
Simulation time 349434103842 ps
CPU time 135.99 seconds
Started May 05 01:34:10 PM PDT 24
Finished May 05 01:36:26 PM PDT 24
Peak memory 208796 kb
Host smart-0b14da6c-2b7c-4443-a667-c89cf7fee034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170819821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2170819821
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3880129490
Short name T610
Test name
Test status
Simulation time 125655397879 ps
CPU time 752.66 seconds
Started May 05 01:34:11 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 216408 kb
Host smart-f5a385c0-6fa6-4fe6-9541-7336ce65666d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880129490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3880129490
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3755567253
Short name T743
Test name
Test status
Simulation time 714240528 ps
CPU time 2.33 seconds
Started May 05 01:34:05 PM PDT 24
Finished May 05 01:34:08 PM PDT 24
Peak memory 198828 kb
Host smart-504edd17-85b5-4b27-9d9c-53a71403baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755567253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3755567253
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3913677431
Short name T1126
Test name
Test status
Simulation time 75730745885 ps
CPU time 149.5 seconds
Started May 05 01:34:05 PM PDT 24
Finished May 05 01:36:35 PM PDT 24
Peak memory 200404 kb
Host smart-7bb61d38-fe74-4605-aef7-6fa65e51e5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913677431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3913677431
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1890921993
Short name T880
Test name
Test status
Simulation time 19740854 ps
CPU time 0.54 seconds
Started May 05 01:34:18 PM PDT 24
Finished May 05 01:34:19 PM PDT 24
Peak memory 195752 kb
Host smart-549ba92b-8002-4f71-848d-4b24baf1094a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890921993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1890921993
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.818346393
Short name T826
Test name
Test status
Simulation time 118694170150 ps
CPU time 201.33 seconds
Started May 05 01:34:09 PM PDT 24
Finished May 05 01:37:31 PM PDT 24
Peak memory 200396 kb
Host smart-774012a5-4f83-4b9f-a802-627e19ea03f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818346393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.818346393
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2598448035
Short name T324
Test name
Test status
Simulation time 10535340264 ps
CPU time 18.67 seconds
Started May 05 01:34:16 PM PDT 24
Finished May 05 01:34:35 PM PDT 24
Peak memory 200268 kb
Host smart-2f1ee93f-1c20-4419-bfcd-6b8844667a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598448035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2598448035
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2520313021
Short name T432
Test name
Test status
Simulation time 295803557269 ps
CPU time 126.85 seconds
Started May 05 01:34:15 PM PDT 24
Finished May 05 01:36:22 PM PDT 24
Peak memory 198052 kb
Host smart-95e1cadd-69f3-4588-8a40-09ec1841c887
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520313021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2520313021
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3382369617
Short name T624
Test name
Test status
Simulation time 182525624207 ps
CPU time 576 seconds
Started May 05 01:34:19 PM PDT 24
Finished May 05 01:43:56 PM PDT 24
Peak memory 200304 kb
Host smart-1f205397-c150-406e-8f2a-3662f8052747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382369617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3382369617
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2039249398
Short name T592
Test name
Test status
Simulation time 7407686692 ps
CPU time 6.57 seconds
Started May 05 01:34:16 PM PDT 24
Finished May 05 01:34:22 PM PDT 24
Peak memory 200280 kb
Host smart-adf30897-814c-4ff5-880c-2d655a25b731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039249398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2039249398
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.303332696
Short name T1113
Test name
Test status
Simulation time 76138950534 ps
CPU time 74.27 seconds
Started May 05 01:34:14 PM PDT 24
Finished May 05 01:35:29 PM PDT 24
Peak memory 200576 kb
Host smart-7b47d6bc-2c15-4d37-876f-ba763f71863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303332696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.303332696
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.283015127
Short name T1168
Test name
Test status
Simulation time 6168223884 ps
CPU time 171.73 seconds
Started May 05 01:34:15 PM PDT 24
Finished May 05 01:37:07 PM PDT 24
Peak memory 200332 kb
Host smart-0da67098-842b-4840-b175-39738ae29248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283015127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.283015127
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.4255974804
Short name T342
Test name
Test status
Simulation time 5831861066 ps
CPU time 53.31 seconds
Started May 05 01:34:17 PM PDT 24
Finished May 05 01:35:10 PM PDT 24
Peak memory 199432 kb
Host smart-39470154-2327-47bf-b44c-f7f4e594727c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255974804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4255974804
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3296691695
Short name T684
Test name
Test status
Simulation time 126312848581 ps
CPU time 44.31 seconds
Started May 05 01:34:15 PM PDT 24
Finished May 05 01:35:00 PM PDT 24
Peak memory 200324 kb
Host smart-57c2fa62-3fa5-4021-a3dc-d0c7cd1433f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296691695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3296691695
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.236401667
Short name T678
Test name
Test status
Simulation time 75367543335 ps
CPU time 18.93 seconds
Started May 05 01:34:14 PM PDT 24
Finished May 05 01:34:33 PM PDT 24
Peak memory 196676 kb
Host smart-2dee8354-ceb2-4bdb-842a-c3406ea95a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236401667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.236401667
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2646110369
Short name T944
Test name
Test status
Simulation time 5728550844 ps
CPU time 20.9 seconds
Started May 05 01:34:10 PM PDT 24
Finished May 05 01:34:31 PM PDT 24
Peak memory 200376 kb
Host smart-4fefa4af-bb65-4e6e-b134-c3c44597bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646110369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2646110369
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1005668749
Short name T544
Test name
Test status
Simulation time 448216153531 ps
CPU time 235.96 seconds
Started May 05 01:34:19 PM PDT 24
Finished May 05 01:38:15 PM PDT 24
Peak memory 200428 kb
Host smart-6fa67484-16a5-4fd8-be27-9e552f9bb9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005668749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1005668749
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.848406275
Short name T648
Test name
Test status
Simulation time 222215859343 ps
CPU time 662.49 seconds
Started May 05 01:34:19 PM PDT 24
Finished May 05 01:45:22 PM PDT 24
Peak memory 216784 kb
Host smart-a9b26415-fc2c-4cb5-a0c9-5a2f61b187f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848406275 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.848406275
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2204866552
Short name T376
Test name
Test status
Simulation time 1981792625 ps
CPU time 2.22 seconds
Started May 05 01:34:14 PM PDT 24
Finished May 05 01:34:17 PM PDT 24
Peak memory 199188 kb
Host smart-b62938c2-5884-44f5-a102-bbe96c19a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204866552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2204866552
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2863436557
Short name T462
Test name
Test status
Simulation time 141925205327 ps
CPU time 148.58 seconds
Started May 05 01:34:10 PM PDT 24
Finished May 05 01:36:39 PM PDT 24
Peak memory 200340 kb
Host smart-b3a0ad08-c371-44fd-a2c2-66971c4b2da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863436557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2863436557
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4073986763
Short name T631
Test name
Test status
Simulation time 38424317 ps
CPU time 0.53 seconds
Started May 05 01:34:26 PM PDT 24
Finished May 05 01:34:27 PM PDT 24
Peak memory 195772 kb
Host smart-7f29ae2e-b46f-449d-b61f-417b64e97aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073986763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4073986763
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1434556182
Short name T1178
Test name
Test status
Simulation time 123176168729 ps
CPU time 59.51 seconds
Started May 05 01:34:20 PM PDT 24
Finished May 05 01:35:20 PM PDT 24
Peak memory 200324 kb
Host smart-214fe355-8e7c-4e3d-b8e0-8b85a77b3b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434556182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1434556182
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2445937976
Short name T791
Test name
Test status
Simulation time 122342302160 ps
CPU time 48.18 seconds
Started May 05 01:34:19 PM PDT 24
Finished May 05 01:35:08 PM PDT 24
Peak memory 200384 kb
Host smart-411a944a-ba01-46ab-8e5c-36466beb62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445937976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2445937976
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3009840388
Short name T558
Test name
Test status
Simulation time 12580140048 ps
CPU time 25.49 seconds
Started May 05 01:34:24 PM PDT 24
Finished May 05 01:34:50 PM PDT 24
Peak memory 200312 kb
Host smart-78ba07bf-ed1b-4d23-bc43-3140a06364c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009840388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3009840388
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3495033551
Short name T702
Test name
Test status
Simulation time 33381794934 ps
CPU time 57.48 seconds
Started May 05 01:34:24 PM PDT 24
Finished May 05 01:35:22 PM PDT 24
Peak memory 200372 kb
Host smart-e45efc4a-b57c-45f9-8bf5-ffbf2d84b9d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495033551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3495033551
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2681793500
Short name T377
Test name
Test status
Simulation time 223811036086 ps
CPU time 292.04 seconds
Started May 05 01:34:26 PM PDT 24
Finished May 05 01:39:19 PM PDT 24
Peak memory 200316 kb
Host smart-41931327-2085-46bc-ab1c-aea84a4ca941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681793500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2681793500
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1060856238
Short name T420
Test name
Test status
Simulation time 9433262865 ps
CPU time 6.93 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:34:32 PM PDT 24
Peak memory 199344 kb
Host smart-0e9ab285-6ee3-4f23-a5ac-07fb7575d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060856238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1060856238
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3278411288
Short name T1169
Test name
Test status
Simulation time 23917416214 ps
CPU time 41.2 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:35:07 PM PDT 24
Peak memory 198332 kb
Host smart-f2625778-c0e7-4052-8663-7d131126a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278411288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3278411288
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1590879602
Short name T451
Test name
Test status
Simulation time 8627103302 ps
CPU time 150.39 seconds
Started May 05 01:34:26 PM PDT 24
Finished May 05 01:36:56 PM PDT 24
Peak memory 200344 kb
Host smart-d51a7bcf-9351-449f-80ca-b7b0313b1beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590879602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1590879602
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.959901553
Short name T934
Test name
Test status
Simulation time 7103001258 ps
CPU time 61.48 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:35:27 PM PDT 24
Peak memory 199064 kb
Host smart-7cecee4a-21f5-4a90-806f-4e0816eb4adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959901553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.959901553
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3299207973
Short name T161
Test name
Test status
Simulation time 501810043794 ps
CPU time 197.4 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:37:43 PM PDT 24
Peak memory 200320 kb
Host smart-8468fe17-b6b8-4f79-9449-0fb64d8dd659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299207973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3299207973
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1059038159
Short name T272
Test name
Test status
Simulation time 55088794803 ps
CPU time 92.05 seconds
Started May 05 01:34:24 PM PDT 24
Finished May 05 01:35:57 PM PDT 24
Peak memory 196384 kb
Host smart-0e8c8e20-0c44-4b50-b4f4-42fdc595650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059038159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1059038159
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3631070337
Short name T1076
Test name
Test status
Simulation time 695234263 ps
CPU time 2.94 seconds
Started May 05 01:34:20 PM PDT 24
Finished May 05 01:34:23 PM PDT 24
Peak memory 200284 kb
Host smart-97071543-29cd-45e4-a75f-0e5b46534d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631070337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3631070337
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2335482587
Short name T453
Test name
Test status
Simulation time 641894806519 ps
CPU time 1489.08 seconds
Started May 05 01:34:26 PM PDT 24
Finished May 05 01:59:16 PM PDT 24
Peak memory 208648 kb
Host smart-36c4b34c-f4cd-4d6f-a75f-801756743b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335482587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2335482587
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.826608675
Short name T720
Test name
Test status
Simulation time 66192838670 ps
CPU time 362.82 seconds
Started May 05 01:34:26 PM PDT 24
Finished May 05 01:40:29 PM PDT 24
Peak memory 208624 kb
Host smart-54cb7319-4fc9-41c1-8a8e-0973dc5b7728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826608675 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.826608675
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.168266538
Short name T722
Test name
Test status
Simulation time 1002421695 ps
CPU time 3.37 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:34:29 PM PDT 24
Peak memory 199080 kb
Host smart-524d60eb-a3b9-4c16-b563-5202b8d4e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168266538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.168266538
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.39444906
Short name T1105
Test name
Test status
Simulation time 72920192524 ps
CPU time 134.89 seconds
Started May 05 01:34:18 PM PDT 24
Finished May 05 01:36:34 PM PDT 24
Peak memory 200380 kb
Host smart-a35fd3bb-b322-4523-b920-fed9bec7792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39444906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.39444906
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3096542914
Short name T828
Test name
Test status
Simulation time 23449507 ps
CPU time 0.55 seconds
Started May 05 01:34:35 PM PDT 24
Finished May 05 01:34:36 PM PDT 24
Peak memory 195728 kb
Host smart-7d783d97-8f3c-466c-9783-1ff54d8b7385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096542914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3096542914
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3832817506
Short name T112
Test name
Test status
Simulation time 141117147515 ps
CPU time 59.88 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:35:25 PM PDT 24
Peak memory 200316 kb
Host smart-7ef4fb98-3d17-47f4-ad06-999cca28a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832817506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3832817506
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.841774458
Short name T639
Test name
Test status
Simulation time 41201698273 ps
CPU time 66.26 seconds
Started May 05 01:34:30 PM PDT 24
Finished May 05 01:35:36 PM PDT 24
Peak memory 200088 kb
Host smart-84ee4375-b011-4aae-8142-20de108bb56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841774458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.841774458
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3793231557
Short name T380
Test name
Test status
Simulation time 30675945978 ps
CPU time 12.08 seconds
Started May 05 01:34:31 PM PDT 24
Finished May 05 01:34:43 PM PDT 24
Peak memory 200292 kb
Host smart-10f50ad6-6ef5-4337-8ba5-62f431d12931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793231557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3793231557
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2869048068
Short name T100
Test name
Test status
Simulation time 43495427865 ps
CPU time 37.93 seconds
Started May 05 01:34:30 PM PDT 24
Finished May 05 01:35:08 PM PDT 24
Peak memory 200336 kb
Host smart-1748e8ce-a006-4584-810a-21412f0490ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869048068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2869048068
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.741054673
Short name T787
Test name
Test status
Simulation time 44230500941 ps
CPU time 370.73 seconds
Started May 05 01:34:36 PM PDT 24
Finished May 05 01:40:47 PM PDT 24
Peak memory 200336 kb
Host smart-3fb1822c-d53d-46d2-99f5-89af16086a66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741054673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.741054673
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1481995936
Short name T349
Test name
Test status
Simulation time 179280137 ps
CPU time 0.72 seconds
Started May 05 01:34:35 PM PDT 24
Finished May 05 01:34:36 PM PDT 24
Peak memory 197164 kb
Host smart-eb91f3ab-8644-4468-8a43-38e5644a8a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481995936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1481995936
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1224475647
Short name T659
Test name
Test status
Simulation time 93549994043 ps
CPU time 76.35 seconds
Started May 05 01:34:30 PM PDT 24
Finished May 05 01:35:47 PM PDT 24
Peak memory 199388 kb
Host smart-b26acfa9-e996-43fc-915f-c10f8502b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224475647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1224475647
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3851784336
Short name T627
Test name
Test status
Simulation time 17998688670 ps
CPU time 253.43 seconds
Started May 05 01:34:35 PM PDT 24
Finished May 05 01:38:49 PM PDT 24
Peak memory 200360 kb
Host smart-9ffa8354-d113-4d52-930c-d814e2d07e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851784336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3851784336
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.835748354
Short name T660
Test name
Test status
Simulation time 3379464597 ps
CPU time 25.43 seconds
Started May 05 01:34:30 PM PDT 24
Finished May 05 01:34:56 PM PDT 24
Peak memory 199220 kb
Host smart-8e3b32fa-f262-4d7a-b0ce-0e2a34039045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835748354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.835748354
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1762078556
Short name T132
Test name
Test status
Simulation time 97522071959 ps
CPU time 45.27 seconds
Started May 05 01:34:29 PM PDT 24
Finished May 05 01:35:15 PM PDT 24
Peak memory 200332 kb
Host smart-cc99356e-82b4-4e8e-bad6-aeef7e25aa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762078556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1762078556
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2527896022
Short name T410
Test name
Test status
Simulation time 4965528736 ps
CPU time 5.4 seconds
Started May 05 01:34:30 PM PDT 24
Finished May 05 01:34:36 PM PDT 24
Peak memory 196672 kb
Host smart-4b70a8ab-6927-473b-a2ae-958c3340b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527896022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2527896022
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1311030479
Short name T683
Test name
Test status
Simulation time 464778954 ps
CPU time 2.41 seconds
Started May 05 01:34:25 PM PDT 24
Finished May 05 01:34:28 PM PDT 24
Peak memory 199388 kb
Host smart-0488bad9-20ec-4897-9314-2e0b047c6fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311030479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1311030479
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3208730134
Short name T886
Test name
Test status
Simulation time 6436283817 ps
CPU time 20.86 seconds
Started May 05 01:34:30 PM PDT 24
Finished May 05 01:34:51 PM PDT 24
Peak memory 200212 kb
Host smart-65a4bd9d-12f4-4696-8aa2-5bfb0e6837f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208730134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3208730134
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1869221267
Short name T543
Test name
Test status
Simulation time 12811411741 ps
CPU time 16.78 seconds
Started May 05 01:34:26 PM PDT 24
Finished May 05 01:34:43 PM PDT 24
Peak memory 197580 kb
Host smart-9cbe6541-3288-407b-be04-acfa2b372778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869221267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1869221267
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3841993627
Short name T1039
Test name
Test status
Simulation time 13713881 ps
CPU time 0.54 seconds
Started May 05 01:34:44 PM PDT 24
Finished May 05 01:34:45 PM PDT 24
Peak memory 195780 kb
Host smart-e89a2a52-8ab8-43a8-8ab1-e60917dbd303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841993627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3841993627
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3813574906
Short name T383
Test name
Test status
Simulation time 37256376583 ps
CPU time 24.89 seconds
Started May 05 01:34:34 PM PDT 24
Finished May 05 01:34:59 PM PDT 24
Peak memory 200356 kb
Host smart-3ec34b2f-9fa2-4ccf-b725-cc2f701bded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813574906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3813574906
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.771776790
Short name T687
Test name
Test status
Simulation time 158632226861 ps
CPU time 25.59 seconds
Started May 05 01:34:36 PM PDT 24
Finished May 05 01:35:02 PM PDT 24
Peak memory 200408 kb
Host smart-1291cffe-a03d-4d0e-9aec-6dd3ce6a67a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771776790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.771776790
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2915843107
Short name T799
Test name
Test status
Simulation time 49360682721 ps
CPU time 121.15 seconds
Started May 05 01:34:35 PM PDT 24
Finished May 05 01:36:36 PM PDT 24
Peak memory 200412 kb
Host smart-faa8d8e6-a362-48ff-ba5d-f3e473b57caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915843107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2915843107
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1476124623
Short name T491
Test name
Test status
Simulation time 161273103914 ps
CPU time 38.46 seconds
Started May 05 01:34:39 PM PDT 24
Finished May 05 01:35:18 PM PDT 24
Peak memory 198712 kb
Host smart-1cf0013f-139e-47a9-b285-11232a38e755
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476124623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1476124623
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2572074781
Short name T364
Test name
Test status
Simulation time 117040875423 ps
CPU time 606.07 seconds
Started May 05 01:34:45 PM PDT 24
Finished May 05 01:44:52 PM PDT 24
Peak memory 200368 kb
Host smart-2042b708-650e-47b6-82f3-08d6da4ac1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2572074781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2572074781
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3937456652
Short name T1144
Test name
Test status
Simulation time 4121172968 ps
CPU time 4.21 seconds
Started May 05 01:34:40 PM PDT 24
Finished May 05 01:34:45 PM PDT 24
Peak memory 200244 kb
Host smart-905e906d-6fe5-4741-9375-f02bb930edb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937456652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3937456652
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2896723012
Short name T276
Test name
Test status
Simulation time 42877803691 ps
CPU time 17.89 seconds
Started May 05 01:34:44 PM PDT 24
Finished May 05 01:35:03 PM PDT 24
Peak memory 200480 kb
Host smart-1fc2c80a-e55a-4533-b9d7-c4f0ae5515b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896723012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2896723012
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3902883585
Short name T460
Test name
Test status
Simulation time 15681820627 ps
CPU time 764.29 seconds
Started May 05 01:34:41 PM PDT 24
Finished May 05 01:47:25 PM PDT 24
Peak memory 200292 kb
Host smart-e9f2de30-1438-423d-9afd-d96afc681703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902883585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3902883585
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1916937748
Short name T918
Test name
Test status
Simulation time 5147306128 ps
CPU time 2.86 seconds
Started May 05 01:34:39 PM PDT 24
Finished May 05 01:34:42 PM PDT 24
Peak memory 198540 kb
Host smart-193d7f1e-86b4-4234-9182-8f86018cb7e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916937748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1916937748
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1566905479
Short name T710
Test name
Test status
Simulation time 67671917811 ps
CPU time 32.48 seconds
Started May 05 01:34:44 PM PDT 24
Finished May 05 01:35:17 PM PDT 24
Peak memory 200392 kb
Host smart-db48b305-35cf-4f87-8e7b-a1ff2c0ff86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566905479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1566905479
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.223671927
Short name T798
Test name
Test status
Simulation time 2659991896 ps
CPU time 4.54 seconds
Started May 05 01:34:41 PM PDT 24
Finished May 05 01:34:46 PM PDT 24
Peak memory 196380 kb
Host smart-a2c3cc92-04e6-4aca-84c7-b48a88743665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223671927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.223671927
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3565173583
Short name T461
Test name
Test status
Simulation time 308999356 ps
CPU time 1.11 seconds
Started May 05 01:34:34 PM PDT 24
Finished May 05 01:34:36 PM PDT 24
Peak memory 200252 kb
Host smart-602a8974-6d9b-4f86-bdd3-51856c896c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565173583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3565173583
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1296590480
Short name T457
Test name
Test status
Simulation time 186933401498 ps
CPU time 420.93 seconds
Started May 05 01:34:44 PM PDT 24
Finished May 05 01:41:46 PM PDT 24
Peak memory 200352 kb
Host smart-99a7eeef-4cbf-42df-83bb-3056dfc5a2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296590480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1296590480
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3941365875
Short name T46
Test name
Test status
Simulation time 67300220228 ps
CPU time 334.8 seconds
Started May 05 01:34:46 PM PDT 24
Finished May 05 01:40:21 PM PDT 24
Peak memory 216304 kb
Host smart-f01c75c4-fad6-483a-a243-0e8f444170f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941365875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3941365875
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3943821610
Short name T838
Test name
Test status
Simulation time 893452377 ps
CPU time 2.73 seconds
Started May 05 01:34:40 PM PDT 24
Finished May 05 01:34:43 PM PDT 24
Peak memory 198652 kb
Host smart-bbc52efa-b1ec-4ee0-b94a-aa1dde82054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943821610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3943821610
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2888098595
Short name T1171
Test name
Test status
Simulation time 203224856791 ps
CPU time 116.61 seconds
Started May 05 01:34:35 PM PDT 24
Finished May 05 01:36:32 PM PDT 24
Peak memory 200360 kb
Host smart-58ecd330-f27c-47cb-ab49-b3c723c83678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888098595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2888098595
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3567964989
Short name T808
Test name
Test status
Simulation time 23310023 ps
CPU time 0.53 seconds
Started May 05 01:34:55 PM PDT 24
Finished May 05 01:34:56 PM PDT 24
Peak memory 195708 kb
Host smart-c1ad18ab-0de5-44b3-a892-7f5f47fceb24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567964989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3567964989
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1546463934
Short name T741
Test name
Test status
Simulation time 37985874811 ps
CPU time 66.94 seconds
Started May 05 01:34:46 PM PDT 24
Finished May 05 01:35:53 PM PDT 24
Peak memory 200388 kb
Host smart-d817c987-8ffa-4f96-b103-cadbb6833e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546463934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1546463934
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1032682389
Short name T921
Test name
Test status
Simulation time 5877101462 ps
CPU time 5.14 seconds
Started May 05 01:34:45 PM PDT 24
Finished May 05 01:34:50 PM PDT 24
Peak memory 198912 kb
Host smart-729f468a-4ffd-419b-9f16-9d25d5f9699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032682389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1032682389
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3552895708
Short name T961
Test name
Test status
Simulation time 25532030205 ps
CPU time 11.05 seconds
Started May 05 01:34:51 PM PDT 24
Finished May 05 01:35:02 PM PDT 24
Peak memory 200308 kb
Host smart-ddc77850-3542-4414-9462-850c96c2218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552895708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3552895708
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3819682868
Short name T41
Test name
Test status
Simulation time 37750292635 ps
CPU time 67.34 seconds
Started May 05 01:34:50 PM PDT 24
Finished May 05 01:35:57 PM PDT 24
Peak memory 200392 kb
Host smart-8e8e56c1-9641-49bc-958b-efd5d2e011f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819682868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3819682868
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_loopback.3874246057
Short name T695
Test name
Test status
Simulation time 2761305375 ps
CPU time 2.91 seconds
Started May 05 01:34:56 PM PDT 24
Finished May 05 01:34:59 PM PDT 24
Peak memory 196408 kb
Host smart-c9a449ec-e52b-42c8-b5bb-4d20f6169a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874246057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3874246057
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2965674909
Short name T689
Test name
Test status
Simulation time 60591611415 ps
CPU time 147.01 seconds
Started May 05 01:34:56 PM PDT 24
Finished May 05 01:37:23 PM PDT 24
Peak memory 199968 kb
Host smart-5c4c87c6-f4a7-429e-9766-ce89a07dcbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965674909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2965674909
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1102234648
Short name T1074
Test name
Test status
Simulation time 9225567024 ps
CPU time 204.45 seconds
Started May 05 01:34:55 PM PDT 24
Finished May 05 01:38:20 PM PDT 24
Peak memory 200584 kb
Host smart-f94fb0a4-601d-451b-9695-b21c937e8c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102234648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1102234648
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1738774105
Short name T565
Test name
Test status
Simulation time 4188777664 ps
CPU time 15.82 seconds
Started May 05 01:34:56 PM PDT 24
Finished May 05 01:35:12 PM PDT 24
Peak memory 199144 kb
Host smart-dd46c7b8-c3da-426c-a427-075229e6e0cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738774105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1738774105
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.286779575
Short name T658
Test name
Test status
Simulation time 41173454200 ps
CPU time 87.76 seconds
Started May 05 01:34:51 PM PDT 24
Finished May 05 01:36:19 PM PDT 24
Peak memory 200372 kb
Host smart-73c7ed45-9b0d-4af2-9114-c3a01f70aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286779575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.286779575
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.201856657
Short name T17
Test name
Test status
Simulation time 4115010777 ps
CPU time 7.12 seconds
Started May 05 01:34:49 PM PDT 24
Finished May 05 01:34:57 PM PDT 24
Peak memory 196652 kb
Host smart-b6b4bfc1-2f28-463d-ba8a-bf8684f5a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201856657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.201856657
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2271241532
Short name T10
Test name
Test status
Simulation time 672700920 ps
CPU time 2.54 seconds
Started May 05 01:34:46 PM PDT 24
Finished May 05 01:34:49 PM PDT 24
Peak memory 200016 kb
Host smart-d6d2f57a-3106-4da2-b9b8-90abe8e01532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271241532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2271241532
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2587725403
Short name T850
Test name
Test status
Simulation time 72708236811 ps
CPU time 528.24 seconds
Started May 05 01:34:56 PM PDT 24
Finished May 05 01:43:44 PM PDT 24
Peak memory 200496 kb
Host smart-3dbbdfd1-3276-416a-a803-1786e3fc2f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587725403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2587725403
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2799611431
Short name T105
Test name
Test status
Simulation time 204588247884 ps
CPU time 413.81 seconds
Started May 05 01:34:55 PM PDT 24
Finished May 05 01:41:49 PM PDT 24
Peak memory 216884 kb
Host smart-a407c1f1-46d4-4c11-ba32-40aacf04830c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799611431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2799611431
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1955079868
Short name T464
Test name
Test status
Simulation time 1135109834 ps
CPU time 2.24 seconds
Started May 05 01:34:55 PM PDT 24
Finished May 05 01:34:58 PM PDT 24
Peak memory 199216 kb
Host smart-6f7353d1-2020-4966-8a45-8b59342d233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955079868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1955079868
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.795297631
Short name T757
Test name
Test status
Simulation time 19595801193 ps
CPU time 40.14 seconds
Started May 05 01:34:46 PM PDT 24
Finished May 05 01:35:27 PM PDT 24
Peak memory 200376 kb
Host smart-97316d12-c0d7-4516-b87b-6c41bd5fc139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795297631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.795297631
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2500819841
Short name T1111
Test name
Test status
Simulation time 14422700 ps
CPU time 0.55 seconds
Started May 05 01:35:05 PM PDT 24
Finished May 05 01:35:06 PM PDT 24
Peak memory 195748 kb
Host smart-879ad86f-4023-4e19-a822-4c6e0f19acc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500819841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2500819841
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3495801321
Short name T1000
Test name
Test status
Simulation time 67568048972 ps
CPU time 24.26 seconds
Started May 05 01:35:02 PM PDT 24
Finished May 05 01:35:27 PM PDT 24
Peak memory 200340 kb
Host smart-71b6c5c3-cc68-416b-b544-a0cac9d316b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495801321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3495801321
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3607617483
Short name T417
Test name
Test status
Simulation time 9959199303 ps
CPU time 19.61 seconds
Started May 05 01:34:59 PM PDT 24
Finished May 05 01:35:19 PM PDT 24
Peak memory 200216 kb
Host smart-5c386d2e-053b-488f-84ea-1c31d6f2fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607617483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3607617483
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.658369723
Short name T205
Test name
Test status
Simulation time 239755423382 ps
CPU time 63.76 seconds
Started May 05 01:35:01 PM PDT 24
Finished May 05 01:36:06 PM PDT 24
Peak memory 200452 kb
Host smart-8e1a6627-978e-43d7-8910-64351972146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658369723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.658369723
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3590845449
Short name T626
Test name
Test status
Simulation time 34727994004 ps
CPU time 30.68 seconds
Started May 05 01:35:01 PM PDT 24
Finished May 05 01:35:32 PM PDT 24
Peak memory 198400 kb
Host smart-3362b474-2c62-4066-8dc3-71784402d248
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590845449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3590845449
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3732112834
Short name T1133
Test name
Test status
Simulation time 81309731853 ps
CPU time 358.81 seconds
Started May 05 01:35:06 PM PDT 24
Finished May 05 01:41:05 PM PDT 24
Peak memory 200324 kb
Host smart-4b2ee137-df04-4db1-8d88-7ab53219818b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732112834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3732112834
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1544026798
Short name T103
Test name
Test status
Simulation time 1187412669 ps
CPU time 2.11 seconds
Started May 05 01:35:05 PM PDT 24
Finished May 05 01:35:07 PM PDT 24
Peak memory 198968 kb
Host smart-2661727c-38f2-4a6b-b408-1f4cb6cb6386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544026798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1544026798
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1963721205
Short name T281
Test name
Test status
Simulation time 9848194976 ps
CPU time 16.23 seconds
Started May 05 01:35:02 PM PDT 24
Finished May 05 01:35:19 PM PDT 24
Peak memory 198088 kb
Host smart-8b2e6b80-0acb-401f-9955-5ab4da4cbb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963721205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1963721205
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2019407065
Short name T636
Test name
Test status
Simulation time 11884446088 ps
CPU time 273.16 seconds
Started May 05 01:35:06 PM PDT 24
Finished May 05 01:39:39 PM PDT 24
Peak memory 200292 kb
Host smart-5b704185-e33e-4aaa-af7f-539f00c62d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019407065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2019407065
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3130363216
Short name T367
Test name
Test status
Simulation time 3989723713 ps
CPU time 9.25 seconds
Started May 05 01:35:01 PM PDT 24
Finished May 05 01:35:10 PM PDT 24
Peak memory 198504 kb
Host smart-5548e8c7-eb9a-4a83-b093-9c9dd8afc223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130363216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3130363216
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3590325749
Short name T712
Test name
Test status
Simulation time 62213867229 ps
CPU time 30.37 seconds
Started May 05 01:35:01 PM PDT 24
Finished May 05 01:35:32 PM PDT 24
Peak memory 200296 kb
Host smart-05b1dfc8-0fce-407a-9ba2-75c73cc8ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590325749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3590325749
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.22413910
Short name T618
Test name
Test status
Simulation time 1935200059 ps
CPU time 1.43 seconds
Started May 05 01:35:01 PM PDT 24
Finished May 05 01:35:03 PM PDT 24
Peak memory 195752 kb
Host smart-77588cfc-4469-4f3b-a90b-4813f3c629cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22413910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.22413910
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3147893455
Short name T860
Test name
Test status
Simulation time 5628035193 ps
CPU time 16.36 seconds
Started May 05 01:34:56 PM PDT 24
Finished May 05 01:35:12 PM PDT 24
Peak memory 200324 kb
Host smart-c58b9ff4-8e03-424a-85d0-e07efe7df671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147893455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3147893455
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2265980703
Short name T1063
Test name
Test status
Simulation time 30726793655 ps
CPU time 22.55 seconds
Started May 05 01:35:05 PM PDT 24
Finished May 05 01:35:28 PM PDT 24
Peak memory 200372 kb
Host smart-078477e7-2659-4af3-a641-cb39b9bd8bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265980703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2265980703
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.206704345
Short name T919
Test name
Test status
Simulation time 4595922397 ps
CPU time 2.44 seconds
Started May 05 01:34:59 PM PDT 24
Finished May 05 01:35:02 PM PDT 24
Peak memory 200104 kb
Host smart-28109042-3e14-4c2c-b9f2-ae23b6231233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206704345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.206704345
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.16020540
Short name T1160
Test name
Test status
Simulation time 53846702304 ps
CPU time 86.29 seconds
Started May 05 01:34:55 PM PDT 24
Finished May 05 01:36:22 PM PDT 24
Peak memory 200320 kb
Host smart-f9eec1a1-8660-4060-9019-572ccf8c7be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16020540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.16020540
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2606982387
Short name T344
Test name
Test status
Simulation time 11072385 ps
CPU time 0.58 seconds
Started May 05 01:30:19 PM PDT 24
Finished May 05 01:30:20 PM PDT 24
Peak memory 195768 kb
Host smart-8af9979b-ea8c-4e11-a986-d4c5324543fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606982387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2606982387
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.676262428
Short name T572
Test name
Test status
Simulation time 61602485237 ps
CPU time 24.12 seconds
Started May 05 01:30:15 PM PDT 24
Finished May 05 01:30:40 PM PDT 24
Peak memory 200112 kb
Host smart-6a126fc6-ff53-4242-8e80-5d0ce703f8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676262428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.676262428
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4272149189
Short name T300
Test name
Test status
Simulation time 61748891563 ps
CPU time 96.54 seconds
Started May 05 01:30:18 PM PDT 24
Finished May 05 01:31:55 PM PDT 24
Peak memory 200148 kb
Host smart-46858e9e-728f-47fe-8b5b-12535be5921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272149189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4272149189
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2311040971
Short name T959
Test name
Test status
Simulation time 39219898882 ps
CPU time 38.37 seconds
Started May 05 01:30:14 PM PDT 24
Finished May 05 01:30:53 PM PDT 24
Peak memory 200372 kb
Host smart-05bf2f62-c8e4-4c5f-b32e-e05a6e005d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311040971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2311040971
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2698022300
Short name T776
Test name
Test status
Simulation time 63799194370 ps
CPU time 94.39 seconds
Started May 05 01:30:19 PM PDT 24
Finished May 05 01:31:54 PM PDT 24
Peak memory 200392 kb
Host smart-70721d94-c30a-4ce3-973b-eef538a62fa4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698022300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2698022300
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4181978337
Short name T920
Test name
Test status
Simulation time 66485968918 ps
CPU time 669.32 seconds
Started May 05 01:30:16 PM PDT 24
Finished May 05 01:41:26 PM PDT 24
Peak memory 200368 kb
Host smart-ee6d48e5-b487-424f-8c3b-f42a7351c2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181978337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4181978337
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1659078783
Short name T345
Test name
Test status
Simulation time 4540075088 ps
CPU time 8.36 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:30:26 PM PDT 24
Peak memory 198952 kb
Host smart-11611502-526c-4728-9f85-eff763dafa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659078783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1659078783
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.4186399369
Short name T1077
Test name
Test status
Simulation time 77750666693 ps
CPU time 38.42 seconds
Started May 05 01:30:19 PM PDT 24
Finished May 05 01:30:58 PM PDT 24
Peak memory 200456 kb
Host smart-0880fc95-22a0-4387-b727-02b2ef400934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186399369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4186399369
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.123750829
Short name T1021
Test name
Test status
Simulation time 12407638024 ps
CPU time 159.68 seconds
Started May 05 01:30:16 PM PDT 24
Finished May 05 01:32:56 PM PDT 24
Peak memory 200384 kb
Host smart-98f2e41d-f688-404e-a8bb-6f94bbbb8159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123750829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.123750829
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2081206545
Short name T906
Test name
Test status
Simulation time 6522883494 ps
CPU time 13.69 seconds
Started May 05 01:30:18 PM PDT 24
Finished May 05 01:30:32 PM PDT 24
Peak memory 199268 kb
Host smart-d0f5c051-a6fa-450b-ac94-fcd4dccef783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081206545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2081206545
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2701632564
Short name T749
Test name
Test status
Simulation time 130950205883 ps
CPU time 194.66 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:33:32 PM PDT 24
Peak memory 200288 kb
Host smart-6358bf5a-606d-4c30-8fd4-9fae988a956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701632564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2701632564
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2908836792
Short name T333
Test name
Test status
Simulation time 3563609477 ps
CPU time 0.97 seconds
Started May 05 01:30:19 PM PDT 24
Finished May 05 01:30:20 PM PDT 24
Peak memory 196652 kb
Host smart-383536c5-d76d-4fd2-ab88-d2e5a3f80987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908836792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2908836792
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1539954285
Short name T94
Test name
Test status
Simulation time 40312533 ps
CPU time 0.78 seconds
Started May 05 01:30:16 PM PDT 24
Finished May 05 01:30:18 PM PDT 24
Peak memory 218576 kb
Host smart-c3aa2387-048f-4feb-baaa-fbe0166d8c0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539954285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1539954285
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3857380758
Short name T756
Test name
Test status
Simulation time 266763186 ps
CPU time 1.43 seconds
Started May 05 01:30:14 PM PDT 24
Finished May 05 01:30:16 PM PDT 24
Peak memory 198924 kb
Host smart-981660de-2823-4661-a1dc-8c1f5c8ff9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857380758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3857380758
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2102036046
Short name T783
Test name
Test status
Simulation time 688279244097 ps
CPU time 459.02 seconds
Started May 05 01:30:19 PM PDT 24
Finished May 05 01:37:58 PM PDT 24
Peak memory 216512 kb
Host smart-db5b7edf-3ef8-4402-a130-0f6097072a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102036046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2102036046
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.377523711
Short name T64
Test name
Test status
Simulation time 67044874490 ps
CPU time 719.17 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:42:17 PM PDT 24
Peak memory 216912 kb
Host smart-6e351f43-c48d-4edb-b28a-d32aa414ced0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377523711 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.377523711
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3848948460
Short name T402
Test name
Test status
Simulation time 659848950 ps
CPU time 2.16 seconds
Started May 05 01:30:16 PM PDT 24
Finished May 05 01:30:19 PM PDT 24
Peak memory 199188 kb
Host smart-abb74050-ab71-40a1-b0ce-60a364b626f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848948460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3848948460
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2620066874
Short name T83
Test name
Test status
Simulation time 35068731343 ps
CPU time 57.03 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:31:15 PM PDT 24
Peak memory 200368 kb
Host smart-8f14ca3a-06d8-4957-b298-52d6d2146ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620066874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2620066874
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1546305104
Short name T606
Test name
Test status
Simulation time 37494080 ps
CPU time 0.54 seconds
Started May 05 01:35:16 PM PDT 24
Finished May 05 01:35:17 PM PDT 24
Peak memory 195728 kb
Host smart-d78519e1-c4f6-4366-ba79-bbe2704fd6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546305104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1546305104
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3470642472
Short name T164
Test name
Test status
Simulation time 70212454941 ps
CPU time 27.3 seconds
Started May 05 01:35:05 PM PDT 24
Finished May 05 01:35:32 PM PDT 24
Peak memory 200368 kb
Host smart-d1edf849-b0d4-4c50-930c-3020caa98cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470642472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3470642472
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3534221379
Short name T1109
Test name
Test status
Simulation time 87192927887 ps
CPU time 38.46 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:48 PM PDT 24
Peak memory 199944 kb
Host smart-4377ae8f-c760-43a8-bc7a-d8279868a05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534221379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3534221379
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1957024069
Short name T237
Test name
Test status
Simulation time 63560806154 ps
CPU time 31.04 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:42 PM PDT 24
Peak memory 200356 kb
Host smart-87fe5a7d-f162-4a8b-9898-885363b2fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957024069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1957024069
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2868843823
Short name T823
Test name
Test status
Simulation time 18935514319 ps
CPU time 30.54 seconds
Started May 05 01:35:11 PM PDT 24
Finished May 05 01:35:43 PM PDT 24
Peak memory 200400 kb
Host smart-f29a5aa7-354b-4c6d-b8a1-ce00fb784909
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868843823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2868843823
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2901537630
Short name T267
Test name
Test status
Simulation time 93574192596 ps
CPU time 637.02 seconds
Started May 05 01:35:12 PM PDT 24
Finished May 05 01:45:50 PM PDT 24
Peak memory 200416 kb
Host smart-b0a5f300-0889-42ac-a31c-545d202adf9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901537630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2901537630
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4278691276
Short name T996
Test name
Test status
Simulation time 833742958 ps
CPU time 1.28 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:12 PM PDT 24
Peak memory 196444 kb
Host smart-ca94235d-dd39-4b1f-b631-87ccd9918fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278691276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4278691276
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.564322272
Short name T766
Test name
Test status
Simulation time 64750758688 ps
CPU time 136.31 seconds
Started May 05 01:35:11 PM PDT 24
Finished May 05 01:37:27 PM PDT 24
Peak memory 200588 kb
Host smart-6510e248-1f5e-45f6-87e8-d6acf77fd1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564322272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.564322272
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.385726068
Short name T1094
Test name
Test status
Simulation time 11940456807 ps
CPU time 159.75 seconds
Started May 05 01:35:12 PM PDT 24
Finished May 05 01:37:52 PM PDT 24
Peak memory 200284 kb
Host smart-3f96aadb-7b1e-4b04-aa02-227c1978c235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=385726068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.385726068
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3854622794
Short name T566
Test name
Test status
Simulation time 4971828357 ps
CPU time 13.59 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:24 PM PDT 24
Peak memory 198948 kb
Host smart-2b4b177a-5e59-4fe5-92fe-73e38da9bbe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854622794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3854622794
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3794283790
Short name T140
Test name
Test status
Simulation time 162223205954 ps
CPU time 27.46 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:38 PM PDT 24
Peak memory 200336 kb
Host smart-3168a2e8-8f32-4ef4-9229-3a5298083174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794283790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3794283790
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1769965742
Short name T890
Test name
Test status
Simulation time 610977494 ps
CPU time 1.62 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:12 PM PDT 24
Peak memory 195776 kb
Host smart-16958df6-833a-4945-8339-5c4f6264a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769965742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1769965742
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2899820496
Short name T829
Test name
Test status
Simulation time 522627779 ps
CPU time 1.07 seconds
Started May 05 01:35:06 PM PDT 24
Finished May 05 01:35:07 PM PDT 24
Peak memory 200308 kb
Host smart-b8083540-f635-44f9-8b21-492ebc659d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899820496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2899820496
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3886778959
Short name T196
Test name
Test status
Simulation time 947283459968 ps
CPU time 165.84 seconds
Started May 05 01:35:13 PM PDT 24
Finished May 05 01:37:59 PM PDT 24
Peak memory 208676 kb
Host smart-9cfa5a32-f268-4bd4-ab9d-6bac3309a6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886778959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3886778959
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.617804982
Short name T733
Test name
Test status
Simulation time 23867659852 ps
CPU time 133.52 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:37:24 PM PDT 24
Peak memory 216984 kb
Host smart-91bdf7a6-dc42-4598-af36-08d0443d2307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617804982 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.617804982
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3896195559
Short name T512
Test name
Test status
Simulation time 1179620163 ps
CPU time 4 seconds
Started May 05 01:35:10 PM PDT 24
Finished May 05 01:35:15 PM PDT 24
Peak memory 199776 kb
Host smart-87039f5a-a47e-4ef8-a6b2-7cc6ed5c79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896195559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3896195559
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4186648543
Short name T1125
Test name
Test status
Simulation time 132110788498 ps
CPU time 22.76 seconds
Started May 05 01:35:05 PM PDT 24
Finished May 05 01:35:28 PM PDT 24
Peak memory 200172 kb
Host smart-be7d6920-e014-40ab-a002-0d7440f36170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186648543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4186648543
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1887206311
Short name T908
Test name
Test status
Simulation time 63194762 ps
CPU time 0.55 seconds
Started May 05 01:35:27 PM PDT 24
Finished May 05 01:35:28 PM PDT 24
Peak memory 195256 kb
Host smart-f9fac16d-5493-45d0-a634-c52041fbe4cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887206311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1887206311
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1988098353
Short name T656
Test name
Test status
Simulation time 189538929194 ps
CPU time 300.24 seconds
Started May 05 01:35:17 PM PDT 24
Finished May 05 01:40:18 PM PDT 24
Peak memory 200340 kb
Host smart-1f615b0c-aed6-444e-beb1-e0285cb358b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988098353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1988098353
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2138366232
Short name T862
Test name
Test status
Simulation time 77756460256 ps
CPU time 21.11 seconds
Started May 05 01:35:17 PM PDT 24
Finished May 05 01:35:39 PM PDT 24
Peak memory 200352 kb
Host smart-5623d2ea-c8e1-4b8f-968a-a36be5201d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138366232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2138366232
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.566036648
Short name T792
Test name
Test status
Simulation time 22951858649 ps
CPU time 36.04 seconds
Started May 05 01:35:14 PM PDT 24
Finished May 05 01:35:50 PM PDT 24
Peak memory 200160 kb
Host smart-f035c579-a360-4657-a8be-dc03ec475c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566036648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.566036648
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3898708610
Short name T1017
Test name
Test status
Simulation time 118602214785 ps
CPU time 37.6 seconds
Started May 05 01:35:14 PM PDT 24
Finished May 05 01:35:52 PM PDT 24
Peak memory 196372 kb
Host smart-890cbff7-466b-452c-a2c7-018b6360d708
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898708610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3898708610
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4173489001
Short name T485
Test name
Test status
Simulation time 92926906891 ps
CPU time 268.56 seconds
Started May 05 01:35:22 PM PDT 24
Finished May 05 01:39:51 PM PDT 24
Peak memory 200380 kb
Host smart-3e3a5598-703e-4450-bfc8-1cdcc5bfdf7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173489001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4173489001
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.4194050344
Short name T676
Test name
Test status
Simulation time 9688516527 ps
CPU time 6.61 seconds
Started May 05 01:35:20 PM PDT 24
Finished May 05 01:35:27 PM PDT 24
Peak memory 198860 kb
Host smart-f86c77f7-0979-44ae-9c84-a8f9483edd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194050344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4194050344
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3904194987
Short name T1174
Test name
Test status
Simulation time 45535969656 ps
CPU time 122.4 seconds
Started May 05 01:35:17 PM PDT 24
Finished May 05 01:37:20 PM PDT 24
Peak memory 199724 kb
Host smart-a59f8d70-308f-4864-a3a6-fc4177334382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904194987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3904194987
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2332332876
Short name T941
Test name
Test status
Simulation time 13414161358 ps
CPU time 164.67 seconds
Started May 05 01:35:20 PM PDT 24
Finished May 05 01:38:05 PM PDT 24
Peak memory 200340 kb
Host smart-768f2635-c131-40bc-9334-a8b920a8a7ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332332876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2332332876
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1945325145
Short name T371
Test name
Test status
Simulation time 7451251888 ps
CPU time 69.01 seconds
Started May 05 01:35:15 PM PDT 24
Finished May 05 01:36:24 PM PDT 24
Peak memory 198968 kb
Host smart-9bb87b87-a4f1-4f72-ace6-55ea7548d37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945325145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1945325145
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1871614764
Short name T500
Test name
Test status
Simulation time 118547398050 ps
CPU time 42.51 seconds
Started May 05 01:35:20 PM PDT 24
Finished May 05 01:36:03 PM PDT 24
Peak memory 200364 kb
Host smart-f2c54de1-40c9-4b4e-b6a1-fc54b8d16157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871614764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1871614764
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3263991774
Short name T443
Test name
Test status
Simulation time 48018514432 ps
CPU time 13.36 seconds
Started May 05 01:35:20 PM PDT 24
Finished May 05 01:35:34 PM PDT 24
Peak memory 196296 kb
Host smart-48885fbb-1e54-4313-8257-9ea0c2851b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263991774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3263991774
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.523901826
Short name T273
Test name
Test status
Simulation time 509926830 ps
CPU time 2.27 seconds
Started May 05 01:35:15 PM PDT 24
Finished May 05 01:35:18 PM PDT 24
Peak memory 199312 kb
Host smart-03462ce1-d455-4418-acac-45e844c975a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523901826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.523901826
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2942601237
Short name T311
Test name
Test status
Simulation time 92257599849 ps
CPU time 287.96 seconds
Started May 05 01:35:22 PM PDT 24
Finished May 05 01:40:11 PM PDT 24
Peak memory 216992 kb
Host smart-0b0ea419-f2b1-4f17-b564-4cc632088e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942601237 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2942601237
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.191299024
Short name T296
Test name
Test status
Simulation time 6807716817 ps
CPU time 11.31 seconds
Started May 05 01:35:20 PM PDT 24
Finished May 05 01:35:32 PM PDT 24
Peak memory 200228 kb
Host smart-61382385-626d-48fe-b2c8-8387f1e0601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191299024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.191299024
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1694906768
Short name T608
Test name
Test status
Simulation time 161268292974 ps
CPU time 113.7 seconds
Started May 05 01:35:15 PM PDT 24
Finished May 05 01:37:10 PM PDT 24
Peak memory 200356 kb
Host smart-2265cc4c-4c14-467f-8265-c41af4ae9b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694906768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1694906768
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.256879389
Short name T441
Test name
Test status
Simulation time 34783603 ps
CPU time 0.55 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:35:35 PM PDT 24
Peak memory 195492 kb
Host smart-5d70b854-1c1a-4588-8df7-ea79939eee27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256879389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.256879389
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2515384959
Short name T1099
Test name
Test status
Simulation time 138797888900 ps
CPU time 242.89 seconds
Started May 05 01:35:24 PM PDT 24
Finished May 05 01:39:28 PM PDT 24
Peak memory 200388 kb
Host smart-29ac9b92-3ca4-4912-a303-e05fd080a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515384959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2515384959
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2909365259
Short name T424
Test name
Test status
Simulation time 90421930552 ps
CPU time 37.26 seconds
Started May 05 01:35:25 PM PDT 24
Finished May 05 01:36:03 PM PDT 24
Peak memory 199244 kb
Host smart-a8c26042-3cee-4cbe-9995-a768bef97323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909365259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2909365259
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.217162200
Short name T240
Test name
Test status
Simulation time 111755031051 ps
CPU time 43.36 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:36:17 PM PDT 24
Peak memory 200116 kb
Host smart-c50aa227-d19d-4e6e-9868-81866634c3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217162200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.217162200
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2892482024
Short name T994
Test name
Test status
Simulation time 9194251722 ps
CPU time 2.82 seconds
Started May 05 01:35:29 PM PDT 24
Finished May 05 01:35:32 PM PDT 24
Peak memory 197172 kb
Host smart-1d45eadb-d48f-45e7-a773-e52f3415496a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892482024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2892482024
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1911691937
Short name T256
Test name
Test status
Simulation time 72953970721 ps
CPU time 148.04 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:37:59 PM PDT 24
Peak memory 200392 kb
Host smart-d5e3694d-0d0f-4ac8-883a-867bf86d1f7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911691937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1911691937
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2795876670
Short name T761
Test name
Test status
Simulation time 9519652346 ps
CPU time 6.54 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:35:38 PM PDT 24
Peak memory 199016 kb
Host smart-eba39cd9-944b-4875-99e4-caed73b0c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795876670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2795876670
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2422137297
Short name T1137
Test name
Test status
Simulation time 29270469513 ps
CPU time 38.84 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:36:10 PM PDT 24
Peak memory 199292 kb
Host smart-cf8df3df-f9b0-44ec-95d9-1c6221343ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422137297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2422137297
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2808091778
Short name T1080
Test name
Test status
Simulation time 9702042782 ps
CPU time 100.47 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:37:11 PM PDT 24
Peak memory 200524 kb
Host smart-53f5914f-8e9e-41b5-a544-cb0528c54575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808091778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2808091778
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2272827852
Short name T331
Test name
Test status
Simulation time 6742592337 ps
CPU time 62.48 seconds
Started May 05 01:35:32 PM PDT 24
Finished May 05 01:36:35 PM PDT 24
Peak memory 198836 kb
Host smart-c558b3bb-9348-45ef-b552-e5fa522b5c9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272827852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2272827852
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.257247676
Short name T725
Test name
Test status
Simulation time 30421650484 ps
CPU time 52.14 seconds
Started May 05 01:35:32 PM PDT 24
Finished May 05 01:36:24 PM PDT 24
Peak memory 200328 kb
Host smart-9c36b2db-40a2-47fe-a539-c9301f66f319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257247676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.257247676
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3492026643
Short name T866
Test name
Test status
Simulation time 844394932 ps
CPU time 2.2 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:35:34 PM PDT 24
Peak memory 195760 kb
Host smart-f1c3b8cc-b2a9-446d-b499-56d731d0d8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492026643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3492026643
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.707725151
Short name T337
Test name
Test status
Simulation time 6004195484 ps
CPU time 15.78 seconds
Started May 05 01:35:28 PM PDT 24
Finished May 05 01:35:44 PM PDT 24
Peak memory 200252 kb
Host smart-c5fccf1a-818f-409a-9068-de3464c1c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707725151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.707725151
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1837604551
Short name T14
Test name
Test status
Simulation time 319966806655 ps
CPU time 82.98 seconds
Started May 05 01:35:29 PM PDT 24
Finished May 05 01:36:53 PM PDT 24
Peak memory 208788 kb
Host smart-91785054-9194-4df0-a3af-7cb6ce5f2ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837604551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1837604551
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1176360275
Short name T106
Test name
Test status
Simulation time 70295842702 ps
CPU time 602.74 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 215112 kb
Host smart-5e5cf9c1-d830-498a-a673-d0b6c7ec6a7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176360275 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1176360275
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2743696750
Short name T355
Test name
Test status
Simulation time 6927816864 ps
CPU time 15.04 seconds
Started May 05 01:35:31 PM PDT 24
Finished May 05 01:35:46 PM PDT 24
Peak memory 200308 kb
Host smart-ee171ab1-2be3-4359-b4b2-51adc7c9058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743696750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2743696750
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2250863473
Short name T973
Test name
Test status
Simulation time 27245822006 ps
CPU time 47.95 seconds
Started May 05 01:35:25 PM PDT 24
Finished May 05 01:36:13 PM PDT 24
Peak memory 200332 kb
Host smart-f6243f24-3e86-4fc0-ab2c-4fb3d42ded35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250863473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2250863473
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1311633783
Short name T526
Test name
Test status
Simulation time 40019057 ps
CPU time 0.54 seconds
Started May 05 01:35:35 PM PDT 24
Finished May 05 01:35:35 PM PDT 24
Peak memory 195768 kb
Host smart-3a60caf5-475c-459f-887f-a63b92ea1c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311633783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1311633783
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1388390328
Short name T1083
Test name
Test status
Simulation time 161861625088 ps
CPU time 83.6 seconds
Started May 05 01:35:29 PM PDT 24
Finished May 05 01:36:53 PM PDT 24
Peak memory 200368 kb
Host smart-d244e0f5-3ab3-4d20-9c09-42250d392132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388390328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1388390328
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3896141894
Short name T163
Test name
Test status
Simulation time 92585136344 ps
CPU time 42.82 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:36:17 PM PDT 24
Peak memory 200356 kb
Host smart-f99be773-08ce-4081-8238-5ac38ea7d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896141894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3896141894
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.757289765
Short name T155
Test name
Test status
Simulation time 249106811448 ps
CPU time 99.95 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:37:15 PM PDT 24
Peak memory 200308 kb
Host smart-818da6f3-bb50-4b94-aa11-0cbe12e09cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757289765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.757289765
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3266555700
Short name T459
Test name
Test status
Simulation time 47553481585 ps
CPU time 47.35 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:36:21 PM PDT 24
Peak memory 199816 kb
Host smart-7c7bfb82-d637-40aa-bd28-5ab9ab11f4ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266555700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3266555700
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1968955862
Short name T821
Test name
Test status
Simulation time 56630909655 ps
CPU time 166.85 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:38:21 PM PDT 24
Peak memory 200320 kb
Host smart-dd19b6b6-95e2-45c8-8f8f-41d55fc633d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968955862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1968955862
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2203931057
Short name T701
Test name
Test status
Simulation time 2039696334 ps
CPU time 5.74 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:35:40 PM PDT 24
Peak memory 198716 kb
Host smart-3ef0a402-12e1-428a-8043-acd64b607dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203931057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2203931057
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.565680361
Short name T284
Test name
Test status
Simulation time 28072319517 ps
CPU time 49.56 seconds
Started May 05 01:35:40 PM PDT 24
Finished May 05 01:36:30 PM PDT 24
Peak memory 200628 kb
Host smart-b5b9ad27-ade0-4f80-95e4-da755424fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565680361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.565680361
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2933738637
Short name T790
Test name
Test status
Simulation time 18626022303 ps
CPU time 267.4 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:40:02 PM PDT 24
Peak memory 200312 kb
Host smart-75bbd51d-cabb-488c-879c-ca7e02d838b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933738637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2933738637
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2000014492
Short name T357
Test name
Test status
Simulation time 3771622024 ps
CPU time 31.49 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:36:06 PM PDT 24
Peak memory 198348 kb
Host smart-74fd466d-a9db-4070-8454-8bf03e63fd48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000014492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2000014492
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3860746976
Short name T372
Test name
Test status
Simulation time 59396437056 ps
CPU time 136.1 seconds
Started May 05 01:35:38 PM PDT 24
Finished May 05 01:37:54 PM PDT 24
Peak memory 200276 kb
Host smart-c1b2f1a7-17d9-4c4c-a9a1-9afafa141d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860746976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3860746976
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3539267016
Short name T1132
Test name
Test status
Simulation time 38968829091 ps
CPU time 19.45 seconds
Started May 05 01:35:36 PM PDT 24
Finished May 05 01:35:55 PM PDT 24
Peak memory 196392 kb
Host smart-64ea7b8b-6ee5-4e36-a565-8ba8a0c12fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539267016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3539267016
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1621466513
Short name T634
Test name
Test status
Simulation time 506144571 ps
CPU time 4.66 seconds
Started May 05 01:35:32 PM PDT 24
Finished May 05 01:35:37 PM PDT 24
Peak memory 199900 kb
Host smart-116c0669-138f-4b36-b690-dd73fe33a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621466513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1621466513
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.959096674
Short name T121
Test name
Test status
Simulation time 212191623674 ps
CPU time 98.62 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 01:37:13 PM PDT 24
Peak memory 200388 kb
Host smart-4133b030-8059-4fbc-a8d5-ffbbd761be2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959096674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.959096674
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3783082820
Short name T1014
Test name
Test status
Simulation time 199131814380 ps
CPU time 1606.72 seconds
Started May 05 01:35:34 PM PDT 24
Finished May 05 02:02:21 PM PDT 24
Peak memory 216844 kb
Host smart-164275de-ab07-4fa3-b96a-defa7ab1e923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783082820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3783082820
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.4062919466
Short name T521
Test name
Test status
Simulation time 2778084423 ps
CPU time 2.71 seconds
Started May 05 01:35:35 PM PDT 24
Finished May 05 01:35:38 PM PDT 24
Peak memory 199820 kb
Host smart-bd70b612-6dcd-4756-a59d-9d21bfb9a35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062919466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4062919466
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3182426246
Short name T591
Test name
Test status
Simulation time 65848203045 ps
CPU time 111.32 seconds
Started May 05 01:35:32 PM PDT 24
Finished May 05 01:37:24 PM PDT 24
Peak memory 200324 kb
Host smart-26ed61ac-5609-422d-a9a9-868ad3af9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182426246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3182426246
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1697677684
Short name T1029
Test name
Test status
Simulation time 33169316 ps
CPU time 0.53 seconds
Started May 05 01:35:46 PM PDT 24
Finished May 05 01:35:47 PM PDT 24
Peak memory 195224 kb
Host smart-1071a1b3-0df3-453a-ab30-54871376b502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697677684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1697677684
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2263368433
Short name T547
Test name
Test status
Simulation time 134183152436 ps
CPU time 195.83 seconds
Started May 05 01:35:35 PM PDT 24
Finished May 05 01:38:51 PM PDT 24
Peak memory 200320 kb
Host smart-d39325b3-af54-47e5-bafd-fc77e53be7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263368433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2263368433
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.251662627
Short name T849
Test name
Test status
Simulation time 28034662704 ps
CPU time 49.86 seconds
Started May 05 01:35:40 PM PDT 24
Finished May 05 01:36:31 PM PDT 24
Peak memory 200384 kb
Host smart-d75b2ae9-b6df-48c6-bb2a-80ad0b1c68b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251662627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.251662627
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1121607677
Short name T167
Test name
Test status
Simulation time 69914487257 ps
CPU time 143.12 seconds
Started May 05 01:35:40 PM PDT 24
Finished May 05 01:38:03 PM PDT 24
Peak memory 200384 kb
Host smart-d1cf6842-9799-4559-aee2-603926a3f2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121607677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1121607677
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1808622049
Short name T714
Test name
Test status
Simulation time 51789015033 ps
CPU time 44.57 seconds
Started May 05 01:35:44 PM PDT 24
Finished May 05 01:36:29 PM PDT 24
Peak memory 200344 kb
Host smart-c4da921e-a1b2-494e-ab34-eb05f1f9d54b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808622049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1808622049
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.170758274
Short name T363
Test name
Test status
Simulation time 283144749598 ps
CPU time 350.3 seconds
Started May 05 01:35:42 PM PDT 24
Finished May 05 01:41:33 PM PDT 24
Peak memory 200380 kb
Host smart-54ebf9e9-c4d6-4306-ba8e-cafe294f7b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170758274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.170758274
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.588942058
Short name T553
Test name
Test status
Simulation time 3327264780 ps
CPU time 7 seconds
Started May 05 01:35:42 PM PDT 24
Finished May 05 01:35:50 PM PDT 24
Peak memory 200436 kb
Host smart-a8807b3e-d140-46ef-b6e1-c2d99c4cf263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588942058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.588942058
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1004329137
Short name T830
Test name
Test status
Simulation time 4388216227 ps
CPU time 60.79 seconds
Started May 05 01:35:42 PM PDT 24
Finished May 05 01:36:44 PM PDT 24
Peak memory 200404 kb
Host smart-bdb5a533-c7e7-40d8-bc2b-277662e4a447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004329137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1004329137
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2339001084
Short name T1082
Test name
Test status
Simulation time 3713536531 ps
CPU time 7.35 seconds
Started May 05 01:35:41 PM PDT 24
Finished May 05 01:35:49 PM PDT 24
Peak memory 198420 kb
Host smart-9ef042cd-4878-4380-b57f-869c52c7fba6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339001084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2339001084
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3912534888
Short name T135
Test name
Test status
Simulation time 63529395292 ps
CPU time 24.44 seconds
Started May 05 01:35:41 PM PDT 24
Finished May 05 01:36:06 PM PDT 24
Peak memory 200256 kb
Host smart-b4149727-80da-426e-8bfb-d2aa0934e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912534888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3912534888
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1460260098
Short name T1170
Test name
Test status
Simulation time 25416014445 ps
CPU time 10.57 seconds
Started May 05 01:35:40 PM PDT 24
Finished May 05 01:35:51 PM PDT 24
Peak memory 196348 kb
Host smart-b83c45ed-d831-43cb-aee4-9f6990758b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460260098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1460260098
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4087852387
Short name T1033
Test name
Test status
Simulation time 701864930 ps
CPU time 2.16 seconds
Started May 05 01:35:36 PM PDT 24
Finished May 05 01:35:38 PM PDT 24
Peak memory 200272 kb
Host smart-b1f0a58f-e7d2-4633-ab00-e7f1f5f10586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087852387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4087852387
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1679775834
Short name T1112
Test name
Test status
Simulation time 82384784047 ps
CPU time 1505.62 seconds
Started May 05 01:35:46 PM PDT 24
Finished May 05 02:00:52 PM PDT 24
Peak memory 200292 kb
Host smart-bd138088-0159-4792-b4f7-33ab8c5c7165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679775834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1679775834
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.949876344
Short name T29
Test name
Test status
Simulation time 18873099615 ps
CPU time 217.47 seconds
Started May 05 01:35:46 PM PDT 24
Finished May 05 01:39:24 PM PDT 24
Peak memory 216848 kb
Host smart-31a49366-29a8-465c-a4b2-3729bb632443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949876344 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.949876344
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1154101313
Short name T395
Test name
Test status
Simulation time 1251915762 ps
CPU time 1.74 seconds
Started May 05 01:35:40 PM PDT 24
Finished May 05 01:35:42 PM PDT 24
Peak memory 198620 kb
Host smart-982172d5-d988-4cc2-ab54-cdd38f31246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154101313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1154101313
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.897329222
Short name T1097
Test name
Test status
Simulation time 15613302318 ps
CPU time 6.93 seconds
Started May 05 01:35:35 PM PDT 24
Finished May 05 01:35:43 PM PDT 24
Peak memory 200288 kb
Host smart-f08ce572-db14-4338-85ac-7942e72dcd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897329222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.897329222
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3491858146
Short name T956
Test name
Test status
Simulation time 29523588 ps
CPU time 0.54 seconds
Started May 05 01:35:52 PM PDT 24
Finished May 05 01:35:53 PM PDT 24
Peak memory 195728 kb
Host smart-4fb31a9d-9b47-4fc2-8aa5-da4d924bf091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491858146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3491858146
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.687134632
Short name T935
Test name
Test status
Simulation time 48975734832 ps
CPU time 74.14 seconds
Started May 05 01:35:47 PM PDT 24
Finished May 05 01:37:02 PM PDT 24
Peak memory 200404 kb
Host smart-cfea50e6-f91c-4997-8aeb-93e2bfe5b83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687134632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.687134632
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4193574849
Short name T147
Test name
Test status
Simulation time 96225859602 ps
CPU time 37.57 seconds
Started May 05 01:35:44 PM PDT 24
Finished May 05 01:36:22 PM PDT 24
Peak memory 200248 kb
Host smart-db33bcf8-ade5-4036-ab13-2d442378400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193574849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4193574849
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.357797025
Short name T230
Test name
Test status
Simulation time 115344309373 ps
CPU time 144.88 seconds
Started May 05 01:35:45 PM PDT 24
Finished May 05 01:38:10 PM PDT 24
Peak memory 200316 kb
Host smart-92fbef08-7810-4815-a52d-5016b8eb8264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357797025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.357797025
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2746192913
Short name T305
Test name
Test status
Simulation time 31081056497 ps
CPU time 14.33 seconds
Started May 05 01:35:45 PM PDT 24
Finished May 05 01:35:59 PM PDT 24
Peak memory 200392 kb
Host smart-51e48740-f095-412f-b762-492e049bea74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746192913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2746192913
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2570122991
Short name T992
Test name
Test status
Simulation time 139158128260 ps
CPU time 402.66 seconds
Started May 05 01:35:50 PM PDT 24
Finished May 05 01:42:33 PM PDT 24
Peak memory 200364 kb
Host smart-50982bad-e979-4c3f-93f9-a20e1f2bc24f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570122991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2570122991
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3661346072
Short name T472
Test name
Test status
Simulation time 3071352747 ps
CPU time 6.59 seconds
Started May 05 01:35:52 PM PDT 24
Finished May 05 01:35:59 PM PDT 24
Peak memory 199104 kb
Host smart-d3ed13e5-eb1e-4fb9-99eb-b3dcd0431dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661346072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3661346072
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.209635068
Short name T835
Test name
Test status
Simulation time 31963341399 ps
CPU time 47.46 seconds
Started May 05 01:35:45 PM PDT 24
Finished May 05 01:36:33 PM PDT 24
Peak memory 200508 kb
Host smart-1edd926f-182d-4ff5-818a-c8fa7ec418f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209635068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.209635068
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2630012065
Short name T1115
Test name
Test status
Simulation time 16922682999 ps
CPU time 187.04 seconds
Started May 05 01:35:53 PM PDT 24
Finished May 05 01:39:00 PM PDT 24
Peak memory 200348 kb
Host smart-f679676f-00e0-47ce-86ef-a2c805254b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630012065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2630012065
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.351878790
Short name T493
Test name
Test status
Simulation time 2245603641 ps
CPU time 3.71 seconds
Started May 05 01:35:46 PM PDT 24
Finished May 05 01:35:50 PM PDT 24
Peak memory 198868 kb
Host smart-8fb48ec9-f3d1-4718-8acd-b9dafe17626a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351878790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.351878790
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2189649464
Short name T165
Test name
Test status
Simulation time 7752586289 ps
CPU time 3.9 seconds
Started May 05 01:35:51 PM PDT 24
Finished May 05 01:35:55 PM PDT 24
Peak memory 199932 kb
Host smart-ff6e4859-39fc-4df5-bf65-ff059a6a1798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189649464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2189649464
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.666885732
Short name T426
Test name
Test status
Simulation time 34640713382 ps
CPU time 14.47 seconds
Started May 05 01:35:45 PM PDT 24
Finished May 05 01:35:59 PM PDT 24
Peak memory 196104 kb
Host smart-82d19975-1bfb-4777-a357-6c8776592f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666885732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.666885732
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1770257905
Short name T752
Test name
Test status
Simulation time 488189779 ps
CPU time 1.48 seconds
Started May 05 01:35:45 PM PDT 24
Finished May 05 01:35:47 PM PDT 24
Peak memory 199668 kb
Host smart-34c3b915-1f14-425b-9c23-f7b5748632ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770257905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1770257905
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1600035484
Short name T463
Test name
Test status
Simulation time 107706480251 ps
CPU time 91.98 seconds
Started May 05 01:35:51 PM PDT 24
Finished May 05 01:37:23 PM PDT 24
Peak memory 200396 kb
Host smart-da5500b3-f44d-485f-a3bd-22e1d14bd098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600035484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1600035484
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1146623748
Short name T47
Test name
Test status
Simulation time 326290126112 ps
CPU time 606.08 seconds
Started May 05 01:35:54 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 216864 kb
Host smart-1d0ae04f-d6ec-4145-a39a-82b6aa29ce24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146623748 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1146623748
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4028919061
Short name T293
Test name
Test status
Simulation time 6966902993 ps
CPU time 10.1 seconds
Started May 05 01:35:50 PM PDT 24
Finished May 05 01:36:01 PM PDT 24
Peak memory 200012 kb
Host smart-469c0606-52f9-4df0-b0b4-87a592c30070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028919061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4028919061
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2226563177
Short name T295
Test name
Test status
Simulation time 9849438001 ps
CPU time 12.11 seconds
Started May 05 01:35:44 PM PDT 24
Finished May 05 01:35:57 PM PDT 24
Peak memory 200432 kb
Host smart-03428cf9-7dc2-41b1-9c5a-01791d858b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226563177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2226563177
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.954257806
Short name T581
Test name
Test status
Simulation time 12821803 ps
CPU time 0.55 seconds
Started May 05 01:35:59 PM PDT 24
Finished May 05 01:35:59 PM PDT 24
Peak memory 195768 kb
Host smart-e8565312-abce-484a-9526-404ca8777042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954257806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.954257806
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4151637436
Short name T1181
Test name
Test status
Simulation time 191674715036 ps
CPU time 75.79 seconds
Started May 05 01:35:50 PM PDT 24
Finished May 05 01:37:06 PM PDT 24
Peak memory 200352 kb
Host smart-ec4463e6-56ee-4354-aaa6-954bce074e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151637436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4151637436
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.963135567
Short name T1167
Test name
Test status
Simulation time 42148459754 ps
CPU time 66.93 seconds
Started May 05 01:35:52 PM PDT 24
Finished May 05 01:36:59 PM PDT 24
Peak memory 200284 kb
Host smart-490a30a0-bc03-4463-8257-cf9c90f34ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963135567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.963135567
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3804288757
Short name T250
Test name
Test status
Simulation time 117427703606 ps
CPU time 218.74 seconds
Started May 05 01:35:55 PM PDT 24
Finished May 05 01:39:34 PM PDT 24
Peak memory 200336 kb
Host smart-70cf7405-209f-4ebc-8f9e-88ed7bb11918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804288757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3804288757
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1244572001
Short name T888
Test name
Test status
Simulation time 29933421534 ps
CPU time 46.63 seconds
Started May 05 01:35:55 PM PDT 24
Finished May 05 01:36:42 PM PDT 24
Peak memory 200344 kb
Host smart-a2fa0d44-ab40-4148-ab31-4dd43dd73f3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244572001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1244572001
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1999798678
Short name T641
Test name
Test status
Simulation time 40118872629 ps
CPU time 262.54 seconds
Started May 05 01:36:01 PM PDT 24
Finished May 05 01:40:23 PM PDT 24
Peak memory 200356 kb
Host smart-1759d558-a991-45b8-a8ae-870d8f08966a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999798678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1999798678
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3362292687
Short name T343
Test name
Test status
Simulation time 1149160931 ps
CPU time 2.33 seconds
Started May 05 01:36:03 PM PDT 24
Finished May 05 01:36:05 PM PDT 24
Peak memory 196292 kb
Host smart-d5af4443-fe3c-4f96-8bfa-19f3409ac8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362292687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3362292687
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4216331463
Short name T285
Test name
Test status
Simulation time 26964764863 ps
CPU time 46.53 seconds
Started May 05 01:35:55 PM PDT 24
Finished May 05 01:36:42 PM PDT 24
Peak memory 200576 kb
Host smart-e8230729-6e39-4338-8828-dbadb0b20314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216331463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4216331463
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1615637653
Short name T265
Test name
Test status
Simulation time 7947417474 ps
CPU time 194.17 seconds
Started May 05 01:36:00 PM PDT 24
Finished May 05 01:39:15 PM PDT 24
Peak memory 200320 kb
Host smart-2c539ff0-2df7-42e4-bc92-f0919354dfc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615637653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1615637653
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.4229401956
Short name T589
Test name
Test status
Simulation time 5777310739 ps
CPU time 6.07 seconds
Started May 05 01:35:55 PM PDT 24
Finished May 05 01:36:01 PM PDT 24
Peak memory 199744 kb
Host smart-778310ce-5740-4aec-bc0c-c94c26af0dae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229401956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4229401956
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2383822539
Short name T844
Test name
Test status
Simulation time 62996215678 ps
CPU time 51.34 seconds
Started May 05 01:35:56 PM PDT 24
Finished May 05 01:36:48 PM PDT 24
Peak memory 200296 kb
Host smart-e52bc5c2-8d47-48a1-8a20-11fce1f502f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383822539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2383822539
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3486027576
Short name T384
Test name
Test status
Simulation time 4409362201 ps
CPU time 4.01 seconds
Started May 05 01:35:57 PM PDT 24
Finished May 05 01:36:01 PM PDT 24
Peak memory 196404 kb
Host smart-3814a6cf-68f8-4bc5-a65b-366b0f068c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486027576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3486027576
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1776760645
Short name T378
Test name
Test status
Simulation time 666883640 ps
CPU time 2.56 seconds
Started May 05 01:35:55 PM PDT 24
Finished May 05 01:35:58 PM PDT 24
Peak memory 199156 kb
Host smart-efaf2835-d1e5-4d16-a182-1ea008fab071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776760645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1776760645
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.110785171
Short name T150
Test name
Test status
Simulation time 34027641793 ps
CPU time 55.97 seconds
Started May 05 01:36:03 PM PDT 24
Finished May 05 01:36:59 PM PDT 24
Peak memory 200420 kb
Host smart-f1a34a94-6730-4fd2-a87a-2a8f88dc195b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110785171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.110785171
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.47184105
Short name T839
Test name
Test status
Simulation time 91351630833 ps
CPU time 631.05 seconds
Started May 05 01:36:00 PM PDT 24
Finished May 05 01:46:31 PM PDT 24
Peak memory 215036 kb
Host smart-f1474688-ced7-42d0-9b9a-e1cf3db93974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47184105 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.47184105
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1250028530
Short name T309
Test name
Test status
Simulation time 7313637715 ps
CPU time 14.22 seconds
Started May 05 01:35:55 PM PDT 24
Finished May 05 01:36:09 PM PDT 24
Peak memory 200308 kb
Host smart-eafb37f2-dd44-432a-babe-56cc02013b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250028530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1250028530
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.550755005
Short name T330
Test name
Test status
Simulation time 7083397966 ps
CPU time 11.16 seconds
Started May 05 01:35:50 PM PDT 24
Finished May 05 01:36:02 PM PDT 24
Peak memory 197376 kb
Host smart-5604fa72-4d25-4d74-9631-a5531036b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550755005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.550755005
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2875768871
Short name T347
Test name
Test status
Simulation time 22696191 ps
CPU time 0.56 seconds
Started May 05 01:36:12 PM PDT 24
Finished May 05 01:36:13 PM PDT 24
Peak memory 195748 kb
Host smart-90c5f401-f651-4a73-bfc1-839a7cf1337d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875768871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2875768871
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2215406492
Short name T516
Test name
Test status
Simulation time 199834540348 ps
CPU time 23.66 seconds
Started May 05 01:36:00 PM PDT 24
Finished May 05 01:36:24 PM PDT 24
Peak memory 200396 kb
Host smart-587e1b36-7846-479d-bf22-4e11b019eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215406492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2215406492
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1841413380
Short name T910
Test name
Test status
Simulation time 22320282297 ps
CPU time 18.07 seconds
Started May 05 01:36:01 PM PDT 24
Finished May 05 01:36:19 PM PDT 24
Peak memory 200288 kb
Host smart-a083eb29-9acb-4ec1-8ce7-bc4208c933b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841413380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1841413380
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1101353065
Short name T503
Test name
Test status
Simulation time 57970815080 ps
CPU time 25.32 seconds
Started May 05 01:36:02 PM PDT 24
Finished May 05 01:36:28 PM PDT 24
Peak memory 199108 kb
Host smart-e8342cb7-ac46-4a5d-97f8-44cfe9fcf30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101353065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1101353065
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.50328763
Short name T534
Test name
Test status
Simulation time 206500860311 ps
CPU time 333.76 seconds
Started May 05 01:36:06 PM PDT 24
Finished May 05 01:41:40 PM PDT 24
Peak memory 199452 kb
Host smart-bb9b2dfd-7376-4326-9755-10d7acb5e411
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50328763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.50328763
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3981300848
Short name T1073
Test name
Test status
Simulation time 164878450978 ps
CPU time 1198.69 seconds
Started May 05 01:36:04 PM PDT 24
Finished May 05 01:56:03 PM PDT 24
Peak memory 200320 kb
Host smart-ca21ec7c-0b0b-4d64-9da4-8ab385f749a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981300848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3981300848
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3421402713
Short name T536
Test name
Test status
Simulation time 1273028419 ps
CPU time 1.67 seconds
Started May 05 01:36:05 PM PDT 24
Finished May 05 01:36:07 PM PDT 24
Peak memory 199296 kb
Host smart-baeb41a1-a9ba-459d-933b-173c5f2f2ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421402713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3421402713
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3463748052
Short name T1121
Test name
Test status
Simulation time 155103752033 ps
CPU time 126.16 seconds
Started May 05 01:36:08 PM PDT 24
Finished May 05 01:38:14 PM PDT 24
Peak memory 208772 kb
Host smart-3fc901c6-da2b-47bc-9232-39731466a7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463748052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3463748052
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2645583781
Short name T33
Test name
Test status
Simulation time 6240339534 ps
CPU time 365.25 seconds
Started May 05 01:36:05 PM PDT 24
Finished May 05 01:42:11 PM PDT 24
Peak memory 200412 kb
Host smart-444a333c-8f95-400f-a973-dbfd383e394f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645583781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2645583781
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3446045291
Short name T654
Test name
Test status
Simulation time 5367659292 ps
CPU time 22.92 seconds
Started May 05 01:36:08 PM PDT 24
Finished May 05 01:36:31 PM PDT 24
Peak memory 199420 kb
Host smart-8caad2fa-5d99-4526-9fe2-6e94a8029af3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446045291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3446045291
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2420548065
Short name T905
Test name
Test status
Simulation time 40097849325 ps
CPU time 20.13 seconds
Started May 05 01:36:06 PM PDT 24
Finished May 05 01:36:26 PM PDT 24
Peak memory 200284 kb
Host smart-83f3e897-ed00-4298-9044-e906becd8316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420548065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2420548065
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1376279577
Short name T303
Test name
Test status
Simulation time 4478894039 ps
CPU time 4.41 seconds
Started May 05 01:36:07 PM PDT 24
Finished May 05 01:36:11 PM PDT 24
Peak memory 196404 kb
Host smart-cafa39c6-ae5b-4bb1-8858-ad94cbae3bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376279577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1376279577
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4284612676
Short name T489
Test name
Test status
Simulation time 503835101 ps
CPU time 2.72 seconds
Started May 05 01:36:00 PM PDT 24
Finished May 05 01:36:03 PM PDT 24
Peak memory 199156 kb
Host smart-713e16a5-2e0f-4940-88f9-31210d36b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284612676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4284612676
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3691164721
Short name T51
Test name
Test status
Simulation time 203481899330 ps
CPU time 670.71 seconds
Started May 05 01:36:06 PM PDT 24
Finished May 05 01:47:17 PM PDT 24
Peak memory 217028 kb
Host smart-a57bc61c-f4a2-4750-8aed-3214d3110c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691164721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3691164721
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1064031678
Short name T784
Test name
Test status
Simulation time 7665195853 ps
CPU time 9.84 seconds
Started May 05 01:36:06 PM PDT 24
Finished May 05 01:36:16 PM PDT 24
Peak memory 200276 kb
Host smart-04ce8bff-ca0f-4036-8756-6bd651a89ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064031678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1064031678
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.817541400
Short name T975
Test name
Test status
Simulation time 71306578296 ps
CPU time 126.69 seconds
Started May 05 01:35:59 PM PDT 24
Finished May 05 01:38:06 PM PDT 24
Peak memory 200356 kb
Host smart-aacb018f-3a93-42ca-8f8a-008a9b93e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817541400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.817541400
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3705348931
Short name T811
Test name
Test status
Simulation time 47775182 ps
CPU time 0.55 seconds
Started May 05 01:36:16 PM PDT 24
Finished May 05 01:36:17 PM PDT 24
Peak memory 195772 kb
Host smart-63bf66e5-2b9c-4a2b-87af-fffb6b2f44f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705348931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3705348931
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2041085010
Short name T1134
Test name
Test status
Simulation time 119265191440 ps
CPU time 198.46 seconds
Started May 05 01:36:10 PM PDT 24
Finished May 05 01:39:29 PM PDT 24
Peak memory 200352 kb
Host smart-ad441945-d1f9-4721-a227-237d585c9c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041085010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2041085010
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2028452497
Short name T486
Test name
Test status
Simulation time 29784318960 ps
CPU time 26.67 seconds
Started May 05 01:36:11 PM PDT 24
Finished May 05 01:36:38 PM PDT 24
Peak memory 200376 kb
Host smart-cd022505-93a6-491e-8c50-562b7bbb5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028452497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2028452497
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.933253773
Short name T221
Test name
Test status
Simulation time 81077347258 ps
CPU time 128.56 seconds
Started May 05 01:36:11 PM PDT 24
Finished May 05 01:38:20 PM PDT 24
Peak memory 200452 kb
Host smart-d8db8d81-b83e-493e-98d1-087293d7e4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933253773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.933253773
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1342684192
Short name T615
Test name
Test status
Simulation time 3932272942 ps
CPU time 1.66 seconds
Started May 05 01:36:11 PM PDT 24
Finished May 05 01:36:13 PM PDT 24
Peak memory 196240 kb
Host smart-673e02ba-905a-4528-9f61-511d64b8e743
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342684192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1342684192
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2062107638
Short name T964
Test name
Test status
Simulation time 138551951838 ps
CPU time 1123.13 seconds
Started May 05 01:36:17 PM PDT 24
Finished May 05 01:55:00 PM PDT 24
Peak memory 200360 kb
Host smart-5a0d2ee5-0115-4844-9f16-f67c33602d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062107638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2062107638
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3520671865
Short name T923
Test name
Test status
Simulation time 2427268903 ps
CPU time 4.07 seconds
Started May 05 01:36:16 PM PDT 24
Finished May 05 01:36:20 PM PDT 24
Peak memory 196548 kb
Host smart-772d0689-d191-4f5d-9f28-605366d29daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520671865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3520671865
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.415595495
Short name T471
Test name
Test status
Simulation time 141328627414 ps
CPU time 62.3 seconds
Started May 05 01:36:11 PM PDT 24
Finished May 05 01:37:14 PM PDT 24
Peak memory 208584 kb
Host smart-a4b241f4-6752-40f7-a848-840a14ea7f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415595495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.415595495
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3078077906
Short name T979
Test name
Test status
Simulation time 15435211033 ps
CPU time 432.64 seconds
Started May 05 01:36:18 PM PDT 24
Finished May 05 01:43:31 PM PDT 24
Peak memory 200364 kb
Host smart-5cf76260-5a2c-4599-89f2-6b38b4c69fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078077906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3078077906
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1101141188
Short name T427
Test name
Test status
Simulation time 3576772280 ps
CPU time 13.72 seconds
Started May 05 01:36:13 PM PDT 24
Finished May 05 01:36:27 PM PDT 24
Peak memory 198788 kb
Host smart-9fe109fd-bb7a-4eae-b712-80bdc6874dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101141188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1101141188
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1205030382
Short name T796
Test name
Test status
Simulation time 81797269865 ps
CPU time 42.65 seconds
Started May 05 01:36:11 PM PDT 24
Finished May 05 01:36:54 PM PDT 24
Peak memory 200364 kb
Host smart-d7651982-1b53-4fa3-8e1f-1ee590a3b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205030382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1205030382
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.544218458
Short name T1050
Test name
Test status
Simulation time 4103038917 ps
CPU time 1.04 seconds
Started May 05 01:36:10 PM PDT 24
Finished May 05 01:36:11 PM PDT 24
Peak memory 196464 kb
Host smart-71ee00d9-b086-4f9a-98f1-cbb98d4e094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544218458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.544218458
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2366185499
Short name T261
Test name
Test status
Simulation time 478751722 ps
CPU time 2.43 seconds
Started May 05 01:36:12 PM PDT 24
Finished May 05 01:36:15 PM PDT 24
Peak memory 198976 kb
Host smart-e0a188c1-750e-474b-b7c4-51e34c09ffe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366185499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2366185499
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1356933734
Short name T742
Test name
Test status
Simulation time 59857289450 ps
CPU time 90.14 seconds
Started May 05 01:36:17 PM PDT 24
Finished May 05 01:37:48 PM PDT 24
Peak memory 200368 kb
Host smart-fde42863-588d-42d8-ae1c-547812699008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356933734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1356933734
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.393155469
Short name T26
Test name
Test status
Simulation time 40946077904 ps
CPU time 384.01 seconds
Started May 05 01:36:17 PM PDT 24
Finished May 05 01:42:42 PM PDT 24
Peak memory 216816 kb
Host smart-7ef077c4-166f-4277-b616-54c73a640f1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393155469 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.393155469
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2844156107
Short name T907
Test name
Test status
Simulation time 1138441565 ps
CPU time 4.15 seconds
Started May 05 01:36:17 PM PDT 24
Finished May 05 01:36:22 PM PDT 24
Peak memory 198816 kb
Host smart-2288354a-e746-489b-9b86-651ce8b79d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844156107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2844156107
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3377945741
Short name T963
Test name
Test status
Simulation time 302791222666 ps
CPU time 98.51 seconds
Started May 05 01:36:13 PM PDT 24
Finished May 05 01:37:52 PM PDT 24
Peak memory 200252 kb
Host smart-6c4bac87-3e45-4b5c-b1ed-57efc3d3b22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377945741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3377945741
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.48930585
Short name T946
Test name
Test status
Simulation time 36351537 ps
CPU time 0.51 seconds
Started May 05 01:36:27 PM PDT 24
Finished May 05 01:36:28 PM PDT 24
Peak memory 195764 kb
Host smart-0823fde7-bf87-4f3b-9eb8-de1262cdb323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48930585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.48930585
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1024279197
Short name T1059
Test name
Test status
Simulation time 49013789597 ps
CPU time 77.54 seconds
Started May 05 01:36:24 PM PDT 24
Finished May 05 01:37:42 PM PDT 24
Peak memory 200316 kb
Host smart-b65d2e61-6854-4989-8960-12f66dd2c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024279197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1024279197
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2721428487
Short name T502
Test name
Test status
Simulation time 28261084689 ps
CPU time 14.22 seconds
Started May 05 01:36:22 PM PDT 24
Finished May 05 01:36:37 PM PDT 24
Peak memory 200024 kb
Host smart-90483a81-7f11-4c04-bb05-08fed1cdb3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721428487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2721428487
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.2528320958
Short name T737
Test name
Test status
Simulation time 34126457176 ps
CPU time 15.06 seconds
Started May 05 01:36:24 PM PDT 24
Finished May 05 01:36:39 PM PDT 24
Peak memory 200064 kb
Host smart-edcbec7f-3628-486e-b2e9-188ffa833aa6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528320958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2528320958
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3191432380
Short name T898
Test name
Test status
Simulation time 46145338842 ps
CPU time 226.26 seconds
Started May 05 01:36:30 PM PDT 24
Finished May 05 01:40:17 PM PDT 24
Peak memory 200348 kb
Host smart-a5dc785f-2793-4239-89d4-d102c9dfa86f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191432380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3191432380
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1799754157
Short name T574
Test name
Test status
Simulation time 1474817841 ps
CPU time 1.23 seconds
Started May 05 01:36:28 PM PDT 24
Finished May 05 01:36:29 PM PDT 24
Peak memory 197200 kb
Host smart-55b5e45f-8bc3-4828-a969-251fe915728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799754157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1799754157
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1586916033
Short name T1103
Test name
Test status
Simulation time 63967158106 ps
CPU time 138.22 seconds
Started May 05 01:36:24 PM PDT 24
Finished May 05 01:38:42 PM PDT 24
Peak memory 208704 kb
Host smart-041944ca-99fa-4a6e-b9e3-56d8b30ce1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586916033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1586916033
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1151324472
Short name T440
Test name
Test status
Simulation time 27993462581 ps
CPU time 125.7 seconds
Started May 05 01:36:26 PM PDT 24
Finished May 05 01:38:32 PM PDT 24
Peak memory 200380 kb
Host smart-1bfac225-35cd-4790-b8ef-0bed59dd67f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151324472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1151324472
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2438191936
Short name T495
Test name
Test status
Simulation time 1796725043 ps
CPU time 4.6 seconds
Started May 05 01:36:23 PM PDT 24
Finished May 05 01:36:28 PM PDT 24
Peak memory 198232 kb
Host smart-ea9533ce-d999-4070-a01d-1041e1c329ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438191936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2438191936
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.288041060
Short name T621
Test name
Test status
Simulation time 60131883857 ps
CPU time 27.18 seconds
Started May 05 01:36:21 PM PDT 24
Finished May 05 01:36:49 PM PDT 24
Peak memory 200388 kb
Host smart-9e9e2dc5-1b96-40e5-8d9d-8d8d85beceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288041060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.288041060
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.878353298
Short name T288
Test name
Test status
Simulation time 32528532908 ps
CPU time 55.66 seconds
Started May 05 01:36:22 PM PDT 24
Finished May 05 01:37:18 PM PDT 24
Peak memory 196380 kb
Host smart-36d6071a-113d-4c3d-a73b-7143eb5cb73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878353298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.878353298
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1856243008
Short name T649
Test name
Test status
Simulation time 672054613 ps
CPU time 1.59 seconds
Started May 05 01:36:16 PM PDT 24
Finished May 05 01:36:18 PM PDT 24
Peak memory 199932 kb
Host smart-38a027f4-cc8c-42d8-bb56-313b979bd432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856243008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1856243008
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2921291580
Short name T111
Test name
Test status
Simulation time 31251150352 ps
CPU time 27.1 seconds
Started May 05 01:36:28 PM PDT 24
Finished May 05 01:36:55 PM PDT 24
Peak memory 200396 kb
Host smart-4311ac4d-7cbd-4871-b642-cc6704e2120e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921291580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2921291580
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2176055697
Short name T604
Test name
Test status
Simulation time 25043170072 ps
CPU time 509.41 seconds
Started May 05 01:36:29 PM PDT 24
Finished May 05 01:44:59 PM PDT 24
Peak memory 216940 kb
Host smart-a442a2c1-f097-476e-a879-0eb719ba983c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176055697 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2176055697
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3903992638
Short name T711
Test name
Test status
Simulation time 2298923645 ps
CPU time 2.04 seconds
Started May 05 01:36:24 PM PDT 24
Finished May 05 01:36:26 PM PDT 24
Peak memory 198312 kb
Host smart-2a51b720-64e9-4c8d-8b0f-79c563bb963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903992638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3903992638
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.921846578
Short name T922
Test name
Test status
Simulation time 3378738853 ps
CPU time 5.73 seconds
Started May 05 01:36:22 PM PDT 24
Finished May 05 01:36:28 PM PDT 24
Peak memory 197008 kb
Host smart-12759da7-19c5-4825-8688-afcb89233a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921846578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.921846578
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.103775579
Short name T19
Test name
Test status
Simulation time 14549419 ps
CPU time 0.57 seconds
Started May 05 01:30:26 PM PDT 24
Finished May 05 01:30:27 PM PDT 24
Peak memory 195828 kb
Host smart-355abcee-7d54-4cea-a64c-7b98f17beb7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103775579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.103775579
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1925591098
Short name T598
Test name
Test status
Simulation time 23608845325 ps
CPU time 31.85 seconds
Started May 05 01:30:18 PM PDT 24
Finished May 05 01:30:51 PM PDT 24
Peak memory 200388 kb
Host smart-3485a176-26be-4855-8d37-82b370a60128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925591098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1925591098
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2591233908
Short name T1067
Test name
Test status
Simulation time 166269956825 ps
CPU time 129.25 seconds
Started May 05 01:30:20 PM PDT 24
Finished May 05 01:32:30 PM PDT 24
Peak memory 200296 kb
Host smart-6b0f4b1a-28ef-458c-a217-863506b240f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591233908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2591233908
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2493764392
Short name T190
Test name
Test status
Simulation time 17147021823 ps
CPU time 30.71 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:30:48 PM PDT 24
Peak memory 200368 kb
Host smart-05003544-df79-48d5-a365-eeb2f288ef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493764392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2493764392
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.140444051
Short name T913
Test name
Test status
Simulation time 30358511414 ps
CPU time 43.08 seconds
Started May 05 01:30:16 PM PDT 24
Finished May 05 01:31:00 PM PDT 24
Peak memory 198704 kb
Host smart-30f26426-cfad-480c-8a5e-84085b605947
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140444051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.140444051
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.791837225
Short name T795
Test name
Test status
Simulation time 89617166479 ps
CPU time 424.74 seconds
Started May 05 01:30:21 PM PDT 24
Finished May 05 01:37:26 PM PDT 24
Peak memory 200396 kb
Host smart-081c98b9-a0ab-41b8-9c54-cd1175c1592a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791837225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.791837225
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3282284105
Short name T681
Test name
Test status
Simulation time 1834512756 ps
CPU time 6.51 seconds
Started May 05 01:30:23 PM PDT 24
Finished May 05 01:30:30 PM PDT 24
Peak memory 198572 kb
Host smart-ba85b703-27f7-4cb5-adcb-089d68a646c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282284105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3282284105
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3649102309
Short name T999
Test name
Test status
Simulation time 72209469846 ps
CPU time 45.7 seconds
Started May 05 01:30:23 PM PDT 24
Finished May 05 01:31:09 PM PDT 24
Peak memory 200568 kb
Host smart-8f8f6152-db8e-425c-adeb-9e5cbab39d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649102309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3649102309
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3959168846
Short name T679
Test name
Test status
Simulation time 20747084414 ps
CPU time 69.77 seconds
Started May 05 01:30:26 PM PDT 24
Finished May 05 01:31:36 PM PDT 24
Peak memory 200356 kb
Host smart-06259ed4-9a50-4c89-b522-de07633fd30b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959168846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3959168846
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3933610356
Short name T580
Test name
Test status
Simulation time 1271314954 ps
CPU time 2.77 seconds
Started May 05 01:30:20 PM PDT 24
Finished May 05 01:30:23 PM PDT 24
Peak memory 198412 kb
Host smart-6d9ff091-68f0-433f-a83d-03cb1fd70650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933610356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3933610356
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1265056024
Short name T122
Test name
Test status
Simulation time 99515869746 ps
CPU time 162.34 seconds
Started May 05 01:30:23 PM PDT 24
Finished May 05 01:33:06 PM PDT 24
Peak memory 200324 kb
Host smart-a0adbc4d-bbdf-4b7c-a308-a2434e29b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265056024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1265056024
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1165969489
Short name T307
Test name
Test status
Simulation time 2023682569 ps
CPU time 1.35 seconds
Started May 05 01:30:24 PM PDT 24
Finished May 05 01:30:26 PM PDT 24
Peak memory 196004 kb
Host smart-f1d01190-6de8-4813-ba9c-fc5541d08a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165969489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1165969489
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.843646214
Short name T579
Test name
Test status
Simulation time 5717491765 ps
CPU time 13.96 seconds
Started May 05 01:30:17 PM PDT 24
Finished May 05 01:30:32 PM PDT 24
Peak memory 200180 kb
Host smart-33bf7530-6989-4435-af3c-1b9f9e825b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843646214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.843646214
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3409538965
Short name T982
Test name
Test status
Simulation time 398482728959 ps
CPU time 330 seconds
Started May 05 01:30:23 PM PDT 24
Finished May 05 01:35:53 PM PDT 24
Peak memory 200404 kb
Host smart-0e84d947-84d0-42c3-ae52-b367b1e6d5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409538965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3409538965
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1428562855
Short name T313
Test name
Test status
Simulation time 51599177077 ps
CPU time 632.53 seconds
Started May 05 01:30:26 PM PDT 24
Finished May 05 01:40:59 PM PDT 24
Peak memory 225228 kb
Host smart-4a19e772-8da3-431a-8c92-14e0538aae92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428562855 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1428562855
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4228530345
Short name T393
Test name
Test status
Simulation time 1800678267 ps
CPU time 2.1 seconds
Started May 05 01:30:24 PM PDT 24
Finished May 05 01:30:26 PM PDT 24
Peak memory 199956 kb
Host smart-292291ef-4215-4f24-97d6-4c7a8d922d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228530345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4228530345
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2589301647
Short name T533
Test name
Test status
Simulation time 117144057434 ps
CPU time 105.39 seconds
Started May 05 01:30:19 PM PDT 24
Finished May 05 01:32:05 PM PDT 24
Peak memory 200340 kb
Host smart-2a23baab-814c-4cfa-a317-f73b1821bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589301647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2589301647
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1227197209
Short name T884
Test name
Test status
Simulation time 89741002231 ps
CPU time 249.43 seconds
Started May 05 01:36:29 PM PDT 24
Finished May 05 01:40:38 PM PDT 24
Peak memory 200416 kb
Host smart-74bd8a75-9d9f-46c0-8118-8d70511e8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227197209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1227197209
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2592424332
Short name T901
Test name
Test status
Simulation time 57602357038 ps
CPU time 642.5 seconds
Started May 05 01:36:29 PM PDT 24
Finished May 05 01:47:12 PM PDT 24
Peak memory 216724 kb
Host smart-d72a0276-e925-4cd0-abbf-d90b498be517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592424332 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2592424332
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2228467750
Short name T231
Test name
Test status
Simulation time 111469621541 ps
CPU time 199.49 seconds
Started May 05 01:36:30 PM PDT 24
Finished May 05 01:39:50 PM PDT 24
Peak memory 200308 kb
Host smart-0ba85cf5-e00f-48bc-82f7-409bbbbad962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228467750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2228467750
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1477125575
Short name T234
Test name
Test status
Simulation time 135037659657 ps
CPU time 363.97 seconds
Started May 05 01:36:28 PM PDT 24
Finished May 05 01:42:32 PM PDT 24
Peak memory 212260 kb
Host smart-96f8f8c1-813f-4d98-be80-ff121d53fb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477125575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1477125575
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1577796135
Short name T878
Test name
Test status
Simulation time 37968221974 ps
CPU time 423.94 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:43:37 PM PDT 24
Peak memory 216996 kb
Host smart-6b7ee1f9-9268-4d7e-8b00-cac5a0c6d94a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577796135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1577796135
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2626673998
Short name T148
Test name
Test status
Simulation time 117081151917 ps
CPU time 61.43 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:37:34 PM PDT 24
Peak memory 200392 kb
Host smart-9eb3977d-5d0a-4610-a3f4-266870589812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626673998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2626673998
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2446137424
Short name T983
Test name
Test status
Simulation time 59749617694 ps
CPU time 25.76 seconds
Started May 05 01:36:36 PM PDT 24
Finished May 05 01:37:02 PM PDT 24
Peak memory 200472 kb
Host smart-b1972ded-ff85-4616-a5cd-5d24f046da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446137424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2446137424
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2876121293
Short name T1004
Test name
Test status
Simulation time 47529386758 ps
CPU time 424.42 seconds
Started May 05 01:36:33 PM PDT 24
Finished May 05 01:43:38 PM PDT 24
Peak memory 216844 kb
Host smart-6d13eb69-08f7-4f57-a22f-9f380856f554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876121293 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2876121293
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.4070766501
Short name T480
Test name
Test status
Simulation time 31080853153 ps
CPU time 47.12 seconds
Started May 05 01:36:33 PM PDT 24
Finished May 05 01:37:21 PM PDT 24
Peak memory 200404 kb
Host smart-f5da8692-5941-4858-b14a-21737d816103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070766501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.4070766501
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1101952520
Short name T1027
Test name
Test status
Simulation time 58953302576 ps
CPU time 258.6 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:40:51 PM PDT 24
Peak memory 214148 kb
Host smart-8b9f15bc-1d51-41b0-9a80-be10598e21fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101952520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1101952520
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.740016091
Short name T1147
Test name
Test status
Simulation time 83479282547 ps
CPU time 41.05 seconds
Started May 05 01:36:33 PM PDT 24
Finished May 05 01:37:14 PM PDT 24
Peak memory 200332 kb
Host smart-483011f6-04e6-4c50-8725-f291fa2e95a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740016091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.740016091
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3790476034
Short name T101
Test name
Test status
Simulation time 33250836614 ps
CPU time 488.2 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:44:41 PM PDT 24
Peak memory 216844 kb
Host smart-1fe7bf3b-f1b4-4f6b-be76-3f98adc41153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790476034 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3790476034
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.745231965
Short name T102
Test name
Test status
Simulation time 64100299145 ps
CPU time 62.05 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:37:35 PM PDT 24
Peak memory 200352 kb
Host smart-64f845bd-3e4f-47af-a0f1-5a0041c15558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745231965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.745231965
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.276876788
Short name T726
Test name
Test status
Simulation time 111160472453 ps
CPU time 733.79 seconds
Started May 05 01:36:32 PM PDT 24
Finished May 05 01:48:47 PM PDT 24
Peak memory 229448 kb
Host smart-44c1264c-e81d-47e6-bd21-778fca6ef74c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276876788 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.276876788
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2323993753
Short name T242
Test name
Test status
Simulation time 18783604833 ps
CPU time 15.45 seconds
Started May 05 01:36:37 PM PDT 24
Finished May 05 01:36:52 PM PDT 24
Peak memory 200356 kb
Host smart-19d7e144-b6a7-4344-ab69-c00994bf5974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323993753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2323993753
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2704043282
Short name T245
Test name
Test status
Simulation time 136980353356 ps
CPU time 953.28 seconds
Started May 05 01:36:36 PM PDT 24
Finished May 05 01:52:30 PM PDT 24
Peak memory 216836 kb
Host smart-728aebfc-3f7b-4198-8e86-59d966e35e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704043282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2704043282
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2955571398
Short name T814
Test name
Test status
Simulation time 108084670980 ps
CPU time 99.73 seconds
Started May 05 01:36:36 PM PDT 24
Finished May 05 01:38:16 PM PDT 24
Peak memory 200396 kb
Host smart-57cc4d8e-3566-471a-a5c4-420d98f83e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955571398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2955571398
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1978244239
Short name T108
Test name
Test status
Simulation time 20532419132 ps
CPU time 185.98 seconds
Started May 05 01:36:36 PM PDT 24
Finished May 05 01:39:42 PM PDT 24
Peak memory 208680 kb
Host smart-bab38f43-f153-44c1-b255-a17a89f167ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978244239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1978244239
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1808789226
Short name T1089
Test name
Test status
Simulation time 55468056 ps
CPU time 0.56 seconds
Started May 05 01:30:37 PM PDT 24
Finished May 05 01:30:38 PM PDT 24
Peak memory 195224 kb
Host smart-35a21107-f16b-46ff-8f6f-7426e09eaa87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808789226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1808789226
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1364392361
Short name T586
Test name
Test status
Simulation time 28514396656 ps
CPU time 47.18 seconds
Started May 05 01:30:22 PM PDT 24
Finished May 05 01:31:10 PM PDT 24
Peak memory 200364 kb
Host smart-13735df1-8b5e-49c8-9568-bc71a20cdc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364392361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1364392361
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.302975981
Short name T352
Test name
Test status
Simulation time 100308861848 ps
CPU time 214.4 seconds
Started May 05 01:30:24 PM PDT 24
Finished May 05 01:33:58 PM PDT 24
Peak memory 200328 kb
Host smart-8eb600a0-83fd-4fdc-a340-9fe1df2ede5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302975981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.302975981
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.632440239
Short name T271
Test name
Test status
Simulation time 84865043531 ps
CPU time 69.83 seconds
Started May 05 01:30:26 PM PDT 24
Finished May 05 01:31:36 PM PDT 24
Peak memory 200332 kb
Host smart-c49f4b67-eae4-4455-a4ad-6704086c6826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632440239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.632440239
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1562523988
Short name T318
Test name
Test status
Simulation time 11511315349 ps
CPU time 6.25 seconds
Started May 05 01:30:26 PM PDT 24
Finished May 05 01:30:32 PM PDT 24
Peak memory 199892 kb
Host smart-915bff1c-bea7-4be2-be5a-877bb72a2f9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562523988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1562523988
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2653272055
Short name T1037
Test name
Test status
Simulation time 84108505744 ps
CPU time 333.42 seconds
Started May 05 01:30:26 PM PDT 24
Finished May 05 01:36:00 PM PDT 24
Peak memory 200340 kb
Host smart-9d74da3a-a4a5-4a52-af1c-c60503e41995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653272055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2653272055
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.476076044
Short name T889
Test name
Test status
Simulation time 2345012077 ps
CPU time 2.37 seconds
Started May 05 01:30:28 PM PDT 24
Finished May 05 01:30:30 PM PDT 24
Peak memory 196672 kb
Host smart-415b8aeb-667d-49ec-a9c5-a6cec3ffd9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476076044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.476076044
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2257321468
Short name T965
Test name
Test status
Simulation time 179215581295 ps
CPU time 21 seconds
Started May 05 01:30:30 PM PDT 24
Finished May 05 01:30:51 PM PDT 24
Peak memory 198600 kb
Host smart-cb0898be-3a3f-4509-b3bf-b3a5cb2052b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257321468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2257321468
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.264835994
Short name T1166
Test name
Test status
Simulation time 18166638792 ps
CPU time 1009.89 seconds
Started May 05 01:30:30 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 200424 kb
Host smart-c39b0db9-b6f1-42e6-9190-ac454ae77eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264835994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.264835994
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3171574103
Short name T1028
Test name
Test status
Simulation time 4347820877 ps
CPU time 8.07 seconds
Started May 05 01:30:22 PM PDT 24
Finished May 05 01:30:31 PM PDT 24
Peak memory 198508 kb
Host smart-ab5d6c05-08e6-4c3a-8780-26275d72dbf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171574103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3171574103
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2814017873
Short name T397
Test name
Test status
Simulation time 174034725763 ps
CPU time 144.22 seconds
Started May 05 01:30:28 PM PDT 24
Finished May 05 01:32:53 PM PDT 24
Peak memory 200316 kb
Host smart-a24ed6b9-feb5-42b3-a77a-2049a6e32675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814017873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2814017873
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1614437057
Short name T294
Test name
Test status
Simulation time 3906517633 ps
CPU time 3.67 seconds
Started May 05 01:30:28 PM PDT 24
Finished May 05 01:30:32 PM PDT 24
Peak memory 196388 kb
Host smart-546f4eb6-8d5a-434c-99e6-02a8e238e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614437057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1614437057
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1287535033
Short name T1110
Test name
Test status
Simulation time 105582087 ps
CPU time 0.9 seconds
Started May 05 01:30:24 PM PDT 24
Finished May 05 01:30:25 PM PDT 24
Peak memory 198024 kb
Host smart-f29f8198-93ad-4046-bedb-00b6d44f44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287535033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1287535033
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.557788668
Short name T966
Test name
Test status
Simulation time 100180739943 ps
CPU time 169.15 seconds
Started May 05 01:30:32 PM PDT 24
Finished May 05 01:33:21 PM PDT 24
Peak memory 200408 kb
Host smart-5af81237-70d3-4b20-8175-5e40c6021553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557788668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.557788668
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3948056759
Short name T633
Test name
Test status
Simulation time 135037820887 ps
CPU time 916.32 seconds
Started May 05 01:30:28 PM PDT 24
Finished May 05 01:45:45 PM PDT 24
Peak memory 225236 kb
Host smart-a4b97b9d-ea1a-41ca-a03b-0624b2255df8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948056759 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3948056759
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2795153484
Short name T928
Test name
Test status
Simulation time 1008100766 ps
CPU time 1.7 seconds
Started May 05 01:30:27 PM PDT 24
Finished May 05 01:30:30 PM PDT 24
Peak memory 198820 kb
Host smart-26e7334a-1731-4cbf-b277-52117b91ffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795153484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2795153484
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.737957028
Short name T1155
Test name
Test status
Simulation time 116576039502 ps
CPU time 52.72 seconds
Started May 05 01:30:24 PM PDT 24
Finished May 05 01:31:17 PM PDT 24
Peak memory 200324 kb
Host smart-0a9c40d4-4619-429d-bb80-72f37299cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737957028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.737957028
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1277466597
Short name T721
Test name
Test status
Simulation time 115278264015 ps
CPU time 174.16 seconds
Started May 05 01:36:38 PM PDT 24
Finished May 05 01:39:32 PM PDT 24
Peak memory 200356 kb
Host smart-8713d8e8-7ada-4441-8b3c-69413f4649ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277466597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1277466597
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1015593778
Short name T1150
Test name
Test status
Simulation time 179476278548 ps
CPU time 656.07 seconds
Started May 05 01:36:38 PM PDT 24
Finished May 05 01:47:35 PM PDT 24
Peak memory 216856 kb
Host smart-22f33972-fd95-462f-9634-a68293647800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015593778 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1015593778
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2885982026
Short name T183
Test name
Test status
Simulation time 21573370730 ps
CPU time 36.28 seconds
Started May 05 01:36:37 PM PDT 24
Finished May 05 01:37:14 PM PDT 24
Peak memory 200360 kb
Host smart-fbd9e055-74e7-4da8-b26c-be3a9c17c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885982026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2885982026
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2118792336
Short name T312
Test name
Test status
Simulation time 176970694291 ps
CPU time 1304.87 seconds
Started May 05 01:36:40 PM PDT 24
Finished May 05 01:58:25 PM PDT 24
Peak memory 217704 kb
Host smart-e1085d47-78e5-486e-a826-7e4e3de6df91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118792336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2118792336
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3874130816
Short name T31
Test name
Test status
Simulation time 123752389044 ps
CPU time 56.35 seconds
Started May 05 01:36:37 PM PDT 24
Finished May 05 01:37:34 PM PDT 24
Peak memory 200320 kb
Host smart-332f0d5a-d4cd-4a45-a8c1-0d342ba031ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874130816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3874130816
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.277669803
Short name T65
Test name
Test status
Simulation time 39438019570 ps
CPU time 528.33 seconds
Started May 05 01:36:40 PM PDT 24
Finished May 05 01:45:29 PM PDT 24
Peak memory 217052 kb
Host smart-58e5addf-154a-4db9-88ac-63f1e2fb5a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277669803 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.277669803
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1635371694
Short name T235
Test name
Test status
Simulation time 211587073789 ps
CPU time 55.41 seconds
Started May 05 01:36:37 PM PDT 24
Finished May 05 01:37:32 PM PDT 24
Peak memory 200308 kb
Host smart-828411d8-66ca-45c1-9b42-2e5fa750b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635371694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1635371694
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3347921921
Short name T49
Test name
Test status
Simulation time 492420745995 ps
CPU time 1332.63 seconds
Started May 05 01:36:37 PM PDT 24
Finished May 05 01:58:50 PM PDT 24
Peak memory 226240 kb
Host smart-71cd84a6-3269-47b2-9b04-f4eecd3c4014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347921921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3347921921
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.640356756
Short name T213
Test name
Test status
Simulation time 62498845344 ps
CPU time 31.89 seconds
Started May 05 01:36:36 PM PDT 24
Finished May 05 01:37:09 PM PDT 24
Peak memory 200344 kb
Host smart-cbc20fca-6b20-4237-9a18-6a998a9fc6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640356756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.640356756
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1335109547
Short name T824
Test name
Test status
Simulation time 89040794884 ps
CPU time 373.02 seconds
Started May 05 01:36:36 PM PDT 24
Finished May 05 01:42:49 PM PDT 24
Peak memory 216808 kb
Host smart-cad38270-891b-46e1-b7bd-a3bbf3289cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335109547 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1335109547
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2423461498
Short name T767
Test name
Test status
Simulation time 17236446074 ps
CPU time 29.18 seconds
Started May 05 01:36:42 PM PDT 24
Finished May 05 01:37:12 PM PDT 24
Peak memory 200260 kb
Host smart-5a891c47-dba8-4cc5-9a70-cc2c6f861abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423461498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2423461498
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.995147532
Short name T1104
Test name
Test status
Simulation time 44653082340 ps
CPU time 489.78 seconds
Started May 05 01:36:41 PM PDT 24
Finished May 05 01:44:51 PM PDT 24
Peak memory 217032 kb
Host smart-be3ef744-d1bb-47e3-af08-de825e1b15ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995147532 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.995147532
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2230475817
Short name T640
Test name
Test status
Simulation time 195788789169 ps
CPU time 41.37 seconds
Started May 05 01:36:41 PM PDT 24
Finished May 05 01:37:22 PM PDT 24
Peak memory 200332 kb
Host smart-43fc606b-d0ba-4248-956c-7370c6e79c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230475817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2230475817
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.465607976
Short name T832
Test name
Test status
Simulation time 39063699513 ps
CPU time 185.89 seconds
Started May 05 01:36:42 PM PDT 24
Finished May 05 01:39:48 PM PDT 24
Peak memory 208656 kb
Host smart-19360946-273e-4c56-bd9e-9b2e546efaf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465607976 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.465607976
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3000302176
Short name T179
Test name
Test status
Simulation time 107225815855 ps
CPU time 15.25 seconds
Started May 05 01:36:48 PM PDT 24
Finished May 05 01:37:03 PM PDT 24
Peak memory 200076 kb
Host smart-c3bed6ea-e284-4613-ad79-3f34dc62fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000302176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3000302176
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1676648364
Short name T734
Test name
Test status
Simulation time 86403063432 ps
CPU time 854.22 seconds
Started May 05 01:36:47 PM PDT 24
Finished May 05 01:51:01 PM PDT 24
Peak memory 227584 kb
Host smart-8b9bac95-441a-42cb-a5cf-c48f6c740a38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676648364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1676648364
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.666355487
Short name T214
Test name
Test status
Simulation time 14822965169 ps
CPU time 26.67 seconds
Started May 05 01:36:47 PM PDT 24
Finished May 05 01:37:15 PM PDT 24
Peak memory 200376 kb
Host smart-23c8e6f5-b5bf-4810-b032-ca6afa31aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666355487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.666355487
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.950339275
Short name T52
Test name
Test status
Simulation time 160524812894 ps
CPU time 1168.21 seconds
Started May 05 01:36:46 PM PDT 24
Finished May 05 01:56:15 PM PDT 24
Peak memory 226252 kb
Host smart-4dfb0f5f-bf0e-4579-a1e4-a117d77c640d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950339275 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.950339275
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1038866698
Short name T675
Test name
Test status
Simulation time 22912907 ps
CPU time 0.54 seconds
Started May 05 01:30:39 PM PDT 24
Finished May 05 01:30:40 PM PDT 24
Peak memory 195760 kb
Host smart-657e731e-ff02-4869-9f08-815e2fa4a01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038866698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1038866698
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.89918477
Short name T745
Test name
Test status
Simulation time 32792318172 ps
CPU time 54.73 seconds
Started May 05 01:30:37 PM PDT 24
Finished May 05 01:31:33 PM PDT 24
Peak memory 199712 kb
Host smart-c1512694-63c0-4349-89f6-8598e554175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89918477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.89918477
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1132854000
Short name T926
Test name
Test status
Simulation time 25358252896 ps
CPU time 59.98 seconds
Started May 05 01:30:33 PM PDT 24
Finished May 05 01:31:33 PM PDT 24
Peak memory 200096 kb
Host smart-54b3015d-f10f-470e-bb60-ff1e18a54c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132854000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1132854000
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3822206197
Short name T509
Test name
Test status
Simulation time 14792574638 ps
CPU time 25.04 seconds
Started May 05 01:30:37 PM PDT 24
Finished May 05 01:31:03 PM PDT 24
Peak memory 200448 kb
Host smart-67a86723-813e-4902-a1b7-10b20ce31275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822206197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3822206197
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1758925493
Short name T466
Test name
Test status
Simulation time 13563958790 ps
CPU time 10.16 seconds
Started May 05 01:30:37 PM PDT 24
Finished May 05 01:30:48 PM PDT 24
Peak memory 197108 kb
Host smart-0157358b-4b4a-4151-80cb-9c8ec2f0a356
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758925493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1758925493
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.870514119
Short name T868
Test name
Test status
Simulation time 52244062773 ps
CPU time 61.69 seconds
Started May 05 01:30:39 PM PDT 24
Finished May 05 01:31:41 PM PDT 24
Peak memory 200312 kb
Host smart-25ac1b89-cc4d-454c-87a1-0b9442d5615c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870514119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.870514119
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1208239856
Short name T1117
Test name
Test status
Simulation time 12070380026 ps
CPU time 8.01 seconds
Started May 05 01:30:38 PM PDT 24
Finished May 05 01:30:47 PM PDT 24
Peak memory 200360 kb
Host smart-4740fd11-6ad8-416d-95de-ef7eb4d29410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208239856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1208239856
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1718683673
Short name T601
Test name
Test status
Simulation time 72793363737 ps
CPU time 31.05 seconds
Started May 05 01:30:37 PM PDT 24
Finished May 05 01:31:09 PM PDT 24
Peak memory 199224 kb
Host smart-15d558c2-a72b-429e-8f0a-de9b53aedec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718683673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1718683673
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.694736161
Short name T257
Test name
Test status
Simulation time 20483351161 ps
CPU time 294.7 seconds
Started May 05 01:30:38 PM PDT 24
Finished May 05 01:35:34 PM PDT 24
Peak memory 200380 kb
Host smart-f727b6e3-a8f7-4e71-8d67-dc455a01699a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694736161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.694736161
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2253407190
Short name T552
Test name
Test status
Simulation time 6363613601 ps
CPU time 57.99 seconds
Started May 05 01:30:40 PM PDT 24
Finished May 05 01:31:39 PM PDT 24
Peak memory 199836 kb
Host smart-b21ebba8-9639-48dd-81f3-6a950d94c714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253407190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2253407190
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2021901388
Short name T290
Test name
Test status
Simulation time 93013450625 ps
CPU time 60.41 seconds
Started May 05 01:30:38 PM PDT 24
Finished May 05 01:31:38 PM PDT 24
Peak memory 200392 kb
Host smart-c92a2c3d-6ad6-414f-b7bb-e90366e7f8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021901388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2021901388
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3183369481
Short name T904
Test name
Test status
Simulation time 3031667435 ps
CPU time 3.1 seconds
Started May 05 01:30:40 PM PDT 24
Finished May 05 01:30:43 PM PDT 24
Peak memory 196468 kb
Host smart-7c6550f5-7a0e-4319-aa2c-5c06817ababa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183369481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3183369481
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3871048539
Short name T575
Test name
Test status
Simulation time 670756495 ps
CPU time 2.44 seconds
Started May 05 01:30:33 PM PDT 24
Finished May 05 01:30:35 PM PDT 24
Peak memory 198620 kb
Host smart-f84032b5-c864-4729-8cc1-6bc7092e2daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871048539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3871048539
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2232138791
Short name T61
Test name
Test status
Simulation time 25624862696 ps
CPU time 166.56 seconds
Started May 05 01:30:40 PM PDT 24
Finished May 05 01:33:26 PM PDT 24
Peak memory 216792 kb
Host smart-25f51778-59e0-495d-83d8-5edab6d6320a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232138791 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2232138791
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3205924699
Short name T897
Test name
Test status
Simulation time 694577041 ps
CPU time 2.82 seconds
Started May 05 01:30:38 PM PDT 24
Finished May 05 01:30:41 PM PDT 24
Peak memory 198852 kb
Host smart-bfe00bb2-adf9-43da-9683-1fbad889745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205924699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3205924699
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.872336234
Short name T506
Test name
Test status
Simulation time 84139294243 ps
CPU time 86.99 seconds
Started May 05 01:30:38 PM PDT 24
Finished May 05 01:32:06 PM PDT 24
Peak memory 200428 kb
Host smart-a716bf1d-3ac3-41cf-8fec-68e0aae318b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872336234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.872336234
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3917932305
Short name T492
Test name
Test status
Simulation time 28718620364 ps
CPU time 16.15 seconds
Started May 05 01:36:47 PM PDT 24
Finished May 05 01:37:04 PM PDT 24
Peak memory 200376 kb
Host smart-0791e1ee-ce23-4cdb-9724-7efda8c2753b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917932305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3917932305
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2794875575
Short name T48
Test name
Test status
Simulation time 45387064590 ps
CPU time 325.29 seconds
Started May 05 01:36:48 PM PDT 24
Finished May 05 01:42:14 PM PDT 24
Peak memory 216080 kb
Host smart-4b492f4d-bd70-4dc8-8880-67c52062892e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794875575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2794875575
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3178662011
Short name T249
Test name
Test status
Simulation time 93692718625 ps
CPU time 45.72 seconds
Started May 05 01:36:46 PM PDT 24
Finished May 05 01:37:32 PM PDT 24
Peak memory 200328 kb
Host smart-1d064b50-b799-400f-9858-565e5230e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178662011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3178662011
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3483127749
Short name T28
Test name
Test status
Simulation time 59283413832 ps
CPU time 574.41 seconds
Started May 05 01:36:51 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 216040 kb
Host smart-0b1811b1-aed3-4c21-a0b9-d725b6f6d92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483127749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3483127749
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1207064662
Short name T1023
Test name
Test status
Simulation time 29568617688 ps
CPU time 26.11 seconds
Started May 05 01:36:51 PM PDT 24
Finished May 05 01:37:17 PM PDT 24
Peak memory 200252 kb
Host smart-a9de8096-d267-44b0-b4db-b675c6438a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207064662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1207064662
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3132063410
Short name T1165
Test name
Test status
Simulation time 53627049869 ps
CPU time 278.84 seconds
Started May 05 01:36:51 PM PDT 24
Finished May 05 01:41:31 PM PDT 24
Peak memory 216216 kb
Host smart-cc23ce85-78d1-410c-a94e-14c66cc838ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132063410 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3132063410
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2040924960
Short name T1129
Test name
Test status
Simulation time 57179227488 ps
CPU time 93.58 seconds
Started May 05 01:36:52 PM PDT 24
Finished May 05 01:38:26 PM PDT 24
Peak memory 200220 kb
Host smart-85743b8c-23f0-4013-8228-3206e0d7d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040924960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2040924960
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3631868453
Short name T30
Test name
Test status
Simulation time 81141936042 ps
CPU time 445.09 seconds
Started May 05 01:36:51 PM PDT 24
Finished May 05 01:44:17 PM PDT 24
Peak memory 216748 kb
Host smart-08b211e5-7e27-4215-891b-4ba9659d17ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631868453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3631868453
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2415453087
Short name T474
Test name
Test status
Simulation time 39491799705 ps
CPU time 17.78 seconds
Started May 05 01:36:52 PM PDT 24
Finished May 05 01:37:10 PM PDT 24
Peak memory 199728 kb
Host smart-59744036-8b78-470c-b077-e8cb367955c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415453087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2415453087
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.761478301
Short name T415
Test name
Test status
Simulation time 93991099160 ps
CPU time 39.56 seconds
Started May 05 01:36:53 PM PDT 24
Finished May 05 01:37:33 PM PDT 24
Peak memory 200336 kb
Host smart-77954169-2b66-431e-8f59-8edd9e0f06de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761478301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.761478301
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.414968874
Short name T1053
Test name
Test status
Simulation time 244114822930 ps
CPU time 312.52 seconds
Started May 05 01:36:56 PM PDT 24
Finished May 05 01:42:09 PM PDT 24
Peak memory 217004 kb
Host smart-309c54bd-0afe-4793-a42e-5d296f57edaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414968874 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.414968874
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2457096313
Short name T246
Test name
Test status
Simulation time 91844689681 ps
CPU time 40.91 seconds
Started May 05 01:36:58 PM PDT 24
Finished May 05 01:37:40 PM PDT 24
Peak memory 200172 kb
Host smart-2537676c-d3e2-40e1-9d1c-de7e2b96d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457096313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2457096313
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1987220958
Short name T1179
Test name
Test status
Simulation time 116139269203 ps
CPU time 1347.79 seconds
Started May 05 01:36:56 PM PDT 24
Finished May 05 01:59:24 PM PDT 24
Peak memory 233408 kb
Host smart-89d61def-2585-4faf-a854-8259fbdc81b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987220958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1987220958
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.282760807
Short name T174
Test name
Test status
Simulation time 69776135044 ps
CPU time 1195.73 seconds
Started May 05 01:36:57 PM PDT 24
Finished May 05 01:56:53 PM PDT 24
Peak memory 225256 kb
Host smart-7ff216e2-5729-471c-ad0f-d48368de8407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282760807 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.282760807
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1048728134
Short name T870
Test name
Test status
Simulation time 16241947065 ps
CPU time 25.84 seconds
Started May 05 01:36:58 PM PDT 24
Finished May 05 01:37:24 PM PDT 24
Peak memory 200320 kb
Host smart-0ea2657f-d636-4cf6-8dfc-39bc620bacf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048728134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1048728134
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3331430913
Short name T707
Test name
Test status
Simulation time 318533461919 ps
CPU time 1367.61 seconds
Started May 05 01:36:58 PM PDT 24
Finished May 05 01:59:46 PM PDT 24
Peak memory 225216 kb
Host smart-a9105d85-8344-49fc-ae1c-c5c2d0e0dc31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331430913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3331430913
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.766403349
Short name T299
Test name
Test status
Simulation time 19797101618 ps
CPU time 33.53 seconds
Started May 05 01:36:55 PM PDT 24
Finished May 05 01:37:29 PM PDT 24
Peak memory 200424 kb
Host smart-730c1dc5-f485-45bf-b2cc-f8671f09e582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766403349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.766403349
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1915203294
Short name T524
Test name
Test status
Simulation time 17315724 ps
CPU time 0.54 seconds
Started May 05 01:30:47 PM PDT 24
Finished May 05 01:30:49 PM PDT 24
Peak memory 195752 kb
Host smart-3304705b-aa13-425d-9ab4-9b302546f811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915203294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1915203294
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.967862434
Short name T286
Test name
Test status
Simulation time 30427897829 ps
CPU time 21.87 seconds
Started May 05 01:30:42 PM PDT 24
Finished May 05 01:31:04 PM PDT 24
Peak memory 199892 kb
Host smart-02a20247-3361-4a74-b140-2804a2741b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967862434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.967862434
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.162677416
Short name T1010
Test name
Test status
Simulation time 54192969084 ps
CPU time 15.38 seconds
Started May 05 01:30:43 PM PDT 24
Finished May 05 01:30:58 PM PDT 24
Peak memory 198836 kb
Host smart-62b9e2c8-3a77-426e-9b83-83aa1eda8214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162677416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.162677416
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3742798957
Short name T876
Test name
Test status
Simulation time 42109149981 ps
CPU time 13.66 seconds
Started May 05 01:30:41 PM PDT 24
Finished May 05 01:30:55 PM PDT 24
Peak memory 200376 kb
Host smart-f2005f9d-c613-45ef-a873-b28b360fa329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742798957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3742798957
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1408708008
Short name T1069
Test name
Test status
Simulation time 20618129532 ps
CPU time 20.57 seconds
Started May 05 01:30:46 PM PDT 24
Finished May 05 01:31:07 PM PDT 24
Peak memory 200372 kb
Host smart-1805ec3c-8b0e-4ae2-af22-9f70feec9e68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408708008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1408708008
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4225985063
Short name T933
Test name
Test status
Simulation time 71816072632 ps
CPU time 133.6 seconds
Started May 05 01:30:47 PM PDT 24
Finished May 05 01:33:01 PM PDT 24
Peak memory 200308 kb
Host smart-2012f349-67ce-431d-9ce6-8e13724451aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225985063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4225985063
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.4226015349
Short name T569
Test name
Test status
Simulation time 1525119383 ps
CPU time 3.24 seconds
Started May 05 01:30:55 PM PDT 24
Finished May 05 01:30:59 PM PDT 24
Peak memory 197896 kb
Host smart-8de59ea8-f105-4386-97e0-455af197b598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226015349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4226015349
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3971061122
Short name T954
Test name
Test status
Simulation time 109608128205 ps
CPU time 265.1 seconds
Started May 05 01:30:46 PM PDT 24
Finished May 05 01:35:11 PM PDT 24
Peak memory 208872 kb
Host smart-f98feefc-2fb1-47e6-93bb-8b147e47a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971061122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3971061122
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.179457371
Short name T990
Test name
Test status
Simulation time 3512081781 ps
CPU time 190.21 seconds
Started May 05 01:30:50 PM PDT 24
Finished May 05 01:34:01 PM PDT 24
Peak memory 200332 kb
Host smart-fcdf63c8-997a-4b16-b72f-2a7b276ca927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179457371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.179457371
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3615907307
Short name T338
Test name
Test status
Simulation time 5073506201 ps
CPU time 54.66 seconds
Started May 05 01:30:44 PM PDT 24
Finished May 05 01:31:38 PM PDT 24
Peak memory 199780 kb
Host smart-c10cec52-848a-4281-9f53-f9e05359598c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615907307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3615907307
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3691476529
Short name T1012
Test name
Test status
Simulation time 126732139382 ps
CPU time 264.46 seconds
Started May 05 01:30:48 PM PDT 24
Finished May 05 01:35:13 PM PDT 24
Peak memory 200392 kb
Host smart-ff04b544-0d2b-4b61-9378-d77a5fbd64aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691476529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3691476529
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3651898392
Short name T467
Test name
Test status
Simulation time 26990079984 ps
CPU time 27.65 seconds
Started May 05 01:30:47 PM PDT 24
Finished May 05 01:31:15 PM PDT 24
Peak memory 196348 kb
Host smart-e2d6334b-3b88-4753-abd1-ddfb3ada5ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651898392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3651898392
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3731767437
Short name T1026
Test name
Test status
Simulation time 620676962 ps
CPU time 0.95 seconds
Started May 05 01:30:43 PM PDT 24
Finished May 05 01:30:44 PM PDT 24
Peak memory 198876 kb
Host smart-da6fa24b-50bd-499b-ad5b-55af8f80793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731767437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3731767437
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2098972479
Short name T42
Test name
Test status
Simulation time 25718407930 ps
CPU time 47.62 seconds
Started May 05 01:30:54 PM PDT 24
Finished May 05 01:31:42 PM PDT 24
Peak memory 200380 kb
Host smart-4f5060d9-3ed9-4982-85c2-654c65b2e519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098972479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2098972479
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.893361395
Short name T753
Test name
Test status
Simulation time 24535563931 ps
CPU time 139.38 seconds
Started May 05 01:30:45 PM PDT 24
Finished May 05 01:33:05 PM PDT 24
Peak memory 216912 kb
Host smart-7a1b335a-25e8-42ec-9eb6-d461bca64003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893361395 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.893361395
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3310383272
Short name T1183
Test name
Test status
Simulation time 1624477354 ps
CPU time 3.08 seconds
Started May 05 01:30:47 PM PDT 24
Finished May 05 01:30:51 PM PDT 24
Peak memory 200124 kb
Host smart-a72ef0ee-3ce1-4d8d-92d0-546b63748b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310383272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3310383272
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3513286656
Short name T746
Test name
Test status
Simulation time 159893507400 ps
CPU time 71.58 seconds
Started May 05 01:30:42 PM PDT 24
Finished May 05 01:31:54 PM PDT 24
Peak memory 200364 kb
Host smart-3373c7cd-e910-4a32-a8da-25c65107aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513286656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3513286656
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2587500121
Short name T632
Test name
Test status
Simulation time 107674441327 ps
CPU time 318.52 seconds
Started May 05 01:36:58 PM PDT 24
Finished May 05 01:42:18 PM PDT 24
Peak memory 216680 kb
Host smart-d7489bb7-06a7-40d8-9b60-c6ac1d30bbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587500121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2587500121
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3148264289
Short name T1007
Test name
Test status
Simulation time 64611026370 ps
CPU time 43 seconds
Started May 05 01:37:00 PM PDT 24
Finished May 05 01:37:44 PM PDT 24
Peak memory 200308 kb
Host smart-75b05f30-b8af-49ca-932d-9812ad9f9625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148264289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3148264289
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2658143605
Short name T932
Test name
Test status
Simulation time 102017515876 ps
CPU time 816.41 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:50:38 PM PDT 24
Peak memory 217048 kb
Host smart-99ef7329-1fee-4b85-9719-000679e2a9b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658143605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2658143605
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.817828984
Short name T704
Test name
Test status
Simulation time 28364307827 ps
CPU time 28.04 seconds
Started May 05 01:37:04 PM PDT 24
Finished May 05 01:37:33 PM PDT 24
Peak memory 200304 kb
Host smart-312065b4-87ed-44e7-9f54-89b060fd76c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817828984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.817828984
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2525813587
Short name T465
Test name
Test status
Simulation time 189216962011 ps
CPU time 534.25 seconds
Started May 05 01:37:03 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 213684 kb
Host smart-d003c735-2324-4524-bab9-e4e07a17b237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525813587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2525813587
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1398439524
Short name T350
Test name
Test status
Simulation time 115979844905 ps
CPU time 69.08 seconds
Started May 05 01:37:02 PM PDT 24
Finished May 05 01:38:11 PM PDT 24
Peak memory 200412 kb
Host smart-4a34b8f1-92e7-4113-981b-9d2368c5a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398439524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1398439524
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2183448233
Short name T806
Test name
Test status
Simulation time 35444939136 ps
CPU time 321.78 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:42:24 PM PDT 24
Peak memory 213816 kb
Host smart-969d0790-81c6-480e-99af-423f5045bdd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183448233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2183448233
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1560452728
Short name T1184
Test name
Test status
Simulation time 93191890288 ps
CPU time 69.26 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:38:10 PM PDT 24
Peak memory 200396 kb
Host smart-df3f92dd-23dd-4a75-8397-72b18587e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560452728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1560452728
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1785049007
Short name T1047
Test name
Test status
Simulation time 193524368650 ps
CPU time 341.02 seconds
Started May 05 01:37:00 PM PDT 24
Finished May 05 01:42:42 PM PDT 24
Peak memory 217084 kb
Host smart-fefb7949-03e6-4c94-b9f3-bee5b02acdb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785049007 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1785049007
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1756427282
Short name T807
Test name
Test status
Simulation time 23131231618 ps
CPU time 43.83 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:37:45 PM PDT 24
Peak memory 200408 kb
Host smart-1fd53ae9-9d86-4f86-b6a2-790a1f26b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756427282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1756427282
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1174568814
Short name T227
Test name
Test status
Simulation time 127906796770 ps
CPU time 339.9 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:42:42 PM PDT 24
Peak memory 209932 kb
Host smart-f8fbe110-18f8-4b05-8557-c15dd8b3dc7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174568814 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1174568814
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.373996090
Short name T718
Test name
Test status
Simulation time 42073512084 ps
CPU time 16.75 seconds
Started May 05 01:37:00 PM PDT 24
Finished May 05 01:37:17 PM PDT 24
Peak memory 200396 kb
Host smart-7b655d1c-2690-4e85-86a8-aedf9c9553c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373996090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.373996090
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.177179965
Short name T63
Test name
Test status
Simulation time 44344161634 ps
CPU time 311.47 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:42:13 PM PDT 24
Peak memory 216156 kb
Host smart-3fc17b74-5dd0-4998-b1e7-bfb77c1f33cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177179965 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.177179965
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1404748252
Short name T204
Test name
Test status
Simulation time 151109706155 ps
CPU time 78.21 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:38:20 PM PDT 24
Peak memory 200340 kb
Host smart-6812916d-9c33-498d-9583-cc35e0235d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404748252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1404748252
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1708274949
Short name T55
Test name
Test status
Simulation time 341496797183 ps
CPU time 201.1 seconds
Started May 05 01:37:01 PM PDT 24
Finished May 05 01:40:23 PM PDT 24
Peak memory 214680 kb
Host smart-158e5511-edaa-427b-903a-696d11ef7c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708274949 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1708274949
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.976989046
Short name T729
Test name
Test status
Simulation time 63320679512 ps
CPU time 19.16 seconds
Started May 05 01:37:05 PM PDT 24
Finished May 05 01:37:24 PM PDT 24
Peak memory 200396 kb
Host smart-07e401bc-680f-45ab-98fe-6b31f1cbc814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976989046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.976989046
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.995517438
Short name T967
Test name
Test status
Simulation time 104698023317 ps
CPU time 306.18 seconds
Started May 05 01:37:04 PM PDT 24
Finished May 05 01:42:11 PM PDT 24
Peak memory 215668 kb
Host smart-c96a08ec-0a39-4f6b-aca5-ddfe52723062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995517438 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.995517438
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3688720572
Short name T1127
Test name
Test status
Simulation time 42531338971 ps
CPU time 419.9 seconds
Started May 05 01:37:05 PM PDT 24
Finished May 05 01:44:05 PM PDT 24
Peak memory 217028 kb
Host smart-b3d4fd7f-7893-4cc9-87ca-5040fabc707b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688720572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3688720572
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4095303878
Short name T408
Test name
Test status
Simulation time 14571691 ps
CPU time 0.53 seconds
Started May 05 01:30:52 PM PDT 24
Finished May 05 01:30:53 PM PDT 24
Peak memory 195732 kb
Host smart-e20bcd24-87dd-4c78-b6c9-7aeaa65e5d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095303878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4095303878
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2657787240
Short name T723
Test name
Test status
Simulation time 162582057104 ps
CPU time 176.08 seconds
Started May 05 01:30:47 PM PDT 24
Finished May 05 01:33:44 PM PDT 24
Peak memory 200404 kb
Host smart-79011441-5336-41cb-ae74-837ed3fcbcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657787240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2657787240
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1773898905
Short name T157
Test name
Test status
Simulation time 67230678644 ps
CPU time 113 seconds
Started May 05 01:30:46 PM PDT 24
Finished May 05 01:32:40 PM PDT 24
Peak memory 200484 kb
Host smart-5bc11f12-5415-44c8-931d-eda2002940b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773898905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1773898905
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3454304777
Short name T815
Test name
Test status
Simulation time 19815799753 ps
CPU time 24.57 seconds
Started May 05 01:30:47 PM PDT 24
Finished May 05 01:31:12 PM PDT 24
Peak memory 200384 kb
Host smart-5291723d-ba98-4a56-9238-a99e910eceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454304777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3454304777
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1920965370
Short name T914
Test name
Test status
Simulation time 259559309258 ps
CPU time 98.47 seconds
Started May 05 01:30:49 PM PDT 24
Finished May 05 01:32:27 PM PDT 24
Peak memory 199480 kb
Host smart-273d9eb9-71c5-45a5-96b9-a6b4d50728ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920965370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1920965370
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.753430255
Short name T892
Test name
Test status
Simulation time 62149308760 ps
CPU time 416.6 seconds
Started May 05 01:30:52 PM PDT 24
Finished May 05 01:37:49 PM PDT 24
Peak memory 200292 kb
Host smart-baab4a2c-3cbe-4e6b-b94d-befa19c5f546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753430255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.753430255
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4187086739
Short name T482
Test name
Test status
Simulation time 11398418219 ps
CPU time 11.92 seconds
Started May 05 01:30:53 PM PDT 24
Finished May 05 01:31:05 PM PDT 24
Peak memory 200036 kb
Host smart-9d78e980-41bd-4b71-801d-4978d9dc8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187086739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4187086739
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.88236462
Short name T373
Test name
Test status
Simulation time 165492363984 ps
CPU time 112.9 seconds
Started May 05 01:30:51 PM PDT 24
Finished May 05 01:32:44 PM PDT 24
Peak memory 200584 kb
Host smart-a60b0b88-9a00-4be1-ad2d-945d7b84958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88236462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.88236462
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3561598062
Short name T468
Test name
Test status
Simulation time 13686945273 ps
CPU time 699.51 seconds
Started May 05 01:30:53 PM PDT 24
Finished May 05 01:42:33 PM PDT 24
Peak memory 200336 kb
Host smart-6f1755ad-b08f-46d4-9de2-83064966c4c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561598062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3561598062
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3717192518
Short name T793
Test name
Test status
Simulation time 4214961932 ps
CPU time 8.08 seconds
Started May 05 01:30:51 PM PDT 24
Finished May 05 01:30:59 PM PDT 24
Peak memory 198508 kb
Host smart-b5299d41-9f45-4e0e-9caa-10178cfe703a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3717192518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3717192518
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1131797184
Short name T149
Test name
Test status
Simulation time 84069613977 ps
CPU time 24.83 seconds
Started May 05 01:30:52 PM PDT 24
Finished May 05 01:31:17 PM PDT 24
Peak memory 200328 kb
Host smart-29e99e38-bab6-4289-9170-2576c308f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131797184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1131797184
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1482580450
Short name T998
Test name
Test status
Simulation time 4696885064 ps
CPU time 4.34 seconds
Started May 05 01:30:53 PM PDT 24
Finished May 05 01:30:58 PM PDT 24
Peak memory 196672 kb
Host smart-4c8ca3ac-64fd-4ecc-a7a5-6eed7afcb27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482580450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1482580450
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1285541353
Short name T611
Test name
Test status
Simulation time 471895815 ps
CPU time 1.41 seconds
Started May 05 01:30:49 PM PDT 24
Finished May 05 01:30:50 PM PDT 24
Peak memory 198664 kb
Host smart-69a664b2-2c3c-4ee4-9ae7-d0b7a8651ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285541353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1285541353
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2519458000
Short name T531
Test name
Test status
Simulation time 201152508179 ps
CPU time 1403.5 seconds
Started May 05 01:30:52 PM PDT 24
Finished May 05 01:54:16 PM PDT 24
Peak memory 200312 kb
Host smart-253b78a6-e08e-4554-9267-aa6ce5b52765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519458000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2519458000
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1866985936
Short name T193
Test name
Test status
Simulation time 132752076168 ps
CPU time 1110.34 seconds
Started May 05 01:30:53 PM PDT 24
Finished May 05 01:49:24 PM PDT 24
Peak memory 225068 kb
Host smart-2c6ca6fd-e80a-4b06-b281-9b92476d47fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866985936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1866985936
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1473135015
Short name T1140
Test name
Test status
Simulation time 1274923224 ps
CPU time 1.49 seconds
Started May 05 01:30:52 PM PDT 24
Finished May 05 01:30:54 PM PDT 24
Peak memory 198996 kb
Host smart-7e4ab0dc-af0a-41e6-b0c6-02876740e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473135015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1473135015
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.315299402
Short name T670
Test name
Test status
Simulation time 97973690308 ps
CPU time 101.53 seconds
Started May 05 01:30:50 PM PDT 24
Finished May 05 01:32:32 PM PDT 24
Peak memory 200324 kb
Host smart-be594061-f18e-4336-99f7-703394227bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315299402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.315299402
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2873884897
Short name T226
Test name
Test status
Simulation time 20139794385 ps
CPU time 18.05 seconds
Started May 05 01:37:05 PM PDT 24
Finished May 05 01:37:24 PM PDT 24
Peak memory 200340 kb
Host smart-7816cf25-5f42-418c-b4f1-2a50d6739c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873884897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2873884897
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1500858139
Short name T27
Test name
Test status
Simulation time 32842292165 ps
CPU time 370.37 seconds
Started May 05 01:37:06 PM PDT 24
Finished May 05 01:43:16 PM PDT 24
Peak memory 217032 kb
Host smart-e8dc0533-1d7d-40ac-8283-d712c0fd3d54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500858139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1500858139
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1792137715
Short name T215
Test name
Test status
Simulation time 19752425346 ps
CPU time 17.18 seconds
Started May 05 01:37:07 PM PDT 24
Finished May 05 01:37:24 PM PDT 24
Peak memory 200348 kb
Host smart-a1b1ac93-dfac-4862-a391-97eecd41ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792137715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1792137715
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2172343201
Short name T861
Test name
Test status
Simulation time 86360789923 ps
CPU time 540.47 seconds
Started May 05 01:37:05 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 225224 kb
Host smart-77f2b509-b81d-4ab6-a2b1-380050edecdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172343201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2172343201
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3703818863
Short name T1128
Test name
Test status
Simulation time 41409635960 ps
CPU time 16.08 seconds
Started May 05 01:37:11 PM PDT 24
Finished May 05 01:37:28 PM PDT 24
Peak memory 199688 kb
Host smart-c9f9be09-320f-4e96-bfc2-6804f9d02a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703818863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3703818863
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3689194729
Short name T738
Test name
Test status
Simulation time 65941987616 ps
CPU time 812.27 seconds
Started May 05 01:37:15 PM PDT 24
Finished May 05 01:50:48 PM PDT 24
Peak memory 215840 kb
Host smart-ed709953-32ea-4260-ad4d-a8d1c3f18c37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689194729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3689194729
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3813433203
Short name T778
Test name
Test status
Simulation time 105331726139 ps
CPU time 47.91 seconds
Started May 05 01:37:12 PM PDT 24
Finished May 05 01:38:00 PM PDT 24
Peak memory 200336 kb
Host smart-126f9d91-15cd-406c-865f-d282f945e19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813433203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3813433203
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1705309093
Short name T530
Test name
Test status
Simulation time 95616367515 ps
CPU time 338.11 seconds
Started May 05 01:37:12 PM PDT 24
Finished May 05 01:42:50 PM PDT 24
Peak memory 216852 kb
Host smart-54b39e6b-a2bc-4258-aab6-7b79597061ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705309093 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1705309093
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2814924962
Short name T986
Test name
Test status
Simulation time 33204395282 ps
CPU time 18.37 seconds
Started May 05 01:37:14 PM PDT 24
Finished May 05 01:37:33 PM PDT 24
Peak memory 200280 kb
Host smart-b30f7500-08f5-4aa5-a1b0-ca4d3290b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814924962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2814924962
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1363267677
Short name T833
Test name
Test status
Simulation time 114047394726 ps
CPU time 922.93 seconds
Started May 05 01:37:15 PM PDT 24
Finished May 05 01:52:39 PM PDT 24
Peak memory 225752 kb
Host smart-b53d99d8-b833-456e-b5aa-596c42731b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363267677 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1363267677
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.158776509
Short name T208
Test name
Test status
Simulation time 157816412293 ps
CPU time 43.94 seconds
Started May 05 01:37:12 PM PDT 24
Finished May 05 01:37:57 PM PDT 24
Peak memory 200604 kb
Host smart-fca2272a-367c-4e04-b4ef-68d8753a92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158776509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.158776509
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1447815443
Short name T1173
Test name
Test status
Simulation time 78695090888 ps
CPU time 423.3 seconds
Started May 05 01:37:11 PM PDT 24
Finished May 05 01:44:15 PM PDT 24
Peak memory 215916 kb
Host smart-8c4413ce-6607-408b-8db5-09d82df7ee4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447815443 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1447815443
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1468724939
Short name T817
Test name
Test status
Simulation time 8069766919 ps
CPU time 4.41 seconds
Started May 05 01:37:15 PM PDT 24
Finished May 05 01:37:20 PM PDT 24
Peak memory 200188 kb
Host smart-bf15a5ab-7b86-4865-b82a-a7512ecab9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468724939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1468724939
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2971537134
Short name T1058
Test name
Test status
Simulation time 234420690368 ps
CPU time 711.58 seconds
Started May 05 01:37:17 PM PDT 24
Finished May 05 01:49:09 PM PDT 24
Peak memory 216876 kb
Host smart-3e8926ca-af4b-4ee6-b8db-12f5913f082c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971537134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2971537134
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1687972547
Short name T1084
Test name
Test status
Simulation time 568788790729 ps
CPU time 2139.6 seconds
Started May 05 01:37:16 PM PDT 24
Finished May 05 02:12:56 PM PDT 24
Peak memory 232944 kb
Host smart-4fc25aea-0d2c-40c5-93c4-4ec7ce4ac752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687972547 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1687972547
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2206067437
Short name T320
Test name
Test status
Simulation time 78202443912 ps
CPU time 134.11 seconds
Started May 05 01:37:21 PM PDT 24
Finished May 05 01:39:35 PM PDT 24
Peak memory 200320 kb
Host smart-91e5aac2-a0a6-4ee8-8790-aa5cd947ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206067437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2206067437
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1184009091
Short name T940
Test name
Test status
Simulation time 51824887836 ps
CPU time 27.49 seconds
Started May 05 01:37:21 PM PDT 24
Finished May 05 01:37:49 PM PDT 24
Peak memory 200404 kb
Host smart-b6d5eb81-185d-4599-9136-ebad7895a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184009091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1184009091
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1849922819
Short name T981
Test name
Test status
Simulation time 36745002564 ps
CPU time 419.03 seconds
Started May 05 01:37:21 PM PDT 24
Finished May 05 01:44:20 PM PDT 24
Peak memory 208632 kb
Host smart-474fb9d8-a330-4c11-b574-953fa974b60d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849922819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1849922819
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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