Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	104715	1			T1	36		T2	14		T3	75
all_values[1]	104715	1			T1	36		T2	14		T3	75
all_values[2]	104715	1			T1	36		T2	14		T3	75
all_values[3]	104715	1			T1	36		T2	14		T3	75
all_values[4]	104715	1			T1	36		T2	14		T3	75
all_values[5]	104715	1			T1	36		T2	14		T3	75
all_values[6]	104715	1			T1	36		T2	14		T3	75
all_values[7]	104715	1			T1	36		T2	14		T3	75

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430740

1

T1

187

T2

61

T3

396

auto[1]

406980

1

T1

101

T2

51

T3

204

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

782235

1

T1

260

T2

97

T3

526

auto[1]

55485

1

T1

28

T2

15

T3

74

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32467	1			T1	18		T5	21		T6	3
all_values[0]	auto[0]	auto[1]	23184	1			T1	18		T2	7		T3	55
all_values[0]	auto[1]	auto[0]	27945	1			T2	3		T3	14		T4	2
all_values[0]	auto[1]	auto[1]	21119	1			T2	4		T3	6		T4	6
all_values[1]	auto[0]	auto[0]	53628	1			T1	36		T2	12		T3	51
all_values[1]	auto[0]	auto[1]	1507	1			T4	4		T11	1		T92	3
all_values[1]	auto[1]	auto[0]	47909	1			T2	2		T3	24		T4	5
all_values[1]	auto[1]	auto[1]	1671	1			T5	22		T6	15		T134	8
all_values[2]	auto[0]	auto[0]	48699	1			T1	26		T2	4		T3	30
all_values[2]	auto[0]	auto[1]	2865	1			T1	10		T2	3		T3	5
all_values[2]	auto[1]	auto[0]	50820	1			T2	6		T3	35		T4	2
all_values[2]	auto[1]	auto[1]	2331	1			T2	1		T3	5		T4	5
all_values[3]	auto[0]	auto[0]	55470	1			T1	28		T2	5		T3	46
all_values[3]	auto[0]	auto[1]	287	1			T12	2		T13	1		T94	1
all_values[3]	auto[1]	auto[0]	48678	1			T1	8		T2	9		T3	29
all_values[3]	auto[1]	auto[1]	280	1			T4	1		T135	1		T16	2
all_values[4]	auto[0]	auto[0]	52496	1			T1	5		T3	53		T6	4
all_values[4]	auto[0]	auto[1]	452	1			T16	4		T20	26		T95	4
all_values[4]	auto[1]	auto[0]	51333	1			T1	31		T2	14		T3	19
all_values[4]	auto[1]	auto[1]	434	1			T3	3		T14	2		T15	13
all_values[5]	auto[0]	auto[0]	54226	1			T1	16		T2	14		T3	42
all_values[5]	auto[0]	auto[1]	149	1			T30	2		T31	2		T32	1
all_values[5]	auto[1]	auto[0]	50166	1			T1	20		T3	33		T4	4
all_values[5]	auto[1]	auto[1]	174	1			T14	1		T30	5		T31	1
all_values[6]	auto[0]	auto[0]	53112	1			T1	17		T2	7		T3	61
all_values[6]	auto[0]	auto[1]	165	1			T29	4		T30	1		T32	1
all_values[6]	auto[1]	auto[0]	51275	1			T1	19		T2	7		T3	14
all_values[6]	auto[1]	auto[1]	163	1			T14	1		T29	3		T30	1
all_values[7]	auto[0]	auto[0]	51681	1			T1	13		T2	9		T3	53
all_values[7]	auto[0]	auto[1]	352	1			T17	2		T16	5		T149	4
all_values[7]	auto[1]	auto[0]	52330	1			T1	23		T2	5		T3	22
all_values[7]	auto[1]	auto[1]	352	1			T15	1		T95	4		T29	2