Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2578

1

T1

4

T2

1

T3

11

auto[UartRx]

2578

1

T1

4

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4583	1			T1	8		T2	2		T3	15
values[1]	47	1			T29	3		T30	1		T33	1
values[2]	55	1			T3	2		T33	1		T276	3
values[3]	47	1			T21	1		T30	1		T276	1
values[4]	55	1			T14	1		T30	1		T35	2
values[5]	52	1			T3	1		T14	1		T31	1
values[6]	66	1			T3	1		T21	1		T29	1
values[7]	63	1			T3	1		T14	3		T29	3
values[8]	50	1			T3	1		T14	1		T29	3
values[9]	50	1			T3	1		T30	1		T33	2
values[10]	59	1			T30	2		T33	2		T276	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2374	1			T1	4		T2	1		T3	9
auto[UartTx]	values[1]	12	1			T29	1		T324	1		T325	1
auto[UartTx]	values[2]	23	1			T33	1		T276	3		T147	1
auto[UartTx]	values[3]	19	1			T21	1		T147	1		T326	1
auto[UartTx]	values[4]	25	1			T30	1		T35	1		T188	3
auto[UartTx]	values[5]	26	1			T14	1		T31	1		T32	1
auto[UartTx]	values[6]	19	1			T33	1		T147	1		T120	1
auto[UartTx]	values[7]	24	1			T3	1		T14	2		T29	1
auto[UartTx]	values[8]	11	1			T29	1		T120	1		T326	1
auto[UartTx]	values[9]	17	1			T3	1		T119	1		T147	1
auto[UartTx]	values[10]	21	1			T30	1		T33	1		T276	1
auto[UartRx]	values[0]	2209	1			T1	4		T2	1		T3	6
auto[UartRx]	values[1]	35	1			T29	2		T30	1		T33	1
auto[UartRx]	values[2]	32	1			T3	2		T147	1		T326	2
auto[UartRx]	values[3]	28	1			T30	1		T276	1		T120	1
auto[UartRx]	values[4]	30	1			T14	1		T35	1		T295	2
auto[UartRx]	values[5]	26	1			T3	1		T147	1		T208	1
auto[UartRx]	values[6]	47	1			T3	1		T21	1		T29	1
auto[UartRx]	values[7]	39	1			T14	1		T29	2		T32	1
auto[UartRx]	values[8]	39	1			T3	1		T14	1		T29	2
auto[UartRx]	values[9]	33	1			T30	1		T33	2		T276	1
auto[UartRx]	values[10]	38	1			T30	1		T33	1		T147	2