Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2353	1			T1	2		T2	1		T3	9
auto[BaudRate115200]	1953	1			T2	3		T3	11		T5	2
auto[BaudRate230400]	2091	1			T3	2		T4	3		T6	1
auto[BaudRate128Kbps]	2039	1			T1	4		T2	1		T3	4
auto[BaudRate256Kbps]	2290	1			T1	2		T2	2		T3	5
auto[BaudRate1Mbps]	1852	1			T1	1		T2	3		T3	5
auto[BaudRate1p5Mbps]	1309	1			T1	2		T3	1		T5	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1340	1			T6	8		T12	10		T280	3
freqs[25]	1236	1			T3	37		T42	6		T16	2
freqs[48]	662	1			T40	7		T17	6		T159	51
freqs[50]	742	1			T18	2		T43	5		T197	9
freqs[100]	1341	1			T13	6		T37	6		T304	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	294	1			T6	1		T12	1		T280	1
auto[BaudRate9600]	freqs[25]	235	1			T3	9		T152	1		T287	2
auto[BaudRate9600]	freqs[48]	105	1			T17	1		T159	4		T306	1
auto[BaudRate9600]	freqs[50]	100	1			T197	1		T46	9		T303	1
auto[BaudRate9600]	freqs[100]	231	1			T13	1		T327	14		T171	1
auto[BaudRate115200]	freqs[24]	148	1			T6	1		T12	3		T41	2
auto[BaudRate115200]	freqs[25]	173	1			T3	11		T42	1		T31	3
auto[BaudRate115200]	freqs[48]	81	1			T40	1		T17	2		T159	9
auto[BaudRate115200]	freqs[50]	84	1			T197	2		T46	6		T122	6
auto[BaudRate115200]	freqs[100]	184	1			T13	1		T304	1		T302	1
auto[BaudRate230400]	freqs[24]	198	1			T6	1		T12	4		T280	1
auto[BaudRate230400]	freqs[25]	190	1			T3	2		T16	1		T152	2
auto[BaudRate230400]	freqs[48]	96	1			T17	1		T159	9		T328	1
auto[BaudRate230400]	freqs[50]	95	1			T18	1		T46	6		T303	3
auto[BaudRate230400]	freqs[100]	189	1			T13	1		T20	2		T302	1
auto[BaudRate128Kbps]	freqs[24]	152	1			T6	2		T12	1		T41	1
auto[BaudRate128Kbps]	freqs[25]	180	1			T3	4		T42	2		T16	1
auto[BaudRate128Kbps]	freqs[48]	86	1			T40	1		T159	4		T306	1
auto[BaudRate128Kbps]	freqs[50]	90	1			T197	1		T46	9		T303	2
auto[BaudRate128Kbps]	freqs[100]	174	1			T20	2		T32	3		T269	3
auto[BaudRate256Kbps]	freqs[24]	219	1			T6	3		T12	1		T280	1
auto[BaudRate256Kbps]	freqs[25]	197	1			T3	5		T42	1		T152	2
auto[BaudRate256Kbps]	freqs[48]	93	1			T17	1		T159	7		T328	1
auto[BaudRate256Kbps]	freqs[50]	111	1			T43	3		T329	1		T303	2
auto[BaudRate256Kbps]	freqs[100]	166	1			T32	1		T171	2		T269	2
auto[BaudRate1Mbps]	freqs[24]	224	1			T263	1		T129	4		T195	2
auto[BaudRate1Mbps]	freqs[25]	180	1			T3	5		T42	2		T152	1
auto[BaudRate1Mbps]	freqs[48]	115	1			T40	1		T159	8		T328	1
auto[BaudRate1Mbps]	freqs[50]	123	1			T18	1		T43	2		T197	2
auto[BaudRate1Mbps]	freqs[100]	202	1			T13	1		T37	1		T304	1
auto[BaudRate1p5Mbps]	freqs[25]	81	1			T3	1		T152	1		T31	3
auto[BaudRate1p5Mbps]	freqs[48]	86	1			T40	4		T17	1		T159	10
auto[BaudRate1p5Mbps]	freqs[50]	139	1			T197	3		T46	12		T329	1
auto[BaudRate1p5Mbps]	freqs[100]	195	1			T13	2		T37	5		T32	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded