Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	14	116	89.23

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	14	116	89.23	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30995082	1			T1	84070		T2	75		T3	319
all_levels[1]	199414	1			T1	691		T3	23		T4	2
all_levels[2]	2274	1			T2	2		T5	1		T6	8
all_levels[3]	1046	1			T5	3		T6	5		T8	1
all_levels[4]	707	1			T3	1		T5	3		T6	4
all_levels[5]	531	1			T3	1		T5	5		T6	3
all_levels[6]	370	1			T5	5		T6	4		T12	1
all_levels[7]	307	1			T6	1		T8	2		T10	1
all_levels[8]	235	1			T3	1		T6	1		T11	1
all_levels[9]	226	1			T2	3		T11	1		T92	1
all_levels[10]	216	1			T5	1		T6	1		T11	1
all_levels[11]	176	1			T2	2		T92	2		T141	1
all_levels[12]	175	1			T4	2		T12	3		T92	2
all_levels[13]	151	1			T8	1		T92	1		T93	1
all_levels[14]	143	1			T2	1		T5	1		T94	1
all_levels[15]	116	1			T3	1		T10	1		T94	1
all_levels[16]	101	1			T142	2		T143	1		T33	1
all_levels[17]	103	1			T94	2		T14	1		T144	1
all_levels[18]	85	1			T8	1		T93	1		T136	1
all_levels[19]	77	1			T94	2		T142	1		T42	1
all_levels[20]	79	1			T94	1		T14	1		T145	1
all_levels[21]	69	1			T93	1		T141	1		T94	2
all_levels[22]	54	1			T3	1		T146	1		T34	1
all_levels[23]	65	1			T2	1		T136	1		T142	1
all_levels[24]	49	1			T33	2		T147	1		T148	1
all_levels[25]	50	1			T42	1		T29	1		T145	1
all_levels[26]	57	1			T2	1		T145	1		T35	1
all_levels[27]	55	1			T141	1		T136	1		T33	1
all_levels[28]	37	1			T4	1		T17	1		T49	1
all_levels[29]	48	1			T149	1		T150	1		T151	2
all_levels[30]	28	1			T41	1		T144	1		T34	1
all_levels[31]	43	1			T152	4		T145	1		T153	1
all_levels[32]	32	1			T136	1		T149	1		T29	1
all_levels[33]	25	1			T146	1		T34	1		T151	1
all_levels[34]	23	1			T141	1		T148	1		T154	1
all_levels[35]	31	1			T136	1		T155	2		T156	1
all_levels[36]	25	1			T29	1		T157	1		T158	1
all_levels[37]	26	1			T159	1		T144	1		T32	1
all_levels[38]	27	1			T34	1		T158	1		T110	1
all_levels[39]	18	1			T129	3		T160	1		T161	1
all_levels[40]	18	1			T49	2		T156	1		T162	1
all_levels[41]	21	1			T150	2		T161	1		T163	1
all_levels[42]	16	1			T164	3		T165	2		T110	1
all_levels[43]	20	1			T160	1		T49	1		T166	1
all_levels[44]	20	1			T29	1		T49	2		T35	1
all_levels[45]	13	1			T14	1		T145	1		T167	1
all_levels[46]	16	1			T157	1		T168	1		T169	1
all_levels[47]	10	1			T159	1		T168	1		T170	1
all_levels[48]	12	1			T171	1		T154	2		T172	1
all_levels[49]	9	1			T173	1		T168	1		T174	1
all_levels[50]	14	1			T41	1		T120	1		T175	1
all_levels[51]	7	1			T4	1		T176	1		T154	1
all_levels[52]	6	1			T17	1		T177	1		T178	1
all_levels[53]	11	1			T160	1		T176	1		T179	1
all_levels[54]	11	1			T176	1		T180	1		T181	1
all_levels[55]	11	1			T176	1		T182	1		T183	2
all_levels[56]	7	1			T151	3		T184	1		T185	1
all_levels[57]	11	1			T34	1		T35	1		T186	1
all_levels[58]	7	1			T29	1		T179	3		T187	1
all_levels[59]	4	1			T93	1		T188	1		T189	1
all_levels[60]	7	1			T176	1		T190	1		T189	2
all_levels[61]	9	1			T34	1		T186	1		T191	1
all_levels[62]	4	1			T192	1		T193	1		T194	1
all_levels[63]	4	1			T195	1		T176	1		T196	1
all_levels[64]	119	1			T4	1		T94	1		T135	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31198548

1

T1

84761

T2

77

T3

339

auto[1]

4215

1

T2

8

T3

8

T4

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	14	116	89.23	14

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[49] , all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53]]	[auto[1]]	--	--	5
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30991255	1			T1	84070		T2	69		T3	311
all_levels[0]	auto[1]	3827	1			T2	6		T3	8		T4	3
all_levels[1]	auto[0]	199344	1			T1	691		T3	23		T4	1
all_levels[1]	auto[1]	70	1			T4	1		T135	1		T129	1
all_levels[2]	auto[0]	2250	1			T2	2		T5	1		T6	8
all_levels[2]	auto[1]	24	1			T141	1		T197	2		T167	2
all_levels[3]	auto[0]	1015	1			T5	3		T6	4		T8	1
all_levels[3]	auto[1]	31	1			T6	1		T141	1		T135	1
all_levels[4]	auto[0]	693	1			T3	1		T5	3		T6	4
all_levels[4]	auto[1]	14	1			T198	1		T199	1		T200	1
all_levels[5]	auto[0]	521	1			T3	1		T5	4		T6	3
all_levels[5]	auto[1]	10	1			T5	1		T201	1		T199	1
all_levels[6]	auto[0]	360	1			T5	5		T6	4		T12	1
all_levels[6]	auto[1]	10	1			T202	2		T203	1		T204	1
all_levels[7]	auto[0]	290	1			T6	1		T8	1		T10	1
all_levels[7]	auto[1]	17	1			T8	1		T205	1		T52	1
all_levels[8]	auto[0]	226	1			T3	1		T6	1		T11	1
all_levels[8]	auto[1]	9	1			T148	1		T206	1		T207	1
all_levels[9]	auto[0]	215	1			T2	1		T11	1		T92	1
all_levels[9]	auto[1]	11	1			T2	2		T208	2		T202	2
all_levels[10]	auto[0]	212	1			T5	1		T6	1		T11	1
all_levels[10]	auto[1]	4	1			T208	1		T57	1		T209	1
all_levels[11]	auto[0]	162	1			T2	2		T92	2		T141	1
all_levels[11]	auto[1]	14	1			T136	1		T210	2		T211	2
all_levels[12]	auto[0]	161	1			T4	2		T12	1		T92	2
all_levels[12]	auto[1]	14	1			T12	2		T42	2		T49	1
all_levels[13]	auto[0]	143	1			T8	1		T92	1		T93	1
all_levels[13]	auto[1]	8	1			T94	1		T148	3		T212	1
all_levels[14]	auto[0]	134	1			T2	1		T5	1		T94	1
all_levels[14]	auto[1]	9	1			T213	1		T154	1		T207	1
all_levels[15]	auto[0]	110	1			T3	1		T10	1		T94	1
all_levels[15]	auto[1]	6	1			T146	1		T214	3		T198	1
all_levels[16]	auto[0]	90	1			T142	2		T143	1		T33	1
all_levels[16]	auto[1]	11	1			T215	2		T165	1		T199	1
all_levels[17]	auto[0]	95	1			T94	2		T14	1		T144	1
all_levels[17]	auto[1]	8	1			T206	1		T216	1		T190	1
all_levels[18]	auto[0]	84	1			T8	1		T93	1		T136	1
all_levels[18]	auto[1]	1	1			T217	1		-	-		-	-
all_levels[19]	auto[0]	72	1			T94	2		T142	1		T42	1
all_levels[19]	auto[1]	5	1			T218	2		T165	1		T219	1
all_levels[20]	auto[0]	72	1			T94	1		T14	1		T145	1
all_levels[20]	auto[1]	7	1			T220	1		T221	2		T222	1
all_levels[21]	auto[0]	63	1			T93	1		T141	1		T94	1
all_levels[21]	auto[1]	6	1			T94	1		T223	2		T224	1
all_levels[22]	auto[0]	51	1			T3	1		T146	1		T34	1
all_levels[22]	auto[1]	3	1			T215	1		T225	1		T226	1
all_levels[23]	auto[0]	62	1			T2	1		T136	1		T142	1
all_levels[23]	auto[1]	3	1			T221	1		T57	1		T227	1
all_levels[24]	auto[0]	44	1			T33	2		T147	1		T148	1
all_levels[24]	auto[1]	5	1			T228	2		T57	1		T229	1
all_levels[25]	auto[0]	44	1			T42	1		T29	1		T145	1
all_levels[25]	auto[1]	6	1			T230	1		T231	3		T232	2
all_levels[26]	auto[0]	54	1			T2	1		T145	1		T35	1
all_levels[26]	auto[1]	3	1			T233	1		T234	1		T235	1
all_levels[27]	auto[0]	54	1			T141	1		T136	1		T33	1
all_levels[27]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[28]	auto[0]	36	1			T4	1		T17	1		T49	1
all_levels[28]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[29]	auto[0]	42	1			T149	1		T150	1		T151	1
all_levels[29]	auto[1]	6	1			T151	1		T110	1		T237	1
all_levels[30]	auto[0]	26	1			T41	1		T144	1		T34	1
all_levels[30]	auto[1]	2	1			T238	2		-	-		-	-
all_levels[31]	auto[0]	32	1			T152	1		T145	1		T153	1
all_levels[31]	auto[1]	11	1			T152	3		T239	2		T240	2
all_levels[32]	auto[0]	28	1			T136	1		T149	1		T29	1
all_levels[32]	auto[1]	4	1			T178	1		T241	1		T227	1
all_levels[33]	auto[0]	24	1			T146	1		T34	1		T151	1
all_levels[33]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[34]	auto[0]	23	1			T141	1		T148	1		T154	1
all_levels[35]	auto[0]	25	1			T136	1		T155	1		T156	1
all_levels[35]	auto[1]	6	1			T155	1		T243	3		T244	1
all_levels[36]	auto[0]	22	1			T29	1		T157	1		T158	1
all_levels[36]	auto[1]	3	1			T245	2		T246	1		-	-
all_levels[37]	auto[0]	24	1			T159	1		T144	1		T32	1
all_levels[37]	auto[1]	2	1			T247	1		T248	1		-	-
all_levels[38]	auto[0]	24	1			T34	1		T158	1		T110	1
all_levels[38]	auto[1]	3	1			T249	1		T250	2		-	-
all_levels[39]	auto[0]	16	1			T129	2		T160	1		T161	1
all_levels[39]	auto[1]	2	1			T129	1		T174	1		-	-
all_levels[40]	auto[0]	16	1			T49	1		T156	1		T162	1
all_levels[40]	auto[1]	2	1			T49	1		T251	1		-	-
all_levels[41]	auto[0]	21	1			T150	2		T161	1		T163	1
all_levels[42]	auto[0]	12	1			T164	2		T165	1		T110	1
all_levels[42]	auto[1]	4	1			T164	1		T165	1		T252	2
all_levels[43]	auto[0]	20	1			T160	1		T49	1		T166	1
all_levels[44]	auto[0]	18	1			T29	1		T49	1		T35	1
all_levels[44]	auto[1]	2	1			T49	1		T253	1		-	-
all_levels[45]	auto[0]	13	1			T14	1		T145	1		T167	1
all_levels[46]	auto[0]	13	1			T157	1		T168	1		T169	1
all_levels[46]	auto[1]	3	1			T254	3		-	-		-	-
all_levels[47]	auto[0]	10	1			T159	1		T168	1		T170	1
all_levels[48]	auto[0]	11	1			T171	1		T154	1		T172	1
all_levels[48]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[49]	auto[0]	9	1			T173	1		T168	1		T174	1
all_levels[50]	auto[0]	14	1			T41	1		T120	1		T175	1
all_levels[51]	auto[0]	7	1			T4	1		T176	1		T154	1
all_levels[52]	auto[0]	6	1			T17	1		T177	1		T178	1
all_levels[53]	auto[0]	11	1			T160	1		T176	1		T179	1
all_levels[54]	auto[0]	10	1			T176	1		T180	1		T181	1
all_levels[54]	auto[1]	1	1			T255	1		-	-		-	-
all_levels[55]	auto[0]	10	1			T176	1		T182	1		T183	2
all_levels[55]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[56]	auto[0]	5	1			T151	1		T184	1		T185	1
all_levels[56]	auto[1]	2	1			T151	2		-	-		-	-
all_levels[57]	auto[0]	9	1			T34	1		T35	1		T186	1
all_levels[57]	auto[1]	2	1			T240	1		T257	1		-	-
all_levels[58]	auto[0]	5	1			T29	1		T179	1		T187	1
all_levels[58]	auto[1]	2	1			T179	2		-	-		-	-
all_levels[59]	auto[0]	4	1			T93	1		T188	1		T189	1
all_levels[60]	auto[0]	6	1			T176	1		T190	1		T189	1
all_levels[60]	auto[1]	1	1			T189	1		-	-		-	-
all_levels[61]	auto[0]	9	1			T34	1		T186	1		T191	1
all_levels[62]	auto[0]	4	1			T192	1		T193	1		T194	1
all_levels[63]	auto[0]	4	1			T195	1		T176	1		T196	1
all_levels[64]	auto[0]	103	1			T4	1		T94	1		T135	1
all_levels[64]	auto[1]	16	1			T35	1		T205	1		T258	2