Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	104715	1			T1	36		T2	14		T3	75
all_pins[1]	104715	1			T1	36		T2	14		T3	75
all_pins[2]	104715	1			T1	36		T2	14		T3	75
all_pins[3]	104715	1			T1	36		T2	14		T3	75
all_pins[4]	104715	1			T1	36		T2	14		T3	75
all_pins[5]	104715	1			T1	36		T2	14		T3	75
all_pins[6]	104715	1			T1	36		T2	14		T3	75
all_pins[7]	104715	1			T1	36		T2	14		T3	75

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	810370	1			T1	288		T2	107		T3	586
values[0x1]	27350	1			T2	5		T3	14		T4	14
transitions[0x0=>0x1]	26249	1			T2	5		T3	14		T4	13
transitions[0x1=>0x0]	25829	1			T2	4		T3	14		T4	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	83519	1			T1	36		T2	10		T3	69
all_pins[0]	values[0x1]	21196	1			T2	4		T3	6		T4	6
all_pins[0]	transitions[0x0=>0x1]	20614	1			T2	4		T3	6		T4	6
all_pins[0]	transitions[0x1=>0x0]	1087	1			T5	22		T6	15		T134	8
all_pins[1]	values[0x0]	103046	1			T1	36		T2	14		T3	75
all_pins[1]	values[0x1]	1669	1			T5	22		T6	15		T134	8
all_pins[1]	transitions[0x0=>0x1]	1571	1			T5	22		T6	15		T134	8
all_pins[1]	transitions[0x1=>0x0]	2272	1			T2	1		T3	5		T4	5
all_pins[2]	values[0x0]	102345	1			T1	36		T2	13		T3	70
all_pins[2]	values[0x1]	2370	1			T2	1		T3	5		T4	5
all_pins[2]	transitions[0x0=>0x1]	2306	1			T2	1		T3	5		T4	4
all_pins[2]	transitions[0x1=>0x0]	216	1			T16	2		T20	1		T95	2
all_pins[3]	values[0x0]	104435	1			T1	36		T2	14		T3	75
all_pins[3]	values[0x1]	280	1			T4	1		T135	1		T16	2
all_pins[3]	transitions[0x0=>0x1]	240	1			T4	1		T135	1		T16	2
all_pins[3]	transitions[0x1=>0x0]	394	1			T3	3		T14	2		T15	13
all_pins[4]	values[0x0]	104281	1			T1	36		T2	14		T3	72
all_pins[4]	values[0x1]	434	1			T3	3		T14	2		T15	13
all_pins[4]	transitions[0x0=>0x1]	368	1			T3	3		T14	1		T15	10
all_pins[4]	transitions[0x1=>0x0]	143	1			T95	1		T30	3		T32	2
all_pins[5]	values[0x0]	104506	1			T1	36		T2	14		T3	75
all_pins[5]	values[0x1]	209	1			T14	1		T15	3		T95	1
all_pins[5]	transitions[0x0=>0x1]	165	1			T15	3		T95	1		T30	5
all_pins[5]	transitions[0x1=>0x0]	796	1			T4	2		T92	3		T94	3
all_pins[6]	values[0x0]	103875	1			T1	36		T2	14		T3	75
all_pins[6]	values[0x1]	840	1			T4	2		T92	3		T94	3
all_pins[6]	transitions[0x0=>0x1]	793	1			T4	2		T92	3		T94	3
all_pins[6]	transitions[0x1=>0x0]	305	1			T15	1		T95	4		T29	2
all_pins[7]	values[0x0]	104363	1			T1	36		T2	14		T3	75
all_pins[7]	values[0x1]	352	1			T15	1		T95	4		T29	2
all_pins[7]	transitions[0x0=>0x1]	192	1			T15	1		T29	2		T30	3
all_pins[7]	transitions[0x1=>0x0]	20616	1			T2	3		T3	6		T4	5