Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7568400	1			T1	7633		T2	68		T3	172
all_levels[1]	898721	1			T1	88		T3	24		T5	3
all_levels[2]	288328	1			T1	88		T3	11		T6	1
all_levels[3]	213786	1			T1	84		T3	23		T4	1
all_levels[4]	355371	1			T1	83		T3	17		T6	1
all_levels[5]	452409	1			T1	77		T3	31		T11	40
all_levels[6]	187066	1			T1	68		T3	4		T6	2
all_levels[7]	244143	1			T1	86		T3	10		T11	38
all_levels[8]	247253	1			T1	67		T3	5		T10	4
all_levels[9]	209676	1			T1	94		T3	2		T6	2
all_levels[10]	318745	1			T1	94		T3	19		T11	61
all_levels[11]	516752	1			T1	75		T3	8		T8	1
all_levels[12]	191092	1			T1	86		T6	2		T10	3
all_levels[13]	263930	1			T1	87		T4	3		T10	1
all_levels[14]	303250	1			T1	94		T2	3		T5	1
all_levels[15]	333933	1			T1	93		T2	12		T92	2
all_levels[16]	262126	1			T1	79		T5	25		T6	52
all_levels[17]	241415	1			T1	65		T10	5		T92	9
all_levels[18]	400774	1			T1	81		T6	5		T92	3
all_levels[19]	340847	1			T1	72		T11	7		T36	17
all_levels[20]	177647	1			T1	67		T11	3		T36	16
all_levels[21]	403670	1			T1	75		T92	1		T36	20
all_levels[22]	268275	1			T1	93		T36	17		T261	1303
all_levels[23]	311410	1			T1	82		T11	22		T36	18
all_levels[24]	170588	1			T1	72		T11	27		T36	19
all_levels[25]	241398	1			T1	78		T36	18		T261	1321
all_levels[26]	480391	1			T1	83		T3	8		T8	1
all_levels[27]	259395	1			T1	84		T3	1		T36	18
all_levels[28]	319001	1			T1	82		T4	2		T11	8
all_levels[29]	201605	1			T1	73		T11	16		T36	18
all_levels[30]	236551	1			T1	88		T11	19		T12	1
all_levels[31]	644815	1			T1	982		T5	2		T11	25
all_levels[32]	13649607	1			T1	73708		T2	3		T3	12

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31198548

1

T1

84761

T2

77

T3

339

auto[1]

3822

1

T2

9

T3

8

T4

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7566437	1			T1	7633		T2	63		T3	164
all_levels[0]	auto[1]	1963	1			T2	5		T3	8		T4	2
all_levels[1]	auto[0]	898442	1			T1	88		T3	24		T5	2
all_levels[1]	auto[1]	279	1			T5	1		T6	2		T8	2
all_levels[2]	auto[0]	288285	1			T1	88		T3	11		T6	1
all_levels[2]	auto[1]	43	1			T205	1		T236	1		T297	1
all_levels[3]	auto[0]	213553	1			T1	84		T3	23		T4	1
all_levels[3]	auto[1]	233	1			T141	1		T15	22		T270	3
all_levels[4]	auto[0]	355343	1			T1	83		T3	17		T6	1
all_levels[4]	auto[1]	28	1			T289	1		T276	1		T161	1
all_levels[5]	auto[0]	452390	1			T1	77		T3	31		T11	40
all_levels[5]	auto[1]	19	1			T130	1		T272	1		T198	1
all_levels[6]	auto[0]	187042	1			T1	68		T3	4		T6	2
all_levels[6]	auto[1]	24	1			T8	1		T12	1		T203	1
all_levels[7]	auto[0]	243982	1			T1	86		T3	10		T11	38
all_levels[7]	auto[1]	161	1			T16	11		T20	20		T145	2
all_levels[8]	auto[0]	247232	1			T1	67		T3	5		T10	4
all_levels[8]	auto[1]	21	1			T282	2		T158	2		T74	1
all_levels[9]	auto[0]	209657	1			T1	94		T3	2		T6	2
all_levels[9]	auto[1]	19	1			T12	3		T135	2		T156	2
all_levels[10]	auto[0]	318724	1			T1	94		T3	19		T11	61
all_levels[10]	auto[1]	21	1			T92	1		T265	1		T236	2
all_levels[11]	auto[0]	516735	1			T1	75		T3	8		T8	1
all_levels[11]	auto[1]	17	1			T164	2		T296	1		T330	1
all_levels[12]	auto[0]	191065	1			T1	86		T6	2		T10	2
all_levels[12]	auto[1]	27	1			T10	1		T167	1		T155	2
all_levels[13]	auto[0]	263909	1			T1	87		T4	2		T10	1
all_levels[13]	auto[1]	21	1			T4	1		T47	1		T164	1
all_levels[14]	auto[0]	303216	1			T1	94		T2	2		T5	1
all_levels[14]	auto[1]	34	1			T2	1		T35	1		T223	2
all_levels[15]	auto[0]	333859	1			T1	93		T2	10		T92	2
all_levels[15]	auto[1]	74	1			T2	2		T29	2		T30	1
all_levels[16]	auto[0]	262103	1			T1	79		T5	24		T6	51
all_levels[16]	auto[1]	23	1			T5	1		T6	1		T135	1
all_levels[17]	auto[0]	241395	1			T1	65		T10	5		T92	9
all_levels[17]	auto[1]	20	1			T323	4		T331	2		T332	1
all_levels[18]	auto[0]	400750	1			T1	81		T6	5		T92	3
all_levels[18]	auto[1]	24	1			T195	2		T210	1		T156	1
all_levels[19]	auto[0]	340832	1			T1	72		T11	7		T36	17
all_levels[19]	auto[1]	15	1			T279	1		T148	2		T207	1
all_levels[20]	auto[0]	177627	1			T1	67		T11	3		T36	16
all_levels[20]	auto[1]	20	1			T49	1		T230	1		T220	1
all_levels[21]	auto[0]	403647	1			T1	75		T92	1		T36	20
all_levels[21]	auto[1]	23	1			T215	2		T208	1		T180	1
all_levels[22]	auto[0]	268245	1			T1	93		T36	17		T261	1303
all_levels[22]	auto[1]	30	1			T315	1		T165	3		T333	1
all_levels[23]	auto[0]	311388	1			T1	82		T11	21		T36	18
all_levels[23]	auto[1]	22	1			T11	1		T230	1		T216	1
all_levels[24]	auto[0]	170571	1			T1	72		T11	27		T36	19
all_levels[24]	auto[1]	17	1			T13	1		T159	2		T173	1
all_levels[25]	auto[0]	241378	1			T1	78		T36	18		T261	1321
all_levels[25]	auto[1]	20	1			T141	1		T159	3		T288	1
all_levels[26]	auto[0]	480372	1			T1	83		T3	8		T8	1
all_levels[26]	auto[1]	19	1			T94	1		T129	1		T146	2
all_levels[27]	auto[0]	259379	1			T1	84		T3	1		T36	18
all_levels[27]	auto[1]	16	1			T159	1		T328	1		T205	1
all_levels[28]	auto[0]	318982	1			T1	82		T4	2		T11	8
all_levels[28]	auto[1]	19	1			T94	1		T210	1		T334	1
all_levels[29]	auto[0]	201597	1			T1	73		T11	16		T36	18
all_levels[29]	auto[1]	8	1			T259	1		T335	1		T224	2
all_levels[30]	auto[0]	236534	1			T1	88		T11	19		T12	1
all_levels[30]	auto[1]	17	1			T49	1		T336	1		T337	1
all_levels[31]	auto[0]	644794	1			T1	982		T5	1		T11	25
all_levels[31]	auto[1]	21	1			T5	1		T12	1		T215	1
all_levels[32]	auto[0]	13649083	1			T1	73708		T2	2		T3	12
all_levels[32]	auto[1]	524	1			T2	1		T4	3		T5	3