Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	730	1			T14	4		T29	11		T30	21
all_values[1]	730	1			T14	4		T29	11		T30	21
all_values[2]	730	1			T14	4		T29	11		T30	21
all_values[3]	730	1			T14	4		T29	11		T30	21
all_values[4]	730	1			T14	4		T29	11		T30	21
all_values[5]	730	1			T14	4		T29	11		T30	21
all_values[6]	730	1			T14	4		T29	11		T30	21
all_values[7]	730	1			T14	4		T29	11		T30	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3127

1

T14

14

T29

46

T30

71

auto[1]

2713

1

T14

18

T29

42

T30

97

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2153

1

T14

14

T29

41

T30

63

auto[1]

3687

1

T14

18

T29

47

T30

105

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3439

1

T14

19

T29

60

T30

96

auto[1]

2401

1

T14

13

T29

28

T30

72

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	247	1			T14	1		T29	6		T30	3
all_values[0]	auto[0]	auto[1]	auto[1]	182	1			T14	2		T29	1		T30	11
all_values[0]	auto[1]	auto[0]	auto[1]	170	1			T29	3		T30	2		T32	3
all_values[0]	auto[1]	auto[1]	auto[1]	131	1			T14	1		T29	1		T30	5
all_values[1]	auto[0]	auto[0]	auto[0]	219	1			T14	2		T29	1		T30	4
all_values[1]	auto[0]	auto[1]	auto[0]	201	1			T14	1		T29	6		T30	6
all_values[1]	auto[1]	auto[0]	auto[1]	162	1			T14	1		T30	6		T32	1
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T29	4		T30	5		T31	4
all_values[2]	auto[0]	auto[0]	auto[0]	152	1			T29	1		T30	4		T31	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T29	1		T30	1		T31	2
all_values[2]	auto[0]	auto[1]	auto[0]	134	1			T29	3		T30	7		T32	1
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T14	1		T29	3		T30	2
all_values[2]	auto[1]	auto[0]	auto[1]	168	1			T14	2		T29	2		T30	6
all_values[2]	auto[1]	auto[1]	auto[1]	128	1			T14	1		T29	1		T30	1
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T14	2		T29	4		T30	4
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T30	2		T32	1		T35	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T14	1		T29	2		T30	5
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T29	3		T32	2		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T14	1		T29	1		T30	9
all_values[3]	auto[1]	auto[1]	auto[1]	134	1			T29	1		T30	1		T31	2
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T29	2		T30	2		T31	1
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T29	2		T30	1		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	109	1			T14	1		T29	4		T30	4
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T30	6		T31	2		T120	2
all_values[4]	auto[1]	auto[0]	auto[1]	167	1			T29	2		T30	3		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	139	1			T14	3		T29	1		T30	5
all_values[5]	auto[0]	auto[0]	auto[0]	175	1			T14	1		T29	10		T30	2
all_values[5]	auto[0]	auto[0]	auto[1]	59	1			T30	1		T31	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[0]	129	1			T14	1		T30	6		T31	2
all_values[5]	auto[0]	auto[1]	auto[1]	79	1			T30	1		T31	1		T32	1
all_values[5]	auto[1]	auto[0]	auto[1]	164	1			T29	1		T30	4		T32	1
all_values[5]	auto[1]	auto[1]	auto[1]	124	1			T14	2		T30	7		T31	3
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T14	1		T29	1		T30	7
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T29	1		T32	1		T132	1
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T29	3		T30	11		T31	3
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T14	1		T29	1		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	154	1			T14	1		T29	3		T32	2
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T14	1		T29	2		T30	3
all_values[7]	auto[0]	auto[0]	auto[0]	161	1			T14	2		T29	2		T31	2
all_values[7]	auto[0]	auto[0]	auto[1]	59	1			T30	1		T32	2		T166	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T14	2		T29	2		T30	1
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T29	1		T30	4		T32	3
all_values[7]	auto[1]	auto[0]	auto[1]	152	1			T29	3		T30	9		T31	1
all_values[7]	auto[1]	auto[1]	auto[1]	135	1			T29	3		T30	6		T31	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal