Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.27 97.95 100.00 98.80 100.00 99.50


Total test records in report: 1315
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T68 /workspace/coverage/cover_reg_top/6.uart_csr_rw.766161608 May 07 12:44:19 PM PDT 24 May 07 12:44:22 PM PDT 24 17907331 ps
T1257 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3791959215 May 07 12:44:32 PM PDT 24 May 07 12:44:35 PM PDT 24 160207503 ps
T1258 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1614933809 May 07 12:44:16 PM PDT 24 May 07 12:44:20 PM PDT 24 21051866 ps
T1259 /workspace/coverage/cover_reg_top/27.uart_intr_test.1878926218 May 07 12:44:13 PM PDT 24 May 07 12:44:20 PM PDT 24 37354224 ps
T1260 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2207714374 May 07 12:44:30 PM PDT 24 May 07 12:44:33 PM PDT 24 43043994 ps
T1261 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1223484069 May 07 12:44:31 PM PDT 24 May 07 12:44:33 PM PDT 24 22247655 ps
T1262 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3028945595 May 07 12:44:17 PM PDT 24 May 07 12:44:20 PM PDT 24 16240665 ps
T105 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3529325165 May 07 12:44:19 PM PDT 24 May 07 12:44:22 PM PDT 24 244078694 ps
T1263 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.794281650 May 07 12:44:15 PM PDT 24 May 07 12:44:19 PM PDT 24 123837106 ps
T1264 /workspace/coverage/cover_reg_top/18.uart_intr_test.3804709156 May 07 12:44:39 PM PDT 24 May 07 12:44:41 PM PDT 24 16696900 ps
T1265 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2699998326 May 07 12:44:27 PM PDT 24 May 07 12:44:30 PM PDT 24 379910683 ps
T69 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1718121888 May 07 12:44:28 PM PDT 24 May 07 12:44:30 PM PDT 24 34784828 ps
T1266 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3265512223 May 07 12:44:32 PM PDT 24 May 07 12:44:36 PM PDT 24 121641399 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1316002465 May 07 12:44:34 PM PDT 24 May 07 12:44:37 PM PDT 24 50850338 ps
T1268 /workspace/coverage/cover_reg_top/14.uart_intr_test.1945345707 May 07 12:44:18 PM PDT 24 May 07 12:44:20 PM PDT 24 41619070 ps
T1269 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1831457036 May 07 12:44:21 PM PDT 24 May 07 12:44:24 PM PDT 24 306260688 ps
T1270 /workspace/coverage/cover_reg_top/4.uart_csr_rw.792124605 May 07 12:44:27 PM PDT 24 May 07 12:44:30 PM PDT 24 14876924 ps
T1271 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.518961987 May 07 12:44:31 PM PDT 24 May 07 12:44:34 PM PDT 24 57772224 ps
T1272 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1982378669 May 07 12:44:34 PM PDT 24 May 07 12:44:39 PM PDT 24 46730599 ps
T1273 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4051763607 May 07 12:44:10 PM PDT 24 May 07 12:44:13 PM PDT 24 27172278 ps
T1274 /workspace/coverage/cover_reg_top/43.uart_intr_test.583721091 May 07 12:44:41 PM PDT 24 May 07 12:44:43 PM PDT 24 44186119 ps
T1275 /workspace/coverage/cover_reg_top/31.uart_intr_test.563326834 May 07 12:44:49 PM PDT 24 May 07 12:44:50 PM PDT 24 49473292 ps
T1276 /workspace/coverage/cover_reg_top/37.uart_intr_test.2686547069 May 07 12:44:36 PM PDT 24 May 07 12:44:39 PM PDT 24 38939898 ps
T1277 /workspace/coverage/cover_reg_top/42.uart_intr_test.1535055343 May 07 12:44:35 PM PDT 24 May 07 12:44:38 PM PDT 24 17302779 ps
T1278 /workspace/coverage/cover_reg_top/29.uart_intr_test.2000636846 May 07 12:44:33 PM PDT 24 May 07 12:44:36 PM PDT 24 22559439 ps
T1279 /workspace/coverage/cover_reg_top/41.uart_intr_test.3929020787 May 07 12:44:40 PM PDT 24 May 07 12:44:42 PM PDT 24 14943080 ps
T1280 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3271929679 May 07 12:44:34 PM PDT 24 May 07 12:44:38 PM PDT 24 52097863 ps
T1281 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2335831699 May 07 12:44:34 PM PDT 24 May 07 12:44:39 PM PDT 24 46999511 ps
T1282 /workspace/coverage/cover_reg_top/4.uart_intr_test.800009695 May 07 12:44:13 PM PDT 24 May 07 12:44:16 PM PDT 24 12082020 ps
T1283 /workspace/coverage/cover_reg_top/8.uart_intr_test.2223124799 May 07 12:44:15 PM PDT 24 May 07 12:44:18 PM PDT 24 15157593 ps
T1284 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2878724852 May 07 12:44:28 PM PDT 24 May 07 12:44:30 PM PDT 24 17973611 ps
T1285 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1328684498 May 07 12:44:43 PM PDT 24 May 07 12:44:46 PM PDT 24 142201543 ps
T1286 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.651484425 May 07 12:44:33 PM PDT 24 May 07 12:44:37 PM PDT 24 49371567 ps
T70 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3539274186 May 07 12:44:26 PM PDT 24 May 07 12:44:30 PM PDT 24 136043806 ps
T1287 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3287507978 May 07 12:44:30 PM PDT 24 May 07 12:44:33 PM PDT 24 29948626 ps
T1288 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1498957735 May 07 12:44:16 PM PDT 24 May 07 12:44:19 PM PDT 24 20570992 ps
T1289 /workspace/coverage/cover_reg_top/45.uart_intr_test.211378854 May 07 12:44:34 PM PDT 24 May 07 12:44:37 PM PDT 24 15687097 ps
T1290 /workspace/coverage/cover_reg_top/34.uart_intr_test.2961655917 May 07 12:44:15 PM PDT 24 May 07 12:44:27 PM PDT 24 40313743 ps
T1291 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1208949017 May 07 12:44:31 PM PDT 24 May 07 12:44:40 PM PDT 24 708274354 ps
T1292 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2869485683 May 07 12:44:33 PM PDT 24 May 07 12:44:36 PM PDT 24 166845794 ps
T1293 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2811309831 May 07 12:44:18 PM PDT 24 May 07 12:44:22 PM PDT 24 92016646 ps
T1294 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2188739987 May 07 12:44:21 PM PDT 24 May 07 12:44:24 PM PDT 24 14041852 ps
T1295 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1785484446 May 07 12:44:10 PM PDT 24 May 07 12:44:12 PM PDT 24 17250040 ps
T1296 /workspace/coverage/cover_reg_top/17.uart_intr_test.981835718 May 07 12:44:23 PM PDT 24 May 07 12:44:26 PM PDT 24 14588112 ps
T1297 /workspace/coverage/cover_reg_top/21.uart_intr_test.3663214288 May 07 12:44:29 PM PDT 24 May 07 12:44:32 PM PDT 24 46090849 ps
T1298 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1478675809 May 07 12:44:37 PM PDT 24 May 07 12:44:40 PM PDT 24 30937399 ps
T1299 /workspace/coverage/cover_reg_top/10.uart_intr_test.1636769409 May 07 12:44:29 PM PDT 24 May 07 12:44:32 PM PDT 24 17090830 ps
T1300 /workspace/coverage/cover_reg_top/1.uart_intr_test.4182097592 May 07 12:44:30 PM PDT 24 May 07 12:44:33 PM PDT 24 17523949 ps
T1301 /workspace/coverage/cover_reg_top/19.uart_csr_rw.386764094 May 07 12:44:28 PM PDT 24 May 07 12:44:31 PM PDT 24 23753730 ps
T1302 /workspace/coverage/cover_reg_top/39.uart_intr_test.1147212744 May 07 12:44:43 PM PDT 24 May 07 12:44:45 PM PDT 24 13256280 ps
T1303 /workspace/coverage/cover_reg_top/4.uart_tl_errors.4115358022 May 07 12:44:17 PM PDT 24 May 07 12:44:21 PM PDT 24 37524909 ps
T1304 /workspace/coverage/cover_reg_top/5.uart_intr_test.4171444595 May 07 12:44:22 PM PDT 24 May 07 12:44:24 PM PDT 24 133441548 ps
T1305 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4168204995 May 07 12:44:20 PM PDT 24 May 07 12:44:23 PM PDT 24 16220421 ps
T1306 /workspace/coverage/cover_reg_top/2.uart_intr_test.2838332335 May 07 12:44:26 PM PDT 24 May 07 12:44:28 PM PDT 24 15734663 ps
T1307 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1991063862 May 07 12:44:15 PM PDT 24 May 07 12:44:19 PM PDT 24 552352831 ps
T1308 /workspace/coverage/cover_reg_top/20.uart_intr_test.3121439039 May 07 12:44:34 PM PDT 24 May 07 12:44:37 PM PDT 24 56239268 ps
T1309 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3955022547 May 07 12:44:26 PM PDT 24 May 07 12:44:29 PM PDT 24 18506812 ps
T1310 /workspace/coverage/cover_reg_top/15.uart_intr_test.3094984964 May 07 12:44:29 PM PDT 24 May 07 12:44:32 PM PDT 24 35787835 ps
T1311 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.301873734 May 07 12:44:30 PM PDT 24 May 07 12:44:33 PM PDT 24 13570352 ps
T106 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.906559791 May 07 12:44:16 PM PDT 24 May 07 12:44:20 PM PDT 24 95117261 ps
T1312 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1144897725 May 07 12:44:27 PM PDT 24 May 07 12:44:31 PM PDT 24 37250469 ps
T1313 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3835252754 May 07 12:44:11 PM PDT 24 May 07 12:44:16 PM PDT 24 49951146 ps
T1314 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.161708963 May 07 12:44:18 PM PDT 24 May 07 12:44:21 PM PDT 24 93900891 ps
T140 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.767191470 May 07 12:44:18 PM PDT 24 May 07 12:44:22 PM PDT 24 240648322 ps
T1315 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4096529225 May 07 12:44:20 PM PDT 24 May 07 12:44:23 PM PDT 24 32940840 ps

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1204818549
Short name T3
Test name
Test status
Simulation time 197317708033 ps
CPU time 581.94 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:14:12 PM PDT 24
Peak memory 217044 kb
Host smart-88279a36-e9b5-40b9-ba55-d7ad3468dd84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204818549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1204818549
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.4117373644
Short name T159
Test name
Test status
Simulation time 228560012085 ps
CPU time 585.92 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:11:20 PM PDT 24
Peak memory 208864 kb
Host smart-492ed6d9-1141-4ac6-8ac3-ba8c51517ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117373644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4117373644
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.407118635
Short name T29
Test name
Test status
Simulation time 117538154451 ps
CPU time 617.06 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:10:51 PM PDT 24
Peak memory 225344 kb
Host smart-0e6af0a5-ad5b-41ef-bc8d-725a0a38c7c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407118635 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.407118635
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all.1832466121
Short name T1
Test name
Test status
Simulation time 119934130450 ps
CPU time 310.53 seconds
Started May 07 01:00:25 PM PDT 24
Finished May 07 01:05:37 PM PDT 24
Peak memory 200376 kb
Host smart-8e08d9af-a722-479f-b9e7-9dd9298aadda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832466121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1832466121
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3363858256
Short name T33
Test name
Test status
Simulation time 278471937978 ps
CPU time 851.96 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:18:42 PM PDT 24
Peak memory 216936 kb
Host smart-3c08e94f-11e9-47aa-ac43-33cdbf505beb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363858256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3363858256
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2892934546
Short name T276
Test name
Test status
Simulation time 458411301574 ps
CPU time 521.64 seconds
Started May 07 01:04:20 PM PDT 24
Finished May 07 01:13:03 PM PDT 24
Peak memory 225316 kb
Host smart-33d4c639-2f15-4bbb-ac71-cc303d731595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892934546 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2892934546
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3968704930
Short name T120
Test name
Test status
Simulation time 248740051082 ps
CPU time 837.08 seconds
Started May 07 01:03:45 PM PDT 24
Finished May 07 01:17:43 PM PDT 24
Peak memory 215660 kb
Host smart-f23747b7-40df-4748-b321-a961e00c6f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968704930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3968704930
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2233101812
Short name T147
Test name
Test status
Simulation time 126240811248 ps
CPU time 1758.62 seconds
Started May 07 01:04:19 PM PDT 24
Finished May 07 01:33:39 PM PDT 24
Peak memory 225100 kb
Host smart-6c3d8508-731d-4611-a210-073665cd50f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233101812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2233101812
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1152850733
Short name T26
Test name
Test status
Simulation time 540066011 ps
CPU time 0.77 seconds
Started May 07 01:00:12 PM PDT 24
Finished May 07 01:00:14 PM PDT 24
Peak memory 218440 kb
Host smart-119f9ed2-4730-4599-9cd3-e6b28aa7a999
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152850733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1152850733
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/25.uart_stress_all.794343322
Short name T166
Test name
Test status
Simulation time 429637348798 ps
CPU time 1124.32 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:20:32 PM PDT 24
Peak memory 208660 kb
Host smart-3d1b06d8-0692-47ad-a7d8-99bfac71b15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794343322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.794343322
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2702369106
Short name T35
Test name
Test status
Simulation time 505653306017 ps
CPU time 465.06 seconds
Started May 07 01:01:14 PM PDT 24
Finished May 07 01:09:00 PM PDT 24
Peak memory 213784 kb
Host smart-b68f3beb-32be-4ada-91e9-42983558ad53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702369106 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2702369106
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3111755217
Short name T49
Test name
Test status
Simulation time 67539962307 ps
CPU time 98.4 seconds
Started May 07 01:05:05 PM PDT 24
Finished May 07 01:06:44 PM PDT 24
Peak memory 200428 kb
Host smart-a69b6349-c6c2-4148-9a9f-1b23deccc23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111755217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3111755217
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3129261556
Short name T188
Test name
Test status
Simulation time 563473266059 ps
CPU time 645.65 seconds
Started May 07 01:04:13 PM PDT 24
Finished May 07 01:15:00 PM PDT 24
Peak memory 217116 kb
Host smart-74206562-9cb4-4464-9c35-c9826575b93b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129261556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3129261556
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.4001358185
Short name T94
Test name
Test status
Simulation time 32830919603 ps
CPU time 35.14 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:46 PM PDT 24
Peak memory 200352 kb
Host smart-cedbc907-18c5-4112-bfb0-919f8a960fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001358185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.4001358185
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2313247233
Short name T205
Test name
Test status
Simulation time 86479317677 ps
CPU time 69.3 seconds
Started May 07 01:05:47 PM PDT 24
Finished May 07 01:06:57 PM PDT 24
Peak memory 200476 kb
Host smart-04185292-fd73-497c-a0a5-6c3b2a5a6f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313247233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2313247233
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.3012833950
Short name T154
Test name
Test status
Simulation time 563332263704 ps
CPU time 446.94 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:07:54 PM PDT 24
Peak memory 200432 kb
Host smart-01d37579-993d-4959-a6f2-bc74cbad7f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012833950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3012833950
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1576157255
Short name T103
Test name
Test status
Simulation time 296290693 ps
CPU time 1.31 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 199548 kb
Host smart-248d8dc4-09d1-4bf1-8bb9-399228de8e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576157255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1576157255
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.854859238
Short name T12
Test name
Test status
Simulation time 186235018301 ps
CPU time 80.58 seconds
Started May 07 01:05:15 PM PDT 24
Finished May 07 01:06:36 PM PDT 24
Peak memory 200448 kb
Host smart-fbc3ce47-4d2f-42f6-9a7c-202ad8d31b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854859238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.854859238
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.351626263
Short name T410
Test name
Test status
Simulation time 37292865 ps
CPU time 0.57 seconds
Started May 07 01:01:00 PM PDT 24
Finished May 07 01:01:02 PM PDT 24
Peak memory 195820 kb
Host smart-319c6ddf-bb76-4425-ad57-ceff6fc7a94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351626263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.351626263
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.795998467
Short name T64
Test name
Test status
Simulation time 29401095 ps
CPU time 0.64 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 196012 kb
Host smart-4c325391-6883-4647-9e41-512f851ba821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795998467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.795998467
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.468070133
Short name T21
Test name
Test status
Simulation time 59127524806 ps
CPU time 559.52 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:13:57 PM PDT 24
Peak memory 216856 kb
Host smart-b18a2351-3b21-4362-b3b3-e89a524c7fb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468070133 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.468070133
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.2871779102
Short name T132
Test name
Test status
Simulation time 200890628030 ps
CPU time 67.03 seconds
Started May 07 01:00:00 PM PDT 24
Finished May 07 01:01:08 PM PDT 24
Peak memory 200448 kb
Host smart-b748d372-8360-4983-b83e-d83f1ba31933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871779102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2871779102
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all.4159802310
Short name T163
Test name
Test status
Simulation time 227225684275 ps
CPU time 138.24 seconds
Started May 07 01:03:05 PM PDT 24
Finished May 07 01:05:25 PM PDT 24
Peak memory 200196 kb
Host smart-c47b02d3-7b27-4ed6-8de7-6689bda0bc56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159802310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4159802310
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3063691714
Short name T272
Test name
Test status
Simulation time 182176057106 ps
CPU time 339.28 seconds
Started May 07 01:05:19 PM PDT 24
Finished May 07 01:11:00 PM PDT 24
Peak memory 200440 kb
Host smart-ecb1c055-d957-4a34-8f20-f47a30e65b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063691714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3063691714
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1563226807
Short name T86
Test name
Test status
Simulation time 19396838 ps
CPU time 0.63 seconds
Started May 07 12:44:22 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 194944 kb
Host smart-6a3a282e-2c36-4e6c-a797-0b37a92855a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563226807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1563226807
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3148240343
Short name T189
Test name
Test status
Simulation time 59474077887 ps
CPU time 53.88 seconds
Started May 07 01:05:15 PM PDT 24
Finished May 07 01:06:10 PM PDT 24
Peak memory 200356 kb
Host smart-3f87c0cc-4e01-43e4-a6e3-61f50844d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148240343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3148240343
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_full.14874209
Short name T41
Test name
Test status
Simulation time 290344233670 ps
CPU time 204.3 seconds
Started May 07 01:01:31 PM PDT 24
Finished May 07 01:04:56 PM PDT 24
Peak memory 200392 kb
Host smart-8b91d27b-f17f-4f23-a335-e29267bc6ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14874209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.14874209
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2350237286
Short name T6
Test name
Test status
Simulation time 111691029836 ps
CPU time 49.95 seconds
Started May 07 01:04:19 PM PDT 24
Finished May 07 01:05:10 PM PDT 24
Peak memory 200428 kb
Host smart-003d39e7-0cca-4b16-9dfb-38fc1ccfac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350237286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2350237286
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4051351445
Short name T100
Test name
Test status
Simulation time 68402272 ps
CPU time 0.93 seconds
Started May 07 12:44:28 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 199224 kb
Host smart-2c67ca02-d0c3-49b3-8bd0-8205208ba58c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051351445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4051351445
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3923794935
Short name T43
Test name
Test status
Simulation time 105068991930 ps
CPU time 531.43 seconds
Started May 07 01:04:14 PM PDT 24
Finished May 07 01:13:07 PM PDT 24
Peak memory 200424 kb
Host smart-ecde2f37-8ac1-46d6-96cb-3fa183c7e9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923794935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3923794935
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_fifo_full.557449045
Short name T267
Test name
Test status
Simulation time 27706408133 ps
CPU time 48.74 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:01:01 PM PDT 24
Peak memory 200444 kb
Host smart-45305e51-c5fe-44fe-bfd7-765bccb108b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557449045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.557449045
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3513508949
Short name T176
Test name
Test status
Simulation time 50110195977 ps
CPU time 91.81 seconds
Started May 07 01:00:35 PM PDT 24
Finished May 07 01:02:09 PM PDT 24
Peak memory 200448 kb
Host smart-5128b2c3-a682-4e01-becd-8cf371f1fc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513508949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3513508949
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3927031996
Short name T93
Test name
Test status
Simulation time 80742541848 ps
CPU time 36.23 seconds
Started May 07 01:02:39 PM PDT 24
Finished May 07 01:03:16 PM PDT 24
Peak memory 200460 kb
Host smart-61d338cb-83fb-4992-9315-0f77b2665161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927031996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3927031996
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2163506356
Short name T184
Test name
Test status
Simulation time 50562221260 ps
CPU time 36.85 seconds
Started May 07 01:00:23 PM PDT 24
Finished May 07 01:01:01 PM PDT 24
Peak memory 200328 kb
Host smart-a6e06429-9a9d-4a0f-b77d-bd5da177bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163506356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2163506356
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.560297161
Short name T110
Test name
Test status
Simulation time 61150016520 ps
CPU time 132.21 seconds
Started May 07 01:05:14 PM PDT 24
Finished May 07 01:07:27 PM PDT 24
Peak memory 200364 kb
Host smart-47f543ed-4bcd-4454-b18d-f752a6484bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560297161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.560297161
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.343065155
Short name T216
Test name
Test status
Simulation time 125392433360 ps
CPU time 144.19 seconds
Started May 07 01:06:05 PM PDT 24
Finished May 07 01:08:31 PM PDT 24
Peak memory 200444 kb
Host smart-1735d2cb-161d-48b4-8ac1-65ea0d5b9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343065155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.343065155
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.227514705
Short name T135
Test name
Test status
Simulation time 56079549029 ps
CPU time 27.66 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:03:24 PM PDT 24
Peak memory 200368 kb
Host smart-0bfcefe3-b259-477b-bd64-8b65f13e370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227514705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.227514705
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1121905618
Short name T200
Test name
Test status
Simulation time 108832001300 ps
CPU time 284.55 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:05:05 PM PDT 24
Peak memory 200524 kb
Host smart-89438fa2-b433-4408-9615-3d58b4493245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121905618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1121905618
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_loopback.384257786
Short name T582
Test name
Test status
Simulation time 5631353033 ps
CPU time 6.31 seconds
Started May 07 01:02:19 PM PDT 24
Finished May 07 01:02:26 PM PDT 24
Peak memory 199760 kb
Host smart-78ba0b09-423a-4a58-a041-678f8a8b75bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384257786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.384257786
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.637080496
Short name T326
Test name
Test status
Simulation time 67053254534 ps
CPU time 2291.15 seconds
Started May 07 01:04:21 PM PDT 24
Finished May 07 01:42:34 PM PDT 24
Peak memory 230236 kb
Host smart-6777f848-c878-4488-9ac5-323d788736eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637080496 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.637080496
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2065501602
Short name T57
Test name
Test status
Simulation time 839438945251 ps
CPU time 745.64 seconds
Started May 07 01:00:07 PM PDT 24
Finished May 07 01:12:34 PM PDT 24
Peak memory 225468 kb
Host smart-7f8ca61d-1357-47c7-87ab-a1c46559c924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065501602 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2065501602
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3296922216
Short name T215
Test name
Test status
Simulation time 97330763746 ps
CPU time 235.68 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:04:34 PM PDT 24
Peak memory 200432 kb
Host smart-fb4fdec8-f566-413a-9736-0372ccf2ebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296922216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3296922216
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.4281188550
Short name T202
Test name
Test status
Simulation time 134758375205 ps
CPU time 31.89 seconds
Started May 07 01:05:38 PM PDT 24
Finished May 07 01:06:11 PM PDT 24
Peak memory 200456 kb
Host smart-72a58f3d-c41b-4bd7-af66-83edc85e63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281188550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.4281188550
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2963308126
Short name T194
Test name
Test status
Simulation time 102004018044 ps
CPU time 181.46 seconds
Started May 07 01:06:07 PM PDT 24
Finished May 07 01:09:09 PM PDT 24
Peak memory 200284 kb
Host smart-063e37cd-afa1-4d8f-a774-00c98361c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963308126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2963308126
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3274593248
Short name T221
Test name
Test status
Simulation time 154578835445 ps
CPU time 44.42 seconds
Started May 07 01:06:11 PM PDT 24
Finished May 07 01:06:57 PM PDT 24
Peak memory 200444 kb
Host smart-573ce2a4-11a1-4601-85d5-27ca1ce2e3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274593248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3274593248
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3798936920
Short name T157
Test name
Test status
Simulation time 78891732522 ps
CPU time 33.61 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:45 PM PDT 24
Peak memory 200388 kb
Host smart-f05314d7-5462-44dd-9094-3269d31094df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798936920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3798936920
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.45182420
Short name T174
Test name
Test status
Simulation time 34601258082 ps
CPU time 61.19 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:03:43 PM PDT 24
Peak memory 200432 kb
Host smart-1c48ff43-8c95-4d9d-860e-9ad5e7540b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45182420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.45182420
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.496419033
Short name T926
Test name
Test status
Simulation time 47268816963 ps
CPU time 74.58 seconds
Started May 07 01:05:07 PM PDT 24
Finished May 07 01:06:23 PM PDT 24
Peak memory 200392 kb
Host smart-4d0d28b1-ca50-49fc-9a44-3b2b961c4c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496419033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.496419033
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2007850265
Short name T372
Test name
Test status
Simulation time 153464812511 ps
CPU time 118.68 seconds
Started May 07 01:05:06 PM PDT 24
Finished May 07 01:07:06 PM PDT 24
Peak memory 200372 kb
Host smart-a2306b91-3d40-4066-a228-da2c642213ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007850265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2007850265
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1755324202
Short name T179
Test name
Test status
Simulation time 179092919286 ps
CPU time 235.47 seconds
Started May 07 01:05:41 PM PDT 24
Finished May 07 01:09:37 PM PDT 24
Peak memory 200464 kb
Host smart-73845f6e-3bf2-4058-bebe-3bbf73eca979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755324202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1755324202
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2523298214
Short name T165
Test name
Test status
Simulation time 59718748274 ps
CPU time 23.17 seconds
Started May 07 01:04:10 PM PDT 24
Finished May 07 01:04:34 PM PDT 24
Peak memory 200444 kb
Host smart-56ada96e-a292-4b7c-95aa-852cb6c8d31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523298214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2523298214
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2025990971
Short name T104
Test name
Test status
Simulation time 1268299121 ps
CPU time 1.27 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 199768 kb
Host smart-d2712184-5916-4c00-b52c-354c76db2814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025990971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2025990971
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3388011722
Short name T262
Test name
Test status
Simulation time 225564133867 ps
CPU time 133.08 seconds
Started May 07 01:00:01 PM PDT 24
Finished May 07 01:02:15 PM PDT 24
Peak memory 200368 kb
Host smart-8bc2f4cd-a98d-4fe2-ad21-aa4cd72c5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388011722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3388011722
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3988432061
Short name T292
Test name
Test status
Simulation time 88586095610 ps
CPU time 147.19 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:02:27 PM PDT 24
Peak memory 200376 kb
Host smart-5ebe3771-86a9-4152-a564-4e4ff21f5c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988432061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3988432061
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_stress_all.2065640999
Short name T509
Test name
Test status
Simulation time 688146923099 ps
CPU time 112.06 seconds
Started May 07 01:00:31 PM PDT 24
Finished May 07 01:02:24 PM PDT 24
Peak memory 208752 kb
Host smart-26ef151f-655b-4a86-b456-29ade7ec552c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065640999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2065640999
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1739961426
Short name T255
Test name
Test status
Simulation time 275167945194 ps
CPU time 246.45 seconds
Started May 07 01:04:52 PM PDT 24
Finished May 07 01:08:59 PM PDT 24
Peak memory 200344 kb
Host smart-f6e4c608-7800-4f0f-8907-3119cd6909e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739961426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1739961426
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.675018538
Short name T235
Test name
Test status
Simulation time 42455111016 ps
CPU time 44.08 seconds
Started May 07 01:04:52 PM PDT 24
Finished May 07 01:05:37 PM PDT 24
Peak memory 200468 kb
Host smart-e8522d17-f0d6-4ba9-9f58-4227daf21d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675018538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.675018538
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2969860411
Short name T245
Test name
Test status
Simulation time 142705573023 ps
CPU time 55.85 seconds
Started May 07 01:04:50 PM PDT 24
Finished May 07 01:05:46 PM PDT 24
Peak memory 200380 kb
Host smart-9d50a75e-52fd-46a7-b72b-9817905b4c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969860411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2969860411
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2421060506
Short name T231
Test name
Test status
Simulation time 23291880441 ps
CPU time 41.95 seconds
Started May 07 01:04:51 PM PDT 24
Finished May 07 01:05:34 PM PDT 24
Peak memory 200440 kb
Host smart-df817ebd-5862-49a1-8d5d-96dbdc8bef4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421060506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2421060506
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2955674397
Short name T955
Test name
Test status
Simulation time 18247524830 ps
CPU time 29.88 seconds
Started May 07 01:04:59 PM PDT 24
Finished May 07 01:05:30 PM PDT 24
Peak memory 200452 kb
Host smart-95e4747d-afef-4dc2-a718-ccd4a1bf4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955674397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2955674397
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.281409861
Short name T240
Test name
Test status
Simulation time 7913235834 ps
CPU time 14.02 seconds
Started May 07 01:00:59 PM PDT 24
Finished May 07 01:01:15 PM PDT 24
Peak memory 200424 kb
Host smart-3b36ac73-a265-4741-972a-0f1bacbd1f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281409861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.281409861
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2208176523
Short name T244
Test name
Test status
Simulation time 100141615804 ps
CPU time 40.29 seconds
Started May 07 01:05:14 PM PDT 24
Finished May 07 01:05:55 PM PDT 24
Peak memory 200372 kb
Host smart-a28a676b-9c39-4a8c-a0fb-670fff24aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208176523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2208176523
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.4210874066
Short name T249
Test name
Test status
Simulation time 55440382065 ps
CPU time 32.35 seconds
Started May 07 01:05:23 PM PDT 24
Finished May 07 01:05:57 PM PDT 24
Peak memory 200428 kb
Host smart-11ec5f64-1c92-4263-b90a-72bfc78f6925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210874066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4210874066
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.4148462423
Short name T238
Test name
Test status
Simulation time 31549948018 ps
CPU time 27.02 seconds
Started May 07 01:05:30 PM PDT 24
Finished May 07 01:05:59 PM PDT 24
Peak memory 200440 kb
Host smart-3fdd4ef2-0280-4513-92c2-d2c947b8c273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148462423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.4148462423
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3376756998
Short name T236
Test name
Test status
Simulation time 52050357858 ps
CPU time 125.25 seconds
Started May 07 01:05:29 PM PDT 24
Finished May 07 01:07:35 PM PDT 24
Peak memory 200464 kb
Host smart-5ae2d325-90cc-49b3-8418-634952256bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376756998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3376756998
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2272170917
Short name T256
Test name
Test status
Simulation time 23758290648 ps
CPU time 19.85 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:05:52 PM PDT 24
Peak memory 200444 kb
Host smart-f7423fe6-94bb-4b30-be19-a910063cc6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272170917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2272170917
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.559109502
Short name T178
Test name
Test status
Simulation time 34283602454 ps
CPU time 62.09 seconds
Started May 07 01:06:06 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 200440 kb
Host smart-9d05f2b3-37f5-43a3-b893-e9a19d1d1ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559109502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.559109502
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2141707666
Short name T217
Test name
Test status
Simulation time 104638444557 ps
CPU time 152.9 seconds
Started May 07 01:06:05 PM PDT 24
Finished May 07 01:08:39 PM PDT 24
Peak memory 200380 kb
Host smart-45a47625-466d-4d7c-9058-413ee79081df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141707666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2141707666
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2268808080
Short name T151
Test name
Test status
Simulation time 75135428871 ps
CPU time 20.51 seconds
Started May 07 01:04:11 PM PDT 24
Finished May 07 01:04:33 PM PDT 24
Peak memory 200404 kb
Host smart-91761a8f-b1a1-4e97-921a-d0ab51a7ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268808080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2268808080
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4073689018
Short name T248
Test name
Test status
Simulation time 106932764050 ps
CPU time 44.13 seconds
Started May 07 01:04:20 PM PDT 24
Finished May 07 01:05:06 PM PDT 24
Peak memory 200388 kb
Host smart-f627e1e2-8a95-4b3f-a488-25dd46914a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073689018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4073689018
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3331679998
Short name T242
Test name
Test status
Simulation time 87615111677 ps
CPU time 38.34 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:05:14 PM PDT 24
Peak memory 200196 kb
Host smart-70b832b5-9a01-4fb4-a13d-0ed7ca0bc115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331679998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3331679998
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1509602971
Short name T254
Test name
Test status
Simulation time 137821814873 ps
CPU time 87.12 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:06:05 PM PDT 24
Peak memory 200432 kb
Host smart-ca8e4bd0-4013-45cf-b7e1-6d8d57fe2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509602971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1509602971
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1958703182
Short name T67
Test name
Test status
Simulation time 31980189 ps
CPU time 0.81 seconds
Started May 07 12:44:23 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 196608 kb
Host smart-38915f75-e97d-47b7-bbcd-4608011b08f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958703182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1958703182
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.821692246
Short name T1202
Test name
Test status
Simulation time 164431806 ps
CPU time 1.34 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 198200 kb
Host smart-0a6d70c3-3103-4dc8-b283-849d303c21da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821692246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.821692246
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.247879341
Short name T1250
Test name
Test status
Simulation time 37240136 ps
CPU time 0.56 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 195696 kb
Host smart-d300eebb-85ae-45b4-b260-b57e88850728
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247879341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.247879341
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1498957735
Short name T1288
Test name
Test status
Simulation time 20570992 ps
CPU time 0.64 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 197584 kb
Host smart-087d7b00-5314-42dc-a9ea-46451b6428e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498957735 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1498957735
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3340156985
Short name T1188
Test name
Test status
Simulation time 17777283 ps
CPU time 0.61 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 195696 kb
Host smart-e8858481-c4e4-4173-b2ba-ecd6792565f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340156985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3340156985
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2591430512
Short name T1254
Test name
Test status
Simulation time 35953452 ps
CPU time 0.55 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 194684 kb
Host smart-1b048473-6d9c-4c0c-a621-d88114eaf08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591430512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2591430512
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1614933809
Short name T1258
Test name
Test status
Simulation time 21051866 ps
CPU time 0.67 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 195856 kb
Host smart-9530ca9b-bc5d-4228-b18d-cf7520b8e82b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614933809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1614933809
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2979571026
Short name T1255
Test name
Test status
Simulation time 104911388 ps
CPU time 1.18 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 200284 kb
Host smart-c8909fce-de50-4f7a-bdd1-a223fe547c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979571026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2979571026
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.906559791
Short name T106
Test name
Test status
Simulation time 95117261 ps
CPU time 0.96 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 199144 kb
Host smart-52f31d78-2552-48d1-a71c-005d19cab10a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906559791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.906559791
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3856954690
Short name T81
Test name
Test status
Simulation time 56641877 ps
CPU time 0.66 seconds
Started May 07 12:44:24 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 195292 kb
Host smart-7e223336-df7a-4ef8-85d9-d91eb483889c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856954690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3856954690
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3539274186
Short name T70
Test name
Test status
Simulation time 136043806 ps
CPU time 1.64 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 197884 kb
Host smart-ae713fb4-787a-4767-834e-34242555cdfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539274186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3539274186
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3839446239
Short name T1194
Test name
Test status
Simulation time 15362005 ps
CPU time 0.61 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 195696 kb
Host smart-c49dc98f-2f68-4565-9b31-11b00f60f14a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839446239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3839446239
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.161708963
Short name T1314
Test name
Test status
Simulation time 93900891 ps
CPU time 1.31 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 200388 kb
Host smart-bc5d49eb-5215-4b9c-832a-9a88997f5bea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161708963 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.161708963
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2188739987
Short name T1294
Test name
Test status
Simulation time 14041852 ps
CPU time 0.63 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 195812 kb
Host smart-b3509056-61a0-4a87-aeff-f9d57d96266e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188739987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2188739987
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4182097592
Short name T1300
Test name
Test status
Simulation time 17523949 ps
CPU time 0.58 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 194560 kb
Host smart-99209813-9955-4ab1-910f-ad48de854805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182097592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4182097592
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3835252754
Short name T1313
Test name
Test status
Simulation time 49951146 ps
CPU time 2.45 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 200324 kb
Host smart-8312b2e1-363b-4593-ab37-437ee6430b20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835252754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3835252754
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3407169292
Short name T1195
Test name
Test status
Simulation time 108100208 ps
CPU time 0.85 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:39 PM PDT 24
Peak memory 200212 kb
Host smart-e1546061-01c3-4bfa-9b7d-1fd95e3f6555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407169292 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3407169292
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3955022547
Short name T1309
Test name
Test status
Simulation time 18506812 ps
CPU time 0.6 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:29 PM PDT 24
Peak memory 195700 kb
Host smart-445fcc60-8bc1-4f88-bda5-2fa56b2d93e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955022547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3955022547
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1636769409
Short name T1299
Test name
Test status
Simulation time 17090830 ps
CPU time 0.56 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 194708 kb
Host smart-65ef88d2-0a6f-4bd7-94af-fcfa5427d89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636769409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1636769409
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.651484425
Short name T1286
Test name
Test status
Simulation time 49371567 ps
CPU time 0.75 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 197384 kb
Host smart-c533a4ee-f277-4cb3-b24e-89c078db9582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651484425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.651484425
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1982378669
Short name T1272
Test name
Test status
Simulation time 46730599 ps
CPU time 2.46 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:39 PM PDT 24
Peak memory 200012 kb
Host smart-7c11df07-7118-4785-903a-02091bf7ecb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982378669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1982378669
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3640207031
Short name T1240
Test name
Test status
Simulation time 176509251 ps
CPU time 0.95 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 199208 kb
Host smart-bfb6b5b5-4a55-426d-9305-6b76fbe504e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640207031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3640207031
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4096529225
Short name T1315
Test name
Test status
Simulation time 32940840 ps
CPU time 0.88 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 200216 kb
Host smart-62b437b6-23ac-43d7-8c90-4e594aca21b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096529225 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4096529225
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1166701151
Short name T91
Test name
Test status
Simulation time 38573649 ps
CPU time 0.59 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 195852 kb
Host smart-271ece11-f274-472f-ac96-60eb3f796d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166701151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1166701151
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3308778269
Short name T1220
Test name
Test status
Simulation time 51289470 ps
CPU time 0.61 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 194764 kb
Host smart-1912709b-c40f-45c6-8b23-d96cbd18825d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308778269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3308778269
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.439501666
Short name T1238
Test name
Test status
Simulation time 37580168 ps
CPU time 0.71 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 196240 kb
Host smart-993d8715-762f-4881-8a6b-72e3261e48c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439501666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.439501666
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1144897725
Short name T1312
Test name
Test status
Simulation time 37250469 ps
CPU time 1.78 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:31 PM PDT 24
Peak memory 200356 kb
Host smart-6168860a-a3d0-423e-900b-600bb4159a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144897725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1144897725
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1382067027
Short name T1233
Test name
Test status
Simulation time 54989538 ps
CPU time 0.98 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 199348 kb
Host smart-46f872a3-5cc0-4e2e-b4d4-f0b9bb0a834a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382067027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1382067027
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.794281650
Short name T1263
Test name
Test status
Simulation time 123837106 ps
CPU time 0.77 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 198620 kb
Host smart-c1d8af9e-9f72-472c-a86e-1345aa301845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794281650 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.794281650
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1965776500
Short name T89
Test name
Test status
Simulation time 12516833 ps
CPU time 0.58 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 195732 kb
Host smart-824d7fb9-7d86-4510-a85a-88bc1ea428e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965776500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1965776500
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1717372790
Short name T1253
Test name
Test status
Simulation time 11838577 ps
CPU time 0.57 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 194708 kb
Host smart-6e7b9083-10c7-4971-a1a9-0892dd417a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717372790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1717372790
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1485136725
Short name T1234
Test name
Test status
Simulation time 64514519 ps
CPU time 0.6 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 195760 kb
Host smart-b21fa05f-d8af-43a7-8bb6-6866b3830aa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485136725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1485136725
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3413137666
Short name T1209
Test name
Test status
Simulation time 274667762 ps
CPU time 1.65 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 200360 kb
Host smart-e3c32d56-0096-4675-80cf-f9801a720cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413137666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3413137666
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3079718334
Short name T99
Test name
Test status
Simulation time 87453998 ps
CPU time 0.99 seconds
Started May 07 12:44:52 PM PDT 24
Finished May 07 12:44:54 PM PDT 24
Peak memory 199292 kb
Host smart-c7ec4776-a4c9-47d9-8e2d-26b10e5b2cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079718334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3079718334
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1281376139
Short name T1221
Test name
Test status
Simulation time 45392111 ps
CPU time 0.79 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:44:44 PM PDT 24
Peak memory 199400 kb
Host smart-d15af03c-4ed4-47ae-adbd-390f2bc2f771
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281376139 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1281376139
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.267281404
Short name T1256
Test name
Test status
Simulation time 35801582 ps
CPU time 0.6 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 194684 kb
Host smart-d0f154b6-1636-4283-8e87-756a1df9d7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267281404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.267281404
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3791959215
Short name T1257
Test name
Test status
Simulation time 160207503 ps
CPU time 0.72 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 197428 kb
Host smart-665669ba-ee52-47ad-b5b8-01015f4cbbb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791959215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3791959215
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2335831699
Short name T1281
Test name
Test status
Simulation time 46999511 ps
CPU time 2.27 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:39 PM PDT 24
Peak memory 200364 kb
Host smart-27cc57a7-fb46-4dd6-bd1d-26f1ab4cae7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335831699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2335831699
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2878724852
Short name T1284
Test name
Test status
Simulation time 17973611 ps
CPU time 0.77 seconds
Started May 07 12:44:28 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 200036 kb
Host smart-92366868-3622-4071-b333-9e05942b8fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878724852 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2878724852
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3032028070
Short name T88
Test name
Test status
Simulation time 13024391 ps
CPU time 0.56 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 195548 kb
Host smart-7aaf904e-a20e-43be-ac97-f326043d6aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032028070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3032028070
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1945345707
Short name T1268
Test name
Test status
Simulation time 41619070 ps
CPU time 0.59 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 194656 kb
Host smart-7096492d-0951-431d-a89b-af132b0483a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945345707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1945345707
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2156716824
Short name T90
Test name
Test status
Simulation time 47611263 ps
CPU time 0.7 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 197132 kb
Host smart-25bf0012-c172-4d69-90b8-70c22d49c83c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156716824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2156716824
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1831457036
Short name T1269
Test name
Test status
Simulation time 306260688 ps
CPU time 1.3 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 200312 kb
Host smart-48673f3d-a6ea-4a37-aae9-9cf655c89b13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831457036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1831457036
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2699998326
Short name T1265
Test name
Test status
Simulation time 379910683 ps
CPU time 1.26 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 199268 kb
Host smart-536542b9-a220-45f0-ab63-d1d615c00cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699998326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2699998326
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2906988768
Short name T1243
Test name
Test status
Simulation time 21001622 ps
CPU time 1.1 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 200428 kb
Host smart-54ebb903-fc91-4769-b464-11b2857dc0f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906988768 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2906988768
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.488842568
Short name T82
Test name
Test status
Simulation time 14836840 ps
CPU time 0.63 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 195848 kb
Host smart-dc1f6c89-98e8-4d2b-9850-47a3013bab47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488842568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.488842568
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3094984964
Short name T1310
Test name
Test status
Simulation time 35787835 ps
CPU time 0.56 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 194588 kb
Host smart-3bdbaf13-5795-48a8-b74f-ba5ceab67e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094984964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3094984964
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1781988128
Short name T1239
Test name
Test status
Simulation time 307600598 ps
CPU time 0.65 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 195964 kb
Host smart-8f17668f-74ba-48af-a741-c7cc6f620b75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781988128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1781988128
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1328684498
Short name T1285
Test name
Test status
Simulation time 142201543 ps
CPU time 1.85 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:44:46 PM PDT 24
Peak memory 200400 kb
Host smart-68c70b78-f37e-4130-8213-5d46e42245a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328684498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1328684498
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3430826123
Short name T137
Test name
Test status
Simulation time 260089643 ps
CPU time 1.22 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 199728 kb
Host smart-f1bcb3fc-d422-4a7e-916f-a9bbae583c91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430826123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3430826123
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1478675809
Short name T1298
Test name
Test status
Simulation time 30937399 ps
CPU time 0.86 seconds
Started May 07 12:44:37 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 200196 kb
Host smart-b867997f-6abe-486a-9bbe-6a6958acffea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478675809 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1478675809
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1564886119
Short name T1215
Test name
Test status
Simulation time 44930100 ps
CPU time 0.58 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 195720 kb
Host smart-9e9fed0e-ae68-445a-8ebb-a2567b40b0aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564886119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1564886119
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.989341887
Short name T1228
Test name
Test status
Simulation time 13051086 ps
CPU time 0.57 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 194400 kb
Host smart-390b24d3-a783-4685-8539-5b25617b3782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989341887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.989341887
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1316002465
Short name T1267
Test name
Test status
Simulation time 50850338 ps
CPU time 0.71 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 197248 kb
Host smart-47bf9f5a-8c6f-42f1-abfb-24a9a22e94ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316002465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1316002465
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4011890839
Short name T1203
Test name
Test status
Simulation time 115757189 ps
CPU time 2.06 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:44:44 PM PDT 24
Peak memory 200376 kb
Host smart-0bceb579-fab4-4dda-b13d-38d50fc4c19e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011890839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4011890839
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.767191470
Short name T140
Test name
Test status
Simulation time 240648322 ps
CPU time 1.57 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 199724 kb
Host smart-aeb550be-2c03-4f87-8ef3-01f2380684b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767191470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.767191470
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2447897088
Short name T1189
Test name
Test status
Simulation time 93711778 ps
CPU time 0.89 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 200060 kb
Host smart-da9002f9-f8cb-4798-a074-df2befee0520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447897088 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2447897088
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4239623662
Short name T83
Test name
Test status
Simulation time 18523622 ps
CPU time 0.57 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 195568 kb
Host smart-439d6575-ab55-4bff-8b03-b4ca0dcda9b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239623662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4239623662
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.981835718
Short name T1296
Test name
Test status
Simulation time 14588112 ps
CPU time 0.57 seconds
Started May 07 12:44:23 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 194520 kb
Host smart-02e9b435-bec4-4d11-8400-f018fb202926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981835718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.981835718
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1223484069
Short name T1261
Test name
Test status
Simulation time 22247655 ps
CPU time 0.65 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 195916 kb
Host smart-c9e3ac71-ee33-4ebf-9398-3c7124d49bc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223484069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1223484069
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2150161382
Short name T1208
Test name
Test status
Simulation time 36077262 ps
CPU time 1.07 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 200332 kb
Host smart-3ea2183c-0c7d-43fa-95d3-4a576998bcb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150161382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2150161382
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2653944297
Short name T98
Test name
Test status
Simulation time 44739392 ps
CPU time 0.94 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 199292 kb
Host smart-e93319e6-68cf-480d-ad9c-ae777e0f3731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653944297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2653944297
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.56565781
Short name T1246
Test name
Test status
Simulation time 62096502 ps
CPU time 0.98 seconds
Started May 07 12:44:51 PM PDT 24
Finished May 07 12:44:53 PM PDT 24
Peak memory 200180 kb
Host smart-6250cfa7-1b7c-4ae1-8ac1-54fe70f6a70e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56565781 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.56565781
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1680172478
Short name T1226
Test name
Test status
Simulation time 43666154 ps
CPU time 0.58 seconds
Started May 07 12:44:57 PM PDT 24
Finished May 07 12:44:58 PM PDT 24
Peak memory 195724 kb
Host smart-4b9c0b44-b7b0-41ae-b7d5-6710ef197cb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680172478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1680172478
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3804709156
Short name T1264
Test name
Test status
Simulation time 16696900 ps
CPU time 0.6 seconds
Started May 07 12:44:39 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 194760 kb
Host smart-cf980ef0-aef8-424a-82c2-3b592e7e5027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804709156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3804709156
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3287507978
Short name T1287
Test name
Test status
Simulation time 29948626 ps
CPU time 0.79 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 197324 kb
Host smart-8af5db58-fb19-4f3d-8ba7-4dd20befe672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287507978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3287507978
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2869485683
Short name T1292
Test name
Test status
Simulation time 166845794 ps
CPU time 0.97 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 199956 kb
Host smart-61c1f67f-ce89-4348-95a3-9949c13af2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869485683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2869485683
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3529325165
Short name T105
Test name
Test status
Simulation time 244078694 ps
CPU time 0.94 seconds
Started May 07 12:44:19 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 199268 kb
Host smart-63375305-4b07-4e18-9509-475c8f673fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529325165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3529325165
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.518961987
Short name T1271
Test name
Test status
Simulation time 57772224 ps
CPU time 0.76 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:44:34 PM PDT 24
Peak memory 198708 kb
Host smart-3d798fd4-66e5-4df3-b0ed-9bf2f4fe8420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518961987 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.518961987
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.386764094
Short name T1301
Test name
Test status
Simulation time 23753730 ps
CPU time 0.6 seconds
Started May 07 12:44:28 PM PDT 24
Finished May 07 12:44:31 PM PDT 24
Peak memory 195688 kb
Host smart-4203c3d8-968c-48fc-a3d8-a19e4d38ea49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386764094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.386764094
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.602171938
Short name T1198
Test name
Test status
Simulation time 41458068 ps
CPU time 0.59 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 194676 kb
Host smart-ff2b2590-e4c8-4348-83d8-009ba29d5a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602171938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.602171938
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3271929679
Short name T1280
Test name
Test status
Simulation time 52097863 ps
CPU time 0.73 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 197336 kb
Host smart-6d5065e3-df67-4edb-8ce0-b560a8cb1075
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271929679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3271929679
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3446288363
Short name T1186
Test name
Test status
Simulation time 69417580 ps
CPU time 1.82 seconds
Started May 07 12:44:45 PM PDT 24
Finished May 07 12:44:48 PM PDT 24
Peak memory 200348 kb
Host smart-5aba8b18-b693-466e-a534-cb04c8fcc253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446288363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3446288363
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3063673510
Short name T1248
Test name
Test status
Simulation time 158441522 ps
CPU time 1.3 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 199536 kb
Host smart-a7ac277a-924c-405b-889b-407080f2c9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063673510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3063673510
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.815908194
Short name T66
Test name
Test status
Simulation time 104082586 ps
CPU time 0.78 seconds
Started May 07 12:44:24 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 196636 kb
Host smart-c31adf3b-3639-4460-a70e-a11de507dee2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815908194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.815908194
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2811309831
Short name T1293
Test name
Test status
Simulation time 92016646 ps
CPU time 1.61 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 198344 kb
Host smart-a1e209d7-dd6f-4484-837c-3a78282798e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811309831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2811309831
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3844044678
Short name T65
Test name
Test status
Simulation time 16778827 ps
CPU time 0.63 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 195708 kb
Host smart-1c21d64f-3076-42c6-b178-c44ce5d29b06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844044678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3844044678
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4087016865
Short name T1187
Test name
Test status
Simulation time 27553665 ps
CPU time 0.79 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 200184 kb
Host smart-60b0415b-efd1-4eba-a079-8f0cb5477513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087016865 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4087016865
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.596930826
Short name T1251
Test name
Test status
Simulation time 37933404 ps
CPU time 0.6 seconds
Started May 07 12:44:23 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 195868 kb
Host smart-0c0d7f8d-569b-4daf-bca8-96b7abbda84b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596930826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.596930826
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2838332335
Short name T1306
Test name
Test status
Simulation time 15734663 ps
CPU time 0.58 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 194636 kb
Host smart-7ceead7e-e11c-4de8-8c7c-728cbb1689ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838332335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2838332335
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4033806389
Short name T1241
Test name
Test status
Simulation time 126987832 ps
CPU time 0.64 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:29 PM PDT 24
Peak memory 196000 kb
Host smart-7228c0a1-c217-4f05-b366-01c83d6ad215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033806389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.4033806389
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.299972649
Short name T1245
Test name
Test status
Simulation time 352392229 ps
CPU time 2.4 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 200448 kb
Host smart-d1570029-a68e-483b-b082-146fd135b24c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299972649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.299972649
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3998313090
Short name T97
Test name
Test status
Simulation time 101062747 ps
CPU time 0.91 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 199140 kb
Host smart-0139a9e7-2e21-4463-8d64-06a6f46c4704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998313090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3998313090
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3121439039
Short name T1308
Test name
Test status
Simulation time 56239268 ps
CPU time 0.57 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 194756 kb
Host smart-633a3616-8cf2-411e-a80f-658c1a6f9d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121439039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3121439039
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3663214288
Short name T1297
Test name
Test status
Simulation time 46090849 ps
CPU time 0.58 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 194652 kb
Host smart-4fc6295d-4cee-4602-9eb8-60e902f4410f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663214288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3663214288
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1923395400
Short name T1216
Test name
Test status
Simulation time 29031350 ps
CPU time 0.59 seconds
Started May 07 12:44:25 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 194708 kb
Host smart-897bf62c-fbcd-4330-844d-7558161928b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923395400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1923395400
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.196026261
Short name T1212
Test name
Test status
Simulation time 141108342 ps
CPU time 0.56 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 194692 kb
Host smart-55971f56-34de-4e2f-8dc3-725245fac601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196026261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.196026261
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.201398994
Short name T1218
Test name
Test status
Simulation time 44831753 ps
CPU time 0.56 seconds
Started May 07 12:44:44 PM PDT 24
Finished May 07 12:44:45 PM PDT 24
Peak memory 194680 kb
Host smart-af26d313-fd5b-43d0-afe1-f5736c4afcea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201398994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.201398994
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2649169977
Short name T1252
Test name
Test status
Simulation time 25012023 ps
CPU time 0.56 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 194736 kb
Host smart-1e981158-b29f-4b6b-b8e7-5201251807cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649169977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2649169977
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.964707846
Short name T1200
Test name
Test status
Simulation time 123245479 ps
CPU time 0.57 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 194680 kb
Host smart-0ce71be8-803d-4e16-b996-43dd152df362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964707846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.964707846
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1878926218
Short name T1259
Test name
Test status
Simulation time 37354224 ps
CPU time 0.6 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 194724 kb
Host smart-541da321-6a59-4eae-95c8-50b302e4660a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878926218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1878926218
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2164039319
Short name T1242
Test name
Test status
Simulation time 67659646 ps
CPU time 0.59 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 194696 kb
Host smart-b7d05d7a-ac1f-45a4-8245-d4126fdb944e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164039319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2164039319
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2000636846
Short name T1278
Test name
Test status
Simulation time 22559439 ps
CPU time 0.56 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 194684 kb
Host smart-e19a3c40-c79c-402e-b816-f7b710dfc2d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000636846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2000636846
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3315092658
Short name T1204
Test name
Test status
Simulation time 19782285 ps
CPU time 0.69 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 195700 kb
Host smart-e34bd8ed-1b45-430b-bb16-696c5a2a61d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315092658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3315092658
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1153457369
Short name T63
Test name
Test status
Simulation time 65854964 ps
CPU time 1.47 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 198076 kb
Host smart-d6fa707b-b450-4123-8643-95ded76ed7b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153457369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1153457369
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4051763607
Short name T1273
Test name
Test status
Simulation time 27172278 ps
CPU time 0.63 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 195724 kb
Host smart-9fe30e3e-687c-490d-907b-c755a9564fcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051763607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4051763607
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1062105925
Short name T1236
Test name
Test status
Simulation time 18258416 ps
CPU time 0.7 seconds
Started May 07 12:44:25 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 197804 kb
Host smart-a25eb525-66eb-4dc3-8efb-4a5004d6fea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062105925 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1062105925
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.156152316
Short name T1227
Test name
Test status
Simulation time 18144372 ps
CPU time 0.63 seconds
Started May 07 12:44:28 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 195732 kb
Host smart-ebcf5a92-18ad-4d1e-ae2e-77a197cbf97e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156152316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.156152316
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2743861129
Short name T1191
Test name
Test status
Simulation time 78511989 ps
CPU time 0.6 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 194668 kb
Host smart-8d550fcd-84a1-426b-9656-3c59a982fa4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743861129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2743861129
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1573054240
Short name T1235
Test name
Test status
Simulation time 44229355 ps
CPU time 0.66 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 194824 kb
Host smart-208a4253-e60a-4c85-9279-3c8e013d8030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573054240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1573054240
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2182872053
Short name T1223
Test name
Test status
Simulation time 124111599 ps
CPU time 1.36 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 200340 kb
Host smart-3afe2be1-3dc6-4b0b-9c9d-4b8f1dff5de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182872053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2182872053
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3334283666
Short name T138
Test name
Test status
Simulation time 89500483 ps
CPU time 1 seconds
Started May 07 12:44:19 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 199316 kb
Host smart-8eeda656-1cb8-4f77-ae18-4a189e8b03f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334283666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3334283666
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3531054142
Short name T1219
Test name
Test status
Simulation time 14017782 ps
CPU time 0.58 seconds
Started May 07 12:44:47 PM PDT 24
Finished May 07 12:44:48 PM PDT 24
Peak memory 194700 kb
Host smart-cd301da3-dc67-4994-a00a-14f4a56aa31c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531054142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3531054142
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.563326834
Short name T1275
Test name
Test status
Simulation time 49473292 ps
CPU time 0.65 seconds
Started May 07 12:44:49 PM PDT 24
Finished May 07 12:44:50 PM PDT 24
Peak memory 194748 kb
Host smart-f678e425-2589-4ead-863c-793311f9af69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563326834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.563326834
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3910210104
Short name T1201
Test name
Test status
Simulation time 51330309 ps
CPU time 0.56 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:34 PM PDT 24
Peak memory 194676 kb
Host smart-bd1b5ed4-c127-4c36-a967-5277be07a1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910210104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3910210104
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.94676016
Short name T1205
Test name
Test status
Simulation time 26460818 ps
CPU time 0.56 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 194680 kb
Host smart-57ff1044-6fd3-40fc-98d8-d11e2b8868a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94676016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.94676016
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2961655917
Short name T1290
Test name
Test status
Simulation time 40313743 ps
CPU time 0.57 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 194740 kb
Host smart-3ec7fc79-0cbe-4ecf-925c-51f8f6e899c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961655917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2961655917
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.881490937
Short name T1196
Test name
Test status
Simulation time 14996326 ps
CPU time 0.67 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:29 PM PDT 24
Peak memory 194684 kb
Host smart-03ca665f-f7a3-40af-879b-f8068c2839b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881490937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.881490937
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3527908160
Short name T1193
Test name
Test status
Simulation time 16482301 ps
CPU time 0.57 seconds
Started May 07 12:44:28 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 194684 kb
Host smart-debcf70f-673d-46e5-859d-4c9900b05b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527908160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3527908160
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2686547069
Short name T1276
Test name
Test status
Simulation time 38939898 ps
CPU time 0.61 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:44:39 PM PDT 24
Peak memory 194700 kb
Host smart-36a7c465-cc13-439b-82a9-fb1ae583ebde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686547069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2686547069
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1448728160
Short name T1206
Test name
Test status
Simulation time 27449874 ps
CPU time 0.56 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 194664 kb
Host smart-e430857e-503d-40a9-957c-6dfb99b61518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448728160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1448728160
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1147212744
Short name T1302
Test name
Test status
Simulation time 13256280 ps
CPU time 0.57 seconds
Started May 07 12:44:43 PM PDT 24
Finished May 07 12:44:45 PM PDT 24
Peak memory 194740 kb
Host smart-81d06574-f1ed-4177-8c61-afd59cf70435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147212744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1147212744
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1718121888
Short name T69
Test name
Test status
Simulation time 34784828 ps
CPU time 0.66 seconds
Started May 07 12:44:28 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 194960 kb
Host smart-92388a1f-1c84-4a61-b473-22817cd67a84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718121888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1718121888
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1917485234
Short name T1232
Test name
Test status
Simulation time 247395519 ps
CPU time 2.21 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 197908 kb
Host smart-72b8395a-0b19-4c71-a8c2-5c7a4e477502
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917485234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1917485234
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.301873734
Short name T1311
Test name
Test status
Simulation time 13570352 ps
CPU time 0.59 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 195540 kb
Host smart-865080f4-6842-4d6e-a028-4c606ca3d7dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301873734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.301873734
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1583724819
Short name T1214
Test name
Test status
Simulation time 100559256 ps
CPU time 0.77 seconds
Started May 07 12:44:24 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 200128 kb
Host smart-9d08260e-6eaf-4dd2-8dac-ed9c557d1524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583724819 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1583724819
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.792124605
Short name T1270
Test name
Test status
Simulation time 14876924 ps
CPU time 0.61 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 195884 kb
Host smart-8ab85942-60e1-49d6-b0ce-ff31872747a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792124605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.792124605
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.800009695
Short name T1282
Test name
Test status
Simulation time 12082020 ps
CPU time 0.55 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 194736 kb
Host smart-e1d004d3-603b-4417-85a1-795dc9896917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800009695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.800009695
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3438165127
Short name T1211
Test name
Test status
Simulation time 20812412 ps
CPU time 0.65 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 196224 kb
Host smart-1cd1c748-eaa0-4482-865d-96e54a92ed0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438165127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3438165127
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4115358022
Short name T1303
Test name
Test status
Simulation time 37524909 ps
CPU time 1.72 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 200348 kb
Host smart-4c068483-40c6-4e7d-9388-0137e995911c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115358022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4115358022
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3000681019
Short name T139
Test name
Test status
Simulation time 45537096 ps
CPU time 0.92 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 199284 kb
Host smart-2c31fdfe-f19e-4cf3-8c63-94b3ba27908e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000681019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3000681019
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.959832352
Short name T1244
Test name
Test status
Simulation time 22602520 ps
CPU time 0.63 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 194744 kb
Host smart-7715c5e9-fb92-4be3-b1a4-73b1c8639a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959832352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.959832352
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3929020787
Short name T1279
Test name
Test status
Simulation time 14943080 ps
CPU time 0.57 seconds
Started May 07 12:44:40 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 194688 kb
Host smart-ec5dfa69-3435-45bd-b56d-7f915ad2fc15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929020787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3929020787
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1535055343
Short name T1277
Test name
Test status
Simulation time 17302779 ps
CPU time 0.58 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 194660 kb
Host smart-4a60a579-cd4d-443c-be50-46531e956a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535055343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1535055343
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.583721091
Short name T1274
Test name
Test status
Simulation time 44186119 ps
CPU time 0.62 seconds
Started May 07 12:44:41 PM PDT 24
Finished May 07 12:44:43 PM PDT 24
Peak memory 194684 kb
Host smart-46e9c1c8-20f2-483f-9a80-d8770aa193f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583721091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.583721091
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3338465522
Short name T1207
Test name
Test status
Simulation time 15832072 ps
CPU time 0.57 seconds
Started May 07 12:44:38 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 194668 kb
Host smart-31259cc4-54ca-420e-9f8e-aa9b745d9414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338465522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3338465522
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.211378854
Short name T1289
Test name
Test status
Simulation time 15687097 ps
CPU time 0.56 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 194672 kb
Host smart-84b905b8-a9ff-4e77-80f5-f1accf5bc3e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211378854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.211378854
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3533108546
Short name T1217
Test name
Test status
Simulation time 14391591 ps
CPU time 0.56 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:39 PM PDT 24
Peak memory 194704 kb
Host smart-e36c6d72-5e33-451b-89f8-de10bda5ce5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533108546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3533108546
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.130048835
Short name T1229
Test name
Test status
Simulation time 40006554 ps
CPU time 0.54 seconds
Started May 07 12:44:22 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 194688 kb
Host smart-853b7fbe-b587-4ae8-a609-58e5edf1a3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130048835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.130048835
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2112904112
Short name T1225
Test name
Test status
Simulation time 13721011 ps
CPU time 0.58 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 194700 kb
Host smart-19b9efd4-bbe2-4edd-ab89-877d2c360b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112904112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2112904112
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.214113909
Short name T1230
Test name
Test status
Simulation time 38335893 ps
CPU time 0.55 seconds
Started May 07 12:44:48 PM PDT 24
Finished May 07 12:44:49 PM PDT 24
Peak memory 194684 kb
Host smart-e517a14c-4444-489f-8fff-439ba7b580eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214113909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.214113909
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2842812167
Short name T1231
Test name
Test status
Simulation time 29061787 ps
CPU time 0.8 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:44:34 PM PDT 24
Peak memory 199924 kb
Host smart-be918bb0-a6c3-467d-90d3-fa0c4141e2b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842812167 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2842812167
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1785484446
Short name T1295
Test name
Test status
Simulation time 17250040 ps
CPU time 0.59 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:12 PM PDT 24
Peak memory 195728 kb
Host smart-8bdb7bcc-0799-47e3-b22a-f4d900aa3b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785484446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1785484446
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4171444595
Short name T1304
Test name
Test status
Simulation time 133441548 ps
CPU time 0.57 seconds
Started May 07 12:44:22 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 194700 kb
Host smart-6052e0fa-89fc-4da1-8a40-97c92d3259c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171444595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4171444595
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.390341937
Short name T85
Test name
Test status
Simulation time 24709566 ps
CPU time 0.74 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 197024 kb
Host smart-845411df-0e47-480b-a017-ff7c36de5549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390341937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.390341937
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1208949017
Short name T1291
Test name
Test status
Simulation time 708274354 ps
CPU time 1.96 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 200316 kb
Host smart-99a46d46-ad10-4451-98e3-c8a3844f8cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208949017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1208949017
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3590786172
Short name T102
Test name
Test status
Simulation time 105300207 ps
CPU time 0.86 seconds
Started May 07 12:44:25 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 198900 kb
Host smart-9dd46f2c-6793-4d69-96e6-2c4ec642ca26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590786172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3590786172
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1121904303
Short name T1210
Test name
Test status
Simulation time 23615549 ps
CPU time 1.1 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 200344 kb
Host smart-7128bdef-8fa5-4405-95be-d645c1f42c32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121904303 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1121904303
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.766161608
Short name T68
Test name
Test status
Simulation time 17907331 ps
CPU time 0.64 seconds
Started May 07 12:44:19 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 195712 kb
Host smart-24e2bd56-6689-4618-886f-f2b2f824cd88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766161608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.766161608
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2503789662
Short name T1222
Test name
Test status
Simulation time 45172027 ps
CPU time 0.57 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 194756 kb
Host smart-e2e1549c-9325-4e88-9fcd-f870963ef982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503789662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2503789662
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4168204995
Short name T1305
Test name
Test status
Simulation time 16220421 ps
CPU time 0.78 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 197376 kb
Host smart-7396f858-1cd1-499e-974b-91de033f762f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168204995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.4168204995
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1938301016
Short name T1192
Test name
Test status
Simulation time 155120047 ps
CPU time 2.85 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 200352 kb
Host smart-416c700b-2c36-4c10-9410-e93d7af2c4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938301016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1938301016
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2853968816
Short name T1197
Test name
Test status
Simulation time 18827218 ps
CPU time 0.7 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:44:34 PM PDT 24
Peak memory 198476 kb
Host smart-508f213b-3b50-47d7-a768-97344c78d336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853968816 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2853968816
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.256059044
Short name T62
Test name
Test status
Simulation time 74564301 ps
CPU time 0.59 seconds
Started May 07 12:44:31 PM PDT 24
Finished May 07 12:44:34 PM PDT 24
Peak memory 195664 kb
Host smart-4d3ffd60-1637-476d-9fb3-e60908bb2d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256059044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.256059044
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2157984153
Short name T1190
Test name
Test status
Simulation time 50371732 ps
CPU time 0.58 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:29 PM PDT 24
Peak memory 194680 kb
Host smart-89ee29fb-afdc-49f6-bc12-7a9340153c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157984153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2157984153
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2207714374
Short name T1260
Test name
Test status
Simulation time 43043994 ps
CPU time 0.63 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 196732 kb
Host smart-42afec93-6990-4390-9e14-beab9f9940aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207714374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2207714374
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2507106243
Short name T1224
Test name
Test status
Simulation time 190123177 ps
CPU time 1.55 seconds
Started May 07 12:44:27 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 200312 kb
Host smart-9e3015fb-02fe-45a2-ada7-e4b7ec53c253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507106243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2507106243
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.825558480
Short name T101
Test name
Test status
Simulation time 58629862 ps
CPU time 0.91 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 198956 kb
Host smart-708de0f5-d80b-4a55-bc7b-c1631cd3e341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825558480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.825558480
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4171555001
Short name T1213
Test name
Test status
Simulation time 57935941 ps
CPU time 0.87 seconds
Started May 07 12:44:36 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 200188 kb
Host smart-0488df60-6a21-4d66-981c-faf29de3fdb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171555001 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4171555001
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3028945595
Short name T1262
Test name
Test status
Simulation time 16240665 ps
CPU time 0.65 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 195744 kb
Host smart-e061514f-31ea-4a5d-bb06-a1227a41f6c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028945595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3028945595
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2223124799
Short name T1283
Test name
Test status
Simulation time 15157593 ps
CPU time 0.57 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:18 PM PDT 24
Peak memory 194648 kb
Host smart-0e430caf-f93f-41b9-a30b-c575233737d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223124799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2223124799
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4163872969
Short name T84
Test name
Test status
Simulation time 20698494 ps
CPU time 0.66 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 196800 kb
Host smart-be01606a-2623-4392-8be6-b932b7dcf788
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163872969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4163872969
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.737807489
Short name T1237
Test name
Test status
Simulation time 308658371 ps
CPU time 1.34 seconds
Started May 07 12:44:24 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 200176 kb
Host smart-d330896c-c55b-4191-afbf-d9c78bdec0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737807489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.737807489
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3111831566
Short name T107
Test name
Test status
Simulation time 113957421 ps
CPU time 1.33 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 199628 kb
Host smart-bd4cd364-de6b-40ce-a0ef-b373d212d6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111831566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3111831566
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2063491097
Short name T1199
Test name
Test status
Simulation time 34487176 ps
CPU time 0.66 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:37 PM PDT 24
Peak memory 197760 kb
Host smart-44e65c3a-60de-45af-a7cb-d271c4261bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063491097 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2063491097
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2860363413
Short name T87
Test name
Test status
Simulation time 14066725 ps
CPU time 0.63 seconds
Started May 07 12:44:35 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 195728 kb
Host smart-0f02f2db-1f37-4377-aecb-7934d5190ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860363413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2860363413
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.166538757
Short name T1249
Test name
Test status
Simulation time 12642501 ps
CPU time 0.56 seconds
Started May 07 12:44:33 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 194656 kb
Host smart-35442668-e315-4bf0-882d-6e1c31272247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166538757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.166538757
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2516004419
Short name T1247
Test name
Test status
Simulation time 41805884 ps
CPU time 0.63 seconds
Started May 07 12:44:22 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 195056 kb
Host smart-8f7c9133-8460-4e5d-9d5e-aefc462a2ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516004419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2516004419
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3265512223
Short name T1266
Test name
Test status
Simulation time 121641399 ps
CPU time 0.97 seconds
Started May 07 12:44:32 PM PDT 24
Finished May 07 12:44:36 PM PDT 24
Peak memory 199988 kb
Host smart-3a2c132d-d663-4010-a1ca-e201853c5ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265512223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3265512223
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1991063862
Short name T1307
Test name
Test status
Simulation time 552352831 ps
CPU time 1.32 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 199644 kb
Host smart-e5ab3cb1-47ec-4167-af2d-811a5c47be2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991063862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1991063862
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1907974289
Short name T1061
Test name
Test status
Simulation time 50588426 ps
CPU time 0.58 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:08 PM PDT 24
Peak memory 195872 kb
Host smart-c2837d3b-66cf-4ba3-924c-71d27330eefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907974289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1907974289
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3074406098
Short name T480
Test name
Test status
Simulation time 66877546374 ps
CPU time 27.91 seconds
Started May 07 12:59:53 PM PDT 24
Finished May 07 01:00:21 PM PDT 24
Peak memory 200448 kb
Host smart-e8332e95-1998-40f7-b603-650c674efe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074406098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3074406098
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3577269403
Short name T649
Test name
Test status
Simulation time 20833753829 ps
CPU time 37.68 seconds
Started May 07 12:59:58 PM PDT 24
Finished May 07 01:00:36 PM PDT 24
Peak memory 200372 kb
Host smart-4b8b0fd8-731a-4035-b749-8c88e893dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577269403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3577269403
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2253821655
Short name T737
Test name
Test status
Simulation time 92223667022 ps
CPU time 137.53 seconds
Started May 07 01:00:00 PM PDT 24
Finished May 07 01:02:18 PM PDT 24
Peak memory 200400 kb
Host smart-a62cb248-63c9-4da5-9687-009591b6fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253821655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2253821655
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2458444162
Short name T1085
Test name
Test status
Simulation time 41856220743 ps
CPU time 17.45 seconds
Started May 07 12:59:58 PM PDT 24
Finished May 07 01:00:17 PM PDT 24
Peak memory 200384 kb
Host smart-902275c1-f460-47fe-abdd-49a96b746308
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458444162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2458444162
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2995764171
Short name T895
Test name
Test status
Simulation time 117510503921 ps
CPU time 296.46 seconds
Started May 07 01:00:00 PM PDT 24
Finished May 07 01:04:58 PM PDT 24
Peak memory 200368 kb
Host smart-d4ee6b9b-99f8-44fd-8ebb-0509ae1aa5f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995764171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2995764171
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2138117165
Short name T609
Test name
Test status
Simulation time 11873848368 ps
CPU time 4.4 seconds
Started May 07 01:00:00 PM PDT 24
Finished May 07 01:00:06 PM PDT 24
Peak memory 198932 kb
Host smart-9411eb7f-9ada-46bd-adeb-0d95902044dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138117165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2138117165
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2432944097
Short name T399
Test name
Test status
Simulation time 135918858444 ps
CPU time 59.28 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:01:00 PM PDT 24
Peak memory 208548 kb
Host smart-84bb85b9-1ab7-457f-96ee-b133c7976853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432944097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2432944097
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2047511377
Short name T421
Test name
Test status
Simulation time 24652154225 ps
CPU time 342.81 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:05:42 PM PDT 24
Peak memory 200448 kb
Host smart-db3b645b-9387-48dd-a028-a91a3c787ca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047511377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2047511377
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.358390690
Short name T538
Test name
Test status
Simulation time 4847676682 ps
CPU time 19.62 seconds
Started May 07 01:00:01 PM PDT 24
Finished May 07 01:00:21 PM PDT 24
Peak memory 199088 kb
Host smart-50fb7be1-c7bc-46ac-9e51-f8e8754aa137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358390690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.358390690
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.942369702
Short name T652
Test name
Test status
Simulation time 3468224912 ps
CPU time 3.63 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:00:04 PM PDT 24
Peak memory 196440 kb
Host smart-7074768d-5f05-4e98-b624-8dd6850d0b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942369702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.942369702
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1861193609
Short name T108
Test name
Test status
Simulation time 216825058 ps
CPU time 0.92 seconds
Started May 07 01:00:03 PM PDT 24
Finished May 07 01:00:05 PM PDT 24
Peak memory 218192 kb
Host smart-d34af7f4-5536-497a-9e47-f6f5708f2b32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861193609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1861193609
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3849894126
Short name T379
Test name
Test status
Simulation time 743772777 ps
CPU time 2.1 seconds
Started May 07 12:59:56 PM PDT 24
Finished May 07 12:59:59 PM PDT 24
Peak memory 198712 kb
Host smart-f947e343-0423-409d-bdcc-ea9461e90c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849894126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3849894126
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3372969024
Short name T888
Test name
Test status
Simulation time 264019010121 ps
CPU time 1853.4 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:30:54 PM PDT 24
Peak memory 226812 kb
Host smart-e98e572d-3358-4bb8-bb95-d403d1a54c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372969024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3372969024
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2643945192
Short name T958
Test name
Test status
Simulation time 368712779 ps
CPU time 1.2 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:00:01 PM PDT 24
Peak memory 199144 kb
Host smart-ec7e42c1-646c-4c27-9489-bd6cd62e156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643945192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2643945192
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2495110376
Short name T269
Test name
Test status
Simulation time 66531981719 ps
CPU time 112.45 seconds
Started May 07 12:59:53 PM PDT 24
Finished May 07 01:01:47 PM PDT 24
Peak memory 200452 kb
Host smart-d0f6952a-ad8b-43d0-8239-da016fb2138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495110376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2495110376
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3539068120
Short name T1011
Test name
Test status
Simulation time 19346159 ps
CPU time 0.56 seconds
Started May 07 01:00:09 PM PDT 24
Finished May 07 01:00:10 PM PDT 24
Peak memory 195256 kb
Host smart-d4d7c4d6-02a0-43f0-80b2-eaeccb8e1c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539068120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3539068120
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2952761740
Short name T1053
Test name
Test status
Simulation time 24856434354 ps
CPU time 40.5 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:00:41 PM PDT 24
Peak memory 200412 kb
Host smart-bba4ad55-36d6-4c0e-ac5a-d6b3ee09a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952761740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2952761740
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.821526384
Short name T781
Test name
Test status
Simulation time 53186035777 ps
CPU time 82.57 seconds
Started May 07 01:00:03 PM PDT 24
Finished May 07 01:01:26 PM PDT 24
Peak memory 200064 kb
Host smart-a7c8a2af-a00a-4d66-850c-c9f6619ace43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821526384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.821526384
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.4026468326
Short name T611
Test name
Test status
Simulation time 24956812551 ps
CPU time 13.04 seconds
Started May 07 01:00:00 PM PDT 24
Finished May 07 01:00:14 PM PDT 24
Peak memory 200448 kb
Host smart-07c5bb32-fbb1-4d24-abeb-dfce7f67f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026468326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4026468326
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2532514851
Short name T433
Test name
Test status
Simulation time 38412642299 ps
CPU time 65.49 seconds
Started May 07 01:00:02 PM PDT 24
Finished May 07 01:01:08 PM PDT 24
Peak memory 200380 kb
Host smart-1caad689-2afe-426d-b493-e4b3bd6a1a14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532514851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2532514851
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2346608517
Short name T840
Test name
Test status
Simulation time 292027365707 ps
CPU time 198.07 seconds
Started May 07 01:00:05 PM PDT 24
Finished May 07 01:03:24 PM PDT 24
Peak memory 200396 kb
Host smart-768007c9-b85b-472a-bbdb-d23ac7f906be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346608517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2346608517
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3562418932
Short name T891
Test name
Test status
Simulation time 1475664888 ps
CPU time 4.67 seconds
Started May 07 01:00:05 PM PDT 24
Finished May 07 01:00:10 PM PDT 24
Peak memory 199020 kb
Host smart-382228cc-e7a6-482f-97b9-124fab7cd9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562418932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3562418932
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.880794582
Short name T750
Test name
Test status
Simulation time 121078559104 ps
CPU time 299.86 seconds
Started May 07 01:00:05 PM PDT 24
Finished May 07 01:05:06 PM PDT 24
Peak memory 200656 kb
Host smart-e482b3c6-db4c-4d52-94a7-9e8aa9b20d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880794582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.880794582
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1906268488
Short name T404
Test name
Test status
Simulation time 12087806074 ps
CPU time 172.5 seconds
Started May 07 01:00:05 PM PDT 24
Finished May 07 01:02:58 PM PDT 24
Peak memory 200364 kb
Host smart-7ca2aac3-3638-433d-84b8-b319f223091e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906268488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1906268488
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2502062406
Short name T1139
Test name
Test status
Simulation time 6435015809 ps
CPU time 15.13 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:00:15 PM PDT 24
Peak memory 199256 kb
Host smart-af27056c-c5a5-422c-8678-e5d31272529a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2502062406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2502062406
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4059684877
Short name T391
Test name
Test status
Simulation time 22967298030 ps
CPU time 37.44 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:45 PM PDT 24
Peak memory 200344 kb
Host smart-4f1d76b8-c7bd-41b5-97ab-e93fef5d51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059684877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4059684877
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1552934107
Short name T1117
Test name
Test status
Simulation time 2253349970 ps
CPU time 2.57 seconds
Started May 07 01:00:09 PM PDT 24
Finished May 07 01:00:12 PM PDT 24
Peak memory 195864 kb
Host smart-f2f08212-2a9a-4310-8e22-238eb3299985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552934107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1552934107
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1389309697
Short name T28
Test name
Test status
Simulation time 58843946 ps
CPU time 0.88 seconds
Started May 07 01:00:07 PM PDT 24
Finished May 07 01:00:09 PM PDT 24
Peak memory 218468 kb
Host smart-7e515468-88d4-435e-bc71-7ca687b234ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389309697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1389309697
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2225834165
Short name T1151
Test name
Test status
Simulation time 6179938887 ps
CPU time 6.74 seconds
Started May 07 12:59:59 PM PDT 24
Finished May 07 01:00:06 PM PDT 24
Peak memory 200212 kb
Host smart-3c0ca7b8-3438-4bf8-a70a-f942e719acd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225834165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2225834165
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1255325154
Short name T687
Test name
Test status
Simulation time 311369570762 ps
CPU time 1267.95 seconds
Started May 07 01:00:07 PM PDT 24
Finished May 07 01:21:17 PM PDT 24
Peak memory 200388 kb
Host smart-de8ce6cc-5053-4f72-bb28-ca126ed5ed00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255325154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1255325154
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1730348710
Short name T423
Test name
Test status
Simulation time 980844384 ps
CPU time 3.9 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:00:16 PM PDT 24
Peak memory 199224 kb
Host smart-4d53b33b-a2de-4530-a39d-2f51c9ba3de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730348710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1730348710
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_alert_test.578590929
Short name T1099
Test name
Test status
Simulation time 36165532 ps
CPU time 0.53 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:00:38 PM PDT 24
Peak memory 195796 kb
Host smart-1510d9f0-d854-4a34-9069-57ddffdc6fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578590929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.578590929
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1083395970
Short name T881
Test name
Test status
Simulation time 156037272909 ps
CPU time 137.03 seconds
Started May 07 01:00:32 PM PDT 24
Finished May 07 01:02:50 PM PDT 24
Peak memory 200448 kb
Host smart-7514c731-58b9-4b7f-8cc1-e4969eaad5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083395970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1083395970
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1944876797
Short name T1169
Test name
Test status
Simulation time 84360078155 ps
CPU time 148.37 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:03:03 PM PDT 24
Peak memory 200304 kb
Host smart-c58db76b-7aad-431f-9f44-ba6468f2cfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944876797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1944876797
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2169245659
Short name T167
Test name
Test status
Simulation time 140155648229 ps
CPU time 35.39 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:01:11 PM PDT 24
Peak memory 200160 kb
Host smart-29f366b3-f65b-49a3-9a98-3689e9362fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169245659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2169245659
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2293190071
Short name T644
Test name
Test status
Simulation time 14133925676 ps
CPU time 11.04 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:00:45 PM PDT 24
Peak memory 200404 kb
Host smart-896f88ed-e008-4975-b21a-2ac3f723f38a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293190071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2293190071
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.39120594
Short name T830
Test name
Test status
Simulation time 54174060557 ps
CPU time 148.74 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:03:03 PM PDT 24
Peak memory 200396 kb
Host smart-2fa4d350-505c-46e9-8277-631855e15641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39120594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.39120594
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.967006351
Short name T429
Test name
Test status
Simulation time 47596332 ps
CPU time 0.62 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:00:39 PM PDT 24
Peak memory 196176 kb
Host smart-c71e4f17-71d9-4d61-bbc7-1545fb2f0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967006351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.967006351
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2386721048
Short name T592
Test name
Test status
Simulation time 176268773779 ps
CPU time 55.21 seconds
Started May 07 01:00:37 PM PDT 24
Finished May 07 01:01:34 PM PDT 24
Peak memory 208768 kb
Host smart-f36ad16b-eee9-443a-82bc-9c92a28b7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386721048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2386721048
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2274359506
Short name T39
Test name
Test status
Simulation time 22570157208 ps
CPU time 564.27 seconds
Started May 07 01:00:32 PM PDT 24
Finished May 07 01:09:58 PM PDT 24
Peak memory 200424 kb
Host smart-79bff0e8-ba90-4ce6-bd74-c131e4ed4df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274359506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2274359506
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1581190041
Short name T674
Test name
Test status
Simulation time 1901712830 ps
CPU time 11.31 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:00:54 PM PDT 24
Peak memory 198572 kb
Host smart-2f4d4dd8-1105-4a55-bca0-da69778195e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581190041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1581190041
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1275038540
Short name T837
Test name
Test status
Simulation time 34527475344 ps
CPU time 51.09 seconds
Started May 07 01:00:30 PM PDT 24
Finished May 07 01:01:23 PM PDT 24
Peak memory 200448 kb
Host smart-e64573b8-f335-4cb5-a1d6-615185bfa563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275038540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1275038540
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1144540784
Short name T1046
Test name
Test status
Simulation time 4553526834 ps
CPU time 6.51 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:00:49 PM PDT 24
Peak memory 196428 kb
Host smart-42b920b1-04dd-4f5d-bfbd-7458f667ba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144540784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1144540784
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4088039881
Short name T953
Test name
Test status
Simulation time 294644874 ps
CPU time 1.72 seconds
Started May 07 01:00:30 PM PDT 24
Finished May 07 01:00:33 PM PDT 24
Peak memory 200296 kb
Host smart-575ed383-8d24-489d-a10d-0eba147cfd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088039881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4088039881
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.230561790
Short name T56
Test name
Test status
Simulation time 57481993560 ps
CPU time 948.84 seconds
Started May 07 01:00:42 PM PDT 24
Finished May 07 01:16:32 PM PDT 24
Peak memory 217096 kb
Host smart-473f0afd-a102-40c8-9493-8b035eaa832f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230561790 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.230561790
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1250342170
Short name T307
Test name
Test status
Simulation time 6611795279 ps
CPU time 14.6 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:00:49 PM PDT 24
Peak memory 200116 kb
Host smart-88252abb-dc45-4f19-9a60-2e324e546ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250342170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1250342170
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.956377952
Short name T293
Test name
Test status
Simulation time 71998457319 ps
CPU time 17.98 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:00:56 PM PDT 24
Peak memory 200456 kb
Host smart-611a38a9-ca85-4cb1-bf7e-a3e6fd5651a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956377952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.956377952
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1028857515
Short name T949
Test name
Test status
Simulation time 142916122991 ps
CPU time 118.9 seconds
Started May 07 01:04:51 PM PDT 24
Finished May 07 01:06:51 PM PDT 24
Peak memory 200464 kb
Host smart-2b1c4893-3110-4026-a462-c9d91bf279e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028857515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1028857515
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.522176555
Short name T1035
Test name
Test status
Simulation time 40703739641 ps
CPU time 26.27 seconds
Started May 07 01:04:53 PM PDT 24
Finished May 07 01:05:20 PM PDT 24
Peak memory 200472 kb
Host smart-4cf37a55-f556-4226-b52f-023721d26b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522176555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.522176555
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1317239146
Short name T790
Test name
Test status
Simulation time 109550532452 ps
CPU time 15.85 seconds
Started May 07 01:04:52 PM PDT 24
Finished May 07 01:05:09 PM PDT 24
Peak memory 200444 kb
Host smart-5bac0613-5086-4843-83e4-192c1a55d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317239146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1317239146
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2616034066
Short name T1010
Test name
Test status
Simulation time 73477313283 ps
CPU time 33.94 seconds
Started May 07 01:04:53 PM PDT 24
Finished May 07 01:05:28 PM PDT 24
Peak memory 200416 kb
Host smart-eaf1d908-3961-4841-acbb-d16f37bb1ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616034066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2616034066
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3362546658
Short name T998
Test name
Test status
Simulation time 20146783823 ps
CPU time 42.61 seconds
Started May 07 01:04:50 PM PDT 24
Finished May 07 01:05:34 PM PDT 24
Peak memory 200424 kb
Host smart-f20142c2-226a-4036-80ea-84929a017cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362546658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3362546658
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2357324836
Short name T1095
Test name
Test status
Simulation time 94302865644 ps
CPU time 154.32 seconds
Started May 07 01:04:53 PM PDT 24
Finished May 07 01:07:28 PM PDT 24
Peak memory 200480 kb
Host smart-865a4177-9898-4f7e-ac6b-a7a8862d1663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357324836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2357324836
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.910572872
Short name T734
Test name
Test status
Simulation time 74006815134 ps
CPU time 33.55 seconds
Started May 07 01:04:52 PM PDT 24
Finished May 07 01:05:26 PM PDT 24
Peak memory 200408 kb
Host smart-06e85a0e-ba17-4747-95e2-38f91e845f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910572872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.910572872
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1631792372
Short name T1022
Test name
Test status
Simulation time 38233665225 ps
CPU time 14.31 seconds
Started May 07 01:04:51 PM PDT 24
Finished May 07 01:05:06 PM PDT 24
Peak memory 200476 kb
Host smart-b89d5647-762e-4399-8656-f472bbaf9a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631792372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1631792372
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3714604720
Short name T253
Test name
Test status
Simulation time 99997596479 ps
CPU time 83.17 seconds
Started May 07 01:04:50 PM PDT 24
Finished May 07 01:06:14 PM PDT 24
Peak memory 200376 kb
Host smart-6b078664-bbae-46dd-b90a-a1fefa7ee4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714604720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3714604720
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.693689642
Short name T525
Test name
Test status
Simulation time 54385677 ps
CPU time 0.55 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:00:35 PM PDT 24
Peak memory 195828 kb
Host smart-dbe480d6-96f4-4e68-b0ff-19ca377e4df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693689642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.693689642
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.578286092
Short name T841
Test name
Test status
Simulation time 144247988146 ps
CPU time 122.15 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:02:36 PM PDT 24
Peak memory 200372 kb
Host smart-5e13f497-cb06-424f-9d3b-9a235367194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578286092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.578286092
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2327921324
Short name T209
Test name
Test status
Simulation time 196976679893 ps
CPU time 141.05 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:02:57 PM PDT 24
Peak memory 200600 kb
Host smart-0d1c1870-3fbb-4e63-9054-e91c3565cf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327921324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2327921324
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.857849304
Short name T475
Test name
Test status
Simulation time 20235145760 ps
CPU time 2.81 seconds
Started May 07 01:00:35 PM PDT 24
Finished May 07 01:00:40 PM PDT 24
Peak memory 198760 kb
Host smart-2987ed5b-5cfa-4719-8204-f942b6a781fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857849304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.857849304
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3591529316
Short name T670
Test name
Test status
Simulation time 61787096118 ps
CPU time 201.94 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:04:01 PM PDT 24
Peak memory 200392 kb
Host smart-6a0b674e-50fc-4787-8069-5eb7e7564e4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591529316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3591529316
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.355234924
Short name T890
Test name
Test status
Simulation time 9319435042 ps
CPU time 16.35 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:00:52 PM PDT 24
Peak memory 196792 kb
Host smart-48cfb8e3-de38-4fc0-b9d6-f7f5226c66e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355234924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.355234924
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3387607769
Short name T1111
Test name
Test status
Simulation time 78510174251 ps
CPU time 37.81 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:01:13 PM PDT 24
Peak memory 200532 kb
Host smart-5add19fa-c67d-456b-99f3-a76e8f291c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387607769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3387607769
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.860540711
Short name T354
Test name
Test status
Simulation time 9377419833 ps
CPU time 444.44 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:07:59 PM PDT 24
Peak memory 200540 kb
Host smart-5e821350-cec5-4ac9-ba9c-9de7bdf3b6ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860540711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.860540711
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3301206881
Short name T537
Test name
Test status
Simulation time 5257072543 ps
CPU time 11.11 seconds
Started May 07 01:00:42 PM PDT 24
Finished May 07 01:00:54 PM PDT 24
Peak memory 199144 kb
Host smart-801a9504-4a81-4f57-b8f2-b5a837549da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301206881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3301206881
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3622415105
Short name T605
Test name
Test status
Simulation time 24517688823 ps
CPU time 20.36 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:00:55 PM PDT 24
Peak memory 200368 kb
Host smart-a59078d3-81c5-40a7-b792-bea26e10cc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622415105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3622415105
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.398467834
Short name T7
Test name
Test status
Simulation time 4611163650 ps
CPU time 7.47 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:00:45 PM PDT 24
Peak memory 196700 kb
Host smart-31916bc5-0e9e-45f4-a561-d0a771c13699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398467834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.398467834
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.269924280
Short name T1052
Test name
Test status
Simulation time 734987014 ps
CPU time 3.28 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:00:39 PM PDT 24
Peak memory 199868 kb
Host smart-3a65ec28-7fca-466d-8292-6ab5a86c0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269924280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.269924280
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2717945871
Short name T743
Test name
Test status
Simulation time 206440585528 ps
CPU time 869.88 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:15:12 PM PDT 24
Peak memory 200400 kb
Host smart-a8e8d0f7-9f3e-40a0-850d-38648d9e1731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717945871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2717945871
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2422352721
Short name T185
Test name
Test status
Simulation time 221844193581 ps
CPU time 689.21 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:12:04 PM PDT 24
Peak memory 229820 kb
Host smart-96a84192-784c-4dea-a6f9-26a3076145f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422352721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2422352721
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3209521315
Short name T907
Test name
Test status
Simulation time 1503856897 ps
CPU time 1.25 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:00:37 PM PDT 24
Peak memory 198096 kb
Host smart-ca4890f9-efec-4fa5-ac84-769b7665def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209521315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3209521315
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3427562617
Short name T266
Test name
Test status
Simulation time 167669737884 ps
CPU time 27.01 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:01:05 PM PDT 24
Peak memory 200388 kb
Host smart-ca81e36b-3f24-42cf-a4ab-3be4cdde6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427562617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3427562617
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3065482486
Short name T226
Test name
Test status
Simulation time 19307702593 ps
CPU time 24.9 seconds
Started May 07 01:04:48 PM PDT 24
Finished May 07 01:05:14 PM PDT 24
Peak memory 200512 kb
Host smart-374c6728-0697-4367-be9c-5c8170219c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065482486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3065482486
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3752039009
Short name T1068
Test name
Test status
Simulation time 15150902130 ps
CPU time 24.31 seconds
Started May 07 01:04:49 PM PDT 24
Finished May 07 01:05:14 PM PDT 24
Peak memory 200172 kb
Host smart-1699b62d-28b5-46e9-8951-c70704df2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752039009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3752039009
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2164811535
Short name T915
Test name
Test status
Simulation time 24885981218 ps
CPU time 47.26 seconds
Started May 07 01:04:49 PM PDT 24
Finished May 07 01:05:37 PM PDT 24
Peak memory 200428 kb
Host smart-a9417314-d566-4fb2-9054-06941049eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164811535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2164811535
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.274661898
Short name T1177
Test name
Test status
Simulation time 240158896936 ps
CPU time 32.11 seconds
Started May 07 01:04:52 PM PDT 24
Finished May 07 01:05:25 PM PDT 24
Peak memory 200404 kb
Host smart-5fbc56b2-8612-4380-a5c1-7607d3e5a252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274661898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.274661898
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.13197265
Short name T213
Test name
Test status
Simulation time 26619935344 ps
CPU time 11.49 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:05:11 PM PDT 24
Peak memory 200416 kb
Host smart-81aa74be-5662-4c52-9584-635ce78eaf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13197265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.13197265
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3527039369
Short name T782
Test name
Test status
Simulation time 112755805193 ps
CPU time 95.84 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 200464 kb
Host smart-d3190511-3d53-44db-ac3a-41274af1c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527039369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3527039369
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3370842575
Short name T1069
Test name
Test status
Simulation time 35581530 ps
CPU time 0.56 seconds
Started May 07 01:00:43 PM PDT 24
Finished May 07 01:00:45 PM PDT 24
Peak memory 195804 kb
Host smart-7ed1cf74-d3b4-4e0a-9558-0d23b2e53b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370842575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3370842575
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.483916463
Short name T660
Test name
Test status
Simulation time 125479834396 ps
CPU time 290.61 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:05:25 PM PDT 24
Peak memory 200524 kb
Host smart-80b904a7-78de-4f72-b6fe-fe0b4d5342fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483916463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.483916463
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2843452108
Short name T817
Test name
Test status
Simulation time 28978206494 ps
CPU time 54.04 seconds
Started May 07 01:00:35 PM PDT 24
Finished May 07 01:01:31 PM PDT 24
Peak memory 200312 kb
Host smart-eeefb19b-1e25-4cca-a0da-c3d22041abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843452108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2843452108
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.2895688767
Short name T1164
Test name
Test status
Simulation time 10905678907 ps
CPU time 20.52 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:00:56 PM PDT 24
Peak memory 200156 kb
Host smart-3602e3ea-c46f-4baf-aa4f-4b090e431d72
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895688767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2895688767
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3773945493
Short name T526
Test name
Test status
Simulation time 96369756425 ps
CPU time 490.04 seconds
Started May 07 01:00:40 PM PDT 24
Finished May 07 01:08:52 PM PDT 24
Peak memory 200436 kb
Host smart-e0ebbb93-1bf5-486a-8c9c-8edd3705aea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773945493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3773945493
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2779992133
Short name T774
Test name
Test status
Simulation time 4993274288 ps
CPU time 12.68 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:00:55 PM PDT 24
Peak memory 199440 kb
Host smart-4fe92e96-810c-401f-985c-8106987ba13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779992133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2779992133
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3185314882
Short name T403
Test name
Test status
Simulation time 147011984283 ps
CPU time 171.96 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:03:27 PM PDT 24
Peak memory 199520 kb
Host smart-efa2fdab-01a9-4d87-9c7d-b0c65d4d1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185314882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3185314882
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4226390554
Short name T663
Test name
Test status
Simulation time 27063765314 ps
CPU time 1263.01 seconds
Started May 07 01:00:40 PM PDT 24
Finished May 07 01:21:45 PM PDT 24
Peak memory 200428 kb
Host smart-ed30b62e-ea36-41c4-a29f-fc402717ef3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226390554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4226390554
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.781485163
Short name T356
Test name
Test status
Simulation time 4422035622 ps
CPU time 31.41 seconds
Started May 07 01:00:42 PM PDT 24
Finished May 07 01:01:14 PM PDT 24
Peak memory 199032 kb
Host smart-158c48d1-b500-4466-873d-7674bb3e09d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781485163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.781485163
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2214779990
Short name T175
Test name
Test status
Simulation time 27112244115 ps
CPU time 26.7 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:01:03 PM PDT 24
Peak memory 200316 kb
Host smart-01d8a2cd-055d-4e56-add2-e4c22f9cc569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214779990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2214779990
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3145307759
Short name T1130
Test name
Test status
Simulation time 3100989047 ps
CPU time 5.54 seconds
Started May 07 01:00:36 PM PDT 24
Finished May 07 01:00:43 PM PDT 24
Peak memory 196420 kb
Host smart-afe388a4-efa3-4659-8118-1476b0a51717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145307759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3145307759
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3343278786
Short name T861
Test name
Test status
Simulation time 540404843 ps
CPU time 1.35 seconds
Started May 07 01:00:34 PM PDT 24
Finished May 07 01:00:37 PM PDT 24
Peak memory 199156 kb
Host smart-2f29b766-3939-4171-acc4-9b94b403795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343278786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3343278786
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.565987642
Short name T413
Test name
Test status
Simulation time 151811903812 ps
CPU time 190.04 seconds
Started May 07 01:00:40 PM PDT 24
Finished May 07 01:03:52 PM PDT 24
Peak memory 200440 kb
Host smart-bc0ce77e-43df-4070-a1af-9f93a30f1bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565987642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.565987642
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3958270081
Short name T324
Test name
Test status
Simulation time 43229238056 ps
CPU time 495.22 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:08:57 PM PDT 24
Peak memory 212408 kb
Host smart-e5669303-95b9-403e-bb61-42e3745c072c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958270081 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3958270081
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1035638240
Short name T411
Test name
Test status
Simulation time 568080922 ps
CPU time 1.5 seconds
Started May 07 01:00:35 PM PDT 24
Finished May 07 01:00:38 PM PDT 24
Peak memory 200304 kb
Host smart-e30829a4-8573-44f9-a261-19858cae195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035638240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1035638240
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1565182123
Short name T835
Test name
Test status
Simulation time 32214336409 ps
CPU time 37.24 seconds
Started May 07 01:00:31 PM PDT 24
Finished May 07 01:01:10 PM PDT 24
Peak memory 200436 kb
Host smart-cabc947f-254e-46bb-8ce9-fbdeba561f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565182123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1565182123
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1586631944
Short name T730
Test name
Test status
Simulation time 87256279533 ps
CPU time 164.75 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:07:43 PM PDT 24
Peak memory 200328 kb
Host smart-e3780b18-527f-49de-88be-4d47264f4cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586631944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1586631944
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3507221195
Short name T606
Test name
Test status
Simulation time 323500248702 ps
CPU time 74.78 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:06:14 PM PDT 24
Peak memory 200388 kb
Host smart-6f183e28-7b63-49ff-95bc-a510a17c0ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507221195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3507221195
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2633766777
Short name T1071
Test name
Test status
Simulation time 233488233050 ps
CPU time 404.97 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:11:44 PM PDT 24
Peak memory 200460 kb
Host smart-8c927ccb-18f5-464f-b8da-79d8b70466ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633766777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2633766777
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2326412693
Short name T388
Test name
Test status
Simulation time 84270380578 ps
CPU time 15.88 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:05:15 PM PDT 24
Peak memory 200224 kb
Host smart-7aa61703-09ee-44eb-ae8a-1cc1d027b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326412693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2326412693
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1714402480
Short name T825
Test name
Test status
Simulation time 89844134063 ps
CPU time 93.44 seconds
Started May 07 01:05:01 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 200444 kb
Host smart-a18c537f-026e-41a9-ad1c-d4fbe86cd6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714402480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1714402480
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4015729455
Short name T809
Test name
Test status
Simulation time 217883908571 ps
CPU time 515.79 seconds
Started May 07 01:04:58 PM PDT 24
Finished May 07 01:13:35 PM PDT 24
Peak memory 200328 kb
Host smart-a4a1a8b6-83d7-4545-97aa-dd7b35ec12fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015729455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4015729455
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3361850336
Short name T753
Test name
Test status
Simulation time 24626081290 ps
CPU time 23.13 seconds
Started May 07 01:05:07 PM PDT 24
Finished May 07 01:05:31 PM PDT 24
Peak memory 200452 kb
Host smart-6a518309-cdd7-4ff7-b06d-c8a3ce32cbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361850336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3361850336
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.4075255604
Short name T784
Test name
Test status
Simulation time 102696819207 ps
CPU time 163.32 seconds
Started May 07 01:05:06 PM PDT 24
Finished May 07 01:07:50 PM PDT 24
Peak memory 200140 kb
Host smart-3217edd5-e83f-4fb6-9a50-83d2fe0ea7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075255604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.4075255604
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.372256289
Short name T959
Test name
Test status
Simulation time 54150132811 ps
CPU time 79.18 seconds
Started May 07 01:05:07 PM PDT 24
Finished May 07 01:06:27 PM PDT 24
Peak memory 200380 kb
Host smart-b957edf4-3588-4aa6-bd09-cad9c6c045ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372256289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.372256289
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2716308451
Short name T564
Test name
Test status
Simulation time 52156041 ps
CPU time 0.54 seconds
Started May 07 01:00:49 PM PDT 24
Finished May 07 01:00:51 PM PDT 24
Peak memory 195816 kb
Host smart-88298276-52fc-43f2-8eeb-6e3e316f2a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716308451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2716308451
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.936333743
Short name T348
Test name
Test status
Simulation time 27074764364 ps
CPU time 16.62 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:00:59 PM PDT 24
Peak memory 200396 kb
Host smart-a11ac487-548c-48c9-93d8-77077fa491c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936333743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.936333743
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1665323142
Short name T785
Test name
Test status
Simulation time 259146149527 ps
CPU time 116.05 seconds
Started May 07 01:00:43 PM PDT 24
Finished May 07 01:02:40 PM PDT 24
Peak memory 199748 kb
Host smart-04ad36d3-ab05-49e9-a0bf-bb9c5a7933c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665323142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1665323142
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1891630039
Short name T680
Test name
Test status
Simulation time 72993329661 ps
CPU time 100.63 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:02:23 PM PDT 24
Peak memory 200364 kb
Host smart-62442014-81e7-4277-8f85-2baf3f2e0b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891630039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1891630039
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2850043885
Short name T893
Test name
Test status
Simulation time 83967076420 ps
CPU time 220.6 seconds
Started May 07 01:00:48 PM PDT 24
Finished May 07 01:04:30 PM PDT 24
Peak memory 200436 kb
Host smart-225334fc-63f4-43bc-a6bc-ef7c4382dce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850043885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2850043885
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2298868642
Short name T493
Test name
Test status
Simulation time 6800280406 ps
CPU time 6.92 seconds
Started May 07 01:00:47 PM PDT 24
Finished May 07 01:00:55 PM PDT 24
Peak memory 200248 kb
Host smart-cd896bd1-7982-451a-a2b6-27595838b33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298868642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2298868642
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3485312668
Short name T1166
Test name
Test status
Simulation time 292028579635 ps
CPU time 56.46 seconds
Started May 07 01:00:44 PM PDT 24
Finished May 07 01:01:42 PM PDT 24
Peak memory 200840 kb
Host smart-1cb1ec5b-ea8a-4721-af9e-64c8947db47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485312668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3485312668
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1294247460
Short name T607
Test name
Test status
Simulation time 25232767974 ps
CPU time 349.2 seconds
Started May 07 01:00:48 PM PDT 24
Finished May 07 01:06:38 PM PDT 24
Peak memory 200428 kb
Host smart-f56e40c5-c383-40c7-b58f-f4a77c4c4875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294247460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1294247460
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3883546654
Short name T658
Test name
Test status
Simulation time 4820724615 ps
CPU time 47.13 seconds
Started May 07 01:00:40 PM PDT 24
Finished May 07 01:01:29 PM PDT 24
Peak memory 199112 kb
Host smart-0dc83935-ea96-4019-a389-e66628464b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883546654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3883546654
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2079827443
Short name T1170
Test name
Test status
Simulation time 37680968822 ps
CPU time 15.15 seconds
Started May 07 01:00:46 PM PDT 24
Finished May 07 01:01:02 PM PDT 24
Peak memory 199460 kb
Host smart-1bb40309-ecca-4041-ba75-cffce9b72bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079827443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2079827443
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2311748371
Short name T1131
Test name
Test status
Simulation time 4667153039 ps
CPU time 2.11 seconds
Started May 07 01:00:39 PM PDT 24
Finished May 07 01:00:43 PM PDT 24
Peak memory 196696 kb
Host smart-ac4dd4ee-4f00-4397-94be-5b8e9eeb0590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311748371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2311748371
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4115590404
Short name T381
Test name
Test status
Simulation time 454468419 ps
CPU time 2.26 seconds
Started May 07 01:00:41 PM PDT 24
Finished May 07 01:00:45 PM PDT 24
Peak memory 199300 kb
Host smart-5487a693-7dc3-43d3-97ac-8ad0bb324c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115590404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4115590404
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.560515293
Short name T1134
Test name
Test status
Simulation time 241530312905 ps
CPU time 323.24 seconds
Started May 07 01:00:47 PM PDT 24
Finished May 07 01:06:11 PM PDT 24
Peak memory 208768 kb
Host smart-8c30dc5d-78dd-4abe-8aef-24b4549e7ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560515293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.560515293
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2442888425
Short name T325
Test name
Test status
Simulation time 89932078735 ps
CPU time 542.56 seconds
Started May 07 01:00:46 PM PDT 24
Finished May 07 01:09:50 PM PDT 24
Peak memory 217116 kb
Host smart-b11f2ffc-0db9-41b8-b1f8-1e685a36febd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442888425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2442888425
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.919482839
Short name T828
Test name
Test status
Simulation time 6796961119 ps
CPU time 1.62 seconds
Started May 07 01:00:46 PM PDT 24
Finished May 07 01:00:49 PM PDT 24
Peak memory 200068 kb
Host smart-7959919f-63f3-4c4f-87bd-6f143fafd8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919482839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.919482839
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2114022348
Short name T508
Test name
Test status
Simulation time 6792918359 ps
CPU time 13.61 seconds
Started May 07 01:00:39 PM PDT 24
Finished May 07 01:00:54 PM PDT 24
Peak memory 200452 kb
Host smart-750eb1a5-7676-4438-a671-1655c26257d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114022348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2114022348
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4105083261
Short name T219
Test name
Test status
Simulation time 19408918597 ps
CPU time 33.69 seconds
Started May 07 01:05:04 PM PDT 24
Finished May 07 01:05:39 PM PDT 24
Peak memory 200056 kb
Host smart-924c510a-c481-4fbb-a963-379b6e64d357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105083261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4105083261
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1793903086
Short name T882
Test name
Test status
Simulation time 68858134981 ps
CPU time 33.14 seconds
Started May 07 01:05:06 PM PDT 24
Finished May 07 01:05:40 PM PDT 24
Peak memory 200460 kb
Host smart-9f9b07f9-2cea-4b27-a675-d25c3fe39481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793903086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1793903086
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2076900211
Short name T1096
Test name
Test status
Simulation time 29161607864 ps
CPU time 23.43 seconds
Started May 07 01:05:06 PM PDT 24
Finished May 07 01:05:30 PM PDT 24
Peak memory 200412 kb
Host smart-6637784e-16ab-49f5-a00d-0ccca4a4d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076900211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2076900211
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3016900730
Short name T319
Test name
Test status
Simulation time 99785554224 ps
CPU time 74.9 seconds
Started May 07 01:05:08 PM PDT 24
Finished May 07 01:06:24 PM PDT 24
Peak memory 200384 kb
Host smart-f689e088-4ea7-4d96-a60c-a034cc10d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016900730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3016900730
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.757175230
Short name T4
Test name
Test status
Simulation time 61729360455 ps
CPU time 22.4 seconds
Started May 07 01:05:06 PM PDT 24
Finished May 07 01:05:29 PM PDT 24
Peak memory 200388 kb
Host smart-daf57c3d-fcd6-4deb-8e0d-b2d85fe01e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757175230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.757175230
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.249604180
Short name T359
Test name
Test status
Simulation time 70717957078 ps
CPU time 31.57 seconds
Started May 07 01:05:04 PM PDT 24
Finished May 07 01:05:36 PM PDT 24
Peak memory 200328 kb
Host smart-ec98f4cb-18ce-4d0a-9279-b5f9191abd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249604180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.249604180
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2768886944
Short name T553
Test name
Test status
Simulation time 179471072124 ps
CPU time 347.66 seconds
Started May 07 01:05:05 PM PDT 24
Finished May 07 01:10:53 PM PDT 24
Peak memory 200476 kb
Host smart-f22e9cfe-1e47-4d0d-9be8-9d14a68caa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768886944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2768886944
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1082690266
Short name T337
Test name
Test status
Simulation time 51380915572 ps
CPU time 49.18 seconds
Started May 07 01:05:08 PM PDT 24
Finished May 07 01:05:58 PM PDT 24
Peak memory 200396 kb
Host smart-b735b857-3ec5-4fb6-a08a-e902a2f3b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082690266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1082690266
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1614276905
Short name T471
Test name
Test status
Simulation time 48294959 ps
CPU time 0.57 seconds
Started May 07 01:00:58 PM PDT 24
Finished May 07 01:00:59 PM PDT 24
Peak memory 195836 kb
Host smart-932eb709-c8e0-41ea-b193-3de1c7c2e5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614276905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1614276905
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1368553327
Short name T279
Test name
Test status
Simulation time 33024982433 ps
CPU time 64.14 seconds
Started May 07 01:00:46 PM PDT 24
Finished May 07 01:01:51 PM PDT 24
Peak memory 200468 kb
Host smart-812e96d1-80a4-4cd1-95d0-a404e0df2784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368553327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1368553327
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3105028872
Short name T803
Test name
Test status
Simulation time 17805757690 ps
CPU time 28.19 seconds
Started May 07 01:00:46 PM PDT 24
Finished May 07 01:01:15 PM PDT 24
Peak memory 200016 kb
Host smart-3c55e83f-70df-4e59-8b2b-ba0a35b061d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105028872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3105028872
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1083565526
Short name T366
Test name
Test status
Simulation time 120394465777 ps
CPU time 54.46 seconds
Started May 07 01:00:47 PM PDT 24
Finished May 07 01:01:42 PM PDT 24
Peak memory 200024 kb
Host smart-73b7ea24-39db-4064-9db9-ad3b5938ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083565526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1083565526
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.303221816
Short name T856
Test name
Test status
Simulation time 21313834128 ps
CPU time 52.58 seconds
Started May 07 01:00:52 PM PDT 24
Finished May 07 01:01:46 PM PDT 24
Peak memory 200400 kb
Host smart-07ea8109-c2fa-44e3-97a1-0e74ec921ee3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303221816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.303221816
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4199277911
Short name T681
Test name
Test status
Simulation time 196705720201 ps
CPU time 1793.84 seconds
Started May 07 01:00:53 PM PDT 24
Finished May 07 01:30:49 PM PDT 24
Peak memory 200376 kb
Host smart-7a533c07-4a6c-468f-9400-83e8443327f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199277911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4199277911
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2763165361
Short name T44
Test name
Test status
Simulation time 7586684292 ps
CPU time 6.19 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:01:03 PM PDT 24
Peak memory 200388 kb
Host smart-966ac410-a9be-44fa-b087-50172f43237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763165361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2763165361
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.557838194
Short name T1030
Test name
Test status
Simulation time 76835515728 ps
CPU time 125.4 seconds
Started May 07 01:00:59 PM PDT 24
Finished May 07 01:03:06 PM PDT 24
Peak memory 200588 kb
Host smart-9a367a43-eec4-41f1-a638-b905fc277e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557838194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.557838194
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.93892656
Short name T925
Test name
Test status
Simulation time 484258728 ps
CPU time 28.53 seconds
Started May 07 01:00:57 PM PDT 24
Finished May 07 01:01:27 PM PDT 24
Peak memory 200324 kb
Host smart-8a99bce0-31b8-40cd-8cc3-2b36f7043bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93892656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.93892656
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.481182935
Short name T946
Test name
Test status
Simulation time 5297202311 ps
CPU time 46.88 seconds
Started May 07 01:00:52 PM PDT 24
Finished May 07 01:01:40 PM PDT 24
Peak memory 199084 kb
Host smart-fa7ae395-bb2e-4e48-9c48-9ddb192b7ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481182935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.481182935
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.4155205189
Short name T171
Test name
Test status
Simulation time 50343967383 ps
CPU time 86.06 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:02:22 PM PDT 24
Peak memory 200336 kb
Host smart-9dbec2b0-22fd-46aa-91d7-8fc4c0b1841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155205189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.4155205189
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1215100419
Short name T341
Test name
Test status
Simulation time 39054794260 ps
CPU time 11.81 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:01:08 PM PDT 24
Peak memory 196060 kb
Host smart-1c7ff687-f59c-444f-a65e-7b1db0121e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215100419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1215100419
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1873199643
Short name T651
Test name
Test status
Simulation time 249638943 ps
CPU time 1.47 seconds
Started May 07 01:00:48 PM PDT 24
Finished May 07 01:00:51 PM PDT 24
Peak memory 199148 kb
Host smart-c279bdb0-3825-4725-98ff-8fb02f25d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873199643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1873199643
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3375621334
Short name T193
Test name
Test status
Simulation time 680148139012 ps
CPU time 1234.25 seconds
Started May 07 01:00:55 PM PDT 24
Finished May 07 01:21:31 PM PDT 24
Peak memory 200380 kb
Host smart-bfad5ceb-5d35-4f78-aed0-402597081cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375621334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3375621334
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.414853743
Short name T277
Test name
Test status
Simulation time 75326799289 ps
CPU time 478.27 seconds
Started May 07 01:00:51 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 228524 kb
Host smart-92d145ca-5505-4533-9f0a-73549dd5bdaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414853743 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.414853743
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2889218944
Short name T853
Test name
Test status
Simulation time 2024939895 ps
CPU time 2.64 seconds
Started May 07 01:00:53 PM PDT 24
Finished May 07 01:00:58 PM PDT 24
Peak memory 199340 kb
Host smart-f5802119-7ad7-4024-a6c3-a0309c81aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889218944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2889218944
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3214709196
Short name T878
Test name
Test status
Simulation time 25738473213 ps
CPU time 8.79 seconds
Started May 07 01:00:49 PM PDT 24
Finished May 07 01:00:59 PM PDT 24
Peak memory 200308 kb
Host smart-4be011cd-0d59-4538-9c77-fcb13e4a8e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214709196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3214709196
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2139834858
Short name T970
Test name
Test status
Simulation time 89902008582 ps
CPU time 60 seconds
Started May 07 01:05:05 PM PDT 24
Finished May 07 01:06:05 PM PDT 24
Peak memory 200396 kb
Host smart-4b6989fe-6b7b-4283-aab3-891418064335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139834858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2139834858
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3448666738
Short name T1137
Test name
Test status
Simulation time 60508272332 ps
CPU time 72.06 seconds
Started May 07 01:05:05 PM PDT 24
Finished May 07 01:06:18 PM PDT 24
Peak memory 200380 kb
Host smart-89166e95-1bc9-42df-8c3a-40bc851a702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448666738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3448666738
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1610577623
Short name T246
Test name
Test status
Simulation time 36258038432 ps
CPU time 34.22 seconds
Started May 07 01:05:08 PM PDT 24
Finished May 07 01:05:43 PM PDT 24
Peak memory 200340 kb
Host smart-67029629-f322-49a1-b955-0b6c35d132ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610577623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1610577623
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3269568463
Short name T873
Test name
Test status
Simulation time 89066742573 ps
CPU time 143.65 seconds
Started May 07 01:05:07 PM PDT 24
Finished May 07 01:07:31 PM PDT 24
Peak memory 200392 kb
Host smart-48dc8a58-6e47-4b59-9873-6e0251e7284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269568463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3269568463
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4224291985
Short name T210
Test name
Test status
Simulation time 62749888255 ps
CPU time 59.82 seconds
Started May 07 01:05:08 PM PDT 24
Finished May 07 01:06:09 PM PDT 24
Peak memory 200448 kb
Host smart-949a2fba-8676-40e0-97a2-8961d6b159d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224291985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4224291985
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.863722848
Short name T172
Test name
Test status
Simulation time 142642726432 ps
CPU time 96.13 seconds
Started May 07 01:05:06 PM PDT 24
Finished May 07 01:06:42 PM PDT 24
Peak memory 200004 kb
Host smart-1a5a0f67-d190-428e-ac73-5d8e425c1ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863722848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.863722848
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1491814345
Short name T557
Test name
Test status
Simulation time 175412409507 ps
CPU time 74.17 seconds
Started May 07 01:05:15 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 200236 kb
Host smart-d991e816-a908-4900-9364-37a72691bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491814345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1491814345
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2185129182
Short name T446
Test name
Test status
Simulation time 33766409448 ps
CPU time 28.55 seconds
Started May 07 01:05:13 PM PDT 24
Finished May 07 01:05:42 PM PDT 24
Peak memory 200432 kb
Host smart-ce62eb18-b455-45ae-8902-9f4821ef37ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185129182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2185129182
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3596800301
Short name T204
Test name
Test status
Simulation time 8256794093 ps
CPU time 7.57 seconds
Started May 07 01:05:14 PM PDT 24
Finished May 07 01:05:22 PM PDT 24
Peak memory 200452 kb
Host smart-0cf61adb-5d58-4e8c-9db8-c2cc9b7d28c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596800301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3596800301
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2496021465
Short name T889
Test name
Test status
Simulation time 62379361193 ps
CPU time 32.42 seconds
Started May 07 01:00:53 PM PDT 24
Finished May 07 01:01:26 PM PDT 24
Peak memory 200380 kb
Host smart-8cd27170-196c-4c9a-92dd-0c2a7d6c8433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496021465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2496021465
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1983441464
Short name T801
Test name
Test status
Simulation time 83853318913 ps
CPU time 65.68 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:02:02 PM PDT 24
Peak memory 200336 kb
Host smart-3f5ba4f2-a136-4c43-b5c9-2b72754cee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983441464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1983441464
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1188908207
Short name T502
Test name
Test status
Simulation time 31329340614 ps
CPU time 71.76 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:02:08 PM PDT 24
Peak memory 200272 kb
Host smart-343af5c8-0156-4574-9b78-30fddd447dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188908207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1188908207
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4287766043
Short name T1173
Test name
Test status
Simulation time 23815837680 ps
CPU time 20.47 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:01:17 PM PDT 24
Peak memory 199720 kb
Host smart-f8af366c-3efa-4e25-ba24-1b7546ac1405
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287766043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4287766043
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3843520114
Short name T1172
Test name
Test status
Simulation time 66569775947 ps
CPU time 115.34 seconds
Started May 07 01:00:53 PM PDT 24
Finished May 07 01:02:51 PM PDT 24
Peak memory 200452 kb
Host smart-7f18e5b4-7d95-44ce-967e-b810160d3382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843520114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3843520114
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4047897029
Short name T340
Test name
Test status
Simulation time 9074533791 ps
CPU time 13 seconds
Started May 07 01:00:59 PM PDT 24
Finished May 07 01:01:14 PM PDT 24
Peak memory 200464 kb
Host smart-35118178-0725-4b2a-b6a0-e10dcf9fb5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047897029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4047897029
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3633516935
Short name T702
Test name
Test status
Simulation time 104803210543 ps
CPU time 97.73 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:02:34 PM PDT 24
Peak memory 200328 kb
Host smart-1c9d420b-818d-4a3d-b7b2-b10c0f47b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633516935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3633516935
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2486045732
Short name T897
Test name
Test status
Simulation time 27254054316 ps
CPU time 107.57 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:02:43 PM PDT 24
Peak memory 200388 kb
Host smart-64df2987-152c-4883-9288-0d606a2d1f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486045732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2486045732
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2114865459
Short name T976
Test name
Test status
Simulation time 4822063260 ps
CPU time 10.45 seconds
Started May 07 01:00:58 PM PDT 24
Finished May 07 01:01:10 PM PDT 24
Peak memory 198572 kb
Host smart-2a920ca3-535c-4852-9146-105da9950a43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114865459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2114865459
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2589265278
Short name T294
Test name
Test status
Simulation time 29995751677 ps
CPU time 50.98 seconds
Started May 07 01:00:53 PM PDT 24
Finished May 07 01:01:46 PM PDT 24
Peak memory 200400 kb
Host smart-bd9673c6-573f-4750-80c8-a36179195d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589265278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2589265278
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4219012210
Short name T814
Test name
Test status
Simulation time 38865279386 ps
CPU time 31.01 seconds
Started May 07 01:00:56 PM PDT 24
Finished May 07 01:01:29 PM PDT 24
Peak memory 196144 kb
Host smart-f2ff153e-d16d-426f-85fc-763a171d0704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219012210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4219012210
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3943166851
Short name T285
Test name
Test status
Simulation time 6078469554 ps
CPU time 21.98 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:01:18 PM PDT 24
Peak memory 200180 kb
Host smart-006efb9d-91b2-41d3-8cb2-55622e628171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943166851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3943166851
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2970136619
Short name T727
Test name
Test status
Simulation time 320132510576 ps
CPU time 426.31 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:08:09 PM PDT 24
Peak memory 200396 kb
Host smart-e79eab6e-a18b-4ced-8aa2-abaadc50c514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970136619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2970136619
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2462629835
Short name T581
Test name
Test status
Simulation time 241074387516 ps
CPU time 400.76 seconds
Started May 07 01:01:00 PM PDT 24
Finished May 07 01:07:42 PM PDT 24
Peak memory 216800 kb
Host smart-52f1532d-b415-4e0f-96e0-2f5d750c77ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462629835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2462629835
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2366728282
Short name T1079
Test name
Test status
Simulation time 2849967830 ps
CPU time 1.77 seconds
Started May 07 01:00:52 PM PDT 24
Finished May 07 01:00:55 PM PDT 24
Peak memory 200372 kb
Host smart-062dfcfa-e475-4b2a-8af1-198f464ab0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366728282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2366728282
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3689191560
Short name T115
Test name
Test status
Simulation time 28063389687 ps
CPU time 90.4 seconds
Started May 07 01:00:54 PM PDT 24
Finished May 07 01:02:26 PM PDT 24
Peak memory 200448 kb
Host smart-32b2a5f3-58fc-46ce-aa39-219559a55f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689191560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3689191560
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1056638694
Short name T813
Test name
Test status
Simulation time 24834659897 ps
CPU time 42.45 seconds
Started May 07 01:05:14 PM PDT 24
Finished May 07 01:05:57 PM PDT 24
Peak memory 200424 kb
Host smart-4912e113-6339-4d2a-a6a3-851f661337e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056638694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1056638694
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3521815239
Short name T1109
Test name
Test status
Simulation time 19754307300 ps
CPU time 34.28 seconds
Started May 07 01:05:13 PM PDT 24
Finished May 07 01:05:48 PM PDT 24
Peak memory 200408 kb
Host smart-f833a807-3b5f-4bdb-b906-0608792e4369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521815239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3521815239
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.880102061
Short name T539
Test name
Test status
Simulation time 64476034555 ps
CPU time 26.69 seconds
Started May 07 01:05:12 PM PDT 24
Finished May 07 01:05:39 PM PDT 24
Peak memory 200440 kb
Host smart-b0b0d55e-0b7d-4a35-a58d-ac4032b17904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880102061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.880102061
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.685406440
Short name T543
Test name
Test status
Simulation time 102051190400 ps
CPU time 103.03 seconds
Started May 07 01:05:16 PM PDT 24
Finished May 07 01:07:00 PM PDT 24
Peak memory 200400 kb
Host smart-40eef87b-560d-4448-b3bc-ec56699844aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685406440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.685406440
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.329427884
Short name T314
Test name
Test status
Simulation time 122352716113 ps
CPU time 193.76 seconds
Started May 07 01:05:15 PM PDT 24
Finished May 07 01:08:30 PM PDT 24
Peak memory 200392 kb
Host smart-8c24a802-d61d-41be-8891-27615ce6624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329427884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.329427884
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2465675451
Short name T847
Test name
Test status
Simulation time 19755818500 ps
CPU time 35.06 seconds
Started May 07 01:05:13 PM PDT 24
Finished May 07 01:05:49 PM PDT 24
Peak memory 200460 kb
Host smart-58fd83f6-e10c-4b8e-866e-71e28b3229ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465675451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2465675451
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2759835060
Short name T1077
Test name
Test status
Simulation time 29255712839 ps
CPU time 46.72 seconds
Started May 07 01:05:16 PM PDT 24
Finished May 07 01:06:03 PM PDT 24
Peak memory 200376 kb
Host smart-3f154df4-ebe8-4a46-a070-6406e9409122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759835060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2759835060
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.543747148
Short name T146
Test name
Test status
Simulation time 36343102228 ps
CPU time 56.12 seconds
Started May 07 01:05:16 PM PDT 24
Finished May 07 01:06:13 PM PDT 24
Peak memory 200456 kb
Host smart-6fda2f22-e35b-4e8e-b5d8-0183c6322f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543747148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.543747148
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2198325880
Short name T871
Test name
Test status
Simulation time 30452890 ps
CPU time 0.6 seconds
Started May 07 01:01:00 PM PDT 24
Finished May 07 01:01:02 PM PDT 24
Peak memory 195160 kb
Host smart-42d6306e-73b6-40cf-89af-52bdd880fcae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198325880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2198325880
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1154465067
Short name T939
Test name
Test status
Simulation time 61719772683 ps
CPU time 102.45 seconds
Started May 07 01:01:02 PM PDT 24
Finished May 07 01:02:45 PM PDT 24
Peak memory 200388 kb
Host smart-69a904e5-e90e-420b-ba88-fd92d972d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154465067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1154465067
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3765682766
Short name T473
Test name
Test status
Simulation time 16581627925 ps
CPU time 11.58 seconds
Started May 07 01:00:59 PM PDT 24
Finished May 07 01:01:12 PM PDT 24
Peak memory 200244 kb
Host smart-6c61f8b1-af1c-40cb-8df7-a557620573f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765682766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3765682766
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.2092843798
Short name T942
Test name
Test status
Simulation time 27335791119 ps
CPU time 43.11 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:01:46 PM PDT 24
Peak memory 199624 kb
Host smart-a7f8691c-aa7d-4c57-82c2-622ef1c733b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092843798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2092843798
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.4259138268
Short name T349
Test name
Test status
Simulation time 158570883654 ps
CPU time 205.56 seconds
Started May 07 01:00:59 PM PDT 24
Finished May 07 01:04:26 PM PDT 24
Peak memory 200392 kb
Host smart-ad5845d1-1906-4e78-b14e-5b4862656771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259138268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4259138268
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1890786797
Short name T1142
Test name
Test status
Simulation time 12226529013 ps
CPU time 17.81 seconds
Started May 07 01:01:00 PM PDT 24
Finished May 07 01:01:19 PM PDT 24
Peak memory 199960 kb
Host smart-81820140-9f8a-4f85-8eb4-1d931b5b78aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890786797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1890786797
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1690858387
Short name T265
Test name
Test status
Simulation time 99860677923 ps
CPU time 42.52 seconds
Started May 07 01:00:59 PM PDT 24
Finished May 07 01:01:43 PM PDT 24
Peak memory 199752 kb
Host smart-3667c435-e6f4-4ead-b959-0bea8e2e8dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690858387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1690858387
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1302107888
Short name T283
Test name
Test status
Simulation time 18027203990 ps
CPU time 414.02 seconds
Started May 07 01:01:02 PM PDT 24
Finished May 07 01:07:57 PM PDT 24
Peak memory 200436 kb
Host smart-55b27dea-3e79-4d9d-9d09-d9e7b77c839e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302107888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1302107888
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.403558189
Short name T636
Test name
Test status
Simulation time 4615147781 ps
CPU time 35.77 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:01:38 PM PDT 24
Peak memory 198584 kb
Host smart-8ddd4bbb-b136-457f-b759-f313e0975dfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403558189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.403558189
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2663016296
Short name T576
Test name
Test status
Simulation time 202632698395 ps
CPU time 29.59 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:01:32 PM PDT 24
Peak memory 200348 kb
Host smart-3379a5d0-6827-4206-b278-9838004da1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663016296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2663016296
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.138060573
Short name T408
Test name
Test status
Simulation time 2051790911 ps
CPU time 3.61 seconds
Started May 07 01:00:58 PM PDT 24
Finished May 07 01:01:03 PM PDT 24
Peak memory 196100 kb
Host smart-7f98fabe-ded7-4d16-a8b7-fc5ab9a7b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138060573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.138060573
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3140838743
Short name T1159
Test name
Test status
Simulation time 5368786596 ps
CPU time 13.68 seconds
Started May 07 01:01:00 PM PDT 24
Finished May 07 01:01:15 PM PDT 24
Peak memory 200304 kb
Host smart-f5fd0197-a6dc-419c-b002-7e35848374c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140838743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3140838743
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.4252339406
Short name T1116
Test name
Test status
Simulation time 237483558779 ps
CPU time 443.49 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:08:26 PM PDT 24
Peak memory 200460 kb
Host smart-b059d6cf-e045-4aff-9c98-528edea2371c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252339406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4252339406
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3798557061
Short name T58
Test name
Test status
Simulation time 105299740817 ps
CPU time 633.25 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:11:36 PM PDT 24
Peak memory 225192 kb
Host smart-20f772f0-5d5c-40b0-a174-ffb3a2675848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798557061 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3798557061
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4260679575
Short name T504
Test name
Test status
Simulation time 8598196144 ps
CPU time 15.52 seconds
Started May 07 01:01:01 PM PDT 24
Finished May 07 01:01:17 PM PDT 24
Peak memory 200320 kb
Host smart-9479bad4-7a8b-424d-a304-1f0943a8a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260679575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4260679575
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1401301317
Short name T288
Test name
Test status
Simulation time 36536826180 ps
CPU time 32.93 seconds
Started May 07 01:01:00 PM PDT 24
Finished May 07 01:01:34 PM PDT 24
Peak memory 200224 kb
Host smart-476314b2-d709-4e7b-98ae-e7d45915f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401301317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1401301317
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.716175942
Short name T920
Test name
Test status
Simulation time 29992278107 ps
CPU time 45.65 seconds
Started May 07 01:05:13 PM PDT 24
Finished May 07 01:06:00 PM PDT 24
Peak memory 200436 kb
Host smart-b5220ed3-96ce-404e-99d8-2648a134fa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716175942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.716175942
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3472852642
Short name T152
Test name
Test status
Simulation time 133697723430 ps
CPU time 56.26 seconds
Started May 07 01:05:13 PM PDT 24
Finished May 07 01:06:10 PM PDT 24
Peak memory 200416 kb
Host smart-a7554760-1a6a-443c-9e4e-2eabfe6e565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472852642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3472852642
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1013363733
Short name T401
Test name
Test status
Simulation time 87299630627 ps
CPU time 39.83 seconds
Started May 07 01:05:14 PM PDT 24
Finished May 07 01:05:55 PM PDT 24
Peak memory 200356 kb
Host smart-f808c8c5-95ec-4c85-9a28-5151a3d2155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013363733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1013363733
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3742027974
Short name T323
Test name
Test status
Simulation time 17944890147 ps
CPU time 14.99 seconds
Started May 07 01:05:13 PM PDT 24
Finished May 07 01:05:29 PM PDT 24
Peak memory 200220 kb
Host smart-d641d404-4779-4996-9162-b16d28bc0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742027974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3742027974
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.142417371
Short name T997
Test name
Test status
Simulation time 241042687111 ps
CPU time 244.19 seconds
Started May 07 01:05:15 PM PDT 24
Finished May 07 01:09:20 PM PDT 24
Peak memory 200404 kb
Host smart-923f8575-f103-499d-baa6-cda9c23e0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142417371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.142417371
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2504211858
Short name T195
Test name
Test status
Simulation time 102488421801 ps
CPU time 40.73 seconds
Started May 07 01:05:14 PM PDT 24
Finished May 07 01:05:56 PM PDT 24
Peak memory 200352 kb
Host smart-e462d124-b44c-479f-acbe-06e9db5b08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504211858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2504211858
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3328995733
Short name T981
Test name
Test status
Simulation time 86524920810 ps
CPU time 125.86 seconds
Started May 07 01:05:16 PM PDT 24
Finished May 07 01:07:23 PM PDT 24
Peak memory 200380 kb
Host smart-c347d6a6-9254-4767-9ce2-66297c93eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328995733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3328995733
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2102584467
Short name T1143
Test name
Test status
Simulation time 110927308246 ps
CPU time 85.08 seconds
Started May 07 01:05:22 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 200420 kb
Host smart-eda3afe5-d2c1-43b0-b101-a930f97e5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102584467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2102584467
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3630219241
Short name T466
Test name
Test status
Simulation time 25275748 ps
CPU time 0.55 seconds
Started May 07 01:01:06 PM PDT 24
Finished May 07 01:01:07 PM PDT 24
Peak memory 195780 kb
Host smart-8d7332ae-7279-4fb2-9b41-04891eb939b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630219241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3630219241
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3749815759
Short name T393
Test name
Test status
Simulation time 57843622698 ps
CPU time 20.63 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:01:29 PM PDT 24
Peak memory 200296 kb
Host smart-ac46b566-b418-40c8-b82e-a234b03cb80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749815759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3749815759
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1215531204
Short name T264
Test name
Test status
Simulation time 57175200468 ps
CPU time 54.06 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:02:02 PM PDT 24
Peak memory 200432 kb
Host smart-a6403a5d-8748-4ee4-beae-8e9802ac6b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215531204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1215531204
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2400908905
Short name T2
Test name
Test status
Simulation time 77257905868 ps
CPU time 50.01 seconds
Started May 07 01:01:06 PM PDT 24
Finished May 07 01:01:57 PM PDT 24
Peak memory 200456 kb
Host smart-d06feea2-2132-456f-895f-e252646acf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400908905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2400908905
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1221037560
Short name T616
Test name
Test status
Simulation time 5629016236 ps
CPU time 3.33 seconds
Started May 07 01:01:05 PM PDT 24
Finished May 07 01:01:09 PM PDT 24
Peak memory 200376 kb
Host smart-a022ff0d-2a71-442d-9b92-2577775f5b0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221037560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1221037560
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.165145751
Short name T725
Test name
Test status
Simulation time 130218414046 ps
CPU time 347.06 seconds
Started May 07 01:01:11 PM PDT 24
Finished May 07 01:06:58 PM PDT 24
Peak memory 200444 kb
Host smart-9fea0a95-5583-4087-835a-50d3f37bcda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165145751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.165145751
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2067018562
Short name T22
Test name
Test status
Simulation time 2438265724 ps
CPU time 5.04 seconds
Started May 07 01:01:10 PM PDT 24
Finished May 07 01:01:16 PM PDT 24
Peak memory 197892 kb
Host smart-040ea865-b3c4-4f14-b25c-5b43bbbf53d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067018562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2067018562
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1159290733
Short name T1150
Test name
Test status
Simulation time 66411527250 ps
CPU time 25.32 seconds
Started May 07 01:01:09 PM PDT 24
Finished May 07 01:01:35 PM PDT 24
Peak memory 200580 kb
Host smart-49c9fc1c-9048-4267-8abf-ec8c83dd23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159290733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1159290733
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2053795085
Short name T560
Test name
Test status
Simulation time 16676765168 ps
CPU time 988.57 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:17:36 PM PDT 24
Peak memory 200420 kb
Host smart-9c5d1f7a-9616-4ae1-936b-fcf2aff5829e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053795085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2053795085
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4987908
Short name T517
Test name
Test status
Simulation time 3816599146 ps
CPU time 8.39 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:01:17 PM PDT 24
Peak memory 199444 kb
Host smart-0e6c3e0a-bc2f-499a-bba2-67e132f49025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4987908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4987908
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3727125239
Short name T618
Test name
Test status
Simulation time 26696957282 ps
CPU time 48.56 seconds
Started May 07 01:01:06 PM PDT 24
Finished May 07 01:01:55 PM PDT 24
Peak memory 200304 kb
Host smart-e4f3d003-a804-4719-b156-c934b8597957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727125239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3727125239
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1687498992
Short name T1138
Test name
Test status
Simulation time 3067095448 ps
CPU time 5.24 seconds
Started May 07 01:01:08 PM PDT 24
Finished May 07 01:01:14 PM PDT 24
Peak memory 196436 kb
Host smart-1bcd404f-f4e3-47a9-9e58-ee8601c001bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687498992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1687498992
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2208255168
Short name T865
Test name
Test status
Simulation time 300012285 ps
CPU time 1.42 seconds
Started May 07 01:01:06 PM PDT 24
Finished May 07 01:01:09 PM PDT 24
Peak memory 198688 kb
Host smart-3fc8f4d6-cebf-4ab8-8f2b-97f0d584cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208255168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2208255168
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.4066295889
Short name T1094
Test name
Test status
Simulation time 286039628837 ps
CPU time 711.99 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:13:01 PM PDT 24
Peak memory 200600 kb
Host smart-85f54c6e-38f0-4024-8830-d18861cec63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066295889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4066295889
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.893430641
Short name T1152
Test name
Test status
Simulation time 82036192753 ps
CPU time 499.94 seconds
Started May 07 01:01:06 PM PDT 24
Finished May 07 01:09:26 PM PDT 24
Peak memory 216508 kb
Host smart-97f003d2-7cd8-4ce7-b5f8-7bcb13273945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893430641 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.893430641
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1816538026
Short name T590
Test name
Test status
Simulation time 7095953249 ps
CPU time 22.98 seconds
Started May 07 01:01:08 PM PDT 24
Finished May 07 01:01:32 PM PDT 24
Peak memory 200384 kb
Host smart-a14b9d0a-d43d-4665-8ada-51a96513a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816538026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1816538026
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2952786694
Short name T979
Test name
Test status
Simulation time 113445565444 ps
CPU time 177.77 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:04:05 PM PDT 24
Peak memory 200408 kb
Host smart-a8e471d5-8951-4b7a-b7cb-03fbc1f5bb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952786694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2952786694
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.4012446869
Short name T334
Test name
Test status
Simulation time 51349619458 ps
CPU time 82.57 seconds
Started May 07 01:05:23 PM PDT 24
Finished May 07 01:06:47 PM PDT 24
Peak memory 200452 kb
Host smart-2ceb4f0a-030b-4cea-9a21-93cb09eb6518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012446869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4012446869
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3528277683
Short name T884
Test name
Test status
Simulation time 43354761580 ps
CPU time 46.86 seconds
Started May 07 01:05:25 PM PDT 24
Finished May 07 01:06:13 PM PDT 24
Peak memory 200412 kb
Host smart-d7c67ee8-14e3-4b0a-a3f1-41e92ff3400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528277683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3528277683
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4268790330
Short name T796
Test name
Test status
Simulation time 11788306611 ps
CPU time 10.18 seconds
Started May 07 01:05:22 PM PDT 24
Finished May 07 01:05:33 PM PDT 24
Peak memory 200104 kb
Host smart-955ee4b4-a4b6-4deb-b785-79efd8318051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268790330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4268790330
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3011331537
Short name T1144
Test name
Test status
Simulation time 13726847342 ps
CPU time 21.75 seconds
Started May 07 01:05:20 PM PDT 24
Finished May 07 01:05:43 PM PDT 24
Peak memory 200436 kb
Host smart-a04007e3-dcd9-4c06-8ae9-a0cf6de6c07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011331537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3011331537
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4057172194
Short name T1101
Test name
Test status
Simulation time 178155105780 ps
CPU time 30.03 seconds
Started May 07 01:05:22 PM PDT 24
Finished May 07 01:05:53 PM PDT 24
Peak memory 200320 kb
Host smart-842b62ea-10cf-40c0-9d5e-4a324b9fd6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057172194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4057172194
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.4257229736
Short name T164
Test name
Test status
Simulation time 18858713225 ps
CPU time 29.75 seconds
Started May 07 01:05:20 PM PDT 24
Finished May 07 01:05:51 PM PDT 24
Peak memory 199872 kb
Host smart-f5e4e962-1308-4df1-9509-de762c7702b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257229736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4257229736
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2659637506
Short name T703
Test name
Test status
Simulation time 93313261108 ps
CPU time 39.34 seconds
Started May 07 01:05:21 PM PDT 24
Finished May 07 01:06:02 PM PDT 24
Peak memory 200384 kb
Host smart-c9e44215-db8f-4807-8995-96ac8165def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659637506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2659637506
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3396522072
Short name T1059
Test name
Test status
Simulation time 13871560625 ps
CPU time 24 seconds
Started May 07 01:05:22 PM PDT 24
Finished May 07 01:05:47 PM PDT 24
Peak memory 200352 kb
Host smart-d5eccef3-c334-4de3-8d29-c7a5a92f1cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396522072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3396522072
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1764726633
Short name T752
Test name
Test status
Simulation time 32197434 ps
CPU time 0.54 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:01:18 PM PDT 24
Peak memory 194752 kb
Host smart-a45fe66c-f3ec-4ed1-91f1-def0e5fe3f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764726633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1764726633
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2329943241
Short name T1056
Test name
Test status
Simulation time 30535440410 ps
CPU time 31.34 seconds
Started May 07 01:01:08 PM PDT 24
Finished May 07 01:01:40 PM PDT 24
Peak memory 200460 kb
Host smart-8dc711b1-e396-4df9-bfd2-b61d14e6a8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329943241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2329943241
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1615302991
Short name T1089
Test name
Test status
Simulation time 83307157236 ps
CPU time 152.14 seconds
Started May 07 01:01:05 PM PDT 24
Finished May 07 01:03:38 PM PDT 24
Peak memory 200316 kb
Host smart-5f8545dc-7206-491f-988e-db20b08d829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615302991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1615302991
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2785731517
Short name T218
Test name
Test status
Simulation time 184196210106 ps
CPU time 67.53 seconds
Started May 07 01:01:10 PM PDT 24
Finished May 07 01:02:18 PM PDT 24
Peak memory 200372 kb
Host smart-5512cd16-07d3-4d28-8bdc-79500e89382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785731517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2785731517
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2191966141
Short name T275
Test name
Test status
Simulation time 47001558224 ps
CPU time 19.52 seconds
Started May 07 01:01:08 PM PDT 24
Finished May 07 01:01:29 PM PDT 24
Peak memory 200408 kb
Host smart-3262f9db-0526-4d30-a98f-b735c0b1adac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191966141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2191966141
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2057266540
Short name T903
Test name
Test status
Simulation time 122955581112 ps
CPU time 309.91 seconds
Started May 07 01:01:18 PM PDT 24
Finished May 07 01:06:28 PM PDT 24
Peak memory 200448 kb
Host smart-099d58b3-6e2b-4b23-8096-03569ec80ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057266540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2057266540
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1095487535
Short name T704
Test name
Test status
Simulation time 7495189553 ps
CPU time 19.93 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:01:36 PM PDT 24
Peak memory 199940 kb
Host smart-0d8afdc6-d0c6-462e-b23e-08c833de1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095487535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1095487535
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3660364714
Short name T755
Test name
Test status
Simulation time 70455278341 ps
CPU time 30.31 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:01:47 PM PDT 24
Peak memory 196272 kb
Host smart-174384cd-6dff-49a8-9e49-6eb78f9a9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660364714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3660364714
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3452287516
Short name T261
Test name
Test status
Simulation time 16714588904 ps
CPU time 571.35 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:10:48 PM PDT 24
Peak memory 200320 kb
Host smart-44c8d7cd-1110-4815-a544-d083af9b8cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452287516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3452287516
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2257595947
Short name T614
Test name
Test status
Simulation time 1603294254 ps
CPU time 4.15 seconds
Started May 07 01:01:10 PM PDT 24
Finished May 07 01:01:15 PM PDT 24
Peak memory 198280 kb
Host smart-bd4ad174-55e6-4c4b-9f8a-fbd734a32d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257595947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2257595947
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3504999118
Short name T819
Test name
Test status
Simulation time 61181929437 ps
CPU time 33.03 seconds
Started May 07 01:01:14 PM PDT 24
Finished May 07 01:01:48 PM PDT 24
Peak memory 200408 kb
Host smart-27bf1650-c542-4b92-9022-59c9922d701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504999118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3504999118
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4178070337
Short name T357
Test name
Test status
Simulation time 516448654 ps
CPU time 1.48 seconds
Started May 07 01:01:20 PM PDT 24
Finished May 07 01:01:22 PM PDT 24
Peak memory 195792 kb
Host smart-e300269d-8493-467a-925d-3d619ade6f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178070337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4178070337
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.808281620
Short name T854
Test name
Test status
Simulation time 856268921 ps
CPU time 3.04 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:01:11 PM PDT 24
Peak memory 199740 kb
Host smart-8ffef213-e89e-49b8-a4de-2fa2509401ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808281620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.808281620
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2823673291
Short name T1123
Test name
Test status
Simulation time 211156369030 ps
CPU time 370.33 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:07:27 PM PDT 24
Peak memory 200384 kb
Host smart-7671d83e-628a-47a1-8954-86e3894d8448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823673291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2823673291
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3678506601
Short name T1013
Test name
Test status
Simulation time 1134238061 ps
CPU time 2.05 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:01:19 PM PDT 24
Peak memory 198820 kb
Host smart-5d1b1537-ab2d-47b6-ab1b-1b656c3af6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678506601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3678506601
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2964158772
Short name T313
Test name
Test status
Simulation time 18777629126 ps
CPU time 32.73 seconds
Started May 07 01:01:07 PM PDT 24
Finished May 07 01:01:40 PM PDT 24
Peak memory 200384 kb
Host smart-16b53203-a3ef-4574-887f-42b2a6953533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964158772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2964158772
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2938296758
Short name T708
Test name
Test status
Simulation time 54949942136 ps
CPU time 15.17 seconds
Started May 07 01:05:21 PM PDT 24
Finished May 07 01:05:37 PM PDT 24
Peak memory 200324 kb
Host smart-aa3224f3-a659-42d4-8415-e9520e0c546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938296758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2938296758
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1643391364
Short name T456
Test name
Test status
Simulation time 62434348228 ps
CPU time 25.56 seconds
Started May 07 01:05:20 PM PDT 24
Finished May 07 01:05:47 PM PDT 24
Peak memory 200360 kb
Host smart-b66c0a4b-0afa-4ac1-bc26-d4382105d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643391364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1643391364
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.4240199363
Short name T270
Test name
Test status
Simulation time 8016130317 ps
CPU time 15.06 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:05:47 PM PDT 24
Peak memory 200344 kb
Host smart-44e42849-bfaf-4dbb-938d-38328164bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240199363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4240199363
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3753594509
Short name T969
Test name
Test status
Simulation time 14752725792 ps
CPU time 28.44 seconds
Started May 07 01:05:30 PM PDT 24
Finished May 07 01:06:00 PM PDT 24
Peak memory 200364 kb
Host smart-56d3c08b-d845-4824-9a92-b50d6dc0eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753594509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3753594509
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2699637660
Short name T336
Test name
Test status
Simulation time 57719877474 ps
CPU time 27.37 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:06:00 PM PDT 24
Peak memory 200464 kb
Host smart-2ba9e849-759e-4af8-80d6-b115926808dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699637660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2699637660
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2372966971
Short name T754
Test name
Test status
Simulation time 70860076406 ps
CPU time 50.27 seconds
Started May 07 01:05:30 PM PDT 24
Finished May 07 01:06:22 PM PDT 24
Peak memory 200440 kb
Host smart-be28f807-f7b0-4714-86a6-98ffb76c6f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372966971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2372966971
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4138510670
Short name T827
Test name
Test status
Simulation time 283317677509 ps
CPU time 81.91 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:06:54 PM PDT 24
Peak memory 200464 kb
Host smart-4e4c4e08-580c-4c51-9752-ba16b3e976eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138510670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4138510670
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2206307630
Short name T843
Test name
Test status
Simulation time 43743036951 ps
CPU time 128.77 seconds
Started May 07 01:05:30 PM PDT 24
Finished May 07 01:07:41 PM PDT 24
Peak memory 200460 kb
Host smart-b0b84e5b-1242-4ada-baaf-4fdb88e6d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206307630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2206307630
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2680643614
Short name T968
Test name
Test status
Simulation time 40127580 ps
CPU time 0.58 seconds
Started May 07 01:01:14 PM PDT 24
Finished May 07 01:01:16 PM PDT 24
Peak memory 195436 kb
Host smart-a519b35f-7674-4b83-8348-8ad0e2448a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680643614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2680643614
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.766661174
Short name T298
Test name
Test status
Simulation time 236108931698 ps
CPU time 732.17 seconds
Started May 07 01:01:17 PM PDT 24
Finished May 07 01:13:30 PM PDT 24
Peak memory 200364 kb
Host smart-612295b8-a2a0-4352-95d0-fbddf5de7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766661174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.766661174
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1074530890
Short name T866
Test name
Test status
Simulation time 68202067260 ps
CPU time 128.02 seconds
Started May 07 01:01:14 PM PDT 24
Finished May 07 01:03:23 PM PDT 24
Peak memory 200272 kb
Host smart-1fb67824-15b6-4d6c-9853-7cace1da9d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074530890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1074530890
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.641538725
Short name T1124
Test name
Test status
Simulation time 27682539676 ps
CPU time 53.93 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:02:10 PM PDT 24
Peak memory 200392 kb
Host smart-65e76507-cd70-4c53-abf2-f3c14264a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641538725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.641538725
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1690503280
Short name T317
Test name
Test status
Simulation time 180384627767 ps
CPU time 96.24 seconds
Started May 07 01:01:17 PM PDT 24
Finished May 07 01:02:54 PM PDT 24
Peak memory 200364 kb
Host smart-50fae196-b56c-4b8c-8563-fe5fb9d4163f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690503280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1690503280
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3997935833
Short name T1036
Test name
Test status
Simulation time 277069184727 ps
CPU time 288.97 seconds
Started May 07 01:01:17 PM PDT 24
Finished May 07 01:06:07 PM PDT 24
Peak memory 200416 kb
Host smart-f90c1945-43f2-453e-8fa1-13064ec1ee7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997935833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3997935833
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.519474424
Short name T1020
Test name
Test status
Simulation time 10200548093 ps
CPU time 12.3 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:01:28 PM PDT 24
Peak memory 200312 kb
Host smart-98662099-b7ed-4e35-bbf0-8bd07989130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519474424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.519474424
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3826020013
Short name T599
Test name
Test status
Simulation time 18275303603 ps
CPU time 33.56 seconds
Started May 07 01:01:17 PM PDT 24
Finished May 07 01:01:52 PM PDT 24
Peak memory 200600 kb
Host smart-5667f2ba-b267-49c5-9cfb-a5ee11595569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826020013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3826020013
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2131633970
Short name T768
Test name
Test status
Simulation time 26869855013 ps
CPU time 186.82 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:04:24 PM PDT 24
Peak memory 200472 kb
Host smart-af36ff6b-4199-4ee2-ba7a-c6778ce4432e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131633970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2131633970
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3524412457
Short name T574
Test name
Test status
Simulation time 4755052249 ps
CPU time 40.35 seconds
Started May 07 01:01:14 PM PDT 24
Finished May 07 01:01:55 PM PDT 24
Peak memory 198664 kb
Host smart-03b5d507-8893-4e6f-aec5-4b4939b9f358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524412457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3524412457
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1042499097
Short name T17
Test name
Test status
Simulation time 21382902603 ps
CPU time 19.21 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:01:35 PM PDT 24
Peak memory 200440 kb
Host smart-fff2bfa5-4d8b-4be4-8529-036b9a46ee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042499097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1042499097
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3290014248
Short name T497
Test name
Test status
Simulation time 47066202024 ps
CPU time 13.17 seconds
Started May 07 01:01:17 PM PDT 24
Finished May 07 01:01:31 PM PDT 24
Peak memory 196432 kb
Host smart-b81eec54-ebd2-475b-8263-cce66631417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290014248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3290014248
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2768944066
Short name T287
Test name
Test status
Simulation time 11061071149 ps
CPU time 29 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:01:45 PM PDT 24
Peak memory 200336 kb
Host smart-d0bbccfd-5d09-4a0d-8cf1-23837fb0b919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768944066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2768944066
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.899710458
Short name T1029
Test name
Test status
Simulation time 113907925135 ps
CPU time 101.44 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:02:57 PM PDT 24
Peak memory 200448 kb
Host smart-00614640-0405-4af1-9b16-50009d5bfe26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899710458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.899710458
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4170343640
Short name T190
Test name
Test status
Simulation time 117163951411 ps
CPU time 718.35 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:13:16 PM PDT 24
Peak memory 216856 kb
Host smart-341b4ad3-76fc-4155-92d7-edfc2628e77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170343640 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4170343640
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2786775024
Short name T545
Test name
Test status
Simulation time 1016076947 ps
CPU time 2.03 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:01:19 PM PDT 24
Peak memory 199132 kb
Host smart-27babf9f-0da7-4fd4-b2d2-7b3072d23030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786775024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2786775024
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.747505805
Short name T11
Test name
Test status
Simulation time 124745314979 ps
CPU time 225.48 seconds
Started May 07 01:01:15 PM PDT 24
Finished May 07 01:05:02 PM PDT 24
Peak memory 200392 kb
Host smart-16ac9aaa-0e94-479c-9a31-882af1d6ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747505805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.747505805
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3502428478
Short name T935
Test name
Test status
Simulation time 144625020638 ps
CPU time 25.54 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:05:58 PM PDT 24
Peak memory 200180 kb
Host smart-24a0fe2d-e147-4cc8-8887-9622eada0334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502428478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3502428478
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2276772601
Short name T710
Test name
Test status
Simulation time 11078603112 ps
CPU time 19.95 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:05:52 PM PDT 24
Peak memory 200184 kb
Host smart-02ddec8e-740e-4845-992e-408ea8be7dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276772601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2276772601
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1343851535
Short name T321
Test name
Test status
Simulation time 120927078111 ps
CPU time 140.73 seconds
Started May 07 01:05:29 PM PDT 24
Finished May 07 01:07:50 PM PDT 24
Peak memory 200400 kb
Host smart-7fea9b93-a673-4018-99aa-b04ce8735940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343851535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1343851535
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1629542704
Short name T487
Test name
Test status
Simulation time 84095721930 ps
CPU time 145.76 seconds
Started May 07 01:05:30 PM PDT 24
Finished May 07 01:07:57 PM PDT 24
Peak memory 200092 kb
Host smart-821d801f-683a-49f7-bf5c-c15dbb928e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629542704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1629542704
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2270679208
Short name T886
Test name
Test status
Simulation time 43922279672 ps
CPU time 89.56 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:07:02 PM PDT 24
Peak memory 200440 kb
Host smart-37708955-cedf-49ca-bb34-ce6497e38b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270679208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2270679208
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2926874386
Short name T673
Test name
Test status
Simulation time 158500917987 ps
CPU time 108.16 seconds
Started May 07 01:05:30 PM PDT 24
Finished May 07 01:07:20 PM PDT 24
Peak memory 200192 kb
Host smart-367f07e3-9f48-477d-ae05-14728ed5d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926874386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2926874386
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2478710195
Short name T527
Test name
Test status
Simulation time 50083123137 ps
CPU time 75.57 seconds
Started May 07 01:05:31 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 200456 kb
Host smart-e4ff3f6d-266e-48ea-ba3e-c0f0e1664108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478710195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2478710195
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.202386100
Short name T8
Test name
Test status
Simulation time 99521129661 ps
CPU time 75.44 seconds
Started May 07 01:05:37 PM PDT 24
Finished May 07 01:06:54 PM PDT 24
Peak memory 200404 kb
Host smart-52f1b23d-b349-47e9-b053-f261cce2bca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202386100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.202386100
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.27674135
Short name T425
Test name
Test status
Simulation time 16852723893 ps
CPU time 35.94 seconds
Started May 07 01:05:38 PM PDT 24
Finished May 07 01:06:15 PM PDT 24
Peak memory 200392 kb
Host smart-d707f6b5-de1c-4529-8784-367981ced2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27674135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.27674135
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2157893702
Short name T407
Test name
Test status
Simulation time 33013361 ps
CPU time 0.53 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:00:12 PM PDT 24
Peak memory 195272 kb
Host smart-9fa6b7b7-79ca-4fdb-bf88-118462f4f097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157893702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2157893702
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1663492045
Short name T799
Test name
Test status
Simulation time 64677083916 ps
CPU time 16.84 seconds
Started May 07 01:00:08 PM PDT 24
Finished May 07 01:00:26 PM PDT 24
Peak memory 200388 kb
Host smart-36af34f1-7bf2-4228-83cc-feb2d77446a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663492045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1663492045
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.479911243
Short name T1157
Test name
Test status
Simulation time 138074791957 ps
CPU time 29.61 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:37 PM PDT 24
Peak memory 200076 kb
Host smart-5dd80928-b1b5-4389-8f18-4bc5e7495156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479911243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.479911243
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3151295687
Short name T857
Test name
Test status
Simulation time 85982498288 ps
CPU time 132.97 seconds
Started May 07 01:00:05 PM PDT 24
Finished May 07 01:02:19 PM PDT 24
Peak memory 200476 kb
Host smart-c450571a-bb7c-4e6b-9e77-be36173dff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151295687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3151295687
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3904413406
Short name T71
Test name
Test status
Simulation time 11504920499 ps
CPU time 2.34 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:09 PM PDT 24
Peak memory 200184 kb
Host smart-1a381772-2ba7-408e-80c8-dab4d2c4b35e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904413406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3904413406
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.924408677
Short name T274
Test name
Test status
Simulation time 102896497066 ps
CPU time 496.45 seconds
Started May 07 01:00:08 PM PDT 24
Finished May 07 01:08:26 PM PDT 24
Peak memory 200420 kb
Host smart-6dd93293-baf7-4c62-8228-ae17bc45d090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924408677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.924408677
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.951931379
Short name T1108
Test name
Test status
Simulation time 3184477214 ps
CPU time 9.04 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:17 PM PDT 24
Peak memory 198724 kb
Host smart-d74b8cdf-f90e-4727-a44d-196c41f802da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951931379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.951931379
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1918517283
Short name T965
Test name
Test status
Simulation time 41263182644 ps
CPU time 16.05 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:23 PM PDT 24
Peak memory 198512 kb
Host smart-889a9f51-474f-4ac0-91f8-221bac76bb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918517283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1918517283
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1018592692
Short name T263
Test name
Test status
Simulation time 5651444577 ps
CPU time 80.95 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:01:29 PM PDT 24
Peak memory 200412 kb
Host smart-c00bcf9a-92f4-4564-a7a7-3beba1f2f053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018592692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1018592692
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2972162751
Short name T430
Test name
Test status
Simulation time 4856839495 ps
CPU time 38.64 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:46 PM PDT 24
Peak memory 198380 kb
Host smart-d45d3ece-711f-49cd-9d5e-16ef9067a586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972162751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2972162751
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.208009228
Short name T745
Test name
Test status
Simulation time 18915079686 ps
CPU time 31.51 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:00:44 PM PDT 24
Peak memory 200348 kb
Host smart-ee3cc786-ce18-47c6-b2f6-3350d3a1b8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208009228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.208009228
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3218302930
Short name T1060
Test name
Test status
Simulation time 31805102555 ps
CPU time 25.14 seconds
Started May 07 01:00:06 PM PDT 24
Finished May 07 01:00:32 PM PDT 24
Peak memory 196444 kb
Host smart-932fce98-1c99-4671-b84e-c1d2766d705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218302930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3218302930
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.959151156
Short name T50
Test name
Test status
Simulation time 471644499 ps
CPU time 1.89 seconds
Started May 07 01:00:09 PM PDT 24
Finished May 07 01:00:12 PM PDT 24
Peak memory 198360 kb
Host smart-e4498d5e-7641-406b-97ec-fe420b9dc938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959151156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.959151156
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.184422724
Short name T1133
Test name
Test status
Simulation time 60892337734 ps
CPU time 563.71 seconds
Started May 07 01:00:05 PM PDT 24
Finished May 07 01:09:30 PM PDT 24
Peak memory 200428 kb
Host smart-4a18df18-17d5-487c-80bc-9ae1da030ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184422724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.184422724
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.411890071
Short name T1000
Test name
Test status
Simulation time 195576246490 ps
CPU time 290.76 seconds
Started May 07 01:00:07 PM PDT 24
Finished May 07 01:04:58 PM PDT 24
Peak memory 216944 kb
Host smart-ed718cbf-da75-4f1a-9879-97dad1e4938a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411890071 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.411890071
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.481277755
Short name T596
Test name
Test status
Simulation time 6733123484 ps
CPU time 18.41 seconds
Started May 07 01:00:07 PM PDT 24
Finished May 07 01:00:27 PM PDT 24
Peak memory 200104 kb
Host smart-09c51409-fde9-4240-8607-6e551b375fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481277755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.481277755
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2784435210
Short name T445
Test name
Test status
Simulation time 118897655765 ps
CPU time 165.14 seconds
Started May 07 01:00:10 PM PDT 24
Finished May 07 01:02:55 PM PDT 24
Peak memory 200440 kb
Host smart-1bb39bdc-0eb8-4556-bd45-b8295340c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784435210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2784435210
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1190774287
Short name T550
Test name
Test status
Simulation time 12051656 ps
CPU time 0.56 seconds
Started May 07 01:01:27 PM PDT 24
Finished May 07 01:01:28 PM PDT 24
Peak memory 195824 kb
Host smart-088eea28-11c1-4435-8f50-50a5d4c99c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190774287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1190774287
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1954022195
Short name T980
Test name
Test status
Simulation time 145857450848 ps
CPU time 253.51 seconds
Started May 07 01:01:25 PM PDT 24
Finished May 07 01:05:39 PM PDT 24
Peak memory 200472 kb
Host smart-80a9f72f-77e3-438f-81c3-3327f541bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954022195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1954022195
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2237902101
Short name T386
Test name
Test status
Simulation time 189968247592 ps
CPU time 74.88 seconds
Started May 07 01:01:26 PM PDT 24
Finished May 07 01:02:42 PM PDT 24
Peak memory 200188 kb
Host smart-44f46d47-756a-4cd7-87b1-b8ccb11905ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237902101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2237902101
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1124425334
Short name T634
Test name
Test status
Simulation time 60567602209 ps
CPU time 72.58 seconds
Started May 07 01:01:25 PM PDT 24
Finished May 07 01:02:39 PM PDT 24
Peak memory 200408 kb
Host smart-099f96bb-1d3c-4d16-9120-6e673e6336f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124425334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1124425334
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3396472001
Short name T684
Test name
Test status
Simulation time 47931783412 ps
CPU time 88.75 seconds
Started May 07 01:01:24 PM PDT 24
Finished May 07 01:02:53 PM PDT 24
Peak memory 200428 kb
Host smart-8a2d936c-e5d7-428d-a87e-aee08db57227
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396472001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3396472001
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4004848380
Short name T720
Test name
Test status
Simulation time 55920127954 ps
CPU time 231.67 seconds
Started May 07 01:01:26 PM PDT 24
Finished May 07 01:05:18 PM PDT 24
Peak memory 200436 kb
Host smart-8c367d44-a4a3-41f2-a03c-b485c4d2b1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004848380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4004848380
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1263424571
Short name T1007
Test name
Test status
Simulation time 12161661105 ps
CPU time 14.49 seconds
Started May 07 01:01:22 PM PDT 24
Finished May 07 01:01:38 PM PDT 24
Peak memory 200348 kb
Host smart-28769d02-cdc5-44cc-a2f5-4b2bf5ad51c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263424571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1263424571
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1680151424
Short name T938
Test name
Test status
Simulation time 12629261172 ps
CPU time 12.94 seconds
Started May 07 01:01:24 PM PDT 24
Finished May 07 01:01:38 PM PDT 24
Peak memory 200620 kb
Host smart-331f9448-35e3-4376-94f6-719dbb7770c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680151424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1680151424
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2848868742
Short name T1181
Test name
Test status
Simulation time 18991437700 ps
CPU time 1133.23 seconds
Started May 07 01:01:26 PM PDT 24
Finished May 07 01:20:20 PM PDT 24
Peak memory 200444 kb
Host smart-65870073-11c0-4994-b0e8-11d3c4c95a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2848868742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2848868742
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3561867043
Short name T623
Test name
Test status
Simulation time 4235564762 ps
CPU time 38.25 seconds
Started May 07 01:01:24 PM PDT 24
Finished May 07 01:02:03 PM PDT 24
Peak memory 198936 kb
Host smart-5c758dff-6686-4542-a1c6-fec3e69b5c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561867043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3561867043
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2668386838
Short name T1057
Test name
Test status
Simulation time 35825507241 ps
CPU time 35.1 seconds
Started May 07 01:01:24 PM PDT 24
Finished May 07 01:02:00 PM PDT 24
Peak memory 200500 kb
Host smart-67a2838b-6801-4906-a824-8edbe27467be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668386838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2668386838
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3510824716
Short name T1033
Test name
Test status
Simulation time 5214272378 ps
CPU time 7.85 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:01:32 PM PDT 24
Peak memory 196720 kb
Host smart-e280e66b-bcfa-4f64-97ec-4c9c9e44b940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510824716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3510824716
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1491331251
Short name T804
Test name
Test status
Simulation time 5692261927 ps
CPU time 12.1 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:01:30 PM PDT 24
Peak memory 199604 kb
Host smart-7d7db906-29ee-4127-a68a-090dc21896f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491331251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1491331251
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.4245802956
Short name T709
Test name
Test status
Simulation time 142260581784 ps
CPU time 1193.56 seconds
Started May 07 01:01:28 PM PDT 24
Finished May 07 01:21:22 PM PDT 24
Peak memory 200380 kb
Host smart-b6310945-1192-4f9b-9ed0-ea45fc70354b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245802956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4245802956
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3400903603
Short name T77
Test name
Test status
Simulation time 314435213194 ps
CPU time 711.43 seconds
Started May 07 01:01:25 PM PDT 24
Finished May 07 01:13:18 PM PDT 24
Peak memory 216880 kb
Host smart-d0e9fbad-73e0-42b0-b022-cd4a98be35dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400903603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3400903603
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.972657916
Short name T627
Test name
Test status
Simulation time 607971583 ps
CPU time 3.32 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:01:28 PM PDT 24
Peak memory 199300 kb
Host smart-52aaba49-d833-4e9f-a241-157d5c2831d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972657916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.972657916
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3819659473
Short name T1067
Test name
Test status
Simulation time 48539872265 ps
CPU time 77.31 seconds
Started May 07 01:01:16 PM PDT 24
Finished May 07 01:02:35 PM PDT 24
Peak memory 200436 kb
Host smart-567b97d0-23dd-4e87-840f-b0eecf000dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819659473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3819659473
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1493718360
Short name T232
Test name
Test status
Simulation time 26426342792 ps
CPU time 63.62 seconds
Started May 07 01:05:40 PM PDT 24
Finished May 07 01:06:44 PM PDT 24
Peak memory 200424 kb
Host smart-59852c8b-b9e1-42c9-ac8b-8f84ac39e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493718360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1493718360
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4237019751
Short name T1115
Test name
Test status
Simulation time 67106521981 ps
CPU time 40.56 seconds
Started May 07 01:05:35 PM PDT 24
Finished May 07 01:06:17 PM PDT 24
Peak memory 200436 kb
Host smart-ba3c46c2-f22b-47a2-8a5b-75f58445d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237019751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4237019751
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.35536278
Short name T780
Test name
Test status
Simulation time 33076087240 ps
CPU time 16.54 seconds
Started May 07 01:05:38 PM PDT 24
Finished May 07 01:05:56 PM PDT 24
Peak memory 199324 kb
Host smart-8dbfc4f8-c1c3-4d2d-a206-e559c787ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35536278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.35536278
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1966205297
Short name T129
Test name
Test status
Simulation time 69011401312 ps
CPU time 26.83 seconds
Started May 07 01:05:37 PM PDT 24
Finished May 07 01:06:05 PM PDT 24
Peak memory 200260 kb
Host smart-c27a5310-74eb-4f62-8f41-3ea4ed796446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966205297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1966205297
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2391556106
Short name T1141
Test name
Test status
Simulation time 51698008417 ps
CPU time 22.88 seconds
Started May 07 01:05:37 PM PDT 24
Finished May 07 01:06:02 PM PDT 24
Peak memory 200444 kb
Host smart-85118d80-96a3-488f-8302-221fb7fb6373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391556106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2391556106
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.100849821
Short name T653
Test name
Test status
Simulation time 209069060479 ps
CPU time 346.09 seconds
Started May 07 01:05:37 PM PDT 24
Finished May 07 01:11:24 PM PDT 24
Peak memory 200428 kb
Host smart-f12af53e-42d5-4f37-ae27-fd0d81606d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100849821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.100849821
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2762070993
Short name T821
Test name
Test status
Simulation time 34886944313 ps
CPU time 40.84 seconds
Started May 07 01:05:37 PM PDT 24
Finished May 07 01:06:19 PM PDT 24
Peak memory 199568 kb
Host smart-15271733-0848-41cf-9d3d-c60e33a30e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762070993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2762070993
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.215240050
Short name T476
Test name
Test status
Simulation time 36930168697 ps
CPU time 62.84 seconds
Started May 07 01:05:38 PM PDT 24
Finished May 07 01:06:42 PM PDT 24
Peak memory 200452 kb
Host smart-ccbab20e-1479-4389-b7c4-adb9657c9bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215240050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.215240050
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.55042762
Short name T1032
Test name
Test status
Simulation time 49179554879 ps
CPU time 16.21 seconds
Started May 07 01:05:41 PM PDT 24
Finished May 07 01:05:58 PM PDT 24
Peak memory 200424 kb
Host smart-7d4cc902-c78f-4845-8f01-4bfddf4ae738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55042762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.55042762
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.98158029
Short name T600
Test name
Test status
Simulation time 19159405 ps
CPU time 0.55 seconds
Started May 07 01:01:34 PM PDT 24
Finished May 07 01:01:36 PM PDT 24
Peak memory 195800 kb
Host smart-f2413fb9-fe43-416c-8c8c-89d3f9cfa549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98158029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.98158029
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.339492066
Short name T510
Test name
Test status
Simulation time 33579606167 ps
CPU time 21.11 seconds
Started May 07 01:01:25 PM PDT 24
Finished May 07 01:01:47 PM PDT 24
Peak memory 200448 kb
Host smart-471a5658-8a9f-4221-b90e-de5636df6185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339492066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.339492066
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.864879099
Short name T588
Test name
Test status
Simulation time 24955568779 ps
CPU time 35.3 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:01:59 PM PDT 24
Peak memory 200296 kb
Host smart-f0586e9b-301c-44ff-b2dd-dcf319a82d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864879099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.864879099
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1254324626
Short name T948
Test name
Test status
Simulation time 92693215647 ps
CPU time 43.26 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:02:08 PM PDT 24
Peak memory 200480 kb
Host smart-f423b454-621f-448c-ad3e-2140d7fdbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254324626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1254324626
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1863912315
Short name T385
Test name
Test status
Simulation time 15083236851 ps
CPU time 8.74 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:01:33 PM PDT 24
Peak memory 198708 kb
Host smart-9a78387e-4920-4118-b0a3-7b0544c47ebd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863912315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1863912315
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2000557465
Short name T864
Test name
Test status
Simulation time 87078795625 ps
CPU time 377.42 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:07:52 PM PDT 24
Peak memory 200428 kb
Host smart-12057ec9-fa14-47bb-aa3c-175f4a8ee8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000557465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2000557465
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2582615379
Short name T485
Test name
Test status
Simulation time 6188078646 ps
CPU time 14.37 seconds
Started May 07 01:01:31 PM PDT 24
Finished May 07 01:01:46 PM PDT 24
Peak memory 199904 kb
Host smart-62f86c94-137a-47cc-b260-7d5918cc77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582615379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2582615379
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3389434226
Short name T833
Test name
Test status
Simulation time 70130478282 ps
CPU time 141.92 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:03:46 PM PDT 24
Peak memory 200284 kb
Host smart-8c77b8d0-0935-4f80-b98d-df3b96003631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389434226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3389434226
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2787115604
Short name T299
Test name
Test status
Simulation time 17432907975 ps
CPU time 480.32 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:09:40 PM PDT 24
Peak memory 200268 kb
Host smart-4d46e129-09ad-461b-b94b-0d28056f29d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787115604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2787115604
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3421872929
Short name T608
Test name
Test status
Simulation time 2099265544 ps
CPU time 15.47 seconds
Started May 07 01:01:28 PM PDT 24
Finished May 07 01:01:44 PM PDT 24
Peak memory 198488 kb
Host smart-f79dc892-f7a9-4343-a1b3-46e3491acb49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421872929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3421872929
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.556535463
Short name T650
Test name
Test status
Simulation time 119999065228 ps
CPU time 55.52 seconds
Started May 07 01:01:24 PM PDT 24
Finished May 07 01:02:20 PM PDT 24
Peak memory 200368 kb
Host smart-99452a05-d459-4c70-9c82-dc54592ed2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556535463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.556535463
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.4133439378
Short name T418
Test name
Test status
Simulation time 44833242377 ps
CPU time 18.48 seconds
Started May 07 01:01:26 PM PDT 24
Finished May 07 01:01:46 PM PDT 24
Peak memory 196412 kb
Host smart-766633b9-cc96-4d9a-81b7-d130dd7a9be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133439378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4133439378
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.482151798
Short name T764
Test name
Test status
Simulation time 10537925594 ps
CPU time 48.03 seconds
Started May 07 01:01:27 PM PDT 24
Finished May 07 01:02:16 PM PDT 24
Peak memory 200024 kb
Host smart-e63921d7-07e0-4fd5-ae01-df592ece6a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482151798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.482151798
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1141762166
Short name T125
Test name
Test status
Simulation time 100223702512 ps
CPU time 238.9 seconds
Started May 07 01:01:32 PM PDT 24
Finished May 07 01:05:32 PM PDT 24
Peak memory 215032 kb
Host smart-4436af19-8b38-4e66-a230-a4d4596fc61b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141762166 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1141762166
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.515540223
Short name T732
Test name
Test status
Simulation time 417418513 ps
CPU time 1.79 seconds
Started May 07 01:01:22 PM PDT 24
Finished May 07 01:01:25 PM PDT 24
Peak memory 198760 kb
Host smart-89da2010-00fe-4385-b814-4deb83c4f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515540223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.515540223
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.667659736
Short name T520
Test name
Test status
Simulation time 62893040338 ps
CPU time 122.4 seconds
Started May 07 01:01:23 PM PDT 24
Finished May 07 01:03:26 PM PDT 24
Peak memory 200452 kb
Host smart-9e894b06-2913-49d3-bdb5-50ceaae2686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667659736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.667659736
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.58951989
Short name T1070
Test name
Test status
Simulation time 158518371393 ps
CPU time 59.55 seconds
Started May 07 01:05:40 PM PDT 24
Finished May 07 01:06:41 PM PDT 24
Peak memory 200428 kb
Host smart-c5d9eb25-e527-4723-ad73-975f4b930e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58951989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.58951989
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2533012978
Short name T887
Test name
Test status
Simulation time 10092015213 ps
CPU time 22.62 seconds
Started May 07 01:05:37 PM PDT 24
Finished May 07 01:06:01 PM PDT 24
Peak memory 200420 kb
Host smart-2632bb0c-7c15-4501-8b71-bccc46cfe4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533012978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2533012978
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.440356794
Short name T858
Test name
Test status
Simulation time 118992626931 ps
CPU time 213.2 seconds
Started May 07 01:05:36 PM PDT 24
Finished May 07 01:09:11 PM PDT 24
Peak memory 200464 kb
Host smart-e682783c-a78b-4d78-baa8-bba1bf8bc466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440356794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.440356794
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.74882371
Short name T412
Test name
Test status
Simulation time 41713051902 ps
CPU time 18.17 seconds
Started May 07 01:05:48 PM PDT 24
Finished May 07 01:06:07 PM PDT 24
Peak memory 200460 kb
Host smart-99e2508f-39d2-4a6a-8f64-93c5e4a114f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74882371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.74882371
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3553550735
Short name T822
Test name
Test status
Simulation time 29812669239 ps
CPU time 12.82 seconds
Started May 07 01:05:47 PM PDT 24
Finished May 07 01:06:01 PM PDT 24
Peak memory 200424 kb
Host smart-c1a39806-7e21-4f90-986a-eb792994f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553550735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3553550735
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1261279467
Short name T233
Test name
Test status
Simulation time 61185356349 ps
CPU time 89.49 seconds
Started May 07 01:05:50 PM PDT 24
Finished May 07 01:07:21 PM PDT 24
Peak memory 200428 kb
Host smart-472a9bc8-6915-4fed-ac25-c749401b41ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261279467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1261279467
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1485127617
Short name T155
Test name
Test status
Simulation time 120839248801 ps
CPU time 197.99 seconds
Started May 07 01:05:48 PM PDT 24
Finished May 07 01:09:07 PM PDT 24
Peak memory 200400 kb
Host smart-7211452d-b180-4e10-b3d4-dd53ddebde07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485127617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1485127617
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.177021641
Short name T297
Test name
Test status
Simulation time 79841245951 ps
CPU time 45.34 seconds
Started May 07 01:05:47 PM PDT 24
Finished May 07 01:06:33 PM PDT 24
Peak memory 200412 kb
Host smart-d169174a-a763-4fd4-a320-9a8c7adeaf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177021641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.177021641
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1047316736
Short name T74
Test name
Test status
Simulation time 97370000500 ps
CPU time 154.42 seconds
Started May 07 01:05:48 PM PDT 24
Finished May 07 01:08:23 PM PDT 24
Peak memory 200532 kb
Host smart-5227e00b-55ca-428f-b690-78bde60f052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047316736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1047316736
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2840336965
Short name T1031
Test name
Test status
Simulation time 24728320 ps
CPU time 0.56 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:01:34 PM PDT 24
Peak memory 195744 kb
Host smart-5db829b0-1606-4dd0-a008-e2acf5a76100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840336965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2840336965
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.716267289
Short name T1093
Test name
Test status
Simulation time 134297789635 ps
CPU time 48.32 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:02:22 PM PDT 24
Peak memory 200468 kb
Host smart-048fb026-a024-4668-bcad-47f44d8b4e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716267289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.716267289
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2527995475
Short name T1064
Test name
Test status
Simulation time 41896284506 ps
CPU time 87.48 seconds
Started May 07 01:01:32 PM PDT 24
Finished May 07 01:03:00 PM PDT 24
Peak memory 200428 kb
Host smart-37b09c16-b644-43b2-a1bb-3a44af1ba886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527995475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2527995475
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1574052501
Short name T910
Test name
Test status
Simulation time 56228427756 ps
CPU time 26.67 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:02:06 PM PDT 24
Peak memory 200248 kb
Host smart-926c815a-2a09-417d-bd49-226eaa5d3458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574052501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1574052501
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4039754070
Short name T16
Test name
Test status
Simulation time 39794651357 ps
CPU time 19.65 seconds
Started May 07 01:01:30 PM PDT 24
Finished May 07 01:01:51 PM PDT 24
Peak memory 200432 kb
Host smart-f580474e-80d8-4ee9-bc64-0ed8772e9b6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039754070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4039754070
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3289328063
Short name T820
Test name
Test status
Simulation time 137486627993 ps
CPU time 1141.18 seconds
Started May 07 01:01:34 PM PDT 24
Finished May 07 01:20:37 PM PDT 24
Peak memory 200396 kb
Host smart-99c1d674-b0a3-46f8-a086-ae3d4890d334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289328063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3289328063
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1787753983
Short name T339
Test name
Test status
Simulation time 8571000226 ps
CPU time 13.64 seconds
Started May 07 01:01:32 PM PDT 24
Finished May 07 01:01:47 PM PDT 24
Peak memory 199072 kb
Host smart-8a9db8f0-85dc-42dd-8de2-e7d03874452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787753983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1787753983
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3010090387
Short name T387
Test name
Test status
Simulation time 128268135480 ps
CPU time 120.38 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:03:34 PM PDT 24
Peak memory 200624 kb
Host smart-78aa754e-86b2-4f97-8baa-a45751512183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010090387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3010090387
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3745964539
Short name T788
Test name
Test status
Simulation time 3065273086 ps
CPU time 87.2 seconds
Started May 07 01:01:31 PM PDT 24
Finished May 07 01:02:59 PM PDT 24
Peak memory 200428 kb
Host smart-b66b1f1d-7484-4792-963d-af751966ebdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745964539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3745964539
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3348010983
Short name T622
Test name
Test status
Simulation time 7693782313 ps
CPU time 19.45 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:01:53 PM PDT 24
Peak memory 199748 kb
Host smart-432d0373-5f1c-4244-839f-38bba2891a43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348010983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3348010983
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2132688529
Short name T1072
Test name
Test status
Simulation time 87859436760 ps
CPU time 77.53 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:02:56 PM PDT 24
Peak memory 200152 kb
Host smart-3ffaa36c-e7d4-4d99-971b-feef83870cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132688529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2132688529
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.791519446
Short name T318
Test name
Test status
Simulation time 25325291952 ps
CPU time 6.72 seconds
Started May 07 01:01:31 PM PDT 24
Finished May 07 01:01:39 PM PDT 24
Peak memory 196212 kb
Host smart-b46b1146-460c-4fe7-8e56-2d16bf054a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791519446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.791519446
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1607676426
Short name T620
Test name
Test status
Simulation time 5824384906 ps
CPU time 12.65 seconds
Started May 07 01:01:34 PM PDT 24
Finished May 07 01:01:48 PM PDT 24
Peak memory 199636 kb
Host smart-18d81084-78ac-4bd4-afcc-f66ec55362ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607676426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1607676426
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3108017755
Short name T243
Test name
Test status
Simulation time 600561474031 ps
CPU time 728.32 seconds
Started May 07 01:01:33 PM PDT 24
Finished May 07 01:13:42 PM PDT 24
Peak memory 200396 kb
Host smart-007eed0e-6e30-43ba-8ca2-3644f35784ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108017755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3108017755
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.976805682
Short name T14
Test name
Test status
Simulation time 47053528042 ps
CPU time 412.51 seconds
Started May 07 01:01:32 PM PDT 24
Finished May 07 01:08:26 PM PDT 24
Peak memory 225224 kb
Host smart-d05a6036-14f5-4e61-9a0e-b5378c9811a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976805682 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.976805682
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1976780722
Short name T131
Test name
Test status
Simulation time 1258523749 ps
CPU time 3.61 seconds
Started May 07 01:01:34 PM PDT 24
Finished May 07 01:01:39 PM PDT 24
Peak memory 198980 kb
Host smart-ab08d8fc-ce65-4790-b315-4be77cb3ed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976780722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1976780722
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3177111449
Short name T966
Test name
Test status
Simulation time 48081299994 ps
CPU time 45.63 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:02:25 PM PDT 24
Peak memory 200392 kb
Host smart-3e6f8c22-6e2e-4df6-8d98-fe1126d48f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177111449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3177111449
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1957725686
Short name T815
Test name
Test status
Simulation time 18427342955 ps
CPU time 13.86 seconds
Started May 07 01:05:46 PM PDT 24
Finished May 07 01:06:01 PM PDT 24
Peak memory 200276 kb
Host smart-d9d57fef-2738-494e-afea-8423b3dd7acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957725686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1957725686
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2554479784
Short name T932
Test name
Test status
Simulation time 23849073484 ps
CPU time 39.45 seconds
Started May 07 01:05:50 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 200452 kb
Host smart-b583a8a0-4a3e-474e-bfcb-861aba4fe316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554479784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2554479784
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2132671445
Short name T542
Test name
Test status
Simulation time 21749858668 ps
CPU time 21.9 seconds
Started May 07 01:05:47 PM PDT 24
Finished May 07 01:06:10 PM PDT 24
Peak memory 200436 kb
Host smart-05843903-b73f-495f-aeb5-f63ebd093e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132671445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2132671445
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1928976905
Short name T347
Test name
Test status
Simulation time 25216007598 ps
CPU time 19.28 seconds
Started May 07 01:05:51 PM PDT 24
Finished May 07 01:06:11 PM PDT 24
Peak memory 200400 kb
Host smart-2ef8ed19-26d4-40da-a7da-e3a8b3376b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928976905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1928976905
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1290935236
Short name T909
Test name
Test status
Simulation time 16866316809 ps
CPU time 31.06 seconds
Started May 07 01:05:48 PM PDT 24
Finished May 07 01:06:20 PM PDT 24
Peak memory 200452 kb
Host smart-ee11d2d6-bb2f-46f6-a97d-0e0269fa5cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290935236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1290935236
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.303380234
Short name T158
Test name
Test status
Simulation time 110898717338 ps
CPU time 148.72 seconds
Started May 07 01:05:47 PM PDT 24
Finished May 07 01:08:17 PM PDT 24
Peak memory 200356 kb
Host smart-59bde48a-8599-4894-97ee-59bdcd9c5fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303380234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.303380234
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2572259456
Short name T646
Test name
Test status
Simulation time 16630893736 ps
CPU time 26.18 seconds
Started May 07 01:05:48 PM PDT 24
Finished May 07 01:06:15 PM PDT 24
Peak memory 200400 kb
Host smart-e63542d2-363b-4b02-9edf-3c52d3847bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572259456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2572259456
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1889758009
Short name T779
Test name
Test status
Simulation time 41464897179 ps
CPU time 25.58 seconds
Started May 07 01:05:46 PM PDT 24
Finished May 07 01:06:12 PM PDT 24
Peak memory 200324 kb
Host smart-3b5c5f41-4562-4d02-aacd-e44616b7fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889758009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1889758009
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1637253573
Short name T1019
Test name
Test status
Simulation time 17822456815 ps
CPU time 33.08 seconds
Started May 07 01:05:46 PM PDT 24
Finished May 07 01:06:20 PM PDT 24
Peak memory 200396 kb
Host smart-ca9bb13a-8bae-4b8c-ba6c-422818c55f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637253573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1637253573
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1932200913
Short name T24
Test name
Test status
Simulation time 79945027 ps
CPU time 0.53 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:01:40 PM PDT 24
Peak memory 195840 kb
Host smart-db2099e9-bab4-4b51-bd47-d19495d3bae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932200913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1932200913
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3024184853
Short name T330
Test name
Test status
Simulation time 111282531993 ps
CPU time 201.56 seconds
Started May 07 01:01:31 PM PDT 24
Finished May 07 01:04:53 PM PDT 24
Peak memory 200316 kb
Host smart-fd1d2df3-712d-4bbe-9a9f-fca9819ca69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024184853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3024184853
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4264015649
Short name T230
Test name
Test status
Simulation time 31499985468 ps
CPU time 27.74 seconds
Started May 07 01:01:40 PM PDT 24
Finished May 07 01:02:09 PM PDT 24
Peak memory 200384 kb
Host smart-6c1fe15a-9119-4541-826f-45f6142ff32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264015649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4264015649
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.587680241
Short name T996
Test name
Test status
Simulation time 18013100264 ps
CPU time 42.48 seconds
Started May 07 01:01:41 PM PDT 24
Finished May 07 01:02:25 PM PDT 24
Peak memory 199868 kb
Host smart-3207adb6-e47d-4047-8bf0-105230522c7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587680241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.587680241
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1152713132
Short name T783
Test name
Test status
Simulation time 52835095280 ps
CPU time 258.36 seconds
Started May 07 01:01:45 PM PDT 24
Finished May 07 01:06:05 PM PDT 24
Peak memory 200484 kb
Host smart-6f5e71ce-2815-40ae-b385-90dc431e22bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152713132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1152713132
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3208286974
Short name T991
Test name
Test status
Simulation time 13240766341 ps
CPU time 5.93 seconds
Started May 07 01:01:42 PM PDT 24
Finished May 07 01:01:49 PM PDT 24
Peak memory 200408 kb
Host smart-c8da8905-8e2c-4122-a27b-f76011a4dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208286974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3208286974
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1385500295
Short name T876
Test name
Test status
Simulation time 55276425525 ps
CPU time 67.61 seconds
Started May 07 01:01:40 PM PDT 24
Finished May 07 01:02:50 PM PDT 24
Peak memory 199536 kb
Host smart-d3d23e7f-057d-480b-b99d-058e8cf4ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385500295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1385500295
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.549241283
Short name T551
Test name
Test status
Simulation time 16434203323 ps
CPU time 808.29 seconds
Started May 07 01:01:48 PM PDT 24
Finished May 07 01:15:17 PM PDT 24
Peak memory 200384 kb
Host smart-a16f8b2b-8827-4356-9bc1-70dbbdd2e5f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549241283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.549241283
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1291030275
Short name T96
Test name
Test status
Simulation time 5653766670 ps
CPU time 11.11 seconds
Started May 07 01:01:39 PM PDT 24
Finished May 07 01:01:51 PM PDT 24
Peak memory 199568 kb
Host smart-0951edef-5fc8-4f00-aae7-787853833f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291030275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1291030275
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.886795887
Short name T852
Test name
Test status
Simulation time 71416239745 ps
CPU time 32.57 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:02:12 PM PDT 24
Peak memory 200376 kb
Host smart-4673b56e-685a-4b6b-9419-a3287c3145c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886795887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.886795887
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.939446192
Short name T524
Test name
Test status
Simulation time 7722750431 ps
CPU time 2.64 seconds
Started May 07 01:01:39 PM PDT 24
Finished May 07 01:01:44 PM PDT 24
Peak memory 196448 kb
Host smart-f1a14d01-7d11-46c6-9345-b112d2d96f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939446192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.939446192
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2157527057
Short name T954
Test name
Test status
Simulation time 279705692 ps
CPU time 1.17 seconds
Started May 07 01:01:32 PM PDT 24
Finished May 07 01:01:34 PM PDT 24
Peak memory 198700 kb
Host smart-f9bf6a0b-52a9-40a3-b6cb-8410a56ee7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157527057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2157527057
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.311544445
Short name T252
Test name
Test status
Simulation time 444358709350 ps
CPU time 79.99 seconds
Started May 07 01:01:49 PM PDT 24
Finished May 07 01:03:10 PM PDT 24
Peak memory 200372 kb
Host smart-53f395a7-743c-4f1e-bdfd-45550b5a4ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311544445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.311544445
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.802481585
Short name T860
Test name
Test status
Simulation time 18013276706 ps
CPU time 78.04 seconds
Started May 07 01:01:48 PM PDT 24
Finished May 07 01:03:08 PM PDT 24
Peak memory 210644 kb
Host smart-60f7b3bd-18d3-41d2-8ad5-d23469e79828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802481585 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.802481585
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.238419605
Short name T643
Test name
Test status
Simulation time 906400046 ps
CPU time 1.63 seconds
Started May 07 01:01:43 PM PDT 24
Finished May 07 01:01:45 PM PDT 24
Peak memory 198896 kb
Host smart-c5b28914-ff4b-468c-a040-0b94bf131e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238419605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.238419605
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3254342290
Short name T922
Test name
Test status
Simulation time 33165788106 ps
CPU time 56.71 seconds
Started May 07 01:01:34 PM PDT 24
Finished May 07 01:02:32 PM PDT 24
Peak memory 200344 kb
Host smart-b7c0c5e5-9ad6-4153-b24b-af5b5b22f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254342290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3254342290
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3747604838
Short name T739
Test name
Test status
Simulation time 64445630897 ps
CPU time 26.93 seconds
Started May 07 01:05:46 PM PDT 24
Finished May 07 01:06:14 PM PDT 24
Peak memory 200428 kb
Host smart-9d35e4fd-665e-4325-a5d7-091668505a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747604838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3747604838
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1024759886
Short name T957
Test name
Test status
Simulation time 50965207894 ps
CPU time 45.3 seconds
Started May 07 01:06:00 PM PDT 24
Finished May 07 01:06:46 PM PDT 24
Peak memory 200412 kb
Host smart-81eddb86-3d29-4f14-95c3-dd39b1cb3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024759886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1024759886
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2823586156
Short name T13
Test name
Test status
Simulation time 53651237172 ps
CPU time 90.71 seconds
Started May 07 01:06:00 PM PDT 24
Finished May 07 01:07:32 PM PDT 24
Peak memory 200248 kb
Host smart-14cc6631-6522-469d-aff3-a556fad5746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823586156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2823586156
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1923334777
Short name T793
Test name
Test status
Simulation time 51325637874 ps
CPU time 100.41 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:07:40 PM PDT 24
Peak memory 200348 kb
Host smart-28d12b5d-8e7e-457a-9062-751afa74610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923334777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1923334777
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2588566473
Short name T136
Test name
Test status
Simulation time 19576209300 ps
CPU time 31.71 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 200456 kb
Host smart-a589c3af-4454-4144-8bf1-939fe7a81c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588566473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2588566473
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.933154457
Short name T212
Test name
Test status
Simulation time 160068921024 ps
CPU time 372.77 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:12:10 PM PDT 24
Peak memory 200468 kb
Host smart-04fa1dc8-17bb-4210-9a4a-4e285da6097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933154457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.933154457
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2628269591
Short name T883
Test name
Test status
Simulation time 43823486777 ps
CPU time 75.5 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:07:13 PM PDT 24
Peak memory 200536 kb
Host smart-f74d7795-9ab0-4085-b3d2-f2785420a4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628269591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2628269591
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.838995223
Short name T927
Test name
Test status
Simulation time 260231283589 ps
CPU time 121.16 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:08:00 PM PDT 24
Peak memory 200392 kb
Host smart-f74d6b6b-4b1a-4a0f-932d-e80c08fc1729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838995223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.838995223
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1263734075
Short name T898
Test name
Test status
Simulation time 106226259834 ps
CPU time 128.71 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:08:07 PM PDT 24
Peak memory 200464 kb
Host smart-147c0e15-b6bc-4587-92fd-5122897fcda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263734075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1263734075
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2742948047
Short name T1090
Test name
Test status
Simulation time 111899416239 ps
CPU time 54.2 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:54 PM PDT 24
Peak memory 200396 kb
Host smart-78d1f504-37f4-4341-826a-544e890e333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742948047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2742948047
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4294375443
Short name T352
Test name
Test status
Simulation time 37208072 ps
CPU time 0.58 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:01:48 PM PDT 24
Peak memory 195808 kb
Host smart-467f8917-54f5-4285-8962-fa035adea3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294375443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4294375443
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.21661272
Short name T688
Test name
Test status
Simulation time 49329980595 ps
CPU time 26.72 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:02:14 PM PDT 24
Peak memory 200392 kb
Host smart-b0851709-5077-4559-9510-7f2ecb39934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21661272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.21661272
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2571288090
Short name T437
Test name
Test status
Simulation time 21571491523 ps
CPU time 33.9 seconds
Started May 07 01:01:38 PM PDT 24
Finished May 07 01:02:13 PM PDT 24
Peak memory 200284 kb
Host smart-56dbd568-3991-4f00-8ba1-aee2832f653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571288090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2571288090
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1019028168
Short name T464
Test name
Test status
Simulation time 186958097873 ps
CPU time 94.69 seconds
Started May 07 01:01:41 PM PDT 24
Finished May 07 01:03:17 PM PDT 24
Peak memory 200400 kb
Host smart-abb349f2-7aba-4927-959f-6aa61acdf077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019028168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1019028168
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4135110253
Short name T440
Test name
Test status
Simulation time 32228806117 ps
CPU time 83.36 seconds
Started May 07 01:01:48 PM PDT 24
Finished May 07 01:03:12 PM PDT 24
Peak memory 200304 kb
Host smart-2c0ea662-727b-45a9-8c2e-b1faa8115892
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135110253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4135110253
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3994205621
Short name T535
Test name
Test status
Simulation time 37319701578 ps
CPU time 101.24 seconds
Started May 07 01:01:41 PM PDT 24
Finished May 07 01:03:24 PM PDT 24
Peak memory 200316 kb
Host smart-2052f19b-434c-47e5-9475-34bfe52bcb55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994205621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3994205621
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2272342894
Short name T977
Test name
Test status
Simulation time 7137596578 ps
CPU time 14.42 seconds
Started May 07 01:01:39 PM PDT 24
Finished May 07 01:01:55 PM PDT 24
Peak memory 198844 kb
Host smart-54313d7f-1ac7-48f6-9bcd-c6ce195b4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272342894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2272342894
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4100862909
Short name T1042
Test name
Test status
Simulation time 190222751383 ps
CPU time 85.33 seconds
Started May 07 01:01:39 PM PDT 24
Finished May 07 01:03:07 PM PDT 24
Peak memory 208692 kb
Host smart-9889f167-668f-4d0d-ba27-c78e55bb97d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100862909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4100862909
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1042849630
Short name T572
Test name
Test status
Simulation time 12837379336 ps
CPU time 726.92 seconds
Started May 07 01:01:41 PM PDT 24
Finished May 07 01:13:49 PM PDT 24
Peak memory 200392 kb
Host smart-539ff2ad-5be3-44c0-86d4-ec2e19d9ca8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042849630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1042849630
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4096515147
Short name T933
Test name
Test status
Simulation time 6181336643 ps
CPU time 53.26 seconds
Started May 07 01:01:40 PM PDT 24
Finished May 07 01:02:35 PM PDT 24
Peak memory 199624 kb
Host smart-ccfa1eb5-5447-4f10-8e56-9fded10b924f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096515147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4096515147
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1897837555
Short name T532
Test name
Test status
Simulation time 156773333685 ps
CPU time 114.88 seconds
Started May 07 01:01:39 PM PDT 24
Finished May 07 01:03:35 PM PDT 24
Peak memory 200380 kb
Host smart-46e07498-5d42-4d0d-ab8b-e26e6e9fa2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897837555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1897837555
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1367658701
Short name T602
Test name
Test status
Simulation time 46446842136 ps
CPU time 36.28 seconds
Started May 07 01:01:43 PM PDT 24
Finished May 07 01:02:20 PM PDT 24
Peak memory 196388 kb
Host smart-882b5d86-36fb-41a9-955f-4febd7e15792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367658701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1367658701
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3447663320
Short name T993
Test name
Test status
Simulation time 884290703 ps
CPU time 3.42 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:01:50 PM PDT 24
Peak memory 199252 kb
Host smart-9385f558-0a66-426f-b8d4-b249b855b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447663320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3447663320
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2977858643
Short name T177
Test name
Test status
Simulation time 244873916753 ps
CPU time 434.64 seconds
Started May 07 01:01:48 PM PDT 24
Finished May 07 01:09:04 PM PDT 24
Peak memory 200024 kb
Host smart-70a8240f-c742-4b77-96f5-8abea65b09db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977858643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2977858643
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3204406587
Short name T126
Test name
Test status
Simulation time 72531264179 ps
CPU time 596.16 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:11:44 PM PDT 24
Peak memory 225288 kb
Host smart-7be06a14-b1cc-4a3f-8d48-7fff3f1e415b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204406587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3204406587
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3984120519
Short name T305
Test name
Test status
Simulation time 635486022 ps
CPU time 2.57 seconds
Started May 07 01:01:42 PM PDT 24
Finished May 07 01:01:45 PM PDT 24
Peak memory 198576 kb
Host smart-c48ec6a3-f3dd-40d6-8d1e-b7f6091585c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984120519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3984120519
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2428959661
Short name T838
Test name
Test status
Simulation time 17805294534 ps
CPU time 15.36 seconds
Started May 07 01:01:45 PM PDT 24
Finished May 07 01:02:02 PM PDT 24
Peak memory 200428 kb
Host smart-19883177-cafb-479d-ab86-3eb69cf34238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428959661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2428959661
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.981545181
Short name T222
Test name
Test status
Simulation time 101146745354 ps
CPU time 138.07 seconds
Started May 07 01:05:55 PM PDT 24
Finished May 07 01:08:14 PM PDT 24
Peak memory 200340 kb
Host smart-67c17589-3405-4575-8e35-50e15daa7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981545181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.981545181
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3249328309
Short name T534
Test name
Test status
Simulation time 30787073839 ps
CPU time 50.29 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:50 PM PDT 24
Peak memory 200412 kb
Host smart-77267d2a-24f5-4f87-bc5e-43ce6bf4138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249328309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3249328309
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1533740580
Short name T863
Test name
Test status
Simulation time 68121210250 ps
CPU time 107.57 seconds
Started May 07 01:05:59 PM PDT 24
Finished May 07 01:07:48 PM PDT 24
Peak memory 200132 kb
Host smart-c58ca072-8361-482f-bee3-38e41fa146cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533740580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1533740580
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.615211866
Short name T1092
Test name
Test status
Simulation time 58318366744 ps
CPU time 10.89 seconds
Started May 07 01:05:55 PM PDT 24
Finished May 07 01:06:07 PM PDT 24
Peak memory 199828 kb
Host smart-826de334-2f0c-4bbb-8cf1-f0781ad9defc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615211866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.615211866
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1717336726
Short name T467
Test name
Test status
Simulation time 33532369377 ps
CPU time 14.81 seconds
Started May 07 01:05:55 PM PDT 24
Finished May 07 01:06:11 PM PDT 24
Peak memory 199288 kb
Host smart-ba82bcc3-d82b-4a2e-a39d-cfd024656390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717336726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1717336726
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2763700481
Short name T603
Test name
Test status
Simulation time 16438100930 ps
CPU time 15.34 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:14 PM PDT 24
Peak memory 200432 kb
Host smart-09da6ba3-0f07-4f47-809e-0d9c0e5d9177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763700481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2763700481
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1731826161
Short name T422
Test name
Test status
Simulation time 229744676684 ps
CPU time 24.23 seconds
Started May 07 01:05:59 PM PDT 24
Finished May 07 01:06:24 PM PDT 24
Peak memory 200196 kb
Host smart-6aacf176-68e1-4d1e-b603-869d0f151a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731826161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1731826161
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1766815122
Short name T846
Test name
Test status
Simulation time 231369176549 ps
CPU time 156.99 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:08:36 PM PDT 24
Peak memory 200396 kb
Host smart-0dc2895b-bd36-4586-8225-b1005fc0a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766815122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1766815122
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3899438845
Short name T1122
Test name
Test status
Simulation time 25795150408 ps
CPU time 41.64 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:41 PM PDT 24
Peak memory 200460 kb
Host smart-dd92ae08-14d3-482d-b74a-80c10ad639ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899438845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3899438845
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3026132313
Short name T569
Test name
Test status
Simulation time 21069038 ps
CPU time 0.54 seconds
Started May 07 01:01:49 PM PDT 24
Finished May 07 01:01:51 PM PDT 24
Peak memory 195820 kb
Host smart-653c0e0b-c6f2-48c2-8eb0-489ecfe36090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026132313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3026132313
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1546386246
Short name T150
Test name
Test status
Simulation time 104669948172 ps
CPU time 47.02 seconds
Started May 07 01:01:45 PM PDT 24
Finished May 07 01:02:34 PM PDT 24
Peak memory 200464 kb
Host smart-0390ab43-b432-4275-a4a2-c5d585211648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546386246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1546386246
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2051053433
Short name T778
Test name
Test status
Simulation time 29184987158 ps
CPU time 18.66 seconds
Started May 07 01:01:47 PM PDT 24
Finished May 07 01:02:07 PM PDT 24
Peak memory 200400 kb
Host smart-3a61453c-24e5-4961-aa15-5cd0b8bea7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051053433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2051053433
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3081215636
Short name T721
Test name
Test status
Simulation time 75584996439 ps
CPU time 25.98 seconds
Started May 07 01:01:49 PM PDT 24
Finished May 07 01:02:16 PM PDT 24
Peak memory 200048 kb
Host smart-3a9da738-7312-4914-8a74-1f2c90911eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081215636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3081215636
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2607465516
Short name T985
Test name
Test status
Simulation time 148996097120 ps
CPU time 57.07 seconds
Started May 07 01:01:49 PM PDT 24
Finished May 07 01:02:47 PM PDT 24
Peak memory 197000 kb
Host smart-e45164d4-d113-4408-b557-b8ba4432e8b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607465516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2607465516
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.899835014
Short name T678
Test name
Test status
Simulation time 105196603782 ps
CPU time 584 seconds
Started May 07 01:01:50 PM PDT 24
Finished May 07 01:11:35 PM PDT 24
Peak memory 200388 kb
Host smart-610c9686-82f8-4bd3-8cc1-fd0dcf54a3fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899835014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.899835014
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1620146853
Short name T994
Test name
Test status
Simulation time 8638948024 ps
CPU time 6.25 seconds
Started May 07 01:01:47 PM PDT 24
Finished May 07 01:01:54 PM PDT 24
Peak memory 200332 kb
Host smart-6723dd32-e54a-4c66-b260-1c7154215362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620146853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1620146853
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3811174487
Short name T1008
Test name
Test status
Simulation time 148462631503 ps
CPU time 61.58 seconds
Started May 07 01:01:45 PM PDT 24
Finished May 07 01:02:48 PM PDT 24
Peak memory 199972 kb
Host smart-21a7c2b4-ed80-4da9-b5d1-2b45f2f02bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811174487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3811174487
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3931268559
Short name T434
Test name
Test status
Simulation time 24905143450 ps
CPU time 157.68 seconds
Started May 07 01:01:45 PM PDT 24
Finished May 07 01:04:24 PM PDT 24
Peak memory 200448 kb
Host smart-dfea0ff5-adcf-4474-b068-9fb7e91513b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931268559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3931268559
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2703539683
Short name T375
Test name
Test status
Simulation time 3689683179 ps
CPU time 7.73 seconds
Started May 07 01:01:49 PM PDT 24
Finished May 07 01:01:58 PM PDT 24
Peak memory 199452 kb
Host smart-0260cb2f-17ef-4eac-886e-53e88c60527f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703539683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2703539683
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1873488901
Short name T1146
Test name
Test status
Simulation time 18412011806 ps
CPU time 31.29 seconds
Started May 07 01:01:47 PM PDT 24
Finished May 07 01:02:20 PM PDT 24
Peak memory 200396 kb
Host smart-697d74f9-e9e7-4362-a896-259a90f1ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873488901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1873488901
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.340455746
Short name T302
Test name
Test status
Simulation time 4838173339 ps
CPU time 8.9 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:01:56 PM PDT 24
Peak memory 196412 kb
Host smart-9b8ad35c-673a-4b6e-94ab-f50ef15f4315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340455746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.340455746
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1040836230
Short name T943
Test name
Test status
Simulation time 10525659488 ps
CPU time 30.55 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:02:18 PM PDT 24
Peak memory 200260 kb
Host smart-5fea0277-76b9-40c6-ae51-8a30469c4ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040836230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1040836230
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3183403557
Short name T503
Test name
Test status
Simulation time 53062191504 ps
CPU time 198.75 seconds
Started May 07 01:01:47 PM PDT 24
Finished May 07 01:05:07 PM PDT 24
Peak memory 217076 kb
Host smart-c8f84160-a6cf-4b37-82ae-3bb3d0c2f658
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183403557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3183403557
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.70121907
Short name T771
Test name
Test status
Simulation time 6052904915 ps
CPU time 2.48 seconds
Started May 07 01:01:46 PM PDT 24
Finished May 07 01:01:49 PM PDT 24
Peak memory 199508 kb
Host smart-cee15a32-72ca-42cd-8a73-b427d17195f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70121907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.70121907
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3754808581
Short name T671
Test name
Test status
Simulation time 39637433513 ps
CPU time 38.8 seconds
Started May 07 01:01:47 PM PDT 24
Finished May 07 01:02:27 PM PDT 24
Peak memory 200388 kb
Host smart-1cd24046-c131-472f-b72e-d206060a894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754808581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3754808581
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3889780063
Short name T191
Test name
Test status
Simulation time 40911739339 ps
CPU time 17.05 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:06:15 PM PDT 24
Peak memory 200136 kb
Host smart-495f04c5-ed59-4c6a-b1c4-0bb2b8ea7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889780063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3889780063
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1434723539
Short name T1078
Test name
Test status
Simulation time 73521374637 ps
CPU time 17.27 seconds
Started May 07 01:06:01 PM PDT 24
Finished May 07 01:06:19 PM PDT 24
Peak memory 199616 kb
Host smart-08a5fab8-0369-48d2-aa97-503c75774093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434723539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1434723539
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1660119207
Short name T1180
Test name
Test status
Simulation time 39613800288 ps
CPU time 18.06 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:17 PM PDT 24
Peak memory 200380 kb
Host smart-a5f48448-0fdf-4fd1-96cd-98f2d30f8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660119207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1660119207
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3904442276
Short name T877
Test name
Test status
Simulation time 113942110806 ps
CPU time 44.82 seconds
Started May 07 01:05:55 PM PDT 24
Finished May 07 01:06:41 PM PDT 24
Peak memory 200444 kb
Host smart-52d2675b-330b-4575-b835-2f53fd0aa48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904442276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3904442276
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2001184522
Short name T141
Test name
Test status
Simulation time 25353004272 ps
CPU time 22.87 seconds
Started May 07 01:06:00 PM PDT 24
Finished May 07 01:06:24 PM PDT 24
Peak memory 200336 kb
Host smart-1cb5d41a-bd8f-48a1-9532-181a51987be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001184522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2001184522
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3395912034
Short name T225
Test name
Test status
Simulation time 48813370398 ps
CPU time 32.14 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 200404 kb
Host smart-ef421247-b365-4baf-9918-e3ab9b5e1480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395912034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3395912034
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1262728210
Short name T879
Test name
Test status
Simulation time 55553523331 ps
CPU time 51.28 seconds
Started May 07 01:05:59 PM PDT 24
Finished May 07 01:06:51 PM PDT 24
Peak memory 200380 kb
Host smart-8b3cc0e2-1e3e-4751-9969-535667a07cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262728210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1262728210
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1607454629
Short name T282
Test name
Test status
Simulation time 57963432665 ps
CPU time 31.76 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 200436 kb
Host smart-222492e3-a256-4624-b5e3-f4016cef7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607454629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1607454629
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3517870199
Short name T490
Test name
Test status
Simulation time 162054206600 ps
CPU time 21.31 seconds
Started May 07 01:05:57 PM PDT 24
Finished May 07 01:06:19 PM PDT 24
Peak memory 200428 kb
Host smart-6c1dda69-eab3-4333-a964-daa78db945f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517870199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3517870199
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2190561029
Short name T170
Test name
Test status
Simulation time 40501526415 ps
CPU time 34.67 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:06:34 PM PDT 24
Peak memory 200400 kb
Host smart-3b882319-8dd0-4e34-a514-dc0e387d6bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190561029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2190561029
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3355381290
Short name T463
Test name
Test status
Simulation time 16146110 ps
CPU time 0.6 seconds
Started May 07 01:01:53 PM PDT 24
Finished May 07 01:01:55 PM PDT 24
Peak memory 195972 kb
Host smart-c4c7d83c-b614-4673-bdf4-7a8e131fd01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355381290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3355381290
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1340401757
Short name T585
Test name
Test status
Simulation time 121636912275 ps
CPU time 16.55 seconds
Started May 07 01:01:49 PM PDT 24
Finished May 07 01:02:06 PM PDT 24
Peak memory 200464 kb
Host smart-7cb4f0a4-2062-488b-883d-7e723d405bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340401757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1340401757
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4014259111
Short name T1074
Test name
Test status
Simulation time 125194176490 ps
CPU time 535.16 seconds
Started May 07 01:01:57 PM PDT 24
Finished May 07 01:10:53 PM PDT 24
Peak memory 200084 kb
Host smart-44447074-32ba-40fb-8348-d9b755df62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014259111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4014259111
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3097316043
Short name T257
Test name
Test status
Simulation time 119349372895 ps
CPU time 50.33 seconds
Started May 07 01:01:53 PM PDT 24
Finished May 07 01:02:44 PM PDT 24
Peak memory 200392 kb
Host smart-768cfbd6-3550-4a4f-acc1-fbb4025dd4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097316043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3097316043
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2722108568
Short name T322
Test name
Test status
Simulation time 48015769886 ps
CPU time 22.78 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:18 PM PDT 24
Peak memory 198344 kb
Host smart-bea72a7a-ca91-4fa4-a07e-2fbd515b6182
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722108568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2722108568
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2909873751
Short name T1178
Test name
Test status
Simulation time 237256177771 ps
CPU time 657.97 seconds
Started May 07 01:01:55 PM PDT 24
Finished May 07 01:12:55 PM PDT 24
Peak memory 200380 kb
Host smart-9004020f-f263-4d2f-b67c-29ec84f1ce82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909873751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2909873751
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4231538716
Short name T374
Test name
Test status
Simulation time 7831195818 ps
CPU time 15.52 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:11 PM PDT 24
Peak memory 199304 kb
Host smart-e1dca85b-e533-4db8-82e3-17316acb64ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231538716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4231538716
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2614909152
Short name T769
Test name
Test status
Simulation time 41247348293 ps
CPU time 19.32 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:15 PM PDT 24
Peak memory 200496 kb
Host smart-5f63ea68-c8f2-4968-9317-6a439481cfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614909152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2614909152
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1326653200
Short name T1001
Test name
Test status
Simulation time 11829615918 ps
CPU time 129.5 seconds
Started May 07 01:01:57 PM PDT 24
Finished May 07 01:04:07 PM PDT 24
Peak memory 200404 kb
Host smart-f908cf19-130c-4cea-a150-206e9753a082
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326653200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1326653200
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.716958165
Short name T492
Test name
Test status
Simulation time 2409722785 ps
CPU time 8.37 seconds
Started May 07 01:01:58 PM PDT 24
Finished May 07 01:02:07 PM PDT 24
Peak memory 199504 kb
Host smart-b0cc719b-a066-4a6c-a1ff-396f5d8e7e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716958165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.716958165
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1547492553
Short name T619
Test name
Test status
Simulation time 101728831044 ps
CPU time 149.2 seconds
Started May 07 01:01:58 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 200396 kb
Host smart-f9f4e25b-30ac-448a-8552-9b3c0c29e54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547492553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1547492553
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3627734886
Short name T304
Test name
Test status
Simulation time 2728972116 ps
CPU time 4.59 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:01 PM PDT 24
Peak memory 196096 kb
Host smart-a088ec4f-0e77-44cd-b0bc-93dc5b00809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627734886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3627734886
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2145257127
Short name T1135
Test name
Test status
Simulation time 5632640222 ps
CPU time 10.51 seconds
Started May 07 01:01:50 PM PDT 24
Finished May 07 01:02:02 PM PDT 24
Peak memory 200104 kb
Host smart-9a7a8303-cd69-4e7e-a8d8-a2e3c8180bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145257127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2145257127
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2253502486
Short name T196
Test name
Test status
Simulation time 243816719860 ps
CPU time 413.48 seconds
Started May 07 01:01:55 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 200448 kb
Host smart-a4971a39-ad5b-4300-b58d-66c2e1d5627e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253502486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2253502486
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1038233922
Short name T59
Test name
Test status
Simulation time 49383806513 ps
CPU time 301.5 seconds
Started May 07 01:01:58 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 216104 kb
Host smart-8a61ace5-adba-4668-afe7-5f6372768b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038233922 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1038233922
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4037596551
Short name T962
Test name
Test status
Simulation time 8430927024 ps
CPU time 8.29 seconds
Started May 07 01:01:55 PM PDT 24
Finished May 07 01:02:05 PM PDT 24
Peak memory 200208 kb
Host smart-2ffe40c2-31c6-4b07-a78f-496e5fed2f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037596551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4037596551
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1584380264
Short name T284
Test name
Test status
Simulation time 54187869243 ps
CPU time 42.54 seconds
Started May 07 01:01:45 PM PDT 24
Finished May 07 01:02:28 PM PDT 24
Peak memory 200320 kb
Host smart-2bfc95ef-d5a2-4c07-a4dd-549acbf75354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584380264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1584380264
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.21078050
Short name T577
Test name
Test status
Simulation time 133423416268 ps
CPU time 57.15 seconds
Started May 07 01:05:59 PM PDT 24
Finished May 07 01:06:57 PM PDT 24
Peak memory 200404 kb
Host smart-a0df5cdf-aac1-4c1b-8ea2-c4dc81f4511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21078050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.21078050
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2897622335
Short name T501
Test name
Test status
Simulation time 96058202623 ps
CPU time 169.4 seconds
Started May 07 01:05:58 PM PDT 24
Finished May 07 01:08:49 PM PDT 24
Peak memory 200356 kb
Host smart-4a862b7b-9bc0-4f1f-9024-60f0198fa067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897622335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2897622335
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1961827351
Short name T481
Test name
Test status
Simulation time 117809142157 ps
CPU time 15.29 seconds
Started May 07 01:06:06 PM PDT 24
Finished May 07 01:06:22 PM PDT 24
Peak memory 200356 kb
Host smart-5497e799-c58e-47b4-9726-9d889fa925ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961827351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1961827351
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.93879381
Short name T744
Test name
Test status
Simulation time 102026912083 ps
CPU time 183 seconds
Started May 07 01:06:04 PM PDT 24
Finished May 07 01:09:08 PM PDT 24
Peak memory 200396 kb
Host smart-9f574853-da64-4e74-9c82-b3f5fcdb4263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93879381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.93879381
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2130258488
Short name T675
Test name
Test status
Simulation time 23092608868 ps
CPU time 42.47 seconds
Started May 07 01:06:05 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 200492 kb
Host smart-45993ba0-1d63-4d6d-a890-a4941cac842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130258488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2130258488
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3063065652
Short name T1088
Test name
Test status
Simulation time 61486007974 ps
CPU time 30.52 seconds
Started May 07 01:06:02 PM PDT 24
Finished May 07 01:06:33 PM PDT 24
Peak memory 200368 kb
Host smart-6c825c38-45a0-44be-85db-41b13afccebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063065652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3063065652
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4271594501
Short name T479
Test name
Test status
Simulation time 41844969130 ps
CPU time 13.91 seconds
Started May 07 01:06:03 PM PDT 24
Finished May 07 01:06:18 PM PDT 24
Peak memory 200448 kb
Host smart-4014c6ae-9ff8-4ee3-99a4-4cbd751d92fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271594501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4271594501
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.161571020
Short name T470
Test name
Test status
Simulation time 14458271354 ps
CPU time 29.63 seconds
Started May 07 01:06:06 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 200444 kb
Host smart-159bc4c9-3aae-4feb-8455-266e2f716e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161571020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.161571020
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3679656464
Short name T595
Test name
Test status
Simulation time 133649045493 ps
CPU time 56.99 seconds
Started May 07 01:06:03 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 200028 kb
Host smart-8e71347c-a493-45de-bb97-5af30e0798a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679656464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3679656464
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1784260741
Short name T489
Test name
Test status
Simulation time 16194498 ps
CPU time 0.55 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:02:05 PM PDT 24
Peak memory 195796 kb
Host smart-fb195d66-f8a4-435d-b2a7-2e5da05dd623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784260741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1784260741
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3833260567
Short name T880
Test name
Test status
Simulation time 52123220293 ps
CPU time 89.94 seconds
Started May 07 01:01:53 PM PDT 24
Finished May 07 01:03:23 PM PDT 24
Peak memory 200404 kb
Host smart-4e9939b2-64df-4602-a8c3-5d176d324899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833260567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3833260567
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.744825152
Short name T536
Test name
Test status
Simulation time 11967470879 ps
CPU time 5.81 seconds
Started May 07 01:01:56 PM PDT 24
Finished May 07 01:02:03 PM PDT 24
Peak memory 199716 kb
Host smart-0aeb16ef-f420-42e9-8293-34767b362684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744825152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.744825152
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.804512231
Short name T482
Test name
Test status
Simulation time 6607614560 ps
CPU time 14.2 seconds
Started May 07 01:01:56 PM PDT 24
Finished May 07 01:02:11 PM PDT 24
Peak memory 200100 kb
Host smart-089644cb-05f8-4b0d-971c-22d01cf89c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804512231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.804512231
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.881569311
Short name T382
Test name
Test status
Simulation time 15182618525 ps
CPU time 28.16 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:24 PM PDT 24
Peak memory 200360 kb
Host smart-48d77c65-f5c0-4a9f-963b-4452fd95c915
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881569311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.881569311
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3803703295
Short name T316
Test name
Test status
Simulation time 117650286623 ps
CPU time 891.97 seconds
Started May 07 01:02:02 PM PDT 24
Finished May 07 01:16:56 PM PDT 24
Peak memory 200388 kb
Host smart-bf64ba1f-b3d5-4d01-900b-cb94615fd8a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803703295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3803703295
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1867036647
Short name T72
Test name
Test status
Simulation time 5195161678 ps
CPU time 11.25 seconds
Started May 07 01:02:02 PM PDT 24
Finished May 07 01:02:14 PM PDT 24
Peak memory 200080 kb
Host smart-331bab03-1606-41ea-bc76-17ae278bbb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867036647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1867036647
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.442336635
Short name T134
Test name
Test status
Simulation time 81565775299 ps
CPU time 135.05 seconds
Started May 07 01:01:55 PM PDT 24
Finished May 07 01:04:11 PM PDT 24
Peak memory 200620 kb
Host smart-ec164cb3-4f1f-4c75-96ca-8f1090720681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442336635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.442336635
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3884046803
Short name T918
Test name
Test status
Simulation time 11522896343 ps
CPU time 631.44 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:12:35 PM PDT 24
Peak memory 200440 kb
Host smart-79c386f9-76b0-41ad-876d-52de6fe86daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884046803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3884046803
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4056099321
Short name T515
Test name
Test status
Simulation time 7716233831 ps
CPU time 4.62 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:01 PM PDT 24
Peak memory 199540 kb
Host smart-88fdf288-84dc-4127-897c-20c59cc71495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056099321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4056099321
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.708272609
Short name T378
Test name
Test status
Simulation time 87172198347 ps
CPU time 27.62 seconds
Started May 07 01:01:53 PM PDT 24
Finished May 07 01:02:22 PM PDT 24
Peak memory 200384 kb
Host smart-cacba394-005d-4def-8f4a-e65855fbe10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708272609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.708272609
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3101840760
Short name T1058
Test name
Test status
Simulation time 2419795605 ps
CPU time 4.37 seconds
Started May 07 01:01:55 PM PDT 24
Finished May 07 01:02:01 PM PDT 24
Peak memory 196136 kb
Host smart-52e879fd-47f7-4223-b88d-884badda0007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101840760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3101840760
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2986251985
Short name T683
Test name
Test status
Simulation time 6171562069 ps
CPU time 23.51 seconds
Started May 07 01:01:54 PM PDT 24
Finished May 07 01:02:19 PM PDT 24
Peak memory 200428 kb
Host smart-54e36867-4425-4f45-b3ac-1fd304b1b028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986251985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2986251985
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2662657
Short name T648
Test name
Test status
Simulation time 11912598693 ps
CPU time 7.55 seconds
Started May 07 01:02:02 PM PDT 24
Finished May 07 01:02:11 PM PDT 24
Peak memory 200396 kb
Host smart-5e6f3fa6-6d46-4f70-b37e-664ee11182b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2662657
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.43662296
Short name T54
Test name
Test status
Simulation time 184654126346 ps
CPU time 1975.04 seconds
Started May 07 01:02:02 PM PDT 24
Finished May 07 01:34:58 PM PDT 24
Peak memory 228568 kb
Host smart-9386f97e-4b46-4c55-890c-fd7562149f9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43662296 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.43662296
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1825176339
Short name T516
Test name
Test status
Simulation time 500045691 ps
CPU time 1.3 seconds
Started May 07 01:02:01 PM PDT 24
Finished May 07 01:02:03 PM PDT 24
Peak memory 198708 kb
Host smart-b35c25d6-02a8-413a-aab6-ccdc950d34ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825176339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1825176339
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2465668394
Short name T672
Test name
Test status
Simulation time 78133114663 ps
CPU time 12.55 seconds
Started May 07 01:01:55 PM PDT 24
Finished May 07 01:02:09 PM PDT 24
Peak memory 197988 kb
Host smart-f983faca-9fbf-4104-9ec7-74696cfd3450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465668394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2465668394
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.983046602
Short name T1081
Test name
Test status
Simulation time 188673185455 ps
CPU time 179.19 seconds
Started May 07 01:06:03 PM PDT 24
Finished May 07 01:09:03 PM PDT 24
Peak memory 200252 kb
Host smart-17ea2059-99ab-4c3b-9bcd-9e17e1f7aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983046602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.983046602
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.167505548
Short name T258
Test name
Test status
Simulation time 321794335620 ps
CPU time 83.6 seconds
Started May 07 01:06:02 PM PDT 24
Finished May 07 01:07:26 PM PDT 24
Peak memory 200412 kb
Host smart-a7f315d9-1120-40aa-a0c9-edad3497ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167505548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.167505548
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.214134213
Short name T203
Test name
Test status
Simulation time 78776204629 ps
CPU time 37.64 seconds
Started May 07 01:06:04 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 200404 kb
Host smart-372bd196-3e79-4143-928f-482d1bddc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214134213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.214134213
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1456327895
Short name T1155
Test name
Test status
Simulation time 85642371492 ps
CPU time 245.11 seconds
Started May 07 01:06:02 PM PDT 24
Finished May 07 01:10:09 PM PDT 24
Peak memory 200608 kb
Host smart-41405f1d-164c-4667-acf4-bb422a33cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456327895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1456327895
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1974577146
Short name T810
Test name
Test status
Simulation time 115775444683 ps
CPU time 161.49 seconds
Started May 07 01:06:05 PM PDT 24
Finished May 07 01:08:48 PM PDT 24
Peak memory 200532 kb
Host smart-87eff94e-45b9-4913-a359-7c70e8d5ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974577146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1974577146
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1508859062
Short name T198
Test name
Test status
Simulation time 73407101726 ps
CPU time 105.75 seconds
Started May 07 01:06:07 PM PDT 24
Finished May 07 01:07:53 PM PDT 24
Peak memory 200472 kb
Host smart-0b8a543a-46ee-4afb-87aa-2f63f917e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508859062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1508859062
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3759048943
Short name T447
Test name
Test status
Simulation time 33444901078 ps
CPU time 17.92 seconds
Started May 07 01:06:02 PM PDT 24
Finished May 07 01:06:21 PM PDT 24
Peak memory 200364 kb
Host smart-01aaa295-6b29-4cde-b4ed-b37aea4aeb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759048943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3759048943
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1729100432
Short name T431
Test name
Test status
Simulation time 40391370 ps
CPU time 0.55 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:12 PM PDT 24
Peak memory 195188 kb
Host smart-a654d971-a971-423a-ae34-25f3436af0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729100432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1729100432
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1086989636
Short name T791
Test name
Test status
Simulation time 23508073864 ps
CPU time 44.13 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:02:48 PM PDT 24
Peak memory 200416 kb
Host smart-a297bbce-d485-488b-af75-6e72b396bbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086989636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1086989636
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2281729543
Short name T505
Test name
Test status
Simulation time 171435465361 ps
CPU time 41.4 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:02:46 PM PDT 24
Peak memory 199836 kb
Host smart-36c300d5-7c6c-4f75-99cd-167856b363ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281729543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2281729543
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.341303721
Short name T465
Test name
Test status
Simulation time 30186346376 ps
CPU time 27.91 seconds
Started May 07 01:02:02 PM PDT 24
Finished May 07 01:02:31 PM PDT 24
Peak memory 200388 kb
Host smart-e21937e1-3e9b-429d-8f71-73f719e44878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341303721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.341303721
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4100100028
Short name T424
Test name
Test status
Simulation time 39617536475 ps
CPU time 53.59 seconds
Started May 07 01:02:05 PM PDT 24
Finished May 07 01:02:59 PM PDT 24
Peak memory 200100 kb
Host smart-39d93809-68e1-45f3-ba83-d24d54e10048
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100100028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4100100028
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2855844554
Short name T747
Test name
Test status
Simulation time 166257012914 ps
CPU time 340.44 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:07:52 PM PDT 24
Peak memory 200456 kb
Host smart-95ca47fd-5435-475a-988b-9d83ca9e52e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855844554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2855844554
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3446334653
Short name T844
Test name
Test status
Simulation time 7639159382 ps
CPU time 5.67 seconds
Started May 07 01:02:09 PM PDT 24
Finished May 07 01:02:16 PM PDT 24
Peak memory 199152 kb
Host smart-f3e8153d-e12a-4bdd-a321-7211fc4a151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446334653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3446334653
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3890144140
Short name T130
Test name
Test status
Simulation time 23801987784 ps
CPU time 39.88 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:02:44 PM PDT 24
Peak memory 200548 kb
Host smart-94bb30e8-2810-456b-8374-35b0bf6267ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890144140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3890144140
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2474212889
Short name T952
Test name
Test status
Simulation time 22491006246 ps
CPU time 1241.81 seconds
Started May 07 01:02:13 PM PDT 24
Finished May 07 01:22:55 PM PDT 24
Peak memory 200424 kb
Host smart-67d6a194-c23b-4189-b583-75d708a1f0c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474212889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2474212889
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2692407629
Short name T1119
Test name
Test status
Simulation time 1911050981 ps
CPU time 5.11 seconds
Started May 07 01:02:00 PM PDT 24
Finished May 07 01:02:06 PM PDT 24
Peak memory 198428 kb
Host smart-d8ec3964-63dd-4e97-8f0f-22b9e561ae25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692407629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2692407629
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2921155731
Short name T169
Test name
Test status
Simulation time 163289322523 ps
CPU time 262.52 seconds
Started May 07 01:02:11 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 200404 kb
Host smart-4b7fb03b-40cc-42bc-9c46-a45d3b7aa3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921155731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2921155731
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.776676176
Short name T906
Test name
Test status
Simulation time 2408918308 ps
CPU time 1.35 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:02:05 PM PDT 24
Peak memory 196152 kb
Host smart-5e6ffc54-c1f2-451d-875e-6398f4e67930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776676176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.776676176
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3750986365
Short name T127
Test name
Test status
Simulation time 820612605 ps
CPU time 3.58 seconds
Started May 07 01:02:02 PM PDT 24
Finished May 07 01:02:07 PM PDT 24
Peak memory 200120 kb
Host smart-888cccad-e6c1-418c-b27e-1ec035756b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750986365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3750986365
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2399727177
Short name T114
Test name
Test status
Simulation time 85895288880 ps
CPU time 93.41 seconds
Started May 07 01:02:12 PM PDT 24
Finished May 07 01:03:46 PM PDT 24
Peak memory 200428 kb
Host smart-d0acf814-a3b2-4107-9ba0-6af5c764433e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399727177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2399727177
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3710809107
Short name T119
Test name
Test status
Simulation time 28562531706 ps
CPU time 258.03 seconds
Started May 07 01:02:12 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 217100 kb
Host smart-54530f4d-6357-4c52-a2eb-de5415513a0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710809107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3710809107
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2952734525
Short name T921
Test name
Test status
Simulation time 6878545925 ps
CPU time 22.65 seconds
Started May 07 01:02:09 PM PDT 24
Finished May 07 01:02:32 PM PDT 24
Peak memory 200212 kb
Host smart-8f3f31b1-c1a5-4fe9-a9ad-749e82027160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952734525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2952734525
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1872860880
Short name T271
Test name
Test status
Simulation time 43395788988 ps
CPU time 80.84 seconds
Started May 07 01:02:03 PM PDT 24
Finished May 07 01:03:25 PM PDT 24
Peak memory 200396 kb
Host smart-c9721fa6-f742-4e45-822c-08ee97ff7837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872860880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1872860880
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3995289221
Short name T156
Test name
Test status
Simulation time 10453826125 ps
CPU time 20.86 seconds
Started May 07 01:06:06 PM PDT 24
Finished May 07 01:06:28 PM PDT 24
Peak memory 200428 kb
Host smart-fe023da6-f164-4545-ba0d-8221774cb424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995289221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3995289221
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2903147128
Short name T478
Test name
Test status
Simulation time 241486462410 ps
CPU time 211.98 seconds
Started May 07 01:06:12 PM PDT 24
Finished May 07 01:09:45 PM PDT 24
Peak memory 200448 kb
Host smart-6c939bbb-3a6f-4fb4-b671-aa8ad46ed5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903147128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2903147128
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1839772555
Short name T201
Test name
Test status
Simulation time 29467248282 ps
CPU time 35.71 seconds
Started May 07 01:06:11 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 200412 kb
Host smart-1c6350f2-6f3f-4c3b-bd39-c445ba2cb950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839772555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1839772555
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2692909878
Short name T594
Test name
Test status
Simulation time 100795079012 ps
CPU time 27.64 seconds
Started May 07 01:06:24 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 200460 kb
Host smart-b4a6e7b2-c74d-4485-b84c-7af44e6ab37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692909878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2692909878
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3020090154
Short name T42
Test name
Test status
Simulation time 52787737892 ps
CPU time 28.33 seconds
Started May 07 01:06:22 PM PDT 24
Finished May 07 01:06:52 PM PDT 24
Peak memory 200436 kb
Host smart-296c5f70-b3f5-4eed-9e00-34e01b229d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020090154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3020090154
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.532623406
Short name T717
Test name
Test status
Simulation time 97737926915 ps
CPU time 353.76 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:12:23 PM PDT 24
Peak memory 200304 kb
Host smart-85e5fcdf-a0a1-4117-9dc2-a612834d4b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532623406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.532623406
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2262303488
Short name T400
Test name
Test status
Simulation time 8751676121 ps
CPU time 18.46 seconds
Started May 07 01:06:12 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 200356 kb
Host smart-fa11365e-206f-4c5b-a64c-7f4cb6b539a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262303488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2262303488
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.68687500
Short name T224
Test name
Test status
Simulation time 86304444400 ps
CPU time 154.2 seconds
Started May 07 01:06:13 PM PDT 24
Finished May 07 01:08:48 PM PDT 24
Peak memory 200416 kb
Host smart-fbeba092-3fd6-491b-a3ba-2b58babad4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68687500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.68687500
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3222769852
Short name T759
Test name
Test status
Simulation time 10528254316 ps
CPU time 26.62 seconds
Started May 07 01:06:13 PM PDT 24
Finished May 07 01:06:41 PM PDT 24
Peak memory 200244 kb
Host smart-f2af20eb-d77d-4d9d-9e07-10741f566949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222769852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3222769852
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2600038643
Short name T380
Test name
Test status
Simulation time 48835174 ps
CPU time 0.55 seconds
Started May 07 01:02:09 PM PDT 24
Finished May 07 01:02:11 PM PDT 24
Peak memory 195800 kb
Host smart-6c8075f1-b277-488c-8fa6-e07adcfd7c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600038643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2600038643
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.190877957
Short name T1113
Test name
Test status
Simulation time 58332921374 ps
CPU time 18.17 seconds
Started May 07 01:02:09 PM PDT 24
Finished May 07 01:02:28 PM PDT 24
Peak memory 200456 kb
Host smart-888bcad0-c6ac-4289-8043-b5642b434fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190877957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.190877957
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2716605821
Short name T1168
Test name
Test status
Simulation time 148890892288 ps
CPU time 38.53 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:50 PM PDT 24
Peak memory 200312 kb
Host smart-36bb5296-4ed9-4b33-b5e2-9962dc1a619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716605821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2716605821
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3186895256
Short name T936
Test name
Test status
Simulation time 29266275482 ps
CPU time 13.56 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:25 PM PDT 24
Peak memory 198732 kb
Host smart-28b8bb7d-3fc4-4115-a549-abf8544e3d8d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186895256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3186895256
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2327359023
Short name T818
Test name
Test status
Simulation time 52231717485 ps
CPU time 241.63 seconds
Started May 07 01:02:13 PM PDT 24
Finished May 07 01:06:15 PM PDT 24
Peak memory 200428 kb
Host smart-d80e22f6-e5b9-4270-9928-457f008f21b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327359023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2327359023
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2222199539
Short name T397
Test name
Test status
Simulation time 10265440629 ps
CPU time 7.4 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:18 PM PDT 24
Peak memory 200164 kb
Host smart-96a41ca2-94a3-41b8-a465-c37d10b478c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222199539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2222199539
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1366908287
Short name T1017
Test name
Test status
Simulation time 395817570155 ps
CPU time 123.77 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:04:15 PM PDT 24
Peak memory 208764 kb
Host smart-4fcf81b0-9c00-49f3-8538-b1335a6d3d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366908287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1366908287
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1063482646
Short name T484
Test name
Test status
Simulation time 14963375445 ps
CPU time 215.31 seconds
Started May 07 01:02:09 PM PDT 24
Finished May 07 01:05:46 PM PDT 24
Peak memory 200424 kb
Host smart-bde5144c-624d-4ad8-aa88-2d1ae38ec05c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063482646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1063482646
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1067742807
Short name T1165
Test name
Test status
Simulation time 1709781328 ps
CPU time 2.55 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:14 PM PDT 24
Peak memory 198512 kb
Host smart-ae723699-3adb-410a-9bea-953bc9a70379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067742807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1067742807
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.611994133
Short name T598
Test name
Test status
Simulation time 197706734297 ps
CPU time 350.94 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:08:02 PM PDT 24
Peak memory 200396 kb
Host smart-70bde9e6-61d9-4c9f-b677-5c62f66ec7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611994133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.611994133
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4004981742
Short name T630
Test name
Test status
Simulation time 1506881225 ps
CPU time 2.97 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:14 PM PDT 24
Peak memory 195800 kb
Host smart-54297d82-76ef-4637-aa30-aaef8a34ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004981742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4004981742
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1432491757
Short name T685
Test name
Test status
Simulation time 476457151 ps
CPU time 1.21 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:12 PM PDT 24
Peak memory 199072 kb
Host smart-11dd5838-0583-4787-90da-ac926f92c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432491757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1432491757
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2580338566
Short name T1012
Test name
Test status
Simulation time 184004217456 ps
CPU time 409.45 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:09:01 PM PDT 24
Peak memory 208744 kb
Host smart-b7c3cbf5-1e95-4d72-b6bf-7fcf538415b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580338566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2580338566
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.548893044
Short name T1121
Test name
Test status
Simulation time 117278003958 ps
CPU time 1181.37 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:21:53 PM PDT 24
Peak memory 216872 kb
Host smart-fe6b337f-7d0c-46c1-93f2-501188ef8264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548893044 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.548893044
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3517256377
Short name T548
Test name
Test status
Simulation time 3342642775 ps
CPU time 1.89 seconds
Started May 07 01:02:10 PM PDT 24
Finished May 07 01:02:13 PM PDT 24
Peak memory 199752 kb
Host smart-d8376eae-dd9b-46ef-84b2-eeba5d3d0b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517256377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3517256377
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1867212819
Short name T360
Test name
Test status
Simulation time 7970359236 ps
CPU time 3.47 seconds
Started May 07 01:02:11 PM PDT 24
Finished May 07 01:02:15 PM PDT 24
Peak memory 197644 kb
Host smart-f4aa51cc-6b57-4b8f-a9ec-f37bde6dcd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867212819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1867212819
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2940017297
Short name T944
Test name
Test status
Simulation time 96741334673 ps
CPU time 145.81 seconds
Started May 07 01:06:11 PM PDT 24
Finished May 07 01:08:38 PM PDT 24
Peak memory 200464 kb
Host smart-8c7c64d1-ce72-4d9e-895d-5d63a3e1fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940017297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2940017297
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1146869320
Short name T1021
Test name
Test status
Simulation time 163796353917 ps
CPU time 25.22 seconds
Started May 07 01:06:11 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 200448 kb
Host smart-adff4ed2-999e-4820-9405-fe19146d348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146869320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1146869320
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2829982725
Short name T749
Test name
Test status
Simulation time 33006999631 ps
CPU time 17.78 seconds
Started May 07 01:06:13 PM PDT 24
Finished May 07 01:06:32 PM PDT 24
Peak memory 200452 kb
Host smart-4622615d-5d66-411c-9e60-a29e1d3d0cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829982725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2829982725
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.362438571
Short name T512
Test name
Test status
Simulation time 42810801292 ps
CPU time 14.46 seconds
Started May 07 01:06:11 PM PDT 24
Finished May 07 01:06:26 PM PDT 24
Peak memory 200468 kb
Host smart-41215447-856d-426a-b789-1a5b53f51a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362438571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.362438571
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2446408007
Short name T234
Test name
Test status
Simulation time 30260883750 ps
CPU time 46.45 seconds
Started May 07 01:06:12 PM PDT 24
Finished May 07 01:07:00 PM PDT 24
Peak memory 200364 kb
Host smart-687056e1-3804-4d49-be96-fc85086819b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446408007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2446408007
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3655834885
Short name T142
Test name
Test status
Simulation time 20317537835 ps
CPU time 30.27 seconds
Started May 07 01:06:13 PM PDT 24
Finished May 07 01:06:44 PM PDT 24
Peak memory 200436 kb
Host smart-b2c9f9ed-75d7-4797-b6c8-b6940f0f64fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655834885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3655834885
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2315545280
Short name T719
Test name
Test status
Simulation time 22725708383 ps
CPU time 36.62 seconds
Started May 07 01:06:11 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 200184 kb
Host smart-2555f225-fdad-4f27-ac46-a34c89fa226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315545280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2315545280
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1881440650
Short name T143
Test name
Test status
Simulation time 125145602779 ps
CPU time 53.32 seconds
Started May 07 01:06:12 PM PDT 24
Finished May 07 01:07:06 PM PDT 24
Peak memory 200160 kb
Host smart-34fcee4b-510b-45a5-8c59-957ffdf9579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881440650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1881440650
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2590359430
Short name T237
Test name
Test status
Simulation time 18643684659 ps
CPU time 27.41 seconds
Started May 07 01:06:18 PM PDT 24
Finished May 07 01:06:47 PM PDT 24
Peak memory 200376 kb
Host smart-0db68cd3-cacd-42b9-94fd-f6daf0beeac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590359430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2590359430
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.136232531
Short name T494
Test name
Test status
Simulation time 17425134966 ps
CPU time 51.29 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:07:13 PM PDT 24
Peak memory 200456 kb
Host smart-91713368-4160-43fa-a821-7daf1b32f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136232531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.136232531
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.45023078
Short name T632
Test name
Test status
Simulation time 14196295 ps
CPU time 0.57 seconds
Started May 07 01:00:14 PM PDT 24
Finished May 07 01:00:16 PM PDT 24
Peak memory 195804 kb
Host smart-9f11f682-34a5-42f0-bce2-daab35d578e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45023078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.45023078
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3108940411
Short name T519
Test name
Test status
Simulation time 199081084011 ps
CPU time 56.75 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:01:11 PM PDT 24
Peak memory 200460 kb
Host smart-8cf8298f-afdc-4637-be6b-5a178fe5ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108940411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3108940411
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3866190187
Short name T974
Test name
Test status
Simulation time 38953183031 ps
CPU time 46.26 seconds
Started May 07 01:00:12 PM PDT 24
Finished May 07 01:01:00 PM PDT 24
Peak memory 200264 kb
Host smart-45cf6667-4f3b-4f3f-8a22-63de38566996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866190187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3866190187
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.630208366
Short name T211
Test name
Test status
Simulation time 14940113275 ps
CPU time 12.42 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:29 PM PDT 24
Peak memory 200416 kb
Host smart-50cfedd0-d361-432e-8c31-42bd0a3591fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630208366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.630208366
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4256479213
Short name T15
Test name
Test status
Simulation time 46608658302 ps
CPU time 41.98 seconds
Started May 07 01:00:17 PM PDT 24
Finished May 07 01:01:00 PM PDT 24
Peak memory 200392 kb
Host smart-4bb678e1-8ff6-40fe-bf2a-48a36aeab680
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256479213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4256479213
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.848388543
Short name T950
Test name
Test status
Simulation time 109773896159 ps
CPU time 876.69 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:14:51 PM PDT 24
Peak memory 200432 kb
Host smart-16871e7b-461b-4403-92b0-2daf57aee0db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848388543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.848388543
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2227703118
Short name T869
Test name
Test status
Simulation time 9592336265 ps
CPU time 5.07 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:00:18 PM PDT 24
Peak memory 200424 kb
Host smart-d23cfccc-17e4-4dc7-99db-ef1811d904ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227703118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2227703118
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1324202646
Short name T10
Test name
Test status
Simulation time 284326978013 ps
CPU time 35.1 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:51 PM PDT 24
Peak memory 200556 kb
Host smart-e8d968f0-74b3-4366-858b-5148c03be24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324202646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1324202646
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.771346450
Short name T273
Test name
Test status
Simulation time 10451322276 ps
CPU time 220.01 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:03:54 PM PDT 24
Peak memory 200396 kb
Host smart-9cc22619-3dfb-4e64-b2a4-4fe06a1b8033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=771346450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.771346450
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4087269209
Short name T452
Test name
Test status
Simulation time 1585884579 ps
CPU time 6.21 seconds
Started May 07 01:00:14 PM PDT 24
Finished May 07 01:00:21 PM PDT 24
Peak memory 198532 kb
Host smart-373c4f91-d6af-468f-a41a-0906b01c12cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087269209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4087269209
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1944349599
Short name T186
Test name
Test status
Simulation time 250436329861 ps
CPU time 215.48 seconds
Started May 07 01:00:12 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 200408 kb
Host smart-183d0cc2-0ed7-41ec-81ea-c19840b3fbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944349599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1944349599
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4211381409
Short name T441
Test name
Test status
Simulation time 4035640274 ps
CPU time 2.17 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:19 PM PDT 24
Peak memory 196040 kb
Host smart-516bbac8-160b-4363-8797-7d112299902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211381409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4211381409
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2167537215
Short name T109
Test name
Test status
Simulation time 62419326 ps
CPU time 0.92 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:00:16 PM PDT 24
Peak memory 218680 kb
Host smart-95b12629-6e06-4c53-8c44-49a68c95512a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167537215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2167537215
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.261512014
Short name T362
Test name
Test status
Simulation time 490115553 ps
CPU time 2.43 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:20 PM PDT 24
Peak memory 200032 kb
Host smart-fbc1a2c4-3120-4d14-908f-42178d6fa3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261512014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.261512014
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2833103461
Short name T984
Test name
Test status
Simulation time 208766059997 ps
CPU time 359.63 seconds
Started May 07 01:00:16 PM PDT 24
Finished May 07 01:06:17 PM PDT 24
Peak memory 208856 kb
Host smart-b1582288-631b-4022-8f28-4e282c52bf18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833103461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2833103461
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1392293847
Short name T34
Test name
Test status
Simulation time 31241380230 ps
CPU time 331.02 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:05:42 PM PDT 24
Peak memory 216400 kb
Host smart-aeb619bd-e329-4819-97a0-51f82782e623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392293847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1392293847
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2625058239
Short name T420
Test name
Test status
Simulation time 1768168540 ps
CPU time 2.12 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:18 PM PDT 24
Peak memory 198760 kb
Host smart-43acad2f-a59c-4a81-a654-4ed811b83b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625058239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2625058239
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3642346940
Short name T912
Test name
Test status
Simulation time 76251795847 ps
CPU time 29.87 seconds
Started May 07 01:00:12 PM PDT 24
Finished May 07 01:00:43 PM PDT 24
Peak memory 200476 kb
Host smart-ba138c24-9f17-4a60-962a-e06005a97229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642346940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3642346940
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1665369557
Short name T546
Test name
Test status
Simulation time 13333811 ps
CPU time 0.54 seconds
Started May 07 01:02:18 PM PDT 24
Finished May 07 01:02:20 PM PDT 24
Peak memory 194796 kb
Host smart-be99cacc-77e2-4c7b-8e62-1c312c7efeee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665369557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1665369557
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4069940535
Short name T144
Test name
Test status
Simulation time 48685603297 ps
CPU time 24.31 seconds
Started May 07 01:02:18 PM PDT 24
Finished May 07 01:02:44 PM PDT 24
Peak memory 200504 kb
Host smart-20614446-7a59-42c8-903c-abfb6f394bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069940535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4069940535
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.899041293
Short name T1162
Test name
Test status
Simulation time 34322256678 ps
CPU time 59.36 seconds
Started May 07 01:02:19 PM PDT 24
Finished May 07 01:03:20 PM PDT 24
Peak memory 200388 kb
Host smart-eca28251-221d-4f37-834c-46d859f01ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899041293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.899041293
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2802419069
Short name T832
Test name
Test status
Simulation time 202421867759 ps
CPU time 102.87 seconds
Started May 07 01:02:17 PM PDT 24
Finished May 07 01:04:01 PM PDT 24
Peak memory 200436 kb
Host smart-5c44226a-d1c2-412d-8ef9-84176ab3e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802419069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2802419069
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.42865304
Short name T1163
Test name
Test status
Simulation time 287005027167 ps
CPU time 146.59 seconds
Started May 07 01:02:19 PM PDT 24
Finished May 07 01:04:46 PM PDT 24
Peak memory 200344 kb
Host smart-2d31c064-2552-4ad1-b523-651e9a48ba24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42865304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.42865304
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1186921156
Short name T530
Test name
Test status
Simulation time 113094069127 ps
CPU time 505.09 seconds
Started May 07 01:02:21 PM PDT 24
Finished May 07 01:10:47 PM PDT 24
Peak memory 200460 kb
Host smart-21a3c0bc-592b-42f5-9f3c-19c2a3b337c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186921156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1186921156
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2850482065
Short name T92
Test name
Test status
Simulation time 183933494440 ps
CPU time 28.38 seconds
Started May 07 01:02:17 PM PDT 24
Finished May 07 01:02:46 PM PDT 24
Peak memory 200544 kb
Host smart-05204a0b-b7aa-402d-b0f7-429f4529b1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850482065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2850482065
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.802362987
Short name T522
Test name
Test status
Simulation time 4535775160 ps
CPU time 241.22 seconds
Started May 07 01:02:19 PM PDT 24
Finished May 07 01:06:21 PM PDT 24
Peak memory 200444 kb
Host smart-0f49680f-76d9-4173-871a-f5821f3eae5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802362987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.802362987
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4119810767
Short name T500
Test name
Test status
Simulation time 3305303197 ps
CPU time 28.61 seconds
Started May 07 01:02:17 PM PDT 24
Finished May 07 01:02:46 PM PDT 24
Peak memory 198760 kb
Host smart-440c4f21-b979-42b1-a1cb-74cd649833d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119810767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4119810767
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.4030858994
Short name T181
Test name
Test status
Simulation time 54731004055 ps
CPU time 85.78 seconds
Started May 07 01:02:18 PM PDT 24
Finished May 07 01:03:45 PM PDT 24
Peak memory 200344 kb
Host smart-55f6ee1d-6d38-41bb-b72c-3bcd036c73f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030858994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.4030858994
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4159682587
Short name T689
Test name
Test status
Simulation time 4929400186 ps
CPU time 4.38 seconds
Started May 07 01:02:20 PM PDT 24
Finished May 07 01:02:25 PM PDT 24
Peak memory 196428 kb
Host smart-f0bcf8d5-09ed-4d11-9f06-e39be52054a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159682587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4159682587
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4209190004
Short name T556
Test name
Test status
Simulation time 504705048 ps
CPU time 1.23 seconds
Started May 07 01:02:19 PM PDT 24
Finished May 07 01:02:21 PM PDT 24
Peak memory 198756 kb
Host smart-977ef8ab-667c-4471-ab02-b288ec3f7bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209190004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4209190004
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3821584694
Short name T787
Test name
Test status
Simulation time 579743620315 ps
CPU time 345.23 seconds
Started May 07 01:02:21 PM PDT 24
Finished May 07 01:08:07 PM PDT 24
Peak memory 200444 kb
Host smart-1b5ce682-b89d-4c6e-b5d4-63018cbc4829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821584694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3821584694
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3916517348
Short name T51
Test name
Test status
Simulation time 344163890275 ps
CPU time 275.1 seconds
Started May 07 01:02:19 PM PDT 24
Finished May 07 01:06:55 PM PDT 24
Peak memory 215960 kb
Host smart-f6e57af3-ccf4-41a9-a6dd-fe5c071899f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916517348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3916517348
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2203155130
Short name T626
Test name
Test status
Simulation time 6093494436 ps
CPU time 18.8 seconds
Started May 07 01:02:21 PM PDT 24
Finished May 07 01:02:40 PM PDT 24
Peak memory 200192 kb
Host smart-b789c043-7b8b-40ec-8a48-c3fd8536ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203155130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2203155130
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2982793453
Short name T776
Test name
Test status
Simulation time 50864605480 ps
CPU time 87.22 seconds
Started May 07 01:02:21 PM PDT 24
Finished May 07 01:03:50 PM PDT 24
Peak memory 200428 kb
Host smart-cd815251-947c-4465-aa4a-745a37708e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982793453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2982793453
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2408439125
Short name T491
Test name
Test status
Simulation time 24661896 ps
CPU time 0.52 seconds
Started May 07 01:02:28 PM PDT 24
Finished May 07 01:02:30 PM PDT 24
Peak memory 195308 kb
Host smart-2f37f6c5-6fbc-4fe8-bae4-5910582b34d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408439125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2408439125
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1374781388
Short name T692
Test name
Test status
Simulation time 48370020085 ps
CPU time 63.14 seconds
Started May 07 01:02:20 PM PDT 24
Finished May 07 01:03:24 PM PDT 24
Peak memory 200380 kb
Host smart-14c79f7d-70cc-40aa-a64a-74d6aee62624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374781388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1374781388
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3039991569
Short name T427
Test name
Test status
Simulation time 26647794629 ps
CPU time 44.61 seconds
Started May 07 01:02:21 PM PDT 24
Finished May 07 01:03:06 PM PDT 24
Peak memory 200352 kb
Host smart-703d915b-44f7-4c47-a64f-1ea07575a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039991569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3039991569
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2379483323
Short name T746
Test name
Test status
Simulation time 83301650195 ps
CPU time 13.15 seconds
Started May 07 01:02:24 PM PDT 24
Finished May 07 01:02:38 PM PDT 24
Peak memory 200348 kb
Host smart-b88c4279-681f-46ef-a291-a94f741f7c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379483323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2379483323
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.891811087
Short name T95
Test name
Test status
Simulation time 24683223053 ps
CPU time 21.59 seconds
Started May 07 01:02:24 PM PDT 24
Finished May 07 01:02:47 PM PDT 24
Peak memory 198916 kb
Host smart-9364ff0f-3e76-479b-9b61-e11b00b9102e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891811087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.891811087
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1214931333
Short name T1073
Test name
Test status
Simulation time 85591182146 ps
CPU time 903.34 seconds
Started May 07 01:02:25 PM PDT 24
Finished May 07 01:17:30 PM PDT 24
Peak memory 200400 kb
Host smart-7b962575-8a66-4ec9-a050-0dc7addbe450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214931333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1214931333
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2582051590
Short name T641
Test name
Test status
Simulation time 4322505829 ps
CPU time 3.69 seconds
Started May 07 01:02:25 PM PDT 24
Finished May 07 01:02:30 PM PDT 24
Peak memory 199276 kb
Host smart-7660bde1-c499-4a5f-b082-a92d3514fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582051590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2582051590
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3361066977
Short name T1080
Test name
Test status
Simulation time 154745004827 ps
CPU time 30.69 seconds
Started May 07 01:02:25 PM PDT 24
Finished May 07 01:02:57 PM PDT 24
Peak memory 208848 kb
Host smart-96b50d61-4565-4a59-88ac-7dc491e549da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361066977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3361066977
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3850355481
Short name T792
Test name
Test status
Simulation time 12460959201 ps
CPU time 708.98 seconds
Started May 07 01:02:26 PM PDT 24
Finished May 07 01:14:16 PM PDT 24
Peak memory 200384 kb
Host smart-7f179158-6699-4a70-bce8-5075781b0921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850355481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3850355481
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1635589975
Short name T842
Test name
Test status
Simulation time 3267650672 ps
CPU time 13.1 seconds
Started May 07 01:02:26 PM PDT 24
Finished May 07 01:02:41 PM PDT 24
Peak memory 199616 kb
Host smart-0ea5e8ac-5170-4ff7-8b65-0099fca4da10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635589975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1635589975
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1216777903
Short name T290
Test name
Test status
Simulation time 13889245376 ps
CPU time 52.45 seconds
Started May 07 01:02:26 PM PDT 24
Finished May 07 01:03:19 PM PDT 24
Peak memory 200356 kb
Host smart-80c281c3-f761-4bfe-9e47-aecbf590b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216777903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1216777903
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1356581410
Short name T885
Test name
Test status
Simulation time 4177248929 ps
CPU time 7.69 seconds
Started May 07 01:02:24 PM PDT 24
Finished May 07 01:02:33 PM PDT 24
Peak memory 196428 kb
Host smart-2b980bc6-23f6-4eef-98f9-7b81c7b67667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356581410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1356581410
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.288008888
Short name T726
Test name
Test status
Simulation time 846146774 ps
CPU time 3.28 seconds
Started May 07 01:02:21 PM PDT 24
Finished May 07 01:02:25 PM PDT 24
Peak memory 200296 kb
Host smart-9cc9fb6b-2edf-45ba-9934-44d42fda578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288008888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.288008888
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2123922459
Short name T733
Test name
Test status
Simulation time 372459324509 ps
CPU time 386.36 seconds
Started May 07 01:02:31 PM PDT 24
Finished May 07 01:08:59 PM PDT 24
Peak memory 208864 kb
Host smart-06a1bf16-fe9d-4e70-b3cf-92a5d595e3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123922459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2123922459
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2390739643
Short name T1167
Test name
Test status
Simulation time 226986818002 ps
CPU time 733.8 seconds
Started May 07 01:02:26 PM PDT 24
Finished May 07 01:14:41 PM PDT 24
Peak memory 216840 kb
Host smart-a606ad6e-990e-43e7-aa60-0d846301e56e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390739643 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2390739643
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1091044565
Short name T18
Test name
Test status
Simulation time 365274986 ps
CPU time 1.24 seconds
Started May 07 01:02:27 PM PDT 24
Finished May 07 01:02:29 PM PDT 24
Peak memory 199752 kb
Host smart-0baa78d1-450a-4549-b39d-fed9fbb2a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091044565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1091044565
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2364374498
Short name T562
Test name
Test status
Simulation time 251213553184 ps
CPU time 33.03 seconds
Started May 07 01:02:18 PM PDT 24
Finished May 07 01:02:52 PM PDT 24
Peak memory 200492 kb
Host smart-78524ae8-6137-4a49-8f55-647e466fc827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364374498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2364374498
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1898667938
Short name T613
Test name
Test status
Simulation time 54549534 ps
CPU time 0.53 seconds
Started May 07 01:02:32 PM PDT 24
Finished May 07 01:02:34 PM PDT 24
Peak memory 195852 kb
Host smart-4a463bd9-ba05-40b5-b9c9-86d934e102a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898667938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1898667938
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1065281105
Short name T697
Test name
Test status
Simulation time 53676821547 ps
CPU time 90.81 seconds
Started May 07 01:02:24 PM PDT 24
Finished May 07 01:03:56 PM PDT 24
Peak memory 200468 kb
Host smart-d4fc2459-19f4-4bdc-a717-861b0447428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065281105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1065281105
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.291661201
Short name T458
Test name
Test status
Simulation time 16458184174 ps
CPU time 18.94 seconds
Started May 07 01:02:25 PM PDT 24
Finished May 07 01:02:45 PM PDT 24
Peak memory 200344 kb
Host smart-e8d489c6-f9d9-44a9-92c1-6f8932a76ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291661201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.291661201
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.4056456952
Short name T751
Test name
Test status
Simulation time 37636591750 ps
CPU time 13.09 seconds
Started May 07 01:02:26 PM PDT 24
Finished May 07 01:02:41 PM PDT 24
Peak memory 199192 kb
Host smart-f493e53a-6a45-4aaf-ba4c-53b8ab2ecb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056456952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4056456952
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3941403593
Short name T617
Test name
Test status
Simulation time 320800055577 ps
CPU time 173.97 seconds
Started May 07 01:02:30 PM PDT 24
Finished May 07 01:05:26 PM PDT 24
Peak memory 200136 kb
Host smart-2d5e7dac-da3d-4527-b6dc-dd260168bc64
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941403593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3941403593
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3449321558
Short name T461
Test name
Test status
Simulation time 143235302554 ps
CPU time 1390.92 seconds
Started May 07 01:02:34 PM PDT 24
Finished May 07 01:25:46 PM PDT 24
Peak memory 200436 kb
Host smart-5dfdc861-c23e-4d79-9f63-3dc8abdd7ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449321558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3449321558
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.4202275725
Short name T682
Test name
Test status
Simulation time 1476047623 ps
CPU time 1.83 seconds
Started May 07 01:02:28 PM PDT 24
Finished May 07 01:02:31 PM PDT 24
Peak memory 196588 kb
Host smart-2139728b-300f-4f60-8e07-48627e58b250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202275725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.4202275725
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.4083118710
Short name T1002
Test name
Test status
Simulation time 61262261606 ps
CPU time 97.84 seconds
Started May 07 01:02:30 PM PDT 24
Finished May 07 01:04:10 PM PDT 24
Peak memory 199852 kb
Host smart-ab13e45c-b928-484e-ac55-d9dacd4d4176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083118710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4083118710
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.4074685594
Short name T1102
Test name
Test status
Simulation time 12356223416 ps
CPU time 747.7 seconds
Started May 07 01:02:33 PM PDT 24
Finished May 07 01:15:02 PM PDT 24
Peak memory 200420 kb
Host smart-16c44a72-4be4-489c-9eb3-4f76da952ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074685594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4074685594
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2240617275
Short name T765
Test name
Test status
Simulation time 1480144048 ps
CPU time 3.76 seconds
Started May 07 01:02:24 PM PDT 24
Finished May 07 01:02:29 PM PDT 24
Peak memory 199048 kb
Host smart-0fbe9f8c-9a31-4db8-bc50-c05506b22c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240617275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2240617275
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.53259486
Short name T541
Test name
Test status
Simulation time 150378735048 ps
CPU time 64.22 seconds
Started May 07 01:02:30 PM PDT 24
Finished May 07 01:03:36 PM PDT 24
Peak memory 200316 kb
Host smart-dfb6c673-5d0a-4c22-b96a-d1b02c6a57b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53259486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.53259486
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2178996805
Short name T1176
Test name
Test status
Simulation time 31569878554 ps
CPU time 21.28 seconds
Started May 07 01:02:27 PM PDT 24
Finished May 07 01:02:49 PM PDT 24
Peak memory 196444 kb
Host smart-dc2f0c8d-cda3-4fa0-8603-197f6ff4c10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178996805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2178996805
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.865432471
Short name T1075
Test name
Test status
Simulation time 250317569 ps
CPU time 1.43 seconds
Started May 07 01:02:24 PM PDT 24
Finished May 07 01:02:27 PM PDT 24
Peak memory 199132 kb
Host smart-f0fe6696-fcf3-44a9-bcb9-3249b39dd33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865432471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.865432471
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.258041471
Short name T559
Test name
Test status
Simulation time 443157128764 ps
CPU time 223.97 seconds
Started May 07 01:02:31 PM PDT 24
Finished May 07 01:06:17 PM PDT 24
Peak memory 200420 kb
Host smart-6891e8de-773f-44b7-9ceb-698c97e52898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258041471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.258041471
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3011753649
Short name T1145
Test name
Test status
Simulation time 23351988422 ps
CPU time 234.86 seconds
Started May 07 01:02:31 PM PDT 24
Finished May 07 01:06:28 PM PDT 24
Peak memory 216308 kb
Host smart-ca5189d3-504c-4d22-a374-f3d8b3a9c66b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011753649 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3011753649
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4095022500
Short name T899
Test name
Test status
Simulation time 6789921559 ps
CPU time 31.6 seconds
Started May 07 01:02:30 PM PDT 24
Finished May 07 01:03:04 PM PDT 24
Peak memory 200204 kb
Host smart-66b0aa40-8e3b-44f6-9a72-a3d3d03e5346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095022500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4095022500
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3127033890
Short name T436
Test name
Test status
Simulation time 42840105910 ps
CPU time 28.75 seconds
Started May 07 01:02:25 PM PDT 24
Finished May 07 01:02:55 PM PDT 24
Peak memory 200396 kb
Host smart-f67b707d-956b-413c-846e-0dda889b5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127033890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3127033890
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3279311432
Short name T555
Test name
Test status
Simulation time 19979951 ps
CPU time 0.56 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:02:42 PM PDT 24
Peak memory 195776 kb
Host smart-11baedaa-0ea6-4b8b-99e8-db20dbf96b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279311432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3279311432
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2864088719
Short name T1184
Test name
Test status
Simulation time 75635188629 ps
CPU time 546.74 seconds
Started May 07 01:02:32 PM PDT 24
Finished May 07 01:11:40 PM PDT 24
Peak memory 200392 kb
Host smart-4af7c796-6726-4253-92b2-f2944757c89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864088719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2864088719
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3417744833
Short name T570
Test name
Test status
Simulation time 136096964990 ps
CPU time 54.59 seconds
Started May 07 01:02:31 PM PDT 24
Finished May 07 01:03:27 PM PDT 24
Peak memory 199972 kb
Host smart-8d82745b-9117-4ebd-ba3a-c10a833546f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417744833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3417744833
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3670927287
Short name T940
Test name
Test status
Simulation time 223609959036 ps
CPU time 88.64 seconds
Started May 07 01:02:33 PM PDT 24
Finished May 07 01:04:03 PM PDT 24
Peak memory 200184 kb
Host smart-995c6e28-da1d-4b33-969b-c446d479a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670927287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3670927287
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3632101808
Short name T731
Test name
Test status
Simulation time 34404690054 ps
CPU time 13.89 seconds
Started May 07 01:02:32 PM PDT 24
Finished May 07 01:02:47 PM PDT 24
Peak memory 199348 kb
Host smart-1e5c234f-c13b-480b-b2ea-fff11d7cbcbc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632101808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3632101808
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3302107285
Short name T416
Test name
Test status
Simulation time 82596021059 ps
CPU time 552.55 seconds
Started May 07 01:02:41 PM PDT 24
Finished May 07 01:11:55 PM PDT 24
Peak memory 200364 kb
Host smart-991b93ea-3d07-4385-a5ce-8583dd98436f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302107285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3302107285
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1229936168
Short name T904
Test name
Test status
Simulation time 5542852974 ps
CPU time 3.33 seconds
Started May 07 01:02:39 PM PDT 24
Finished May 07 01:02:44 PM PDT 24
Peak memory 198556 kb
Host smart-1121eb70-eeb1-4714-876f-a243f0bb3448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229936168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1229936168
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4151915025
Short name T462
Test name
Test status
Simulation time 15124440535 ps
CPU time 27.21 seconds
Started May 07 01:02:39 PM PDT 24
Finished May 07 01:03:08 PM PDT 24
Peak memory 198648 kb
Host smart-dd198e42-6b6a-4c52-baba-097cb47cfc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151915025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4151915025
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.599289685
Short name T1125
Test name
Test status
Simulation time 11709778051 ps
CPU time 110.77 seconds
Started May 07 01:02:42 PM PDT 24
Finished May 07 01:04:35 PM PDT 24
Peak memory 200412 kb
Host smart-f8e1d84c-0b7a-4c55-ae6c-5554b815bab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599289685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.599289685
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3638093289
Short name T1049
Test name
Test status
Simulation time 5681755826 ps
CPU time 16.72 seconds
Started May 07 01:02:32 PM PDT 24
Finished May 07 01:02:50 PM PDT 24
Peak memory 199208 kb
Host smart-955a884f-460d-4cf6-8e65-d590fd6b10b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638093289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3638093289
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.677075774
Short name T371
Test name
Test status
Simulation time 56887436237 ps
CPU time 27.76 seconds
Started May 07 01:02:41 PM PDT 24
Finished May 07 01:03:11 PM PDT 24
Peak memory 200372 kb
Host smart-977623fb-801d-49b3-8dc9-67333a625806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677075774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.677075774
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.973208811
Short name T971
Test name
Test status
Simulation time 2407142045 ps
CPU time 1.35 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:02:43 PM PDT 24
Peak memory 196144 kb
Host smart-aeb9cd0c-6d83-4ab4-bdda-5dca20611d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973208811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.973208811
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2907220695
Short name T802
Test name
Test status
Simulation time 725325126 ps
CPU time 1.89 seconds
Started May 07 01:02:33 PM PDT 24
Finished May 07 01:02:36 PM PDT 24
Peak memory 199260 kb
Host smart-fe83df8c-1c24-463a-bd8b-16453ecd0816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907220695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2907220695
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3133400292
Short name T488
Test name
Test status
Simulation time 56178063234 ps
CPU time 89.79 seconds
Started May 07 01:02:41 PM PDT 24
Finished May 07 01:04:13 PM PDT 24
Peak memory 200680 kb
Host smart-631ab415-6735-4dc3-9eea-eacf1ca6db0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133400292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3133400292
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3241885750
Short name T625
Test name
Test status
Simulation time 193339265261 ps
CPU time 848.86 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:16:51 PM PDT 24
Peak memory 216828 kb
Host smart-4f00573d-651a-435e-b94f-856f4eaef6d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241885750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3241885750
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.207435336
Short name T1051
Test name
Test status
Simulation time 495031491 ps
CPU time 1.59 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:02:43 PM PDT 24
Peak memory 198768 kb
Host smart-b00c6963-5b96-4943-9dcd-96aa90ad37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207435336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.207435336
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1288756664
Short name T667
Test name
Test status
Simulation time 27256289742 ps
CPU time 48.02 seconds
Started May 07 01:02:32 PM PDT 24
Finished May 07 01:03:21 PM PDT 24
Peak memory 200260 kb
Host smart-03b84dec-a4ca-4b01-a4be-78d540411b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288756664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1288756664
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.908826725
Short name T417
Test name
Test status
Simulation time 22058835 ps
CPU time 0.57 seconds
Started May 07 01:02:46 PM PDT 24
Finished May 07 01:02:48 PM PDT 24
Peak memory 195800 kb
Host smart-339c02ba-1965-4079-a920-f7fdc69a76bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908826725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.908826725
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2207843027
Short name T419
Test name
Test status
Simulation time 251119056592 ps
CPU time 356.33 seconds
Started May 07 01:02:41 PM PDT 24
Finished May 07 01:08:39 PM PDT 24
Peak memory 200392 kb
Host smart-b7aeb53d-511e-417e-a4f0-b452fea9a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207843027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2207843027
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.1527081683
Short name T291
Test name
Test status
Simulation time 27010197080 ps
CPU time 45.14 seconds
Started May 07 01:02:42 PM PDT 24
Finished May 07 01:03:29 PM PDT 24
Peak memory 200296 kb
Host smart-d6cacf11-8614-4556-83fd-d8cd2114e1c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527081683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1527081683
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2058253017
Short name T376
Test name
Test status
Simulation time 62818729804 ps
CPU time 336.94 seconds
Started May 07 01:02:39 PM PDT 24
Finished May 07 01:08:18 PM PDT 24
Peak memory 200304 kb
Host smart-dc356f67-ac03-4f8a-a73f-53e386db835c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058253017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2058253017
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3851922340
Short name T365
Test name
Test status
Simulation time 6527378167 ps
CPU time 11.74 seconds
Started May 07 01:02:42 PM PDT 24
Finished May 07 01:02:55 PM PDT 24
Peak memory 199000 kb
Host smart-5163d5cd-eb3e-4a31-a245-b718f3583cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851922340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3851922340
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2077605925
Short name T1006
Test name
Test status
Simulation time 20839126342 ps
CPU time 19.93 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:03:01 PM PDT 24
Peak memory 199964 kb
Host smart-0559b224-67f3-4f06-aeb9-15f9a2866c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077605925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2077605925
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.174295328
Short name T384
Test name
Test status
Simulation time 23848950880 ps
CPU time 719.36 seconds
Started May 07 01:02:42 PM PDT 24
Finished May 07 01:14:43 PM PDT 24
Peak memory 200368 kb
Host smart-21db8bbc-1c15-4a7c-9848-6ae07932bb23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174295328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.174295328
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1206306260
Short name T395
Test name
Test status
Simulation time 6817203832 ps
CPU time 60.84 seconds
Started May 07 01:02:41 PM PDT 24
Finished May 07 01:03:44 PM PDT 24
Peak memory 198760 kb
Host smart-4f230d9c-c213-4c10-b6ee-19d36b365fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206306260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1206306260
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.836001028
Short name T900
Test name
Test status
Simulation time 41164192947 ps
CPU time 76.16 seconds
Started May 07 01:02:42 PM PDT 24
Finished May 07 01:04:00 PM PDT 24
Peak memory 200424 kb
Host smart-a1131e1d-5c82-4626-b346-4eed50663807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836001028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.836001028
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2015879097
Short name T867
Test name
Test status
Simulation time 5019797975 ps
CPU time 2.86 seconds
Started May 07 01:02:42 PM PDT 24
Finished May 07 01:02:47 PM PDT 24
Peak memory 196424 kb
Host smart-35d1df96-ab86-4020-9395-b0ff6d72fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015879097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2015879097
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3861658494
Short name T1086
Test name
Test status
Simulation time 299721286 ps
CPU time 0.99 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:02:42 PM PDT 24
Peak memory 200052 kb
Host smart-94aebde1-5d4a-4120-a4be-c147ffc6b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861658494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3861658494
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.145071991
Short name T402
Test name
Test status
Simulation time 194872973103 ps
CPU time 420.82 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:09:50 PM PDT 24
Peak memory 200440 kb
Host smart-9f837f4e-132a-42c9-831c-5caefdef494f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145071991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.145071991
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2663948756
Short name T775
Test name
Test status
Simulation time 92812636679 ps
CPU time 258.78 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 217264 kb
Host smart-5fde2838-4f5e-4c5d-8769-c15c45ac5397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663948756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2663948756
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3885614391
Short name T117
Test name
Test status
Simulation time 200330011 ps
CPU time 1.33 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:02:43 PM PDT 24
Peak memory 198860 kb
Host smart-ddfc5334-a8e7-4b26-b0db-3ab27d1e1334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885614391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3885614391
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.387366251
Short name T333
Test name
Test status
Simulation time 36345241895 ps
CPU time 54.77 seconds
Started May 07 01:02:40 PM PDT 24
Finished May 07 01:03:37 PM PDT 24
Peak memory 200372 kb
Host smart-46c7b24f-2008-4535-b434-44bdd7e52d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387366251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.387366251
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.306441227
Short name T439
Test name
Test status
Simulation time 20878472 ps
CPU time 0.57 seconds
Started May 07 01:02:48 PM PDT 24
Finished May 07 01:02:51 PM PDT 24
Peak memory 195748 kb
Host smart-ffefa5d7-c621-46bc-8e7a-f6dc98e123b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306441227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.306441227
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1929424627
Short name T454
Test name
Test status
Simulation time 161754896876 ps
CPU time 278.67 seconds
Started May 07 01:02:48 PM PDT 24
Finished May 07 01:07:29 PM PDT 24
Peak memory 200340 kb
Host smart-2b42a2e6-ac64-4a7d-8a44-a3a4667f7a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929424627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1929424627
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1150045016
Short name T183
Test name
Test status
Simulation time 90314432403 ps
CPU time 42.65 seconds
Started May 07 01:02:49 PM PDT 24
Finished May 07 01:03:33 PM PDT 24
Peak memory 200360 kb
Host smart-05d7dad6-08d4-4f76-b86e-2b9bfc7b4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150045016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1150045016
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2613360046
Short name T405
Test name
Test status
Simulation time 226955496610 ps
CPU time 28.65 seconds
Started May 07 01:02:48 PM PDT 24
Finished May 07 01:03:19 PM PDT 24
Peak memory 200388 kb
Host smart-6709fd6e-3ee7-4930-9ca1-55004aeb6de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613360046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2613360046
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.600135672
Short name T1050
Test name
Test status
Simulation time 20936689407 ps
CPU time 32.99 seconds
Started May 07 01:02:50 PM PDT 24
Finished May 07 01:03:25 PM PDT 24
Peak memory 200224 kb
Host smart-465e36bf-0daa-49df-95e1-6fe77bf4669c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600135672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.600135672
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2111271762
Short name T1005
Test name
Test status
Simulation time 80129588961 ps
CPU time 408.49 seconds
Started May 07 01:02:49 PM PDT 24
Finished May 07 01:09:39 PM PDT 24
Peak memory 200380 kb
Host smart-541608cf-d18c-480b-b66e-8411380f14bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111271762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2111271762
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3194331786
Short name T363
Test name
Test status
Simulation time 93910229 ps
CPU time 1.22 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:02:51 PM PDT 24
Peak memory 199052 kb
Host smart-e2f81849-afce-45b9-b96b-d136722c2649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194331786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3194331786
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2405816963
Short name T760
Test name
Test status
Simulation time 14628726987 ps
CPU time 12.36 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:03:02 PM PDT 24
Peak memory 200344 kb
Host smart-ebda6814-df25-4de5-af67-5c3c3e6c5c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405816963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2405816963
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2747239062
Short name T523
Test name
Test status
Simulation time 5403646565 ps
CPU time 326.17 seconds
Started May 07 01:02:48 PM PDT 24
Finished May 07 01:08:16 PM PDT 24
Peak memory 200392 kb
Host smart-22ad1177-0137-43e7-8b3e-358ef895725a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747239062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2747239062
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.599689373
Short name T868
Test name
Test status
Simulation time 2848761085 ps
CPU time 8.63 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:02:58 PM PDT 24
Peak memory 198568 kb
Host smart-0566e128-7e57-4284-91ed-7931aa4e1181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599689373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.599689373
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1250921932
Short name T715
Test name
Test status
Simulation time 118007052021 ps
CPU time 186.49 seconds
Started May 07 01:02:50 PM PDT 24
Finished May 07 01:05:58 PM PDT 24
Peak memory 200000 kb
Host smart-2d599246-6231-4c71-b4bc-979e504cd41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250921932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1250921932
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.116063694
Short name T507
Test name
Test status
Simulation time 2911107515 ps
CPU time 1.55 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:02:50 PM PDT 24
Peak memory 196152 kb
Host smart-f1c75dd7-26c5-4fe5-894f-fe8b9c73a566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116063694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.116063694
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2908710589
Short name T862
Test name
Test status
Simulation time 5676719914 ps
CPU time 10.15 seconds
Started May 07 01:02:48 PM PDT 24
Finished May 07 01:03:00 PM PDT 24
Peak memory 200088 kb
Host smart-9bfe322c-c4d5-4033-a77a-31d682e4da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908710589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2908710589
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3624634150
Short name T757
Test name
Test status
Simulation time 198890629550 ps
CPU time 106.32 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:04:36 PM PDT 24
Peak memory 200392 kb
Host smart-bf717b84-8a5e-47d9-9a0a-5cb16b9840c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624634150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3624634150
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.4205303899
Short name T961
Test name
Test status
Simulation time 422669950030 ps
CPU time 1409.7 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:26:19 PM PDT 24
Peak memory 226168 kb
Host smart-47f25773-e634-467f-8e73-d9b04c1501da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205303899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.4205303899
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2180355434
Short name T571
Test name
Test status
Simulation time 6083275733 ps
CPU time 1.62 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:02:51 PM PDT 24
Peak memory 199360 kb
Host smart-54c59b8e-28f6-4485-9de5-661281ea4277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180355434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2180355434
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3978620472
Short name T664
Test name
Test status
Simulation time 69918102171 ps
CPU time 40.99 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:03:30 PM PDT 24
Peak memory 200384 kb
Host smart-a08d20b5-379d-4db3-a59c-5523b80d6b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978620472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3978620472
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2091687593
Short name T848
Test name
Test status
Simulation time 24786925 ps
CPU time 0.57 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:02:58 PM PDT 24
Peak memory 195804 kb
Host smart-6f13c157-7960-4f21-acf6-65902d9bdd40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091687593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2091687593
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.471718075
Short name T1185
Test name
Test status
Simulation time 131561632067 ps
CPU time 166.7 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:05:35 PM PDT 24
Peak memory 200376 kb
Host smart-6975afe8-a9f7-4acc-8168-7b6ed356bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471718075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.471718075
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1985352006
Short name T736
Test name
Test status
Simulation time 127175900564 ps
CPU time 223.25 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:06:39 PM PDT 24
Peak memory 199520 kb
Host smart-75761f44-d893-4281-a97c-7a7ee42ea4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985352006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1985352006
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2873511550
Short name T987
Test name
Test status
Simulation time 153163321443 ps
CPU time 156.81 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:05:33 PM PDT 24
Peak memory 200436 kb
Host smart-137acb2d-7f61-47c0-8369-99c53d9a4855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873511550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2873511550
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2966414919
Short name T666
Test name
Test status
Simulation time 110853028132 ps
CPU time 662.31 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:13:59 PM PDT 24
Peak memory 200396 kb
Host smart-e1a964af-25a3-4be2-a5ce-cb0e0b939788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966414919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2966414919
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3017484313
Short name T911
Test name
Test status
Simulation time 6016618123 ps
CPU time 6.34 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:03:04 PM PDT 24
Peak memory 199756 kb
Host smart-0a32d2cf-f98f-4f68-8fd2-7293ba472f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017484313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3017484313
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2551819474
Short name T259
Test name
Test status
Simulation time 113743759152 ps
CPU time 92.55 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:04:30 PM PDT 24
Peak memory 200600 kb
Host smart-a1078e54-e20d-46d7-bae6-66a5d3806bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551819474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2551819474
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1708689242
Short name T40
Test name
Test status
Simulation time 4099274350 ps
CPU time 114.65 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:04:51 PM PDT 24
Peak memory 200460 kb
Host smart-1f390a1c-8eae-4dae-b2f4-9b2cbd18b864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708689242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1708689242
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3821649398
Short name T728
Test name
Test status
Simulation time 7841929325 ps
CPU time 18.07 seconds
Started May 07 01:02:54 PM PDT 24
Finished May 07 01:03:14 PM PDT 24
Peak memory 199664 kb
Host smart-4a9e8137-fd2c-4f09-a575-4fbb12ce9245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821649398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3821649398
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.4179643070
Short name T161
Test name
Test status
Simulation time 114456931698 ps
CPU time 208.93 seconds
Started May 07 01:02:57 PM PDT 24
Finished May 07 01:06:27 PM PDT 24
Peak memory 200404 kb
Host smart-62f017d9-c054-471b-9f04-06ae6e05c3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179643070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.4179643070
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1030042311
Short name T633
Test name
Test status
Simulation time 36567048460 ps
CPU time 5.41 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:03:03 PM PDT 24
Peak memory 196148 kb
Host smart-bf2703f2-7b66-479c-b624-7b630bb30b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030042311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1030042311
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2633510531
Short name T1018
Test name
Test status
Simulation time 475423310 ps
CPU time 2.18 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:02:52 PM PDT 24
Peak memory 199980 kb
Host smart-a546ce2d-09a9-4bf6-ad1f-aec952cd235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633510531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2633510531
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.764268307
Short name T615
Test name
Test status
Simulation time 182427292926 ps
CPU time 535.19 seconds
Started May 07 01:02:54 PM PDT 24
Finished May 07 01:11:50 PM PDT 24
Peak memory 200396 kb
Host smart-7f237051-de0f-4c79-8564-4576a7629177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764268307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.764268307
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3024976139
Short name T52
Test name
Test status
Simulation time 117885745625 ps
CPU time 693.06 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:14:29 PM PDT 24
Peak memory 225336 kb
Host smart-b08e4206-5942-4aa4-889a-6af96d4c9458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024976139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3024976139
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.366181620
Short name T805
Test name
Test status
Simulation time 1565743736 ps
CPU time 2.09 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:02:59 PM PDT 24
Peak memory 198868 kb
Host smart-0dc9a753-6f6e-44db-8251-3557c79eae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366181620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.366181620
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3513288867
Short name T1105
Test name
Test status
Simulation time 121091964644 ps
CPU time 316.6 seconds
Started May 07 01:02:47 PM PDT 24
Finished May 07 01:08:06 PM PDT 24
Peak memory 200376 kb
Host smart-b3f2d1da-fcc2-446b-b8f0-59dc5c4fd081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513288867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3513288867
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1393089333
Short name T358
Test name
Test status
Simulation time 11087417 ps
CPU time 0.59 seconds
Started May 07 01:03:05 PM PDT 24
Finished May 07 01:03:07 PM PDT 24
Peak memory 195436 kb
Host smart-99703244-f287-4a10-b7fc-ce75dafb4d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393089333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1393089333
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.858334124
Short name T638
Test name
Test status
Simulation time 101531217643 ps
CPU time 61.03 seconds
Started May 07 01:02:57 PM PDT 24
Finished May 07 01:03:59 PM PDT 24
Peak memory 200356 kb
Host smart-00397c78-142f-43e6-a917-79f45bdcdab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858334124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.858334124
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1725130930
Short name T518
Test name
Test status
Simulation time 57464921260 ps
CPU time 97.2 seconds
Started May 07 01:02:58 PM PDT 24
Finished May 07 01:04:36 PM PDT 24
Peak memory 200424 kb
Host smart-f66dd4c0-8c9a-4dea-82bc-e59f2b0f9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725130930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1725130930
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.138210824
Short name T20
Test name
Test status
Simulation time 44439388053 ps
CPU time 68.8 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:04:06 PM PDT 24
Peak memory 200312 kb
Host smart-7a325b70-deaa-43ce-ad70-bd81360a9d97
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138210824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.138210824
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4262313395
Short name T346
Test name
Test status
Simulation time 119457615380 ps
CPU time 715.82 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:14:53 PM PDT 24
Peak memory 200396 kb
Host smart-64c1e950-1437-433c-9391-a2dab6861f9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262313395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4262313395
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2170014506
Short name T989
Test name
Test status
Simulation time 8433778120 ps
CPU time 17.15 seconds
Started May 07 01:02:54 PM PDT 24
Finished May 07 01:03:13 PM PDT 24
Peak memory 200320 kb
Host smart-b0f2972d-d22a-4eb6-be62-c8bd9cbf9951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170014506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2170014506
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3037911703
Short name T303
Test name
Test status
Simulation time 59622708976 ps
CPU time 49.36 seconds
Started May 07 01:02:54 PM PDT 24
Finished May 07 01:03:44 PM PDT 24
Peak memory 200268 kb
Host smart-bad35d44-2a6a-4d4f-baeb-15383ea1b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037911703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3037911703
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.419156205
Short name T635
Test name
Test status
Simulation time 6926963162 ps
CPU time 201.06 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:06:17 PM PDT 24
Peak memory 200424 kb
Host smart-da00170b-063f-421f-a375-2b8633d9f565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419156205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.419156205
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3593475820
Short name T831
Test name
Test status
Simulation time 5363309606 ps
CPU time 9.61 seconds
Started May 07 01:02:57 PM PDT 24
Finished May 07 01:03:08 PM PDT 24
Peak memory 199020 kb
Host smart-18f60eb0-336f-44cd-9ed3-420fdf2cc753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593475820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3593475820
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3201001465
Short name T1043
Test name
Test status
Simulation time 144890897131 ps
CPU time 126.55 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:05:04 PM PDT 24
Peak memory 200404 kb
Host smart-b144620a-98e8-4891-83a9-9c6651eec185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201001465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3201001465
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1632047122
Short name T972
Test name
Test status
Simulation time 26427062795 ps
CPU time 45.25 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:03:42 PM PDT 24
Peak memory 196144 kb
Host smart-67025964-89cf-4fab-8176-58df3ad1cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632047122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1632047122
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3169045288
Short name T699
Test name
Test status
Simulation time 6331027354 ps
CPU time 17.77 seconds
Started May 07 01:02:57 PM PDT 24
Finished May 07 01:03:16 PM PDT 24
Peak memory 200148 kb
Host smart-0591e955-d3df-4144-b4d2-b5bf23623de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169045288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3169045288
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2709300784
Short name T973
Test name
Test status
Simulation time 9097801373 ps
CPU time 134.92 seconds
Started May 07 01:02:56 PM PDT 24
Finished May 07 01:05:12 PM PDT 24
Peak memory 208928 kb
Host smart-2fa4807c-9e0a-4c34-9462-addd875001d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709300784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2709300784
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3061695367
Short name T389
Test name
Test status
Simulation time 471092209 ps
CPU time 1.62 seconds
Started May 07 01:02:57 PM PDT 24
Finished May 07 01:02:59 PM PDT 24
Peak memory 198144 kb
Host smart-4f912787-3770-42db-adb8-d4c062190ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061695367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3061695367
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2815796125
Short name T811
Test name
Test status
Simulation time 196226709606 ps
CPU time 29.8 seconds
Started May 07 01:02:55 PM PDT 24
Finished May 07 01:03:26 PM PDT 24
Peak memory 200404 kb
Host smart-99fd06b3-5ddb-4d1a-8e70-47fd5b8d3868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815796125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2815796125
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.817178972
Short name T691
Test name
Test status
Simulation time 30000984 ps
CPU time 0.56 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:03:03 PM PDT 24
Peak memory 195804 kb
Host smart-147613d1-6a0f-41b3-926a-03a866eb498e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817178972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.817178972
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.587122225
Short name T398
Test name
Test status
Simulation time 123600624673 ps
CPU time 241.72 seconds
Started May 07 01:03:05 PM PDT 24
Finished May 07 01:07:08 PM PDT 24
Peak memory 200356 kb
Host smart-6afcb5f3-3d93-4cd2-94f5-d7a5d14867b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587122225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.587122225
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3393947120
Short name T160
Test name
Test status
Simulation time 156768405465 ps
CPU time 63.93 seconds
Started May 07 01:03:02 PM PDT 24
Finished May 07 01:04:08 PM PDT 24
Peak memory 200464 kb
Host smart-d54bafb2-8ab0-442d-b76f-a9753cd49bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393947120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3393947120
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1256446145
Short name T251
Test name
Test status
Simulation time 110053442858 ps
CPU time 31.07 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:03:33 PM PDT 24
Peak memory 200448 kb
Host smart-0242db0d-dd9c-4a52-afb0-fb47d2ab0b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256446145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1256446145
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2314114078
Short name T1103
Test name
Test status
Simulation time 267937109541 ps
CPU time 424.3 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:10:06 PM PDT 24
Peak memory 200052 kb
Host smart-09346d13-cad5-436d-a0c7-cbd6b61e1ca2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314114078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2314114078
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.53166261
Short name T36
Test name
Test status
Simulation time 73091551081 ps
CPU time 296.57 seconds
Started May 07 01:03:02 PM PDT 24
Finished May 07 01:08:00 PM PDT 24
Peak memory 200416 kb
Host smart-c2a4146c-e92e-4cee-98ba-45c0f4c886fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53166261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.53166261
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3871100965
Short name T718
Test name
Test status
Simulation time 7388918927 ps
CPU time 13.3 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:03:16 PM PDT 24
Peak memory 197764 kb
Host smart-ebb30948-fd5c-409e-8959-41a1f42e1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871100965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3871100965
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.897539566
Short name T552
Test name
Test status
Simulation time 17778763535 ps
CPU time 15.62 seconds
Started May 07 01:03:03 PM PDT 24
Finished May 07 01:03:19 PM PDT 24
Peak memory 196684 kb
Host smart-5fc2437c-48f4-426c-af96-3a6a0ec2491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897539566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.897539566
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2135899135
Short name T642
Test name
Test status
Simulation time 14968011966 ps
CPU time 795.43 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:16:18 PM PDT 24
Peak memory 200412 kb
Host smart-1bdcbd2a-174c-4975-8d63-6adb62dbe6a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135899135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2135899135
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2293729148
Short name T713
Test name
Test status
Simulation time 7179311702 ps
CPU time 10.31 seconds
Started May 07 01:03:05 PM PDT 24
Finished May 07 01:03:16 PM PDT 24
Peak memory 198660 kb
Host smart-72b8094c-6265-411d-8a24-6de7bc95fa30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293729148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2293729148
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1460703503
Short name T153
Test name
Test status
Simulation time 271345562229 ps
CPU time 48.68 seconds
Started May 07 01:03:02 PM PDT 24
Finished May 07 01:03:52 PM PDT 24
Peak memory 200240 kb
Host smart-916f1488-2b89-4166-8869-116a706f1cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460703503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1460703503
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.4280305626
Short name T872
Test name
Test status
Simulation time 4268564503 ps
CPU time 1.72 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:03:04 PM PDT 24
Peak memory 196424 kb
Host smart-6cff199f-89ff-4505-9218-4961083d2310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280305626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.4280305626
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3232521464
Short name T45
Test name
Test status
Simulation time 524672633 ps
CPU time 1.43 seconds
Started May 07 01:03:01 PM PDT 24
Finished May 07 01:03:03 PM PDT 24
Peak memory 200312 kb
Host smart-66f8a405-66b8-47b7-aaf7-1817d420b8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232521464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3232521464
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.233024554
Short name T133
Test name
Test status
Simulation time 196808551212 ps
CPU time 165.85 seconds
Started May 07 01:03:02 PM PDT 24
Finished May 07 01:05:49 PM PDT 24
Peak memory 200424 kb
Host smart-e49aae5e-44a2-4c9b-b851-4ed665be8b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233024554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.233024554
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1764866929
Short name T964
Test name
Test status
Simulation time 24497929398 ps
CPU time 286.94 seconds
Started May 07 01:03:05 PM PDT 24
Finished May 07 01:07:53 PM PDT 24
Peak memory 217064 kb
Host smart-7e76fadb-e719-4ac5-bf23-1ec0b9e2e8e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764866929 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1764866929
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.275953883
Short name T1025
Test name
Test status
Simulation time 961299632 ps
CPU time 3.46 seconds
Started May 07 01:03:02 PM PDT 24
Finished May 07 01:03:07 PM PDT 24
Peak memory 199184 kb
Host smart-ba01287c-f70f-4944-8a7e-2bcf2b9a1eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275953883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.275953883
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.504674236
Short name T113
Test name
Test status
Simulation time 45560129661 ps
CPU time 81.39 seconds
Started May 07 01:03:03 PM PDT 24
Finished May 07 01:04:26 PM PDT 24
Peak memory 200452 kb
Host smart-f2c037c1-ee31-481f-8e4e-eafeb6123996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504674236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.504674236
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.56877587
Short name T707
Test name
Test status
Simulation time 42590121 ps
CPU time 0.54 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:12 PM PDT 24
Peak memory 194788 kb
Host smart-969e4be5-f163-4369-b026-649ba6b1a074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56877587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.56877587
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.342988482
Short name T806
Test name
Test status
Simulation time 54055483749 ps
CPU time 108.54 seconds
Started May 07 01:03:12 PM PDT 24
Finished May 07 01:05:02 PM PDT 24
Peak memory 200380 kb
Host smart-fc9fa7f5-bd4b-44ca-a62e-aa55464dca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342988482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.342988482
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.222725623
Short name T1034
Test name
Test status
Simulation time 23219639082 ps
CPU time 21.32 seconds
Started May 07 01:03:11 PM PDT 24
Finished May 07 01:03:33 PM PDT 24
Peak memory 200412 kb
Host smart-1b0e7e8f-e74b-401a-b5ca-6167e611da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222725623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.222725623
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3409552478
Short name T406
Test name
Test status
Simulation time 27933589436 ps
CPU time 36.89 seconds
Started May 07 01:03:11 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 200284 kb
Host smart-d395ca4f-8301-4618-bcf0-ec4b925d0d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409552478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3409552478
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3265771609
Short name T992
Test name
Test status
Simulation time 41932500901 ps
CPU time 65.39 seconds
Started May 07 01:03:12 PM PDT 24
Finished May 07 01:04:18 PM PDT 24
Peak memory 200412 kb
Host smart-1760cf36-e9e4-4061-a7e5-f51094373da9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265771609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3265771609
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.910673259
Short name T870
Test name
Test status
Simulation time 80221116193 ps
CPU time 243.95 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 200404 kb
Host smart-b743c291-027c-4c3d-8e3b-03d302697713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910673259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.910673259
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1671176763
Short name T851
Test name
Test status
Simulation time 4749060532 ps
CPU time 6.66 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:18 PM PDT 24
Peak memory 200132 kb
Host smart-fdc5a82d-e300-4e57-af96-e3cc5ccc6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671176763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1671176763
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3809781136
Short name T823
Test name
Test status
Simulation time 37149761233 ps
CPU time 29.2 seconds
Started May 07 01:03:09 PM PDT 24
Finished May 07 01:03:39 PM PDT 24
Peak memory 200452 kb
Host smart-a6ebda6c-a3c0-42a4-bad1-920bed7e8099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809781136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3809781136
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2214156774
Short name T1136
Test name
Test status
Simulation time 20443508615 ps
CPU time 506.1 seconds
Started May 07 01:03:09 PM PDT 24
Finished May 07 01:11:36 PM PDT 24
Peak memory 200348 kb
Host smart-25b8421b-cfa0-44a4-81f1-ae906ace8418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214156774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2214156774
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3161628619
Short name T1153
Test name
Test status
Simulation time 2672356730 ps
CPU time 5.14 seconds
Started May 07 01:03:09 PM PDT 24
Finished May 07 01:03:15 PM PDT 24
Peak memory 198540 kb
Host smart-fca6f8c5-dd4c-4544-9d1c-8d9e5249fe22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161628619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3161628619
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1999178773
Short name T116
Test name
Test status
Simulation time 19233751965 ps
CPU time 27.23 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:39 PM PDT 24
Peak memory 200412 kb
Host smart-dbdbc930-bea4-490a-b317-00a5329d3bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999178773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1999178773
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1916375288
Short name T586
Test name
Test status
Simulation time 4193536563 ps
CPU time 2.1 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:14 PM PDT 24
Peak memory 196732 kb
Host smart-6da7f622-0a4f-4c55-b8b5-6772b80b866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916375288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1916375288
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1050671466
Short name T834
Test name
Test status
Simulation time 524775714 ps
CPU time 1.25 seconds
Started May 07 01:03:03 PM PDT 24
Finished May 07 01:03:06 PM PDT 24
Peak memory 198740 kb
Host smart-aad33938-e8ed-4ccc-9e38-d3ec336febfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050671466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1050671466
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2734602748
Short name T1160
Test name
Test status
Simulation time 133113372979 ps
CPU time 44.53 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:56 PM PDT 24
Peak memory 200404 kb
Host smart-92ce3c54-30c0-42db-83d4-f472d720a690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734602748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2734602748
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.511528103
Short name T80
Test name
Test status
Simulation time 209077464955 ps
CPU time 1286.4 seconds
Started May 07 01:03:13 PM PDT 24
Finished May 07 01:24:40 PM PDT 24
Peak memory 224916 kb
Host smart-89e17b88-3390-47e1-8223-16bb6c443cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511528103 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.511528103
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1353164578
Short name T370
Test name
Test status
Simulation time 800860468 ps
CPU time 1.8 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:13 PM PDT 24
Peak memory 199148 kb
Host smart-07c9355d-a367-498f-b010-b1a1d5af5960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353164578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1353164578
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4144421276
Short name T563
Test name
Test status
Simulation time 52157818426 ps
CPU time 19.37 seconds
Started May 07 01:03:03 PM PDT 24
Finished May 07 01:03:23 PM PDT 24
Peak memory 200252 kb
Host smart-ae77793d-2d87-4693-bd85-f5704daf5a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144421276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4144421276
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.315923929
Short name T23
Test name
Test status
Simulation time 23794088 ps
CPU time 0.56 seconds
Started May 07 01:00:16 PM PDT 24
Finished May 07 01:00:18 PM PDT 24
Peak memory 195820 kb
Host smart-3215b9a4-02ae-417a-8cab-f15e8c328be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315923929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.315923929
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3495109784
Short name T735
Test name
Test status
Simulation time 34072208843 ps
CPU time 14.42 seconds
Started May 07 01:00:12 PM PDT 24
Finished May 07 01:00:27 PM PDT 24
Peak memory 200260 kb
Host smart-dd80be13-27fa-4056-bae3-e5b952019a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495109784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3495109784
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4248733945
Short name T567
Test name
Test status
Simulation time 127445997074 ps
CPU time 59.53 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:01:14 PM PDT 24
Peak memory 200328 kb
Host smart-b9bb5200-9dda-41ba-a948-919f7b258331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248733945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4248733945
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2193172477
Short name T656
Test name
Test status
Simulation time 177301527401 ps
CPU time 301.11 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:05:18 PM PDT 24
Peak memory 200432 kb
Host smart-174dcd26-a029-4878-88b7-9824767312e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193172477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2193172477
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2649490214
Short name T300
Test name
Test status
Simulation time 262531915638 ps
CPU time 83.96 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:01:41 PM PDT 24
Peak memory 199676 kb
Host smart-ee0e7e88-0481-4e95-8dc9-1c65ee801efb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649490214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2649490214
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1853544551
Short name T1114
Test name
Test status
Simulation time 259095908164 ps
CPU time 666.86 seconds
Started May 07 01:00:14 PM PDT 24
Finished May 07 01:11:22 PM PDT 24
Peak memory 200352 kb
Host smart-1f071a28-e2bb-47e5-a101-691c7dcb1747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853544551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1853544551
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2645388129
Short name T565
Test name
Test status
Simulation time 3877749377 ps
CPU time 2.85 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:19 PM PDT 24
Peak memory 199364 kb
Host smart-8d28dcca-3b9a-4291-9ab0-1d8f9ba3a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645388129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2645388129
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3855651298
Short name T1014
Test name
Test status
Simulation time 45150096510 ps
CPU time 28.57 seconds
Started May 07 01:00:14 PM PDT 24
Finished May 07 01:00:44 PM PDT 24
Peak memory 198848 kb
Host smart-40a5cd2c-995f-4959-895b-b2b7018c071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855651298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3855651298
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2982770636
Short name T268
Test name
Test status
Simulation time 23204268570 ps
CPU time 185.89 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:03:23 PM PDT 24
Peak memory 200312 kb
Host smart-5e1365fe-6ea8-48cc-b01a-0b87bd3f2f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982770636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2982770636
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1775799294
Short name T345
Test name
Test status
Simulation time 4100091504 ps
CPU time 31.48 seconds
Started May 07 01:00:11 PM PDT 24
Finished May 07 01:00:44 PM PDT 24
Peak memory 198808 kb
Host smart-a9c9f289-5b5f-49d6-a01f-73aa0e34df22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775799294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1775799294
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1996241391
Short name T923
Test name
Test status
Simulation time 24296248071 ps
CPU time 11.65 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:00:25 PM PDT 24
Peak memory 200336 kb
Host smart-925bb95e-19d7-4f9f-9f38-da35d1da8376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996241391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1996241391
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.680587262
Short name T916
Test name
Test status
Simulation time 53867590288 ps
CPU time 30.3 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:00:44 PM PDT 24
Peak memory 196412 kb
Host smart-d7b27da1-886b-46c6-a2b7-44d71b644c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680587262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.680587262
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.40526023
Short name T27
Test name
Test status
Simulation time 287780112 ps
CPU time 0.83 seconds
Started May 07 01:00:17 PM PDT 24
Finished May 07 01:00:19 PM PDT 24
Peak memory 218276 kb
Host smart-934be793-5a23-4bb7-a1d7-8f1554f9415c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40526023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.40526023
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3226483033
Short name T839
Test name
Test status
Simulation time 288535297 ps
CPU time 1.15 seconds
Started May 07 01:00:17 PM PDT 24
Finished May 07 01:00:19 PM PDT 24
Peak memory 198380 kb
Host smart-ca1c3ab9-c4bb-439f-be25-ff0c37a0800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226483033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3226483033
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.533980394
Short name T777
Test name
Test status
Simulation time 121248330469 ps
CPU time 41.52 seconds
Started May 07 01:00:14 PM PDT 24
Finished May 07 01:00:57 PM PDT 24
Peak memory 216936 kb
Host smart-da1c822e-51ec-4962-af07-36422788df35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533980394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.533980394
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3347688453
Short name T756
Test name
Test status
Simulation time 118524186901 ps
CPU time 218.95 seconds
Started May 07 01:00:13 PM PDT 24
Finished May 07 01:03:53 PM PDT 24
Peak memory 216904 kb
Host smart-dbc34e0d-8a50-46ba-baff-74671a51605c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347688453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3347688453
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3779320420
Short name T1054
Test name
Test status
Simulation time 3587104426 ps
CPU time 2.08 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:00:18 PM PDT 24
Peak memory 200404 kb
Host smart-804db04f-94cd-42f7-a85d-42488b6bdc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779320420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3779320420
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2564158762
Short name T767
Test name
Test status
Simulation time 93635410558 ps
CPU time 94.14 seconds
Started May 07 01:00:12 PM PDT 24
Finished May 07 01:01:47 PM PDT 24
Peak memory 200460 kb
Host smart-e274b63c-7e05-4a17-a815-0252f0342288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564158762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2564158762
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1228876384
Short name T770
Test name
Test status
Simulation time 36127475 ps
CPU time 0.56 seconds
Started May 07 01:03:18 PM PDT 24
Finished May 07 01:03:19 PM PDT 24
Peak memory 195196 kb
Host smart-bce7f401-9931-448d-a6b6-58a8e4f8a7b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228876384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1228876384
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3326845404
Short name T859
Test name
Test status
Simulation time 90697871771 ps
CPU time 84.48 seconds
Started May 07 01:03:12 PM PDT 24
Finished May 07 01:04:37 PM PDT 24
Peak memory 200460 kb
Host smart-7e5a4379-e9f8-4555-bd36-165b6a87f569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326845404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3326845404
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1455838809
Short name T892
Test name
Test status
Simulation time 150034085177 ps
CPU time 103.75 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:04:55 PM PDT 24
Peak memory 200376 kb
Host smart-76e2e3f7-3352-4e3d-98d6-cea741eb7956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455838809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1455838809
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.227952959
Short name T695
Test name
Test status
Simulation time 41241361371 ps
CPU time 33.32 seconds
Started May 07 01:03:09 PM PDT 24
Finished May 07 01:03:43 PM PDT 24
Peak memory 200448 kb
Host smart-db5aa377-a764-478d-bd72-e5100153c8d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227952959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.227952959
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3851919052
Short name T723
Test name
Test status
Simulation time 154588049885 ps
CPU time 467.48 seconds
Started May 07 01:03:20 PM PDT 24
Finished May 07 01:11:08 PM PDT 24
Peak memory 200300 kb
Host smart-1f7797d2-0ecc-408d-b42e-706175ab204f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851919052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3851919052
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2855325402
Short name T738
Test name
Test status
Simulation time 8906671972 ps
CPU time 19.74 seconds
Started May 07 01:03:20 PM PDT 24
Finished May 07 01:03:41 PM PDT 24
Peak memory 199896 kb
Host smart-c49bfb4c-0075-4553-8200-db0b2457c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855325402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2855325402
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.4257037227
Short name T47
Test name
Test status
Simulation time 91940652578 ps
CPU time 13.68 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:25 PM PDT 24
Peak memory 200344 kb
Host smart-85646031-9a78-4885-91cc-53d7b2923678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257037227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4257037227
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.187243979
Short name T1076
Test name
Test status
Simulation time 20294410668 ps
CPU time 151.76 seconds
Started May 07 01:03:17 PM PDT 24
Finished May 07 01:05:50 PM PDT 24
Peak memory 200364 kb
Host smart-84deba46-563f-495c-a4c8-002eb78ad486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187243979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.187243979
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.699429449
Short name T327
Test name
Test status
Simulation time 5761118245 ps
CPU time 47.52 seconds
Started May 07 01:03:11 PM PDT 24
Finished May 07 01:04:00 PM PDT 24
Peak memory 199088 kb
Host smart-c4d23fba-a1f7-445a-bb20-8f7abf0d274f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699429449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.699429449
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.539708294
Short name T929
Test name
Test status
Simulation time 62556671428 ps
CPU time 93.02 seconds
Started May 07 01:03:17 PM PDT 24
Finished May 07 01:04:51 PM PDT 24
Peak memory 200252 kb
Host smart-f1e8c657-2187-4848-928c-090f9a72570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539708294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.539708294
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.734752188
Short name T1044
Test name
Test status
Simulation time 46460589035 ps
CPU time 19.41 seconds
Started May 07 01:03:11 PM PDT 24
Finished May 07 01:03:31 PM PDT 24
Peak memory 196136 kb
Host smart-db6c3ea4-20c7-49fd-a40b-acfd134e78de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734752188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.734752188
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2562500056
Short name T453
Test name
Test status
Simulation time 900475902 ps
CPU time 2.26 seconds
Started May 07 01:03:10 PM PDT 24
Finished May 07 01:03:14 PM PDT 24
Peak memory 199948 kb
Host smart-5bd85840-0d7a-47bc-b92c-c39e514f28fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562500056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2562500056
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.4223910042
Short name T1171
Test name
Test status
Simulation time 82350909202 ps
CPU time 116.63 seconds
Started May 07 01:03:19 PM PDT 24
Finished May 07 01:05:17 PM PDT 24
Peak memory 200448 kb
Host smart-1b7c7c70-d225-489c-950c-1ad2b5dc4288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223910042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.4223910042
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3826580710
Short name T740
Test name
Test status
Simulation time 12253847800 ps
CPU time 48.12 seconds
Started May 07 01:03:16 PM PDT 24
Finished May 07 01:04:05 PM PDT 24
Peak memory 216832 kb
Host smart-b9f11c9f-daa3-4086-8f1b-55285c162d93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826580710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3826580710
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.988960549
Short name T450
Test name
Test status
Simulation time 6831835171 ps
CPU time 16.1 seconds
Started May 07 01:03:19 PM PDT 24
Finished May 07 01:03:37 PM PDT 24
Peak memory 200332 kb
Host smart-bb934e02-ff48-440e-8d10-13f92df7d371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988960549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.988960549
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1487969446
Short name T561
Test name
Test status
Simulation time 9562172522 ps
CPU time 21.08 seconds
Started May 07 01:03:12 PM PDT 24
Finished May 07 01:03:34 PM PDT 24
Peak memory 200436 kb
Host smart-2fb95564-681e-43af-9eae-ed4380a8e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487969446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1487969446
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.993637294
Short name T690
Test name
Test status
Simulation time 71412699 ps
CPU time 0.56 seconds
Started May 07 01:03:30 PM PDT 24
Finished May 07 01:03:32 PM PDT 24
Peak memory 194768 kb
Host smart-c32552f2-d94e-4dad-9a08-c9960d42edab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993637294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.993637294
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1817976630
Short name T1066
Test name
Test status
Simulation time 20584272920 ps
CPU time 16.39 seconds
Started May 07 01:03:17 PM PDT 24
Finished May 07 01:03:34 PM PDT 24
Peak memory 200432 kb
Host smart-23a00653-4601-45a0-acb3-01859595f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817976630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1817976630
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3780046659
Short name T902
Test name
Test status
Simulation time 31531849897 ps
CPU time 42.2 seconds
Started May 07 01:03:18 PM PDT 24
Finished May 07 01:04:01 PM PDT 24
Peak memory 200396 kb
Host smart-8a1d9042-fa08-4892-829e-8ae802cfa691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780046659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3780046659
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3859728755
Short name T990
Test name
Test status
Simulation time 16460923327 ps
CPU time 27.63 seconds
Started May 07 01:03:20 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 200428 kb
Host smart-3335f59e-3c71-4892-8030-ef3815fefccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859728755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3859728755
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1431179481
Short name T1037
Test name
Test status
Simulation time 254641927913 ps
CPU time 428.74 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:10:43 PM PDT 24
Peak memory 199024 kb
Host smart-cb44b744-78ab-4bac-a5d1-569f0e38e9af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431179481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1431179481
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1844794137
Short name T472
Test name
Test status
Simulation time 97526998412 ps
CPU time 319.04 seconds
Started May 07 01:03:24 PM PDT 24
Finished May 07 01:08:44 PM PDT 24
Peak memory 200452 kb
Host smart-df634451-63f2-423f-a177-457f047b8e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844794137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1844794137
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3397548254
Short name T583
Test name
Test status
Simulation time 1117135414 ps
CPU time 1.54 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:03:37 PM PDT 24
Peak memory 196088 kb
Host smart-b15ae4c7-1e1e-4a7f-991d-2be622dab6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397548254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3397548254
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.4033028159
Short name T662
Test name
Test status
Simulation time 62754941821 ps
CPU time 17.96 seconds
Started May 07 01:03:31 PM PDT 24
Finished May 07 01:03:50 PM PDT 24
Peak memory 197964 kb
Host smart-54d22d15-2a10-467b-acc2-69a6dde51aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033028159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4033028159
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3079990354
Short name T513
Test name
Test status
Simulation time 35706262351 ps
CPU time 919.06 seconds
Started May 07 01:03:29 PM PDT 24
Finished May 07 01:18:49 PM PDT 24
Peak memory 200416 kb
Host smart-2e7fe51d-c235-4f82-94d6-861917c545e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079990354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3079990354
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4086157915
Short name T679
Test name
Test status
Simulation time 3481033010 ps
CPU time 3.78 seconds
Started May 07 01:03:17 PM PDT 24
Finished May 07 01:03:21 PM PDT 24
Peak memory 198560 kb
Host smart-4488ab05-d184-4e38-8c20-941a8556be69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086157915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4086157915
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2250275332
Short name T931
Test name
Test status
Simulation time 96378476943 ps
CPU time 110.58 seconds
Started May 07 01:03:25 PM PDT 24
Finished May 07 01:05:16 PM PDT 24
Peak memory 200164 kb
Host smart-39f3bdce-3473-4e5a-a33e-5f55441156ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250275332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2250275332
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1187089930
Short name T1118
Test name
Test status
Simulation time 46543857623 ps
CPU time 75.48 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:04:51 PM PDT 24
Peak memory 196412 kb
Host smart-4e3ac13e-56ab-4481-84a9-ccc4b765b2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187089930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1187089930
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4013282529
Short name T1087
Test name
Test status
Simulation time 997388944 ps
CPU time 1.43 seconds
Started May 07 01:03:17 PM PDT 24
Finished May 07 01:03:19 PM PDT 24
Peak memory 198692 kb
Host smart-e5728c31-66c6-4507-a4c7-879028850879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013282529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4013282529
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.119808992
Short name T905
Test name
Test status
Simulation time 4879976957 ps
CPU time 9.46 seconds
Started May 07 01:03:24 PM PDT 24
Finished May 07 01:03:35 PM PDT 24
Peak memory 200344 kb
Host smart-06bc7241-b7ee-49a0-bb69-5851255b40aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119808992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.119808992
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3965703712
Short name T60
Test name
Test status
Simulation time 34345557817 ps
CPU time 386.5 seconds
Started May 07 01:03:25 PM PDT 24
Finished May 07 01:09:53 PM PDT 24
Peak memory 216904 kb
Host smart-dda30447-9a6f-4e38-a22a-c6a91df6b6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965703712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3965703712
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1535992471
Short name T1039
Test name
Test status
Simulation time 456726561 ps
CPU time 1.16 seconds
Started May 07 01:03:30 PM PDT 24
Finished May 07 01:03:33 PM PDT 24
Peak memory 197004 kb
Host smart-efa041a5-0e2d-4cc5-bc17-c3481b9bee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535992471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1535992471
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3239006235
Short name T415
Test name
Test status
Simulation time 158400466189 ps
CPU time 68.14 seconds
Started May 07 01:03:20 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 200456 kb
Host smart-dca87fc0-57b9-4683-9338-78718c1c5c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239006235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3239006235
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1893668142
Short name T591
Test name
Test status
Simulation time 29360144 ps
CPU time 0.56 seconds
Started May 07 01:03:24 PM PDT 24
Finished May 07 01:03:26 PM PDT 24
Peak memory 195804 kb
Host smart-99047258-4dae-48f3-90c4-5c0c6b69b655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893668142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1893668142
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.4101743211
Short name T1055
Test name
Test status
Simulation time 113056679114 ps
CPU time 67.94 seconds
Started May 07 01:03:25 PM PDT 24
Finished May 07 01:04:34 PM PDT 24
Peak memory 200416 kb
Host smart-34690ebd-591b-4017-baed-d59bc21aa7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101743211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4101743211
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3604546695
Short name T48
Test name
Test status
Simulation time 73614843499 ps
CPU time 34.68 seconds
Started May 07 01:03:25 PM PDT 24
Finished May 07 01:04:01 PM PDT 24
Peak memory 200444 kb
Host smart-52d21d4a-cd79-455f-9df5-a659c7f12d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604546695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3604546695
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3444887687
Short name T849
Test name
Test status
Simulation time 40412083990 ps
CPU time 89.56 seconds
Started May 07 01:03:25 PM PDT 24
Finished May 07 01:04:56 PM PDT 24
Peak memory 200356 kb
Host smart-25db09d0-c38b-4ade-b052-d0118d8e90ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444887687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3444887687
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.602848938
Short name T712
Test name
Test status
Simulation time 37236332407 ps
CPU time 30.98 seconds
Started May 07 01:03:31 PM PDT 24
Finished May 07 01:04:03 PM PDT 24
Peak memory 200448 kb
Host smart-2cc9bfcb-2d86-41c6-a23a-88f08438250f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602848938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.602848938
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2834272416
Short name T604
Test name
Test status
Simulation time 95760473224 ps
CPU time 263.52 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:07:57 PM PDT 24
Peak memory 200376 kb
Host smart-0798b833-560a-4fb1-977f-e297f54830b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834272416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2834272416
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2282799446
Short name T46
Test name
Test status
Simulation time 4845108132 ps
CPU time 8.92 seconds
Started May 07 01:03:24 PM PDT 24
Finished May 07 01:03:34 PM PDT 24
Peak memory 199956 kb
Host smart-6a37da6e-a2ef-4c81-80d9-778ecd56f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282799446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2282799446
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1460941386
Short name T278
Test name
Test status
Simulation time 148558919371 ps
CPU time 99.62 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:05:14 PM PDT 24
Peak memory 208756 kb
Host smart-4484d989-de06-4615-ac09-a3a36a38ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460941386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1460941386
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2510934385
Short name T1179
Test name
Test status
Simulation time 14449245593 ps
CPU time 714.85 seconds
Started May 07 01:03:24 PM PDT 24
Finished May 07 01:15:20 PM PDT 24
Peak memory 200456 kb
Host smart-17473113-8c71-46d0-b8f7-2ee55c07299e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510934385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2510934385
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.124914560
Short name T498
Test name
Test status
Simulation time 1918008237 ps
CPU time 3.71 seconds
Started May 07 01:03:23 PM PDT 24
Finished May 07 01:03:28 PM PDT 24
Peak memory 198640 kb
Host smart-65383589-6234-477d-b456-3330cb54949f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124914560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.124914560
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3036551236
Short name T1098
Test name
Test status
Simulation time 58095382372 ps
CPU time 25.94 seconds
Started May 07 01:03:30 PM PDT 24
Finished May 07 01:03:57 PM PDT 24
Peak memory 200424 kb
Host smart-167fb80e-b68d-401d-b750-b13507b8b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036551236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3036551236
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4106227241
Short name T286
Test name
Test status
Simulation time 71764012424 ps
CPU time 104.4 seconds
Started May 07 01:03:31 PM PDT 24
Finished May 07 01:05:16 PM PDT 24
Peak memory 196044 kb
Host smart-f97f560d-1846-4078-89bd-bc2f761cb9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106227241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4106227241
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2451503270
Short name T1106
Test name
Test status
Simulation time 6170735295 ps
CPU time 10.35 seconds
Started May 07 01:03:25 PM PDT 24
Finished May 07 01:03:36 PM PDT 24
Peak memory 200200 kb
Host smart-dd641710-f77f-43a3-ab76-e18e021dce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451503270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2451503270
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2353739540
Short name T79
Test name
Test status
Simulation time 251054054588 ps
CPU time 119.68 seconds
Started May 07 01:03:31 PM PDT 24
Finished May 07 01:05:32 PM PDT 24
Peak memory 200468 kb
Host smart-45f9b223-bb30-4c71-ab7f-a1f8784789a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353739540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2353739540
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2034894652
Short name T310
Test name
Test status
Simulation time 589566842 ps
CPU time 2.45 seconds
Started May 07 01:03:31 PM PDT 24
Finished May 07 01:03:34 PM PDT 24
Peak memory 198628 kb
Host smart-6545f1f6-74cd-47c0-8cff-20fe7e78b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034894652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2034894652
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3038700534
Short name T460
Test name
Test status
Simulation time 70804698944 ps
CPU time 146.74 seconds
Started May 07 01:03:32 PM PDT 24
Finished May 07 01:05:59 PM PDT 24
Peak memory 200388 kb
Host smart-621fc0b1-d2f6-45c2-bb97-733c4d8f157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038700534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3038700534
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2050254938
Short name T1015
Test name
Test status
Simulation time 13472970 ps
CPU time 0.55 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:03:35 PM PDT 24
Peak memory 194816 kb
Host smart-44606d53-8eee-445f-a971-abec13793c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050254938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2050254938
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2522997952
Short name T361
Test name
Test status
Simulation time 40085655933 ps
CPU time 18.76 seconds
Started May 07 01:03:32 PM PDT 24
Finished May 07 01:03:52 PM PDT 24
Peak memory 200308 kb
Host smart-7813035d-664c-4550-a2be-59698a304366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522997952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2522997952
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1447776028
Short name T432
Test name
Test status
Simulation time 172837554906 ps
CPU time 71.87 seconds
Started May 07 01:03:36 PM PDT 24
Finished May 07 01:04:49 PM PDT 24
Peak memory 200500 kb
Host smart-83f848a7-b851-4d05-9980-cdb26377c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447776028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1447776028
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2514144282
Short name T229
Test name
Test status
Simulation time 23828808884 ps
CPU time 43.61 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:04:19 PM PDT 24
Peak memory 200424 kb
Host smart-e9653cba-aa24-40dc-8df0-b8dc8f5cab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514144282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2514144282
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.886824786
Short name T1045
Test name
Test status
Simulation time 23346443315 ps
CPU time 14.4 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 200448 kb
Host smart-87efb9d3-0784-4464-9be6-8c8a2e9c724f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886824786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.886824786
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1312693166
Short name T826
Test name
Test status
Simulation time 133955140605 ps
CPU time 372.95 seconds
Started May 07 01:03:36 PM PDT 24
Finished May 07 01:09:50 PM PDT 24
Peak memory 200428 kb
Host smart-30b63e5a-a78d-473d-876e-308291c3679a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312693166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1312693166
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1777226273
Short name T451
Test name
Test status
Simulation time 452255040 ps
CPU time 0.77 seconds
Started May 07 01:03:35 PM PDT 24
Finished May 07 01:03:38 PM PDT 24
Peak memory 195864 kb
Host smart-515d7f35-389a-45fb-b4ad-e099c5285bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777226273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1777226273
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3501537236
Short name T474
Test name
Test status
Simulation time 8795534184 ps
CPU time 17.19 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:03:52 PM PDT 24
Peak memory 196476 kb
Host smart-d4a20075-c4f3-4882-8db1-ac67e84b4b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501537236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3501537236
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.920289156
Short name T301
Test name
Test status
Simulation time 10334495345 ps
CPU time 533.32 seconds
Started May 07 01:03:36 PM PDT 24
Finished May 07 01:12:31 PM PDT 24
Peak memory 200364 kb
Host smart-c0804ed2-3d7a-45e7-b05c-285492445146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920289156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.920289156
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2868296482
Short name T654
Test name
Test status
Simulation time 5473636701 ps
CPU time 48.63 seconds
Started May 07 01:03:35 PM PDT 24
Finished May 07 01:04:25 PM PDT 24
Peak memory 198612 kb
Host smart-e8e5521e-4dfc-4c6f-8b1a-b4d344b088a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868296482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2868296482
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2729000486
Short name T149
Test name
Test status
Simulation time 90726190727 ps
CPU time 58.49 seconds
Started May 07 01:03:33 PM PDT 24
Finished May 07 01:04:32 PM PDT 24
Peak memory 200376 kb
Host smart-106778fa-5b9e-42b1-af17-77e55c67aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729000486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2729000486
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.250951221
Short name T329
Test name
Test status
Simulation time 1783658034 ps
CPU time 1.89 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:03:38 PM PDT 24
Peak memory 196088 kb
Host smart-8c0a77e6-5da6-44d7-832e-0beac67f218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250951221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.250951221
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1334219178
Short name T442
Test name
Test status
Simulation time 668334169 ps
CPU time 3.18 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:03:39 PM PDT 24
Peak memory 198960 kb
Host smart-681297c6-0f1d-482b-8ae5-1b814bb40e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334219178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1334219178
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2626970019
Short name T409
Test name
Test status
Simulation time 167925847461 ps
CPU time 322.59 seconds
Started May 07 01:03:35 PM PDT 24
Finished May 07 01:08:59 PM PDT 24
Peak memory 200472 kb
Host smart-1211e618-ed86-44a6-a7cc-755dbd2bae44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626970019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2626970019
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.4199494658
Short name T486
Test name
Test status
Simulation time 161341222484 ps
CPU time 472.01 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:11:28 PM PDT 24
Peak memory 228044 kb
Host smart-75c01d9a-de22-4475-a3c1-d91fa9eea72b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199494658 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.4199494658
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3828571747
Short name T311
Test name
Test status
Simulation time 4533966953 ps
CPU time 2.15 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:03:37 PM PDT 24
Peak memory 199656 kb
Host smart-586b5931-fe43-4d40-83b1-6e47e13d2bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828571747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3828571747
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1154573561
Short name T1100
Test name
Test status
Simulation time 5341894010 ps
CPU time 9.33 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:03:45 PM PDT 24
Peak memory 197080 kb
Host smart-cde0257a-91ce-4b46-a9ab-5498a3887ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154573561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1154573561
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.304381293
Short name T1174
Test name
Test status
Simulation time 14227998 ps
CPU time 0.59 seconds
Started May 07 01:03:43 PM PDT 24
Finished May 07 01:03:44 PM PDT 24
Peak memory 195744 kb
Host smart-c6e199ab-4a40-46bc-a8e8-efc8bc2ce03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304381293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.304381293
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4184863852
Short name T1024
Test name
Test status
Simulation time 146662146123 ps
CPU time 247.5 seconds
Started May 07 01:03:35 PM PDT 24
Finished May 07 01:07:45 PM PDT 24
Peak memory 200480 kb
Host smart-336b2ae5-62cd-4e10-9f45-6fdfb23e0899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184863852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4184863852
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.10783434
Short name T951
Test name
Test status
Simulation time 6787438916 ps
CPU time 13.03 seconds
Started May 07 01:03:35 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 200384 kb
Host smart-31ed3bd0-3cfb-4bb2-a0bc-2bcbf8441d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10783434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.10783434
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1656049344
Short name T729
Test name
Test status
Simulation time 127970867713 ps
CPU time 110.95 seconds
Started May 07 01:03:39 PM PDT 24
Finished May 07 01:05:31 PM PDT 24
Peak memory 200360 kb
Host smart-43f1b153-c724-4031-8f32-51529c8d3567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656049344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1656049344
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2502108477
Short name T544
Test name
Test status
Simulation time 40490997182 ps
CPU time 16.32 seconds
Started May 07 01:03:41 PM PDT 24
Finished May 07 01:03:59 PM PDT 24
Peak memory 199316 kb
Host smart-436eee04-f3cd-4085-8041-9f0e939e787f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502108477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2502108477
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2683344972
Short name T773
Test name
Test status
Simulation time 78803386951 ps
CPU time 281.2 seconds
Started May 07 01:03:44 PM PDT 24
Finished May 07 01:08:26 PM PDT 24
Peak memory 200452 kb
Host smart-45ddd7b6-0b84-499b-aeac-9ef72ce32be1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683344972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2683344972
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.4223594555
Short name T722
Test name
Test status
Simulation time 6572663606 ps
CPU time 4.77 seconds
Started May 07 01:03:40 PM PDT 24
Finished May 07 01:03:46 PM PDT 24
Peak memory 200356 kb
Host smart-245cd546-7578-424b-998a-8885625c5cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223594555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.4223594555
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.397676359
Short name T320
Test name
Test status
Simulation time 53080565847 ps
CPU time 114.36 seconds
Started May 07 01:03:40 PM PDT 24
Finished May 07 01:05:36 PM PDT 24
Peak memory 199768 kb
Host smart-e236d42e-d7ae-4b68-8c24-bf55ad27db8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397676359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.397676359
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3836040858
Short name T836
Test name
Test status
Simulation time 11026171434 ps
CPU time 299 seconds
Started May 07 01:03:42 PM PDT 24
Finished May 07 01:08:42 PM PDT 24
Peak memory 200408 kb
Host smart-c1618d9c-f6b2-4d75-9247-15948cec8aa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836040858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3836040858
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.130040667
Short name T578
Test name
Test status
Simulation time 3691240547 ps
CPU time 7.57 seconds
Started May 07 01:03:41 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 198472 kb
Host smart-3e059c5d-0f46-455e-a7f0-a08909621c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130040667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.130040667
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3889421039
Short name T741
Test name
Test status
Simulation time 34229825541 ps
CPU time 50.73 seconds
Started May 07 01:03:42 PM PDT 24
Finished May 07 01:04:33 PM PDT 24
Peak memory 200348 kb
Host smart-a5924401-7e99-48ab-8531-cb66f3e45879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889421039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3889421039
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3783851371
Short name T983
Test name
Test status
Simulation time 36419675884 ps
CPU time 51.12 seconds
Started May 07 01:03:40 PM PDT 24
Finished May 07 01:04:32 PM PDT 24
Peak memory 196432 kb
Host smart-b9b7a71d-7bec-4c3f-8b67-2de5f42a1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783851371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3783851371
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.952999908
Short name T798
Test name
Test status
Simulation time 825113371 ps
CPU time 0.89 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:03:37 PM PDT 24
Peak memory 198644 kb
Host smart-52fb6a20-f3da-43d9-b315-f3606f891166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952999908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.952999908
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3139883662
Short name T76
Test name
Test status
Simulation time 224424812561 ps
CPU time 94.43 seconds
Started May 07 01:03:41 PM PDT 24
Finished May 07 01:05:16 PM PDT 24
Peak memory 200428 kb
Host smart-6c84febe-acdd-4b8e-81f6-0b0387799fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139883662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3139883662
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3709509441
Short name T444
Test name
Test status
Simulation time 824209792 ps
CPU time 2.67 seconds
Started May 07 01:03:41 PM PDT 24
Finished May 07 01:03:45 PM PDT 24
Peak memory 200280 kb
Host smart-ab67ebed-b49e-4eb3-88e5-4dfd1a950046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709509441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3709509441
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.243762266
Short name T1129
Test name
Test status
Simulation time 40005567117 ps
CPU time 56.89 seconds
Started May 07 01:03:34 PM PDT 24
Finished May 07 01:04:33 PM PDT 24
Peak memory 200376 kb
Host smart-23107275-3a50-447e-9460-4bd5041a044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243762266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.243762266
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1699538642
Short name T369
Test name
Test status
Simulation time 24701027 ps
CPU time 0.58 seconds
Started May 07 01:03:50 PM PDT 24
Finished May 07 01:03:52 PM PDT 24
Peak memory 195824 kb
Host smart-a8d8ee0a-acb7-490f-8ab7-86692ff1df32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699538642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1699538642
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3021953445
Short name T368
Test name
Test status
Simulation time 158319837112 ps
CPU time 547.83 seconds
Started May 07 01:03:40 PM PDT 24
Finished May 07 01:12:49 PM PDT 24
Peak memory 200396 kb
Host smart-d3712746-0bb2-4fe4-bf68-1a49b0e192f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021953445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3021953445
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4258361767
Short name T587
Test name
Test status
Simulation time 69695108238 ps
CPU time 29.25 seconds
Started May 07 01:03:41 PM PDT 24
Finished May 07 01:04:11 PM PDT 24
Peak memory 200352 kb
Host smart-8902aca4-644c-446b-bcdd-9d7e49b948b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258361767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4258361767
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2563112616
Short name T800
Test name
Test status
Simulation time 37478638453 ps
CPU time 69.3 seconds
Started May 07 01:03:42 PM PDT 24
Finished May 07 01:04:52 PM PDT 24
Peak memory 200460 kb
Host smart-3fc625c7-643d-48a3-a331-8cc1a088e002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563112616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2563112616
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3802150310
Short name T716
Test name
Test status
Simulation time 109959023195 ps
CPU time 29.18 seconds
Started May 07 01:03:43 PM PDT 24
Finished May 07 01:04:13 PM PDT 24
Peak memory 200188 kb
Host smart-1a3ca831-eb7f-4b32-ae79-297ec7fb3012
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802150310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3802150310
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3672342648
Short name T1128
Test name
Test status
Simulation time 78926803137 ps
CPU time 272.05 seconds
Started May 07 01:03:49 PM PDT 24
Finished May 07 01:08:22 PM PDT 24
Peak memory 200316 kb
Host smart-12ec3dce-9d5b-4860-8c9c-74151e5f6d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672342648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3672342648
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1922417136
Short name T930
Test name
Test status
Simulation time 1742629502 ps
CPU time 2.38 seconds
Started May 07 01:03:48 PM PDT 24
Finished May 07 01:03:52 PM PDT 24
Peak memory 199036 kb
Host smart-68e5ebb5-a956-4ac5-900e-67c35bf5284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922417136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1922417136
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2708098359
Short name T621
Test name
Test status
Simulation time 195742175878 ps
CPU time 106.19 seconds
Started May 07 01:03:44 PM PDT 24
Finished May 07 01:05:31 PM PDT 24
Peak memory 200128 kb
Host smart-f239eecb-95ea-44cd-8e21-8178b6d826ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708098359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2708098359
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1191576646
Short name T829
Test name
Test status
Simulation time 12532265709 ps
CPU time 673.88 seconds
Started May 07 01:03:50 PM PDT 24
Finished May 07 01:15:05 PM PDT 24
Peak memory 200396 kb
Host smart-49416d12-51a4-4372-9a32-191d72fc6700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191576646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1191576646
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.157277009
Short name T945
Test name
Test status
Simulation time 7186162720 ps
CPU time 16.32 seconds
Started May 07 01:03:45 PM PDT 24
Finished May 07 01:04:02 PM PDT 24
Peak memory 198560 kb
Host smart-f182e52e-1b09-4bce-b01b-9b27bcff21b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157277009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.157277009
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1548940041
Short name T335
Test name
Test status
Simulation time 49960823833 ps
CPU time 52.84 seconds
Started May 07 01:03:46 PM PDT 24
Finished May 07 01:04:41 PM PDT 24
Peak memory 200436 kb
Host smart-de27e1c8-77ef-4b0c-bcb7-92a02e06f2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548940041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1548940041
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4148754984
Short name T1062
Test name
Test status
Simulation time 2665374610 ps
CPU time 4.81 seconds
Started May 07 01:03:41 PM PDT 24
Finished May 07 01:03:47 PM PDT 24
Peak memory 196144 kb
Host smart-3537a608-e0b4-4633-86c1-74b45ffeb52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148754984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4148754984
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2103718903
Short name T309
Test name
Test status
Simulation time 5743274524 ps
CPU time 30.67 seconds
Started May 07 01:03:40 PM PDT 24
Finished May 07 01:04:12 PM PDT 24
Peak memory 200268 kb
Host smart-950e4086-85b1-415b-a8e5-90d8607b1899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103718903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2103718903
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.928912286
Short name T999
Test name
Test status
Simulation time 378121136850 ps
CPU time 1551.08 seconds
Started May 07 01:03:48 PM PDT 24
Finished May 07 01:29:40 PM PDT 24
Peak memory 208748 kb
Host smart-584e95cd-1cb9-4d9d-b3b9-e8d4733345ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928912286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.928912286
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2065051959
Short name T657
Test name
Test status
Simulation time 218685671543 ps
CPU time 2135.55 seconds
Started May 07 01:03:49 PM PDT 24
Finished May 07 01:39:27 PM PDT 24
Peak memory 232940 kb
Host smart-79804d64-ed15-4b2d-89fa-e4a74bbaddeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065051959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2065051959
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1354966180
Short name T19
Test name
Test status
Simulation time 1116174803 ps
CPU time 3.27 seconds
Started May 07 01:03:49 PM PDT 24
Finished May 07 01:03:54 PM PDT 24
Peak memory 200228 kb
Host smart-c9884e69-4b76-4ca9-9e30-2958e1e0097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354966180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1354966180
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3625251373
Short name T315
Test name
Test status
Simulation time 73460765110 ps
CPU time 45.56 seconds
Started May 07 01:03:42 PM PDT 24
Finished May 07 01:04:28 PM PDT 24
Peak memory 200364 kb
Host smart-7e56509b-eed5-4252-a400-65130b7ca6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625251373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3625251373
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3236950811
Short name T1004
Test name
Test status
Simulation time 13498102 ps
CPU time 0.57 seconds
Started May 07 01:03:58 PM PDT 24
Finished May 07 01:04:00 PM PDT 24
Peak memory 195816 kb
Host smart-a2a24c71-c67c-4da4-9b53-26dc86b1a73f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236950811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3236950811
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4041170059
Short name T647
Test name
Test status
Simulation time 43827775834 ps
CPU time 37.45 seconds
Started May 07 01:03:50 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 200332 kb
Host smart-195df5b3-c152-4092-9768-4b77eb3c5e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041170059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4041170059
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1710909222
Short name T669
Test name
Test status
Simulation time 38311516792 ps
CPU time 22.64 seconds
Started May 07 01:03:49 PM PDT 24
Finished May 07 01:04:13 PM PDT 24
Peak memory 200356 kb
Host smart-daef30c1-8e69-4bc0-a810-00263e5de777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710909222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1710909222
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3671169452
Short name T396
Test name
Test status
Simulation time 118539526119 ps
CPU time 47.59 seconds
Started May 07 01:03:47 PM PDT 24
Finished May 07 01:04:36 PM PDT 24
Peak memory 200412 kb
Host smart-94abbbc6-78da-46b9-bf4c-1de5ad98a814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671169452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3671169452
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3889682530
Short name T428
Test name
Test status
Simulation time 5364337138 ps
CPU time 7.53 seconds
Started May 07 01:03:50 PM PDT 24
Finished May 07 01:03:59 PM PDT 24
Peak memory 200060 kb
Host smart-79b4ea64-edf5-4f99-ae25-348eb918d3e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889682530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3889682530
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4014159004
Short name T353
Test name
Test status
Simulation time 123236516227 ps
CPU time 973.3 seconds
Started May 07 01:04:02 PM PDT 24
Finished May 07 01:20:16 PM PDT 24
Peak memory 200360 kb
Host smart-b9dc210d-c7a5-4275-8653-b1a112dec0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014159004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4014159004
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1354399
Short name T901
Test name
Test status
Simulation time 7051390280 ps
CPU time 19.87 seconds
Started May 07 01:03:58 PM PDT 24
Finished May 07 01:04:19 PM PDT 24
Peak memory 200124 kb
Host smart-ae4c4d76-6fad-4875-91f9-efc98b14477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1354399
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3322097867
Short name T845
Test name
Test status
Simulation time 82645983456 ps
CPU time 33.54 seconds
Started May 07 01:03:50 PM PDT 24
Finished May 07 01:04:25 PM PDT 24
Peak memory 200220 kb
Host smart-9f9d893c-4dba-4459-a6dc-c0518f02a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322097867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3322097867
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.800991111
Short name T941
Test name
Test status
Simulation time 5167365659 ps
CPU time 144.43 seconds
Started May 07 01:03:56 PM PDT 24
Finished May 07 01:06:21 PM PDT 24
Peak memory 200416 kb
Host smart-55c5c765-44a6-4a14-bf8b-0f30fcce58e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800991111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.800991111
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2939634470
Short name T533
Test name
Test status
Simulation time 6508375432 ps
CPU time 16.67 seconds
Started May 07 01:03:48 PM PDT 24
Finished May 07 01:04:06 PM PDT 24
Peak memory 199596 kb
Host smart-86170acd-a9b7-4cc7-ac41-7ed496f3d0ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939634470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2939634470
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1968259168
Short name T1027
Test name
Test status
Simulation time 71666042348 ps
CPU time 52.26 seconds
Started May 07 01:03:49 PM PDT 24
Finished May 07 01:04:43 PM PDT 24
Peak memory 200320 kb
Host smart-e42e9457-8863-4fbf-abcf-b701806182b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968259168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1968259168
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3070557300
Short name T1149
Test name
Test status
Simulation time 41903015371 ps
CPU time 76.21 seconds
Started May 07 01:03:49 PM PDT 24
Finished May 07 01:05:07 PM PDT 24
Peak memory 196136 kb
Host smart-f1778fd0-7572-4a0e-b5b1-9c4f71ef2419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070557300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3070557300
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1540362939
Short name T373
Test name
Test status
Simulation time 88899898 ps
CPU time 0.91 seconds
Started May 07 01:03:47 PM PDT 24
Finished May 07 01:03:49 PM PDT 24
Peak memory 197552 kb
Host smart-3906b109-48a1-4d1a-847e-ce5394f4a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540362939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1540362939
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1721995553
Short name T794
Test name
Test status
Simulation time 736405914216 ps
CPU time 320.19 seconds
Started May 07 01:03:56 PM PDT 24
Finished May 07 01:09:17 PM PDT 24
Peak memory 200412 kb
Host smart-46dd71ae-178e-4257-bce0-61cdc25f85d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721995553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1721995553
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3394755060
Short name T457
Test name
Test status
Simulation time 31535361237 ps
CPU time 610.38 seconds
Started May 07 01:03:58 PM PDT 24
Finished May 07 01:14:10 PM PDT 24
Peak memory 208872 kb
Host smart-104078c5-1008-45ee-9370-c3e9e33ef7a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394755060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3394755060
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1501859116
Short name T812
Test name
Test status
Simulation time 3796958004 ps
CPU time 2.01 seconds
Started May 07 01:03:50 PM PDT 24
Finished May 07 01:03:53 PM PDT 24
Peak memory 198988 kb
Host smart-fd61da30-70e4-481c-9285-e834c4e3aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501859116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1501859116
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3911587222
Short name T260
Test name
Test status
Simulation time 74355143692 ps
CPU time 257.34 seconds
Started May 07 01:03:51 PM PDT 24
Finished May 07 01:08:10 PM PDT 24
Peak memory 200084 kb
Host smart-42c58ace-03ea-4fb7-af96-9d89631815aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911587222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3911587222
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3784709852
Short name T111
Test name
Test status
Simulation time 46189863 ps
CPU time 0.57 seconds
Started May 07 01:04:03 PM PDT 24
Finished May 07 01:04:05 PM PDT 24
Peak memory 195228 kb
Host smart-52ee9380-06f3-4253-a02a-49914040b365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784709852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3784709852
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2444942152
Short name T514
Test name
Test status
Simulation time 43589211912 ps
CPU time 77.96 seconds
Started May 07 01:03:59 PM PDT 24
Finished May 07 01:05:18 PM PDT 24
Peak memory 200400 kb
Host smart-e0e7028d-e380-423d-a05a-1b35c2167ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444942152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2444942152
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1100135539
Short name T182
Test name
Test status
Simulation time 9250568020 ps
CPU time 7.46 seconds
Started May 07 01:03:59 PM PDT 24
Finished May 07 01:04:08 PM PDT 24
Peak memory 200392 kb
Host smart-31f3bd9c-7290-4bb3-b8d5-b8dbaf5f62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100135539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1100135539
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2771500671
Short name T228
Test name
Test status
Simulation time 56462930632 ps
CPU time 18.33 seconds
Started May 07 01:03:56 PM PDT 24
Finished May 07 01:04:15 PM PDT 24
Peak memory 200396 kb
Host smart-0ae1d92e-77da-46db-8cba-0caaee488fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771500671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2771500671
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.64204035
Short name T426
Test name
Test status
Simulation time 21684305602 ps
CPU time 31.24 seconds
Started May 07 01:03:57 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 198916 kb
Host smart-a12c1afd-da62-4953-9aa8-b52480a1bebf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64204035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.64204035
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.39180253
Short name T896
Test name
Test status
Simulation time 119278887196 ps
CPU time 218.37 seconds
Started May 07 01:03:57 PM PDT 24
Finished May 07 01:07:36 PM PDT 24
Peak memory 200448 kb
Host smart-808cd7bc-0dbe-471c-9088-8bd9df340127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39180253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.39180253
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3608121867
Short name T351
Test name
Test status
Simulation time 3349395217 ps
CPU time 3.94 seconds
Started May 07 01:03:59 PM PDT 24
Finished May 07 01:04:04 PM PDT 24
Peak memory 199972 kb
Host smart-58366029-d2de-4fde-99ee-fd7846956824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608121867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3608121867
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2084908797
Short name T748
Test name
Test status
Simulation time 117780229237 ps
CPU time 102.74 seconds
Started May 07 01:03:57 PM PDT 24
Finished May 07 01:05:41 PM PDT 24
Peak memory 200588 kb
Host smart-81ac1e8e-0741-4159-b09c-87e56a73f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084908797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2084908797
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3128391392
Short name T528
Test name
Test status
Simulation time 10750890446 ps
CPU time 260.93 seconds
Started May 07 01:03:55 PM PDT 24
Finished May 07 01:08:17 PM PDT 24
Peak memory 200268 kb
Host smart-d4467f3b-af1d-4f65-af38-4cbef82a90ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128391392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3128391392
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.579054338
Short name T355
Test name
Test status
Simulation time 3597495847 ps
CPU time 7.17 seconds
Started May 07 01:03:57 PM PDT 24
Finished May 07 01:04:05 PM PDT 24
Peak memory 199340 kb
Host smart-433a65b6-79dd-487e-8fa1-76d99547bc5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579054338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.579054338
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2232819713
Short name T1009
Test name
Test status
Simulation time 152174521647 ps
CPU time 75.79 seconds
Started May 07 01:03:59 PM PDT 24
Finished May 07 01:05:16 PM PDT 24
Peak memory 200196 kb
Host smart-386bc94a-4ebb-4779-9be7-99da77801495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232819713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2232819713
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1897083097
Short name T808
Test name
Test status
Simulation time 4315850422 ps
CPU time 7.94 seconds
Started May 07 01:04:02 PM PDT 24
Finished May 07 01:04:10 PM PDT 24
Peak memory 196420 kb
Host smart-b2dfe075-2bc3-4b73-a3df-f6cc870915ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897083097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1897083097
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.625109645
Short name T807
Test name
Test status
Simulation time 465688132 ps
CPU time 1.34 seconds
Started May 07 01:03:58 PM PDT 24
Finished May 07 01:04:01 PM PDT 24
Peak memory 199068 kb
Host smart-4ee65dbd-53d4-4b5b-b9a5-20c6ccc8b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625109645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.625109645
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3520164629
Short name T772
Test name
Test status
Simulation time 22843384881 ps
CPU time 25.19 seconds
Started May 07 01:04:02 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 200420 kb
Host smart-f852bc61-1646-4e54-b610-88f54b292cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520164629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3520164629
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1667438425
Short name T640
Test name
Test status
Simulation time 78477639108 ps
CPU time 1070.7 seconds
Started May 07 01:04:04 PM PDT 24
Finished May 07 01:21:56 PM PDT 24
Peak memory 225304 kb
Host smart-2226658d-3261-41d9-abca-a16e8bc4de4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667438425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1667438425
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2926472601
Short name T377
Test name
Test status
Simulation time 1245915096 ps
CPU time 2.32 seconds
Started May 07 01:03:56 PM PDT 24
Finished May 07 01:03:59 PM PDT 24
Peak memory 198876 kb
Host smart-6ac46c0f-78b6-4b2c-bcfc-0cf170aaaa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926472601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2926472601
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2471092858
Short name T280
Test name
Test status
Simulation time 31278046851 ps
CPU time 23.99 seconds
Started May 07 01:03:58 PM PDT 24
Finished May 07 01:04:24 PM PDT 24
Peak memory 200336 kb
Host smart-453ee3fb-1cf1-495c-af3e-fe98bc24ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471092858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2471092858
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.616164004
Short name T1127
Test name
Test status
Simulation time 13656393 ps
CPU time 0.54 seconds
Started May 07 01:04:04 PM PDT 24
Finished May 07 01:04:05 PM PDT 24
Peak memory 194768 kb
Host smart-64a632bd-9d89-4561-9d54-be6c3ad9afa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616164004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.616164004
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.310889094
Short name T655
Test name
Test status
Simulation time 28120319336 ps
CPU time 42.03 seconds
Started May 07 01:04:05 PM PDT 24
Finished May 07 01:04:48 PM PDT 24
Peak memory 200084 kb
Host smart-f7ad90dc-6b6e-4d29-baac-e6799b98e517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310889094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.310889094
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1290702201
Short name T75
Test name
Test status
Simulation time 241337881100 ps
CPU time 30.97 seconds
Started May 07 01:04:15 PM PDT 24
Finished May 07 01:04:47 PM PDT 24
Peak memory 200424 kb
Host smart-17f8e234-c96f-4002-8f53-651203a2ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290702201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1290702201
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1129367092
Short name T874
Test name
Test status
Simulation time 71956764583 ps
CPU time 10.25 seconds
Started May 07 01:04:05 PM PDT 24
Finished May 07 01:04:16 PM PDT 24
Peak memory 200372 kb
Host smart-4a75cdbe-57f3-41be-bef2-6a00fde747f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129367092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1129367092
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1058368325
Short name T529
Test name
Test status
Simulation time 132019120230 ps
CPU time 182 seconds
Started May 07 01:04:15 PM PDT 24
Finished May 07 01:07:18 PM PDT 24
Peak memory 200436 kb
Host smart-543f0005-215e-4182-800c-038e50fec813
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058368325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1058368325
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4259340294
Short name T1148
Test name
Test status
Simulation time 88851277778 ps
CPU time 424.85 seconds
Started May 07 01:04:03 PM PDT 24
Finished May 07 01:11:09 PM PDT 24
Peak memory 200372 kb
Host smart-cd415cd2-f87f-46a5-8ea3-83e54a4bc2ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259340294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4259340294
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2057048649
Short name T659
Test name
Test status
Simulation time 3141856928 ps
CPU time 3.18 seconds
Started May 07 01:04:15 PM PDT 24
Finished May 07 01:04:19 PM PDT 24
Peak memory 198020 kb
Host smart-0fb07b4d-9b0a-4888-b4e9-406551da3bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057048649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2057048649
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2667271067
Short name T924
Test name
Test status
Simulation time 106320458949 ps
CPU time 188.32 seconds
Started May 07 01:04:02 PM PDT 24
Finished May 07 01:07:12 PM PDT 24
Peak memory 208768 kb
Host smart-c1c8379e-b240-457b-b2af-52faf07a5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667271067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2667271067
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.455787740
Short name T448
Test name
Test status
Simulation time 7378202316 ps
CPU time 377.73 seconds
Started May 07 01:04:05 PM PDT 24
Finished May 07 01:10:23 PM PDT 24
Peak memory 200408 kb
Host smart-3961ce85-85d8-4755-9634-ed6728f4eb98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455787740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.455787740
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3933632012
Short name T631
Test name
Test status
Simulation time 5075222366 ps
CPU time 12.27 seconds
Started May 07 01:04:15 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 198800 kb
Host smart-6f42f2ca-82a5-43de-b1a1-a6d10f64335f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933632012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3933632012
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.620390500
Short name T162
Test name
Test status
Simulation time 120876477717 ps
CPU time 50.56 seconds
Started May 07 01:04:04 PM PDT 24
Finished May 07 01:04:56 PM PDT 24
Peak memory 200428 kb
Host smart-1d42fe50-b361-43d3-8fde-b17f0f1d6550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620390500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.620390500
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2916753956
Short name T875
Test name
Test status
Simulation time 5187724755 ps
CPU time 2.56 seconds
Started May 07 01:04:05 PM PDT 24
Finished May 07 01:04:08 PM PDT 24
Peak memory 196428 kb
Host smart-140e9369-32be-4403-a2f5-c2fa7f852d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916753956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2916753956
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2495896201
Short name T928
Test name
Test status
Simulation time 478723246 ps
CPU time 1.48 seconds
Started May 07 01:04:03 PM PDT 24
Finished May 07 01:04:05 PM PDT 24
Peak memory 198788 kb
Host smart-1d8f3628-0cc0-4626-b0c8-ab9d6f2e3fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495896201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2495896201
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2518143874
Short name T443
Test name
Test status
Simulation time 17898049452 ps
CPU time 29.65 seconds
Started May 07 01:04:03 PM PDT 24
Finished May 07 01:04:34 PM PDT 24
Peak memory 200456 kb
Host smart-d53b05c7-0a91-4137-96ba-382adf36c5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518143874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2518143874
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1786026229
Short name T919
Test name
Test status
Simulation time 7594189592 ps
CPU time 94.93 seconds
Started May 07 01:04:05 PM PDT 24
Finished May 07 01:05:41 PM PDT 24
Peak memory 200404 kb
Host smart-f927aee3-82ec-4166-8fb6-22d741af582e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786026229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1786026229
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3367160590
Short name T758
Test name
Test status
Simulation time 662187875 ps
CPU time 1.71 seconds
Started May 07 01:04:04 PM PDT 24
Finished May 07 01:04:07 PM PDT 24
Peak memory 198444 kb
Host smart-0a56ce3d-b965-4f04-957c-b8b5398bdfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367160590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3367160590
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1665542502
Short name T610
Test name
Test status
Simulation time 28516084085 ps
CPU time 11.85 seconds
Started May 07 01:04:04 PM PDT 24
Finished May 07 01:04:17 PM PDT 24
Peak memory 199568 kb
Host smart-088d15cc-cd8a-400a-8cd4-034007ac0fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665542502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1665542502
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4268181773
Short name T584
Test name
Test status
Simulation time 12427100 ps
CPU time 0.56 seconds
Started May 07 01:04:13 PM PDT 24
Finished May 07 01:04:15 PM PDT 24
Peak memory 195860 kb
Host smart-75db0c7f-c748-426f-a121-bf2637ad4779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268181773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4268181773
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.838252999
Short name T1063
Test name
Test status
Simulation time 44105172324 ps
CPU time 75.09 seconds
Started May 07 01:04:04 PM PDT 24
Finished May 07 01:05:20 PM PDT 24
Peak memory 200388 kb
Host smart-aa42d913-c540-470d-9611-b518a2742d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838252999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.838252999
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2841489492
Short name T483
Test name
Test status
Simulation time 128656441854 ps
CPU time 143.88 seconds
Started May 07 01:04:15 PM PDT 24
Finished May 07 01:06:40 PM PDT 24
Peak memory 200352 kb
Host smart-77a0626d-0ec8-406a-b0ab-122e07a1336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841489492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2841489492
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.700648040
Short name T438
Test name
Test status
Simulation time 18562305491 ps
CPU time 27.2 seconds
Started May 07 01:04:18 PM PDT 24
Finished May 07 01:04:46 PM PDT 24
Peak memory 200368 kb
Host smart-f89a5511-84fc-4a89-9085-1a890d658cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700648040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.700648040
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.658219638
Short name T668
Test name
Test status
Simulation time 11876055780 ps
CPU time 4.12 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:04:18 PM PDT 24
Peak memory 197344 kb
Host smart-ff1b56b3-225d-41fb-badb-61d870690337
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658219638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.658219638
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_loopback.3694723971
Short name T766
Test name
Test status
Simulation time 773346692 ps
CPU time 0.93 seconds
Started May 07 01:04:10 PM PDT 24
Finished May 07 01:04:12 PM PDT 24
Peak memory 196112 kb
Host smart-a5c079f2-b1f3-4ade-b8aa-3020a97153ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694723971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3694723971
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1160224734
Short name T328
Test name
Test status
Simulation time 14911645316 ps
CPU time 13.34 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:04:27 PM PDT 24
Peak memory 196428 kb
Host smart-692450b0-eebb-4f4a-baa0-e0f6d8441c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160224734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1160224734
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.901427315
Short name T1183
Test name
Test status
Simulation time 11078133874 ps
CPU time 533.79 seconds
Started May 07 01:04:11 PM PDT 24
Finished May 07 01:13:06 PM PDT 24
Peak memory 200404 kb
Host smart-303b5222-04bc-4aa7-bf6c-9a9ce362608a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901427315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.901427315
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4022597013
Short name T9
Test name
Test status
Simulation time 7092452131 ps
CPU time 13.58 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:04:27 PM PDT 24
Peak memory 200368 kb
Host smart-a0ca2ece-7922-4c9c-b8a8-f6a1f88d5f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022597013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4022597013
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2370060950
Short name T786
Test name
Test status
Simulation time 36921651994 ps
CPU time 28.42 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:04:42 PM PDT 24
Peak memory 200212 kb
Host smart-846ae578-b384-4200-86c1-847057ea5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370060950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2370060950
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1561253131
Short name T701
Test name
Test status
Simulation time 35349886035 ps
CPU time 13.97 seconds
Started May 07 01:04:14 PM PDT 24
Finished May 07 01:04:29 PM PDT 24
Peak memory 196720 kb
Host smart-5edd4d6b-a923-4ae6-a87b-2e765a6bbe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561253131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1561253131
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3005621398
Short name T982
Test name
Test status
Simulation time 270290378 ps
CPU time 1.54 seconds
Started May 07 01:04:15 PM PDT 24
Finished May 07 01:04:18 PM PDT 24
Peak memory 198784 kb
Host smart-391026ce-9c00-4f5e-aec9-34c113d63261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005621398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3005621398
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.4240784291
Short name T575
Test name
Test status
Simulation time 262464437385 ps
CPU time 299.86 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:09:13 PM PDT 24
Peak memory 208816 kb
Host smart-ad150ed1-f60f-4d74-b14e-c761e68c2fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240784291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.4240784291
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1362650816
Short name T53
Test name
Test status
Simulation time 103069518773 ps
CPU time 568.19 seconds
Started May 07 01:04:13 PM PDT 24
Finished May 07 01:13:43 PM PDT 24
Peak memory 216012 kb
Host smart-1a50519e-c0b7-4dae-be9f-252e8a246766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362650816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1362650816
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2261860341
Short name T850
Test name
Test status
Simulation time 615507750 ps
CPU time 1.92 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:04:15 PM PDT 24
Peak memory 199048 kb
Host smart-edf86bc3-3c6c-47ad-bc74-94a9fc382963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261860341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2261860341
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1173502361
Short name T937
Test name
Test status
Simulation time 106754726484 ps
CPU time 208.91 seconds
Started May 07 01:04:06 PM PDT 24
Finished May 07 01:07:35 PM PDT 24
Peak memory 200340 kb
Host smart-77ce4c37-8219-499a-8346-d128bf65a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173502361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1173502361
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2568368100
Short name T1097
Test name
Test status
Simulation time 13928250 ps
CPU time 0.54 seconds
Started May 07 01:00:24 PM PDT 24
Finished May 07 01:00:26 PM PDT 24
Peak memory 194800 kb
Host smart-2cd3d322-41be-40dd-8f10-1897c0bd3cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568368100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2568368100
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.290980364
Short name T711
Test name
Test status
Simulation time 21232732404 ps
CPU time 31.4 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:54 PM PDT 24
Peak memory 199836 kb
Host smart-c98cee72-c670-45d2-a4c5-53327188d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290980364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.290980364
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2205651599
Short name T5
Test name
Test status
Simulation time 34244135556 ps
CPU time 68.99 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:01:30 PM PDT 24
Peak memory 200392 kb
Host smart-b1aa87bd-8663-45e4-ba8d-641609e34457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205651599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2205651599
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.4185131326
Short name T449
Test name
Test status
Simulation time 149708873816 ps
CPU time 63.5 seconds
Started May 07 01:00:19 PM PDT 24
Finished May 07 01:01:24 PM PDT 24
Peak memory 200316 kb
Host smart-b2db550a-f782-4f32-b5b3-1a6bf1d84049
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185131326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.4185131326
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.361061668
Short name T37
Test name
Test status
Simulation time 29120197546 ps
CPU time 150.38 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:02:53 PM PDT 24
Peak memory 200292 kb
Host smart-5cfecde3-3252-4b79-9ad3-4bec504f0bbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361061668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.361061668
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.125701921
Short name T367
Test name
Test status
Simulation time 5040652695 ps
CPU time 3.3 seconds
Started May 07 01:00:19 PM PDT 24
Finished May 07 01:00:24 PM PDT 24
Peak memory 198116 kb
Host smart-73f937e0-e105-47d8-a48c-2690933cccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125701921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.125701921
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2497064726
Short name T700
Test name
Test status
Simulation time 99666591444 ps
CPU time 95.06 seconds
Started May 07 01:00:19 PM PDT 24
Finished May 07 01:01:55 PM PDT 24
Peak memory 200368 kb
Host smart-96357a12-2448-4ee4-b720-b23e9c74afaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497064726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2497064726
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.171128522
Short name T686
Test name
Test status
Simulation time 39969636638 ps
CPU time 596.09 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:10:18 PM PDT 24
Peak memory 200452 kb
Host smart-f625855c-bf05-4a46-8591-79dff81fb5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171128522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.171128522
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3204562046
Short name T342
Test name
Test status
Simulation time 4104278256 ps
CPU time 25.56 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:00:49 PM PDT 24
Peak memory 198764 kb
Host smart-dcaba6b5-53fa-43a6-823d-646599f29a4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204562046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3204562046
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3334342826
Short name T511
Test name
Test status
Simulation time 63376454102 ps
CPU time 82.22 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:01:44 PM PDT 24
Peak memory 200392 kb
Host smart-988380f5-cdbb-4c19-86e6-6b021735d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334342826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3334342826
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3034197202
Short name T816
Test name
Test status
Simulation time 3180141625 ps
CPU time 5.49 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:00:27 PM PDT 24
Peak memory 196684 kb
Host smart-a101ffe1-8236-4543-960f-d11626667958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034197202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3034197202
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1855649056
Short name T593
Test name
Test status
Simulation time 11071100723 ps
CPU time 13.5 seconds
Started May 07 01:00:14 PM PDT 24
Finished May 07 01:00:29 PM PDT 24
Peak memory 200384 kb
Host smart-42287d68-2eca-4535-9801-70717d86e297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855649056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1855649056
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3101360899
Short name T676
Test name
Test status
Simulation time 224782320846 ps
CPU time 225.1 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:04:08 PM PDT 24
Peak memory 200364 kb
Host smart-e3206bd0-d617-4f04-9dc2-d9e3047d2673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101360899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3101360899
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1749785570
Short name T698
Test name
Test status
Simulation time 275868315923 ps
CPU time 636.28 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:11:00 PM PDT 24
Peak memory 230020 kb
Host smart-e65d0c24-2964-413b-a54e-3d125a1b450e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749785570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1749785570
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1427825192
Short name T338
Test name
Test status
Simulation time 931098407 ps
CPU time 3.15 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:26 PM PDT 24
Peak memory 198648 kb
Host smart-a3de91ba-cfda-440f-9084-9f0da12e4f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427825192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1427825192
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.4273505128
Short name T1104
Test name
Test status
Simulation time 85461835896 ps
CPU time 79.84 seconds
Started May 07 01:00:15 PM PDT 24
Finished May 07 01:01:36 PM PDT 24
Peak memory 200432 kb
Host smart-6a5ee3d5-cd9a-433c-ac86-69a8b36673d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273505128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4273505128
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2704067251
Short name T913
Test name
Test status
Simulation time 25205062498 ps
CPU time 146.54 seconds
Started May 07 01:04:13 PM PDT 24
Finished May 07 01:06:41 PM PDT 24
Peak memory 217068 kb
Host smart-d57fa888-8dfb-4741-80e2-a6e86b0c5d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704067251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2704067251
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1289766546
Short name T1040
Test name
Test status
Simulation time 11777188268 ps
CPU time 18.82 seconds
Started May 07 01:04:11 PM PDT 24
Finished May 07 01:04:31 PM PDT 24
Peak memory 200420 kb
Host smart-a1420ed5-7f60-45db-9995-a4327ab90ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289766546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1289766546
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3301801718
Short name T558
Test name
Test status
Simulation time 111941412575 ps
CPU time 295.89 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:09:09 PM PDT 24
Peak memory 216300 kb
Host smart-797c5d93-c5de-431f-9fe1-c846a3c92bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301801718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3301801718
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3520383479
Short name T696
Test name
Test status
Simulation time 329397874574 ps
CPU time 89.17 seconds
Started May 07 01:04:13 PM PDT 24
Finished May 07 01:05:43 PM PDT 24
Peak memory 200384 kb
Host smart-3a5e017c-19d9-4bdb-93b3-98c7bb85a43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520383479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3520383479
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4225989372
Short name T763
Test name
Test status
Simulation time 29968518809 ps
CPU time 276.68 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:08:50 PM PDT 24
Peak memory 216536 kb
Host smart-e4615e7c-2416-4a71-9d9f-dd6376d39606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225989372 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4225989372
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1815478210
Short name T521
Test name
Test status
Simulation time 99633659394 ps
CPU time 40.79 seconds
Started May 07 01:04:12 PM PDT 24
Finished May 07 01:04:55 PM PDT 24
Peak memory 200428 kb
Host smart-736f36d1-b077-45b8-b4d1-702d964b2f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815478210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1815478210
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3700485296
Short name T1120
Test name
Test status
Simulation time 94195819048 ps
CPU time 36.3 seconds
Started May 07 01:04:10 PM PDT 24
Finished May 07 01:04:48 PM PDT 24
Peak memory 200200 kb
Host smart-c01ef14a-1c42-499e-85e1-89fe639520f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700485296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3700485296
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.631413469
Short name T568
Test name
Test status
Simulation time 636004235464 ps
CPU time 1139.91 seconds
Started May 07 01:04:14 PM PDT 24
Finished May 07 01:23:15 PM PDT 24
Peak memory 225236 kb
Host smart-a48d42d9-e411-45f9-8c68-0f643df528e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631413469 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.631413469
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1722568116
Short name T223
Test name
Test status
Simulation time 37881818954 ps
CPU time 17.85 seconds
Started May 07 01:04:21 PM PDT 24
Finished May 07 01:04:40 PM PDT 24
Peak memory 200424 kb
Host smart-b0844e8c-8fc4-442b-ba70-c19db5070054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722568116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1722568116
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2632146049
Short name T214
Test name
Test status
Simulation time 89072317031 ps
CPU time 14.32 seconds
Started May 07 01:04:19 PM PDT 24
Finished May 07 01:04:35 PM PDT 24
Peak memory 200396 kb
Host smart-7c23784b-7a6d-4cee-b2ad-5ef7fc45398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632146049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2632146049
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1547530475
Short name T55
Test name
Test status
Simulation time 127941272519 ps
CPU time 736.28 seconds
Started May 07 01:04:21 PM PDT 24
Finished May 07 01:16:39 PM PDT 24
Peak memory 225300 kb
Host smart-fe1fe903-c55f-469b-84af-4d026d930932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547530475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1547530475
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3966403235
Short name T554
Test name
Test status
Simulation time 95682350074 ps
CPU time 19.12 seconds
Started May 07 01:04:19 PM PDT 24
Finished May 07 01:04:40 PM PDT 24
Peak memory 199324 kb
Host smart-44a9eaf7-39c7-4e67-972e-37367d1d59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966403235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3966403235
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3010341184
Short name T677
Test name
Test status
Simulation time 90407055851 ps
CPU time 908.53 seconds
Started May 07 01:04:22 PM PDT 24
Finished May 07 01:19:32 PM PDT 24
Peak memory 225136 kb
Host smart-fb1e429f-754e-4dde-b769-8898cb47c789
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010341184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3010341184
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2165946025
Short name T947
Test name
Test status
Simulation time 7403198496 ps
CPU time 50.37 seconds
Started May 07 01:04:19 PM PDT 24
Finished May 07 01:05:10 PM PDT 24
Peak memory 200452 kb
Host smart-d0b59d56-0820-48c7-9d34-7d8afc0b46db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165946025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2165946025
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1778898728
Short name T124
Test name
Test status
Simulation time 122088905289 ps
CPU time 345.66 seconds
Started May 07 01:04:18 PM PDT 24
Finished May 07 01:10:05 PM PDT 24
Peak memory 217036 kb
Host smart-650f574e-5d5b-4311-b51a-718a6611479c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778898728 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1778898728
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.337261816
Short name T25
Test name
Test status
Simulation time 47226348 ps
CPU time 0.6 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:00:22 PM PDT 24
Peak memory 195976 kb
Host smart-ed323824-57de-43b0-8654-b94751f875e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337261816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.337261816
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2822868845
Short name T693
Test name
Test status
Simulation time 209624723619 ps
CPU time 168.13 seconds
Started May 07 01:00:19 PM PDT 24
Finished May 07 01:03:09 PM PDT 24
Peak memory 200312 kb
Host smart-b9e56cc7-0435-4b6d-89fa-ef1c7f3a49b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822868845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2822868845
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.426739602
Short name T1023
Test name
Test status
Simulation time 68411009196 ps
CPU time 36.22 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:59 PM PDT 24
Peak memory 200276 kb
Host smart-fbd94c9b-84eb-430a-a72c-df3fd3c59131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426739602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.426739602
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2816887831
Short name T394
Test name
Test status
Simulation time 76214209662 ps
CPU time 84.1 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:01:46 PM PDT 24
Peak memory 200464 kb
Host smart-4c43e771-d716-4bf5-af7b-07d740de66ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816887831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2816887831
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4072251915
Short name T344
Test name
Test status
Simulation time 25829923772 ps
CPU time 18.13 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:41 PM PDT 24
Peak memory 200368 kb
Host smart-0fc6acd1-481c-48a0-a074-044510f1e584
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072251915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4072251915
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1538400635
Short name T128
Test name
Test status
Simulation time 127850040935 ps
CPU time 868.43 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:14:52 PM PDT 24
Peak memory 200448 kb
Host smart-c84e7779-0d66-4ccc-992d-66ad3fabb3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538400635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1538400635
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.391856739
Short name T531
Test name
Test status
Simulation time 12811755726 ps
CPU time 8.08 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:00:29 PM PDT 24
Peak memory 199184 kb
Host smart-e354e730-2efe-4134-b393-6d504a4a3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391856739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.391856739
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1501584362
Short name T589
Test name
Test status
Simulation time 39398635887 ps
CPU time 16.4 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:39 PM PDT 24
Peak memory 199020 kb
Host smart-8ca0840b-fdba-4309-b256-e4d631f9fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501584362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1501584362
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.562857825
Short name T281
Test name
Test status
Simulation time 10464788950 ps
CPU time 112.59 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:02:15 PM PDT 24
Peak memory 200328 kb
Host smart-f0c317c1-c855-496f-a9d6-0ba8b8b37f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562857825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.562857825
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1638619112
Short name T639
Test name
Test status
Simulation time 5554212519 ps
CPU time 17.45 seconds
Started May 07 01:00:19 PM PDT 24
Finished May 07 01:00:37 PM PDT 24
Peak memory 200352 kb
Host smart-3654ed78-63b2-4c3a-a645-3b4a17843225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638619112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1638619112
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.111406895
Short name T392
Test name
Test status
Simulation time 22633951795 ps
CPU time 32.14 seconds
Started May 07 01:00:24 PM PDT 24
Finished May 07 01:00:58 PM PDT 24
Peak memory 200436 kb
Host smart-50617529-e323-4267-bfe8-afcf98efaab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111406895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.111406895
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2491754281
Short name T1156
Test name
Test status
Simulation time 3883502826 ps
CPU time 1.17 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:24 PM PDT 24
Peak memory 196444 kb
Host smart-5dc2a75a-9e31-42e4-bb45-47fbbec32d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491754281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2491754281
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.39174368
Short name T1161
Test name
Test status
Simulation time 505381375 ps
CPU time 1.4 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:00:25 PM PDT 24
Peak memory 200044 kb
Host smart-936a56ee-916b-4c2f-ab35-d9dafe0a8ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39174368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.39174368
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1133467666
Short name T629
Test name
Test status
Simulation time 155909997192 ps
CPU time 788.77 seconds
Started May 07 01:00:18 PM PDT 24
Finished May 07 01:13:28 PM PDT 24
Peak memory 200428 kb
Host smart-592a303b-909c-484f-aa09-056d277a0bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133467666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1133467666
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3900018175
Short name T1038
Test name
Test status
Simulation time 29444727725 ps
CPU time 280.55 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:05:03 PM PDT 24
Peak memory 216052 kb
Host smart-671b9b32-13dc-47b9-a6e6-781a6f4a1e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900018175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3900018175
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3240341214
Short name T1041
Test name
Test status
Simulation time 2100085793 ps
CPU time 2.57 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:00:26 PM PDT 24
Peak memory 198720 kb
Host smart-e3b58f2b-d5b8-4e99-9b5d-636bbc92b8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240341214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3240341214
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.527745772
Short name T1091
Test name
Test status
Simulation time 51056831810 ps
CPU time 44.41 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:01:08 PM PDT 24
Peak memory 200368 kb
Host smart-63906ecc-9e79-4f7c-9b4b-9c630bb2c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527745772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.527745772
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3532478396
Short name T469
Test name
Test status
Simulation time 65007444104 ps
CPU time 22.36 seconds
Started May 07 01:04:18 PM PDT 24
Finished May 07 01:04:41 PM PDT 24
Peak memory 200384 kb
Host smart-1b22b61c-466f-49ca-8c99-81962bb7ae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532478396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3532478396
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3503372782
Short name T390
Test name
Test status
Simulation time 20294519037 ps
CPU time 258.15 seconds
Started May 07 01:04:20 PM PDT 24
Finished May 07 01:08:40 PM PDT 24
Peak memory 216284 kb
Host smart-a173cbf4-d4f9-47f7-83f3-85bfd5c72c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503372782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3503372782
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1158993741
Short name T1065
Test name
Test status
Simulation time 48717195291 ps
CPU time 70.75 seconds
Started May 07 01:04:20 PM PDT 24
Finished May 07 01:05:32 PM PDT 24
Peak memory 200396 kb
Host smart-96aa3429-b3d4-4727-92a8-cca4c6efa8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158993741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1158993741
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2699274660
Short name T122
Test name
Test status
Simulation time 63065473711 ps
CPU time 267.73 seconds
Started May 07 01:04:22 PM PDT 24
Finished May 07 01:08:51 PM PDT 24
Peak memory 216856 kb
Host smart-31638978-0bdc-48ad-98b0-7ad5b6a7a188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699274660 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2699274660
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2311163778
Short name T762
Test name
Test status
Simulation time 66974104526 ps
CPU time 19.27 seconds
Started May 07 01:04:21 PM PDT 24
Finished May 07 01:04:41 PM PDT 24
Peak memory 200316 kb
Host smart-2776a93c-0331-4c8c-90e2-14d327ed9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311163778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2311163778
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4165159513
Short name T1158
Test name
Test status
Simulation time 3157194236 ps
CPU time 11.88 seconds
Started May 07 01:04:20 PM PDT 24
Finished May 07 01:04:33 PM PDT 24
Peak memory 208896 kb
Host smart-3cf88439-3ca3-45f4-9131-9eb495811554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165159513 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4165159513
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2313408232
Short name T250
Test name
Test status
Simulation time 100002716921 ps
CPU time 56.29 seconds
Started May 07 01:04:21 PM PDT 24
Finished May 07 01:05:19 PM PDT 24
Peak memory 200392 kb
Host smart-c5292041-cb63-4864-8fe6-03968fd7e600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313408232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2313408232
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2871344836
Short name T934
Test name
Test status
Simulation time 75930383772 ps
CPU time 612.8 seconds
Started May 07 01:04:19 PM PDT 24
Finished May 07 01:14:34 PM PDT 24
Peak memory 211432 kb
Host smart-ff33c53e-9acc-4d0b-9236-68fc3fd262a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871344836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2871344836
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4276205956
Short name T742
Test name
Test status
Simulation time 69073245378 ps
CPU time 255.52 seconds
Started May 07 01:04:18 PM PDT 24
Finished May 07 01:08:35 PM PDT 24
Peak memory 216136 kb
Host smart-1f63c00f-7cb0-4d4b-aaf1-ba84dec75f9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276205956 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4276205956
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2827267432
Short name T988
Test name
Test status
Simulation time 13246569962 ps
CPU time 33.11 seconds
Started May 07 01:04:21 PM PDT 24
Finished May 07 01:04:56 PM PDT 24
Peak memory 200456 kb
Host smart-543c1a08-d352-4cb0-8ee0-aeb1c508eabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827267432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2827267432
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.367991155
Short name T706
Test name
Test status
Simulation time 189546451784 ps
CPU time 679.21 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:15:50 PM PDT 24
Peak memory 225188 kb
Host smart-9a1f7f02-0c34-4764-8ef4-5f4bc5dc405d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367991155 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.367991155
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.834786542
Short name T148
Test name
Test status
Simulation time 37483838118 ps
CPU time 65.98 seconds
Started May 07 01:04:27 PM PDT 24
Finished May 07 01:05:34 PM PDT 24
Peak memory 200500 kb
Host smart-c1a643f5-b105-407f-9467-3d309b77ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834786542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.834786542
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2869218854
Short name T123
Test name
Test status
Simulation time 18885210883 ps
CPU time 310.54 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:09:40 PM PDT 24
Peak memory 208772 kb
Host smart-227d8dc8-05fd-4847-b9a9-d90432618b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869218854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2869218854
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3854952610
Short name T795
Test name
Test status
Simulation time 52145526831 ps
CPU time 80.69 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:05:52 PM PDT 24
Peak memory 200456 kb
Host smart-27821834-1a9c-413a-a81e-d6ec87dcbe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854952610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3854952610
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3424239521
Short name T295
Test name
Test status
Simulation time 41825111085 ps
CPU time 515 seconds
Started May 07 01:04:30 PM PDT 24
Finished May 07 01:13:07 PM PDT 24
Peak memory 217100 kb
Host smart-a40d9180-53f7-402a-bf3f-8121b32083e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424239521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3424239521
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3937753090
Short name T180
Test name
Test status
Simulation time 30852250210 ps
CPU time 14.5 seconds
Started May 07 01:04:30 PM PDT 24
Finished May 07 01:04:46 PM PDT 24
Peak memory 200280 kb
Host smart-675cc23a-a60a-4440-8e39-bc8002d4a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937753090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3937753090
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.4280918008
Short name T1126
Test name
Test status
Simulation time 47082196251 ps
CPU time 285.75 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:09:16 PM PDT 24
Peak memory 215944 kb
Host smart-4390951d-cefc-4200-a490-c2617b8cf9e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280918008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.4280918008
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3858628242
Short name T118
Test name
Test status
Simulation time 57461155 ps
CPU time 0.54 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:00:28 PM PDT 24
Peak memory 194780 kb
Host smart-d7ffc62c-5a44-4e6a-8295-94c6fc363494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858628242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3858628242
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4132619434
Short name T332
Test name
Test status
Simulation time 107228912458 ps
CPU time 95.36 seconds
Started May 07 01:00:23 PM PDT 24
Finished May 07 01:01:59 PM PDT 24
Peak memory 200408 kb
Host smart-bd336376-849b-4da5-b914-35dab72a9977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132619434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4132619434
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2973405466
Short name T705
Test name
Test status
Simulation time 93062913971 ps
CPU time 230.51 seconds
Started May 07 01:00:24 PM PDT 24
Finished May 07 01:04:15 PM PDT 24
Peak memory 200428 kb
Host smart-77cb7487-672c-4f58-b66f-31804cd49aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973405466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2973405466
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.3613987160
Short name T1016
Test name
Test status
Simulation time 36047703841 ps
CPU time 62.31 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:01:24 PM PDT 24
Peak memory 200444 kb
Host smart-b1d37592-1517-4ebb-b49d-e765a2219137
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613987160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3613987160
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.4121870916
Short name T38
Test name
Test status
Simulation time 196356948126 ps
CPU time 1722.64 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:29:13 PM PDT 24
Peak memory 200376 kb
Host smart-28766cd1-4eb4-4dff-ac78-1e95a20b0248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121870916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.4121870916
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3917964844
Short name T978
Test name
Test status
Simulation time 6179203161 ps
CPU time 4.83 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:00:35 PM PDT 24
Peak memory 199540 kb
Host smart-f24bf5f9-89ba-46df-8636-9f700779ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917964844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3917964844
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2379032744
Short name T383
Test name
Test status
Simulation time 113587543511 ps
CPU time 46.39 seconds
Started May 07 01:00:23 PM PDT 24
Finished May 07 01:01:11 PM PDT 24
Peak memory 200620 kb
Host smart-a34f4a85-5908-4607-8f5b-d04dcbe08818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379032744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2379032744
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2782873805
Short name T455
Test name
Test status
Simulation time 5721457672 ps
CPU time 58.17 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:01:26 PM PDT 24
Peak memory 200416 kb
Host smart-b0c5383f-ce73-44d2-85a2-0c99896985e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782873805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2782873805
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.903198133
Short name T789
Test name
Test status
Simulation time 3009094866 ps
CPU time 10.25 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:33 PM PDT 24
Peak memory 199556 kb
Host smart-d30f54a3-4e18-4f72-931d-776ef3a7cd9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903198133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.903198133
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3188169004
Short name T645
Test name
Test status
Simulation time 41281363662 ps
CPU time 35.69 seconds
Started May 07 01:00:21 PM PDT 24
Finished May 07 01:00:58 PM PDT 24
Peak memory 196144 kb
Host smart-95292583-f138-4663-aa8e-a73f0db648a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188169004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3188169004
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3070733649
Short name T306
Test name
Test status
Simulation time 6276765040 ps
CPU time 14.47 seconds
Started May 07 01:00:22 PM PDT 24
Finished May 07 01:00:38 PM PDT 24
Peak memory 200184 kb
Host smart-fc31376c-0d0f-4c28-9e11-bd4fef9768bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070733649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3070733649
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.105653333
Short name T724
Test name
Test status
Simulation time 41023672556 ps
CPU time 433.34 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:07:43 PM PDT 24
Peak memory 217108 kb
Host smart-13ff2048-7b46-4330-a933-135fdc1a178d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105653333 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.105653333
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1036979428
Short name T506
Test name
Test status
Simulation time 3741115357 ps
CPU time 2.16 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:00:31 PM PDT 24
Peak memory 199336 kb
Host smart-006658e1-965f-45c7-a8e4-af06c4510126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036979428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1036979428
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.963465234
Short name T855
Test name
Test status
Simulation time 10113275839 ps
CPU time 16.51 seconds
Started May 07 01:00:20 PM PDT 24
Finished May 07 01:00:39 PM PDT 24
Peak memory 197252 kb
Host smart-7e85a8a5-4457-45a8-9118-057f70e282fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963465234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.963465234
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2711168713
Short name T206
Test name
Test status
Simulation time 103069952198 ps
CPU time 53.7 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:05:25 PM PDT 24
Peak memory 200364 kb
Host smart-7f635549-6dd9-44bf-999b-bad2db8a82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711168713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2711168713
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.176536199
Short name T637
Test name
Test status
Simulation time 67985341915 ps
CPU time 186.1 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:07:36 PM PDT 24
Peak memory 217028 kb
Host smart-bf494e3b-0bcd-4c5d-92b8-d7df88ff0726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176536199 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.176536199
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3360290460
Short name T914
Test name
Test status
Simulation time 24270443639 ps
CPU time 25.53 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:04:56 PM PDT 24
Peak memory 200504 kb
Host smart-b292d552-701c-48a7-938b-410a32c0ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360290460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3360290460
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2138604076
Short name T312
Test name
Test status
Simulation time 40570158910 ps
CPU time 840.95 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:18:30 PM PDT 24
Peak memory 225140 kb
Host smart-f74c7d76-9a9e-4eba-bdb7-f3f96279bd25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138604076 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2138604076
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3115070120
Short name T239
Test name
Test status
Simulation time 39417926358 ps
CPU time 72.23 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:05:42 PM PDT 24
Peak memory 200452 kb
Host smart-744d9cb3-d247-47b8-8197-621ff3fbffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115070120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3115070120
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3546202354
Short name T331
Test name
Test status
Simulation time 38121990148 ps
CPU time 21.47 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:04:50 PM PDT 24
Peak memory 200436 kb
Host smart-6b3a5c0d-55a0-433b-bbfd-9513b35020c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546202354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3546202354
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4043384668
Short name T32
Test name
Test status
Simulation time 22996548268 ps
CPU time 261.05 seconds
Started May 07 01:04:31 PM PDT 24
Finished May 07 01:08:54 PM PDT 24
Peak memory 217080 kb
Host smart-1655d7dd-ee92-409a-bbfb-36733693e505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043384668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4043384668
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3792367194
Short name T1132
Test name
Test status
Simulation time 65046770935 ps
CPU time 28.9 seconds
Started May 07 01:04:32 PM PDT 24
Finished May 07 01:05:03 PM PDT 24
Peak memory 199872 kb
Host smart-7bc0a2fd-8664-4f90-8439-605e7f268e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792367194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3792367194
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.339235009
Short name T601
Test name
Test status
Simulation time 119405200677 ps
CPU time 370.03 seconds
Started May 07 01:04:26 PM PDT 24
Finished May 07 01:10:37 PM PDT 24
Peak memory 216884 kb
Host smart-5398bbba-cbe9-4076-958f-00ffb39db3ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339235009 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.339235009
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1548459948
Short name T199
Test name
Test status
Simulation time 171348297503 ps
CPU time 107.86 seconds
Started May 07 01:04:30 PM PDT 24
Finished May 07 01:06:20 PM PDT 24
Peak memory 200388 kb
Host smart-db2cb4b3-7b62-4c18-af97-4f6ea08b8328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548459948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1548459948
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3161539073
Short name T580
Test name
Test status
Simulation time 19261327146 ps
CPU time 3.46 seconds
Started May 07 01:04:30 PM PDT 24
Finished May 07 01:04:35 PM PDT 24
Peak memory 200168 kb
Host smart-7c9ec5e9-b375-45f3-8aaf-f1ddd2a0709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161539073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3161539073
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1340556713
Short name T665
Test name
Test status
Simulation time 132140222825 ps
CPU time 406.5 seconds
Started May 07 01:04:29 PM PDT 24
Finished May 07 01:11:18 PM PDT 24
Peak memory 217004 kb
Host smart-3a978dcf-f14d-4b17-bca5-8dd64d8214a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340556713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1340556713
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.49409985
Short name T761
Test name
Test status
Simulation time 41619452651 ps
CPU time 24.15 seconds
Started May 07 01:04:31 PM PDT 24
Finished May 07 01:04:56 PM PDT 24
Peak memory 200412 kb
Host smart-07dda714-2f64-4835-b94d-7eadfb6d6e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49409985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.49409985
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2490852776
Short name T963
Test name
Test status
Simulation time 38134587751 ps
CPU time 662.02 seconds
Started May 07 01:04:28 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 217144 kb
Host smart-489c9575-2515-40d3-aa5f-14b4e6fce547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490852776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2490852776
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1943978201
Short name T241
Test name
Test status
Simulation time 20572062015 ps
CPU time 38.5 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:05:15 PM PDT 24
Peak memory 200452 kb
Host smart-9dff19b9-7841-4d45-85d6-51137901fac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943978201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1943978201
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.780659773
Short name T1026
Test name
Test status
Simulation time 32468914738 ps
CPU time 382.43 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:10:58 PM PDT 24
Peak memory 216060 kb
Host smart-7a13d241-cca8-4e72-b77f-2110095ab1ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780659773 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.780659773
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3274750920
Short name T1047
Test name
Test status
Simulation time 109292197042 ps
CPU time 539.88 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:13:36 PM PDT 24
Peak memory 200440 kb
Host smart-f6818edc-5121-42b7-af36-334a6629ffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274750920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3274750920
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3752447226
Short name T477
Test name
Test status
Simulation time 18394554 ps
CPU time 0.55 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:00:30 PM PDT 24
Peak memory 195816 kb
Host smart-1b0306bb-45b0-4811-bea8-26f735460ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752447226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3752447226
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1749970403
Short name T496
Test name
Test status
Simulation time 87810090479 ps
CPU time 122.39 seconds
Started May 07 01:00:29 PM PDT 24
Finished May 07 01:02:33 PM PDT 24
Peak memory 200336 kb
Host smart-1c4c9eb3-bd8b-44d9-881a-3f310e3cec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749970403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1749970403
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3425756960
Short name T967
Test name
Test status
Simulation time 47270751602 ps
CPU time 67.05 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:01:35 PM PDT 24
Peak memory 200332 kb
Host smart-235c505d-2c77-4450-a44b-44d7ae021495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425756960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3425756960
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.28258478
Short name T694
Test name
Test status
Simulation time 21380757838 ps
CPU time 23.91 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:00:51 PM PDT 24
Peak memory 199504 kb
Host smart-31e26faa-78a4-4a4f-9f8a-07d855e04d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28258478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.28258478
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3015839096
Short name T566
Test name
Test status
Simulation time 31792822313 ps
CPU time 8.15 seconds
Started May 07 01:00:29 PM PDT 24
Finished May 07 01:00:39 PM PDT 24
Peak memory 200428 kb
Host smart-e4fe06c1-6960-4f2f-9bf8-69a06ae8348a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015839096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3015839096
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.919552462
Short name T956
Test name
Test status
Simulation time 122415127894 ps
CPU time 398.92 seconds
Started May 07 01:00:27 PM PDT 24
Finished May 07 01:07:07 PM PDT 24
Peak memory 200452 kb
Host smart-7891138a-c13c-4870-9123-9864ab6eda16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919552462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.919552462
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1064168256
Short name T495
Test name
Test status
Simulation time 8660362928 ps
CPU time 10.64 seconds
Started May 07 01:00:25 PM PDT 24
Finished May 07 01:00:37 PM PDT 24
Peak memory 200320 kb
Host smart-c289700e-b40e-4450-b52f-9ee26c259568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064168256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1064168256
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.411745010
Short name T1182
Test name
Test status
Simulation time 6292463828 ps
CPU time 9.97 seconds
Started May 07 01:00:32 PM PDT 24
Finished May 07 01:00:44 PM PDT 24
Peak memory 198532 kb
Host smart-037cc7d0-f6c9-412a-ad4f-42e348016cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411745010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.411745010
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1977546481
Short name T624
Test name
Test status
Simulation time 28234254181 ps
CPU time 552.81 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:09:42 PM PDT 24
Peak memory 200468 kb
Host smart-f3682ab0-6dce-4abc-9f45-6e2c7f8f6802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977546481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1977546481
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3679904897
Short name T350
Test name
Test status
Simulation time 2388340597 ps
CPU time 4.1 seconds
Started May 07 01:00:29 PM PDT 24
Finished May 07 01:00:35 PM PDT 24
Peak memory 198296 kb
Host smart-ec612e1d-e7af-458e-aebb-739cf484f5bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679904897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3679904897
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.721069931
Short name T468
Test name
Test status
Simulation time 102484672025 ps
CPU time 407.93 seconds
Started May 07 01:00:25 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 200444 kb
Host smart-d47e29d9-57e0-4701-97bf-68b67b6d0929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721069931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.721069931
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1232958541
Short name T364
Test name
Test status
Simulation time 5303447138 ps
CPU time 2.09 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:00:30 PM PDT 24
Peak memory 196416 kb
Host smart-9cd12d87-c6f8-4c27-ae0d-02d04c942206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232958541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1232958541
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3291757377
Short name T986
Test name
Test status
Simulation time 489249803 ps
CPU time 1.41 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:00:35 PM PDT 24
Peak memory 199984 kb
Host smart-065b1042-bbd5-4c54-b6f8-a76cd220fae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291757377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3291757377
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.614779345
Short name T1028
Test name
Test status
Simulation time 1801052776 ps
CPU time 2.69 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:00:33 PM PDT 24
Peak memory 199040 kb
Host smart-ec2a6aa4-ebe1-4570-88e6-897185b02c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614779345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.614779345
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.926375283
Short name T714
Test name
Test status
Simulation time 41587355982 ps
CPU time 70.51 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:01:40 PM PDT 24
Peak memory 200432 kb
Host smart-4a63236f-3d78-4fe0-b49d-d8c177e35289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926375283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.926375283
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2884197585
Short name T1154
Test name
Test status
Simulation time 19856553969 ps
CPU time 32.5 seconds
Started May 07 01:04:34 PM PDT 24
Finished May 07 01:05:08 PM PDT 24
Peak memory 200152 kb
Host smart-cc1314e5-c453-4bb3-9e9b-d567a67cb1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884197585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2884197585
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4246008166
Short name T208
Test name
Test status
Simulation time 44926018158 ps
CPU time 521.65 seconds
Started May 07 01:04:37 PM PDT 24
Finished May 07 01:13:20 PM PDT 24
Peak memory 217224 kb
Host smart-0d0880da-0fbd-4774-963a-40118cbea69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246008166 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4246008166
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.242965543
Short name T207
Test name
Test status
Simulation time 26536696314 ps
CPU time 22.1 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:04:59 PM PDT 24
Peak memory 200468 kb
Host smart-dcb9bd68-75de-4245-840e-d8086876c6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242965543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.242965543
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2876407661
Short name T73
Test name
Test status
Simulation time 8661016457 ps
CPU time 111.98 seconds
Started May 07 01:04:37 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 208900 kb
Host smart-9965952e-d88b-4847-9edc-c298ce878fa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876407661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2876407661
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3652519367
Short name T197
Test name
Test status
Simulation time 19346024892 ps
CPU time 16.85 seconds
Started May 07 01:04:34 PM PDT 24
Finished May 07 01:04:52 PM PDT 24
Peak memory 200408 kb
Host smart-92de0e99-0732-4d41-9953-7da764184b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652519367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3652519367
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1454880974
Short name T1147
Test name
Test status
Simulation time 46075630970 ps
CPU time 703.29 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:16:21 PM PDT 24
Peak memory 217080 kb
Host smart-a6e7f27a-6c6e-46e6-aed4-f03aac7e7d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454880974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1454880974
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3133146619
Short name T960
Test name
Test status
Simulation time 504891943634 ps
CPU time 1619.54 seconds
Started May 07 01:04:37 PM PDT 24
Finished May 07 01:31:38 PM PDT 24
Peak memory 229324 kb
Host smart-df358c54-3ada-48ce-be32-4605f88363ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133146619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3133146619
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1457477610
Short name T78
Test name
Test status
Simulation time 10555818532 ps
CPU time 9.31 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:04:47 PM PDT 24
Peak memory 199040 kb
Host smart-8cddae14-d7b1-49a9-abf7-b76fb09e440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457477610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1457477610
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.264880168
Short name T30
Test name
Test status
Simulation time 66526863845 ps
CPU time 785.55 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:17:42 PM PDT 24
Peak memory 225304 kb
Host smart-07bd426d-924b-4f85-b1f6-febb45c99e4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264880168 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.264880168
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2928279098
Short name T414
Test name
Test status
Simulation time 96139022494 ps
CPU time 41.22 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:05:19 PM PDT 24
Peak memory 200372 kb
Host smart-58c624a3-2e0a-458c-8e99-1a2649573854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928279098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2928279098
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3542407218
Short name T227
Test name
Test status
Simulation time 153825695645 ps
CPU time 481.51 seconds
Started May 07 01:04:38 PM PDT 24
Finished May 07 01:12:41 PM PDT 24
Peak memory 216896 kb
Host smart-9a64429b-a6f6-495d-ad29-65365dc4c8a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542407218 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3542407218
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2574537460
Short name T220
Test name
Test status
Simulation time 14219141163 ps
CPU time 29.32 seconds
Started May 07 01:04:39 PM PDT 24
Finished May 07 01:05:09 PM PDT 24
Peak memory 200412 kb
Host smart-e39d9fad-18b9-4804-a22a-4906b216413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574537460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2574537460
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.830193831
Short name T31
Test name
Test status
Simulation time 113575851783 ps
CPU time 417.49 seconds
Started May 07 01:04:36 PM PDT 24
Finished May 07 01:11:35 PM PDT 24
Peak memory 225244 kb
Host smart-277221ab-f108-4033-bfff-e6c1bfca17a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830193831 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.830193831
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.61444245
Short name T308
Test name
Test status
Simulation time 161931967175 ps
CPU time 81.98 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:05:59 PM PDT 24
Peak memory 200400 kb
Host smart-80b7d1da-25f7-480f-97cb-d0c653deded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61444245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.61444245
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3893593705
Short name T894
Test name
Test status
Simulation time 73744985824 ps
CPU time 189.23 seconds
Started May 07 01:04:37 PM PDT 24
Finished May 07 01:07:47 PM PDT 24
Peak memory 217108 kb
Host smart-71c0bfe3-5e8e-4037-8a3e-4128d399d632
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893593705 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3893593705
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2103365532
Short name T1003
Test name
Test status
Simulation time 12086634045 ps
CPU time 130.27 seconds
Started May 07 01:04:38 PM PDT 24
Finished May 07 01:06:49 PM PDT 24
Peak memory 208716 kb
Host smart-a3451e55-3d2c-4f75-a2c6-8864896310cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103365532 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2103365532
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2882736463
Short name T547
Test name
Test status
Simulation time 103580599621 ps
CPU time 190.47 seconds
Started May 07 01:04:35 PM PDT 24
Finished May 07 01:07:47 PM PDT 24
Peak memory 200432 kb
Host smart-fc84757a-cf99-4d19-b094-482acb4dda8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882736463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2882736463
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.4182534398
Short name T121
Test name
Test status
Simulation time 60708353617 ps
CPU time 180.65 seconds
Started May 07 01:04:44 PM PDT 24
Finished May 07 01:07:46 PM PDT 24
Peak memory 208736 kb
Host smart-e2b55f56-9963-467e-b26f-4dc8596648cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182534398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.4182534398
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1960785412
Short name T628
Test name
Test status
Simulation time 49581418 ps
CPU time 0.6 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:00:30 PM PDT 24
Peak memory 195880 kb
Host smart-72ba693f-0ec6-40b9-8b61-48aead4d77fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960785412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1960785412
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2364497808
Short name T612
Test name
Test status
Simulation time 223579321807 ps
CPU time 303.76 seconds
Started May 07 01:00:33 PM PDT 24
Finished May 07 01:05:38 PM PDT 24
Peak memory 200508 kb
Host smart-39e2ed62-6e26-4859-9e48-7294f7dc091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364497808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2364497808
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.4166766884
Short name T112
Test name
Test status
Simulation time 150808722881 ps
CPU time 321.69 seconds
Started May 07 01:00:24 PM PDT 24
Finished May 07 01:05:48 PM PDT 24
Peak memory 200364 kb
Host smart-61afbfdf-893a-4d95-bec3-0b252232e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166766884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.4166766884
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.435674055
Short name T1083
Test name
Test status
Simulation time 6706577088 ps
CPU time 11.86 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:00:40 PM PDT 24
Peak memory 198884 kb
Host smart-6648394e-0a95-487f-bafd-e5942ff33a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435674055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.435674055
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.177037163
Short name T908
Test name
Test status
Simulation time 52150965757 ps
CPU time 22.55 seconds
Started May 07 01:00:32 PM PDT 24
Finished May 07 01:00:56 PM PDT 24
Peak memory 200140 kb
Host smart-6683875b-93c2-4fc1-a636-2b5196b5b978
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177037163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.177037163
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2155112577
Short name T459
Test name
Test status
Simulation time 118288904223 ps
CPU time 219.5 seconds
Started May 07 01:00:30 PM PDT 24
Finished May 07 01:04:11 PM PDT 24
Peak memory 200364 kb
Host smart-0e8f29c8-414f-445a-9e02-1a0cc5c1f852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155112577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2155112577
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2398988010
Short name T499
Test name
Test status
Simulation time 10705235762 ps
CPU time 18.57 seconds
Started May 07 01:00:29 PM PDT 24
Finished May 07 01:00:49 PM PDT 24
Peak memory 200348 kb
Host smart-19b70adc-3f51-49b7-b3ea-a78768451e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398988010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2398988010
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2549112557
Short name T1084
Test name
Test status
Simulation time 99543171704 ps
CPU time 105.12 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:02:15 PM PDT 24
Peak memory 200168 kb
Host smart-8a78e757-cf90-4a0c-a6d1-0e6ad23942d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549112557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2549112557
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3577469673
Short name T1140
Test name
Test status
Simulation time 6237330900 ps
CPU time 91.06 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:02:00 PM PDT 24
Peak memory 200420 kb
Host smart-fa502163-cefe-4ece-90f5-57da5b01ddc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577469673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3577469673
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1005314937
Short name T343
Test name
Test status
Simulation time 1610873987 ps
CPU time 2.03 seconds
Started May 07 01:00:28 PM PDT 24
Finished May 07 01:00:32 PM PDT 24
Peak memory 198516 kb
Host smart-9f2ba273-d179-424c-a07a-ae94881eebae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005314937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1005314937
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3258841963
Short name T1048
Test name
Test status
Simulation time 115889429844 ps
CPU time 118.97 seconds
Started May 07 01:00:29 PM PDT 24
Finished May 07 01:02:30 PM PDT 24
Peak memory 200332 kb
Host smart-1f27a7fd-6d2a-4f98-954b-ba7f89588a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258841963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3258841963
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2646208987
Short name T540
Test name
Test status
Simulation time 3745477751 ps
CPU time 1.64 seconds
Started May 07 01:00:30 PM PDT 24
Finished May 07 01:00:33 PM PDT 24
Peak memory 196728 kb
Host smart-a1c7ed8f-124c-492a-848c-b599e5c29f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646208987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2646208987
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2689828901
Short name T597
Test name
Test status
Simulation time 652642936 ps
CPU time 3.06 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:00:30 PM PDT 24
Peak memory 198724 kb
Host smart-f6a4f680-e3ed-4482-960f-93bc3f2c5122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689828901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2689828901
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.781424557
Short name T1175
Test name
Test status
Simulation time 341244574181 ps
CPU time 508.02 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:08:56 PM PDT 24
Peak memory 200380 kb
Host smart-4829ce3c-9b70-42f2-a108-414256e3e90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781424557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.781424557
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3525470860
Short name T1112
Test name
Test status
Simulation time 167913918489 ps
CPU time 467.88 seconds
Started May 07 01:00:25 PM PDT 24
Finished May 07 01:08:15 PM PDT 24
Peak memory 216892 kb
Host smart-9ae057ad-7758-4980-9411-cf6ce1aebfd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525470860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3525470860
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2084852166
Short name T549
Test name
Test status
Simulation time 433996030 ps
CPU time 1.85 seconds
Started May 07 01:00:27 PM PDT 24
Finished May 07 01:00:30 PM PDT 24
Peak memory 200296 kb
Host smart-9c05c4e3-fb62-492c-a77b-e7a442889ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084852166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2084852166
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1512729689
Short name T995
Test name
Test status
Simulation time 12167837589 ps
CPU time 19.62 seconds
Started May 07 01:00:26 PM PDT 24
Finished May 07 01:00:47 PM PDT 24
Peak memory 200456 kb
Host smart-5d3c9e73-d002-4ac2-a6af-112f4e35fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512729689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1512729689
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1812228918
Short name T573
Test name
Test status
Simulation time 148893513193 ps
CPU time 112.21 seconds
Started May 07 01:04:44 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 200412 kb
Host smart-f74b78b8-b799-49c1-8ac2-d618c26b5261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812228918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1812228918
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.4028509016
Short name T168
Test name
Test status
Simulation time 321574707477 ps
CPU time 889.49 seconds
Started May 07 01:04:45 PM PDT 24
Finished May 07 01:19:36 PM PDT 24
Peak memory 225240 kb
Host smart-257af621-b7b8-4735-9b32-741baaa4a612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028509016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4028509016
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3756432300
Short name T579
Test name
Test status
Simulation time 7801038873 ps
CPU time 8.74 seconds
Started May 07 01:04:43 PM PDT 24
Finished May 07 01:04:52 PM PDT 24
Peak memory 200352 kb
Host smart-253f9b59-4931-426b-a106-59e2b4068c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756432300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3756432300
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1589978289
Short name T797
Test name
Test status
Simulation time 20636111944 ps
CPU time 256.33 seconds
Started May 07 01:04:46 PM PDT 24
Finished May 07 01:09:03 PM PDT 24
Peak memory 217088 kb
Host smart-bbc00e01-4fb3-43af-b18d-03754a0cea33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589978289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1589978289
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2012803751
Short name T296
Test name
Test status
Simulation time 27854976960 ps
CPU time 18.85 seconds
Started May 07 01:04:43 PM PDT 24
Finished May 07 01:05:02 PM PDT 24
Peak memory 200408 kb
Host smart-17762f09-5f17-49ed-9d56-972b871bb483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012803751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2012803751
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3443490864
Short name T61
Test name
Test status
Simulation time 195002273289 ps
CPU time 467.88 seconds
Started May 07 01:04:44 PM PDT 24
Finished May 07 01:12:34 PM PDT 24
Peak memory 216988 kb
Host smart-315a6ee1-8268-4e54-bc72-981b53c652d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443490864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3443490864
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.68080669
Short name T289
Test name
Test status
Simulation time 35920105039 ps
CPU time 71.95 seconds
Started May 07 01:04:48 PM PDT 24
Finished May 07 01:06:01 PM PDT 24
Peak memory 200364 kb
Host smart-cb1089f8-184d-4844-8d6a-81c5348486a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68080669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.68080669
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3975615979
Short name T661
Test name
Test status
Simulation time 475601723129 ps
CPU time 762.34 seconds
Started May 07 01:04:47 PM PDT 24
Finished May 07 01:17:30 PM PDT 24
Peak memory 225188 kb
Host smart-a0fe7bec-076f-4627-8700-d95e2dba4df3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975615979 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3975615979
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2796271699
Short name T435
Test name
Test status
Simulation time 24213411661 ps
CPU time 22.6 seconds
Started May 07 01:04:45 PM PDT 24
Finished May 07 01:05:09 PM PDT 24
Peak memory 200372 kb
Host smart-7074e211-e927-4e96-8976-2ebcbfc36caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796271699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2796271699
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3152540990
Short name T1082
Test name
Test status
Simulation time 18877568765 ps
CPU time 329.67 seconds
Started May 07 01:04:44 PM PDT 24
Finished May 07 01:10:15 PM PDT 24
Peak memory 215804 kb
Host smart-255d13f1-182c-4036-9c73-78816dfc9ed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152540990 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3152540990
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3220479049
Short name T1107
Test name
Test status
Simulation time 78468988820 ps
CPU time 24.51 seconds
Started May 07 01:04:45 PM PDT 24
Finished May 07 01:05:10 PM PDT 24
Peak memory 200464 kb
Host smart-1fb46651-a2be-42ce-9e61-6dc329483569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220479049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3220479049
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1876145431
Short name T917
Test name
Test status
Simulation time 3049444265 ps
CPU time 21.02 seconds
Started May 07 01:04:43 PM PDT 24
Finished May 07 01:05:06 PM PDT 24
Peak memory 200516 kb
Host smart-45e66917-c8f6-414e-816e-6277396975ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876145431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1876145431
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.518067673
Short name T1110
Test name
Test status
Simulation time 40931094568 ps
CPU time 65.21 seconds
Started May 07 01:04:45 PM PDT 24
Finished May 07 01:05:52 PM PDT 24
Peak memory 200500 kb
Host smart-d95f1ada-cc7c-4e15-98ea-511b38b7ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518067673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.518067673
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2274948778
Short name T187
Test name
Test status
Simulation time 65002710204 ps
CPU time 261.5 seconds
Started May 07 01:04:46 PM PDT 24
Finished May 07 01:09:09 PM PDT 24
Peak memory 216864 kb
Host smart-67342ce8-db89-4a0b-9097-8a220e7d9deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274948778 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2274948778
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3567567053
Short name T173
Test name
Test status
Simulation time 65749976835 ps
CPU time 59.34 seconds
Started May 07 01:04:44 PM PDT 24
Finished May 07 01:05:45 PM PDT 24
Peak memory 200444 kb
Host smart-4cf5fa17-00af-4e22-8624-2b8f64a869c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567567053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3567567053
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1071278315
Short name T192
Test name
Test status
Simulation time 160491152669 ps
CPU time 1112.21 seconds
Started May 07 01:04:44 PM PDT 24
Finished May 07 01:23:17 PM PDT 24
Peak memory 225360 kb
Host smart-efbfd6b0-fa5f-4d40-82a9-0fa7ef4febb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071278315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1071278315
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3999726847
Short name T145
Test name
Test status
Simulation time 15112066525 ps
CPU time 27.23 seconds
Started May 07 01:04:41 PM PDT 24
Finished May 07 01:05:09 PM PDT 24
Peak memory 200388 kb
Host smart-b2b12c72-3741-4f35-9d5d-a0e23e109df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999726847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3999726847
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.4179578622
Short name T975
Test name
Test status
Simulation time 299575119790 ps
CPU time 828.35 seconds
Started May 07 01:04:42 PM PDT 24
Finished May 07 01:18:31 PM PDT 24
Peak memory 227256 kb
Host smart-650893d8-f44e-4280-aa7a-b94576604496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179578622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.4179578622
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2154985962
Short name T247
Test name
Test status
Simulation time 10145963885 ps
CPU time 17.86 seconds
Started May 07 01:04:43 PM PDT 24
Finished May 07 01:05:02 PM PDT 24
Peak memory 200364 kb
Host smart-11acca0e-03e2-4420-b697-600f0534ae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154985962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2154985962
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1539817285
Short name T824
Test name
Test status
Simulation time 15883095284 ps
CPU time 139.92 seconds
Started May 07 01:04:47 PM PDT 24
Finished May 07 01:07:07 PM PDT 24
Peak memory 216796 kb
Host smart-fc9ee551-9e1f-464e-9813-6263ace66b66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539817285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1539817285
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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