Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	114434	1			T1	27		T3	161		T4	32
all_values[1]	114434	1			T1	27		T3	161		T4	32
all_values[2]	114434	1			T1	27		T3	161		T4	32
all_values[3]	114434	1			T1	27		T3	161		T4	32
all_values[4]	114434	1			T1	27		T3	161		T4	32
all_values[5]	114434	1			T1	27		T3	161		T4	32
all_values[6]	114434	1			T1	27		T3	161		T4	32
all_values[7]	114434	1			T1	27		T3	161		T4	32

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

459423

1

T1

81

T3

714

T4

103

auto[1]

456049

1

T1

135

T3

574

T4

153

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

858811

1

T1

180

T3

1282

T4

252

auto[1]

56661

1

T1

36

T3

6

T4

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36117	1			T3	94		T6	1		T7	3
all_values[0]	auto[0]	auto[1]	20814	1			T3	2		T4	3		T5	3
all_values[0]	auto[1]	auto[0]	33761	1			T3	65		T4	29		T7	569
all_values[0]	auto[1]	auto[1]	23742	1			T1	27		T6	13		T7	1
all_values[1]	auto[0]	auto[0]	50634	1			T3	156		T4	3		T6	1
all_values[1]	auto[0]	auto[1]	1699	1			T7	9		T12	2		T36	4
all_values[1]	auto[1]	auto[0]	60258	1			T1	27		T3	5		T4	29
all_values[1]	auto[1]	auto[1]	1843	1			T6	13		T12	1		T35	1
all_values[2]	auto[0]	auto[0]	54704	1			T1	27		T3	3		T4	30
all_values[2]	auto[0]	auto[1]	2875	1			T8	2		T9	1		T10	1
all_values[2]	auto[1]	auto[0]	54413	1			T3	154		T4	1		T5	1
all_values[2]	auto[1]	auto[1]	2442	1			T3	4		T4	1		T5	2
all_values[3]	auto[0]	auto[0]	63440	1			T3	161		T4	30		T5	2
all_values[3]	auto[0]	auto[1]	320	1			T5	1		T14	1		T15	1
all_values[3]	auto[1]	auto[0]	50311	1			T1	27		T4	2		T7	481
all_values[3]	auto[1]	auto[1]	363	1			T12	1		T17	5		T42	2
all_values[4]	auto[0]	auto[0]	56227	1			T3	67		T4	30		T5	3
all_values[4]	auto[0]	auto[1]	516	1			T17	3		T21	9		T103	1
all_values[4]	auto[1]	auto[0]	57220	1			T1	18		T3	94		T4	2
all_values[4]	auto[1]	auto[1]	471	1			T1	9		T12	4		T17	3
all_values[5]	auto[0]	auto[0]	57501	1			T1	27		T3	5		T4	3
all_values[5]	auto[0]	auto[1]	198	1			T12	1		T17	3		T102	1
all_values[5]	auto[1]	auto[0]	56525	1			T3	156		T4	29		T5	3
all_values[5]	auto[1]	auto[1]	210	1			T12	3		T17	5		T102	3
all_values[6]	auto[0]	auto[0]	56980	1			T1	27		T3	67		T4	3
all_values[6]	auto[0]	auto[1]	190	1			T17	4		T102	3		T33	1
all_values[6]	auto[1]	auto[0]	57075	1			T3	94		T4	29		T6	16
all_values[6]	auto[1]	auto[1]	189	1			T12	3		T17	3		T102	1
all_values[7]	auto[0]	auto[0]	56768	1			T3	159		T4	1		T5	3
all_values[7]	auto[0]	auto[1]	440	1			T18	7		T17	5		T22	5
all_values[7]	auto[1]	auto[0]	56877	1			T1	27		T3	2		T4	31
all_values[7]	auto[1]	auto[1]	349	1			T17	4		T153	1		T102	2