Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2401	1			T3	2		T4	1		T9	1
auto[BaudRate115200]	2006	1			T4	1		T5	1		T9	1
auto[BaudRate230400]	1940	1			T1	1		T3	1		T6	1
auto[BaudRate128Kbps]	2143	1			T3	2		T5	1		T6	3
auto[BaudRate256Kbps]	2297	1			T3	3		T4	2		T5	1
auto[BaudRate1Mbps]	1862	1			T3	1		T4	2		T5	2
auto[BaudRate1p5Mbps]	1274	1			T3	1		T6	1		T7	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1603	1			T5	5		T23	27		T40	8
freqs[25]	1315	1			T37	5		T15	51		T351	5
freqs[48]	539	1			T36	8		T186	6		T212	7
freqs[50]	714	1			T4	6		T311	8		T358	30
freqs[100]	1398	1			T18	49		T46	6		T281	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	243	1			T23	3		T40	1		T43	4
auto[BaudRate9600]	freqs[25]	213	1			T37	2		T15	5		T359	6
auto[BaudRate9600]	freqs[48]	114	1			T299	2		T183	4		T360	14
auto[BaudRate9600]	freqs[50]	123	1			T4	1		T311	3		T361	1
auto[BaudRate9600]	freqs[100]	228	1			T18	6		T24	1		T303	1
auto[BaudRate115200]	freqs[24]	240	1			T5	1		T23	9		T40	1
auto[BaudRate115200]	freqs[25]	212	1			T37	1		T15	10		T351	1
auto[BaudRate115200]	freqs[48]	72	1			T186	3		T212	2		T322	1
auto[BaudRate115200]	freqs[50]	86	1			T4	1		T311	1		T358	3
auto[BaudRate115200]	freqs[100]	185	1			T18	6		T281	3		T24	5
auto[BaudRate230400]	freqs[24]	236	1			T23	3		T40	1		T43	2
auto[BaudRate230400]	freqs[25]	166	1			T15	7		T351	1		T359	6
auto[BaudRate230400]	freqs[48]	69	1			T322	1		T299	4		T183	6
auto[BaudRate230400]	freqs[50]	78	1			T190	1		T349	1		T60	2
auto[BaudRate230400]	freqs[100]	196	1			T18	6		T103	2		T24	5
auto[BaudRate128Kbps]	freqs[24]	270	1			T5	1		T23	6		T40	1
auto[BaudRate128Kbps]	freqs[25]	218	1			T15	4		T351	1		T171	2
auto[BaudRate128Kbps]	freqs[48]	54	1			T299	1		T183	6		T362	3
auto[BaudRate128Kbps]	freqs[50]	108	1			T358	9		T361	1		T190	2
auto[BaudRate128Kbps]	freqs[100]	190	1			T18	11		T103	1		T24	7
auto[BaudRate256Kbps]	freqs[24]	246	1			T5	1		T40	2		T20	7
auto[BaudRate256Kbps]	freqs[25]	204	1			T37	2		T15	10		T351	2
auto[BaudRate256Kbps]	freqs[48]	66	1			T36	3		T186	1		T212	2
auto[BaudRate256Kbps]	freqs[50]	119	1			T4	2		T311	1		T361	1
auto[BaudRate256Kbps]	freqs[100]	218	1			T18	9		T46	2		T281	1
auto[BaudRate1Mbps]	freqs[24]	266	1			T5	2		T23	6		T40	1
auto[BaudRate1Mbps]	freqs[25]	212	1			T15	10		T171	2		T359	3
auto[BaudRate1Mbps]	freqs[48]	71	1			T36	3		T322	1		T299	1
auto[BaudRate1Mbps]	freqs[50]	101	1			T4	2		T311	2		T358	6
auto[BaudRate1Mbps]	freqs[100]	186	1			T18	6		T46	1		T24	4
auto[BaudRate1p5Mbps]	freqs[25]	90	1			T15	5		T359	6		T363	3
auto[BaudRate1p5Mbps]	freqs[48]	93	1			T36	2		T186	2		T212	3
auto[BaudRate1p5Mbps]	freqs[50]	99	1			T311	1		T358	12		T361	2
auto[BaudRate1p5Mbps]	freqs[100]	195	1			T18	5		T46	3		T281	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded