Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.97	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	4	126	96.92

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	4	126	96.92	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28422706	1			T1	10		T3	486		T4	83
all_levels[1]	177782	1			T3	86		T4	44		T5	2
all_levels[2]	2102	1			T3	5		T4	12		T34	2
all_levels[3]	971	1			T4	9		T6	3		T34	1
all_levels[4]	673	1			T4	1		T6	1		T35	7
all_levels[5]	488	1			T6	1		T35	2		T38	1
all_levels[6]	402	1			T35	3		T37	1		T38	2
all_levels[7]	340	1			T35	2		T38	1		T39	1
all_levels[8]	282	1			T9	2		T35	1		T15	1
all_levels[9]	276	1			T6	1		T9	2		T148	1
all_levels[10]	219	1			T6	2		T9	1		T40	2
all_levels[11]	166	1			T38	2		T40	1		T15	2
all_levels[12]	186	1			T9	1		T38	1		T15	1
all_levels[13]	125	1			T9	1		T148	1		T17	1
all_levels[14]	128	1			T148	1		T17	1		T133	2
all_levels[15]	130	1			T44	1		T149	1		T134	1
all_levels[16]	95	1			T15	1		T150	1		T151	1
all_levels[17]	92	1			T43	1		T152	1		T153	1
all_levels[18]	83	1			T38	2		T154	1		T133	1
all_levels[19]	93	1			T154	1		T155	2		T152	1
all_levels[20]	70	1			T38	1		T152	1		T139	1
all_levels[21]	62	1			T9	1		T154	1		T30	1
all_levels[22]	54	1			T148	1		T44	1		T156	1
all_levels[23]	77	1			T15	1		T17	1		T133	2
all_levels[24]	66	1			T15	1		T17	1		T30	1
all_levels[25]	51	1			T133	1		T157	1		T158	2
all_levels[26]	47	1			T40	2		T159	1		T160	1
all_levels[27]	54	1			T6	2		T15	2		T161	1
all_levels[28]	38	1			T153	1		T162	2		T163	2
all_levels[29]	39	1			T155	1		T164	3		T165	2
all_levels[30]	32	1			T38	1		T17	1		T133	1
all_levels[31]	33	1			T6	1		T166	1		T158	1
all_levels[32]	32	1			T40	1		T155	2		T135	3
all_levels[33]	39	1			T38	1		T148	2		T167	1
all_levels[34]	29	1			T40	1		T148	1		T168	1
all_levels[35]	32	1			T40	3		T148	1		T156	1
all_levels[36]	25	1			T151	3		T169	1		T170	1
all_levels[37]	26	1			T148	1		T17	2		T134	1
all_levels[38]	28	1			T6	1		T134	2		T171	1
all_levels[39]	39	1			T38	1		T172	1		T173	1
all_levels[40]	15	1			T174	1		T175	1		T176	1
all_levels[41]	17	1			T177	1		T178	1		T179	1
all_levels[42]	14	1			T166	1		T180	1		T162	1
all_levels[43]	31	1			T14	1		T181	1		T158	1
all_levels[44]	23	1			T135	1		T168	1		T32	1
all_levels[45]	17	1			T32	1		T162	1		T182	1
all_levels[46]	11	1			T183	1		T184	1		T185	1
all_levels[47]	17	1			T186	1		T187	1		T175	1
all_levels[48]	15	1			T188	1		T189	2		T190	1
all_levels[49]	12	1			T154	1		T183	1		T158	1
all_levels[50]	13	1			T18	1		T17	1		T156	2
all_levels[51]	10	1			T17	1		T30	2		T190	1
all_levels[52]	13	1			T20	1		T191	1		T192	6
all_levels[53]	14	1			T20	1		T30	1		T168	1
all_levels[54]	17	1			T40	1		T161	1		T193	2
all_levels[55]	10	1			T148	1		T194	1		T195	1
all_levels[56]	10	1			T14	1		T196	1		T197	1
all_levels[57]	10	1			T138	1		T188	1		T166	1
all_levels[58]	12	1			T184	1		T176	1		T198	2
all_levels[59]	5	1			T89	1		T199	1		T200	1
all_levels[60]	7	1			T17	1		T201	1		T202	1
all_levels[61]	5	1			T161	1		T201	1		T203	1
all_levels[62]	7	1			T139	1		T204	2		T205	2
all_levels[63]	11	1			T20	1		T206	1		T207	1
all_levels[64]	143	1			T5	2		T14	1		T17	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28603707

1

T3

568

T4

146

T5

7

auto[1]

4964

1

T1

10

T3

9

T4

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	4	126	96.92	4

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28418267	1			T3	477		T4	80		T5	5
all_levels[0]	auto[1]	4439	1			T1	10		T3	9		T4	3
all_levels[1]	auto[0]	177706	1			T3	86		T4	44		T5	1
all_levels[1]	auto[1]	76	1			T5	1		T6	1		T35	1
all_levels[2]	auto[0]	2069	1			T3	5		T4	12		T34	2
all_levels[2]	auto[1]	33	1			T162	1		T208	1		T209	1
all_levels[3]	auto[0]	952	1			T4	9		T6	3		T34	1
all_levels[3]	auto[1]	19	1			T133	1		T181	2		T210	1
all_levels[4]	auto[0]	649	1			T4	1		T6	1		T35	7
all_levels[4]	auto[1]	24	1			T161	1		T138	1		T211	2
all_levels[5]	auto[0]	479	1			T6	1		T35	2		T38	1
all_levels[5]	auto[1]	9	1			T212	1		T159	1		T113	1
all_levels[6]	auto[0]	384	1			T35	3		T37	1		T38	2
all_levels[6]	auto[1]	18	1			T211	1		T172	3		T213	1
all_levels[7]	auto[0]	326	1			T35	2		T38	1		T39	1
all_levels[7]	auto[1]	14	1			T152	1		T157	2		T169	1
all_levels[8]	auto[0]	266	1			T9	2		T35	1		T15	1
all_levels[8]	auto[1]	16	1			T209	1		T214	1		T215	1
all_levels[9]	auto[0]	250	1			T6	1		T9	2		T148	1
all_levels[9]	auto[1]	26	1			T169	1		T209	1		T213	1
all_levels[10]	auto[0]	202	1			T6	2		T9	1		T40	2
all_levels[10]	auto[1]	17	1			T216	1		T217	1		T218	1
all_levels[11]	auto[0]	158	1			T38	1		T40	1		T15	2
all_levels[11]	auto[1]	8	1			T38	1		T175	1		T219	2
all_levels[12]	auto[0]	181	1			T9	1		T38	1		T15	1
all_levels[12]	auto[1]	5	1			T220	1		T221	1		T222	1
all_levels[13]	auto[0]	116	1			T9	1		T148	1		T17	1
all_levels[13]	auto[1]	9	1			T157	2		T223	1		T224	2
all_levels[14]	auto[0]	117	1			T148	1		T17	1		T133	1
all_levels[14]	auto[1]	11	1			T133	1		T152	2		T225	1
all_levels[15]	auto[0]	117	1			T44	1		T149	1		T134	1
all_levels[15]	auto[1]	13	1			T58	1		T173	2		T226	1
all_levels[16]	auto[0]	86	1			T15	1		T150	1		T151	1
all_levels[16]	auto[1]	9	1			T165	1		T122	1		T227	1
all_levels[17]	auto[0]	80	1			T43	1		T152	1		T153	1
all_levels[17]	auto[1]	12	1			T228	1		T58	1		T229	2
all_levels[18]	auto[0]	74	1			T38	2		T154	1		T133	1
all_levels[18]	auto[1]	9	1			T208	1		T228	1		T230	3
all_levels[19]	auto[0]	80	1			T154	1		T155	1		T152	1
all_levels[19]	auto[1]	13	1			T155	1		T231	2		T232	1
all_levels[20]	auto[0]	64	1			T38	1		T152	1		T139	1
all_levels[20]	auto[1]	6	1			T233	1		T234	1		T235	1
all_levels[21]	auto[0]	58	1			T9	1		T154	1		T30	1
all_levels[21]	auto[1]	4	1			T236	2		T75	1		T237	1
all_levels[22]	auto[0]	49	1			T148	1		T44	1		T156	1
all_levels[22]	auto[1]	5	1			T123	1		T238	1		T239	1
all_levels[23]	auto[0]	67	1			T15	1		T17	1		T133	1
all_levels[23]	auto[1]	10	1			T133	1		T240	1		T241	3
all_levels[24]	auto[0]	62	1			T15	1		T17	1		T30	1
all_levels[24]	auto[1]	4	1			T192	1		T242	1		T221	1
all_levels[25]	auto[0]	48	1			T133	1		T157	1		T158	2
all_levels[25]	auto[1]	3	1			T243	2		T244	1		-	-
all_levels[26]	auto[0]	45	1			T40	1		T159	1		T160	1
all_levels[26]	auto[1]	2	1			T40	1		T220	1		-	-
all_levels[27]	auto[0]	43	1			T6	2		T15	1		T161	1
all_levels[27]	auto[1]	11	1			T15	1		T150	1		T245	1
all_levels[28]	auto[0]	32	1			T153	1		T162	1		T163	2
all_levels[28]	auto[1]	6	1			T162	1		T246	4		T247	1
all_levels[29]	auto[0]	35	1			T155	1		T164	2		T165	1
all_levels[29]	auto[1]	4	1			T164	1		T165	1		T248	1
all_levels[30]	auto[0]	32	1			T38	1		T17	1		T133	1
all_levels[31]	auto[0]	32	1			T6	1		T166	1		T158	1
all_levels[31]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[32]	auto[0]	27	1			T40	1		T155	1		T135	1
all_levels[32]	auto[1]	5	1			T155	1		T135	2		T250	1
all_levels[33]	auto[0]	32	1			T38	1		T148	2		T167	1
all_levels[33]	auto[1]	7	1			T251	3		T170	1		T252	1
all_levels[34]	auto[0]	25	1			T40	1		T148	1		T168	1
all_levels[34]	auto[1]	4	1			T169	1		T253	3		-	-
all_levels[35]	auto[0]	20	1			T40	1		T148	1		T156	1
all_levels[35]	auto[1]	12	1			T40	2		T254	1		T255	1
all_levels[36]	auto[0]	19	1			T151	1		T169	1		T170	1
all_levels[36]	auto[1]	6	1			T151	2		T256	1		T257	1
all_levels[37]	auto[0]	25	1			T148	1		T17	2		T134	1
all_levels[37]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[38]	auto[0]	25	1			T6	1		T134	2		T171	1
all_levels[38]	auto[1]	3	1			T259	3		-	-		-	-
all_levels[39]	auto[0]	14	1			T38	1		T172	1		T173	1
all_levels[39]	auto[1]	25	1			T260	22		T261	3		-	-
all_levels[40]	auto[0]	14	1			T174	1		T175	1		T176	1
all_levels[40]	auto[1]	1	1			T262	1		-	-		-	-
all_levels[41]	auto[0]	16	1			T177	1		T178	1		T179	1
all_levels[41]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[42]	auto[0]	13	1			T166	1		T180	1		T162	1
all_levels[42]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[43]	auto[0]	26	1			T14	1		T181	1		T158	1
all_levels[43]	auto[1]	5	1			T263	1		T260	1		T264	3
all_levels[44]	auto[0]	21	1			T135	1		T168	1		T32	1
all_levels[44]	auto[1]	2	1			T182	2		-	-		-	-
all_levels[45]	auto[0]	15	1			T32	1		T162	1		T182	1
all_levels[45]	auto[1]	2	1			T265	2		-	-		-	-
all_levels[46]	auto[0]	11	1			T183	1		T184	1		T185	1
all_levels[47]	auto[0]	16	1			T186	1		T187	1		T175	1
all_levels[47]	auto[1]	1	1			T182	1		-	-		-	-
all_levels[48]	auto[0]	14	1			T188	1		T189	2		T190	1
all_levels[48]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[49]	auto[0]	11	1			T154	1		T183	1		T158	1
all_levels[49]	auto[1]	1	1			T266	1		-	-		-	-
all_levels[50]	auto[0]	12	1			T18	1		T17	1		T156	1
all_levels[50]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[51]	auto[0]	8	1			T17	1		T30	2		T190	1
all_levels[51]	auto[1]	2	1			T233	1		T194	1		-	-
all_levels[52]	auto[0]	8	1			T20	1		T191	1		T192	1
all_levels[52]	auto[1]	5	1			T192	5		-	-		-	-
all_levels[53]	auto[0]	13	1			T20	1		T30	1		T168	1
all_levels[53]	auto[1]	1	1			T207	1		-	-		-	-
all_levels[54]	auto[0]	13	1			T40	1		T161	1		T193	1
all_levels[54]	auto[1]	4	1			T193	1		T267	1		T268	2
all_levels[55]	auto[0]	8	1			T148	1		T194	1		T195	1
all_levels[55]	auto[1]	2	1			T269	1		T270	1		-	-
all_levels[56]	auto[0]	9	1			T14	1		T196	1		T197	1
all_levels[56]	auto[1]	1	1			T271	1		-	-		-	-
all_levels[57]	auto[0]	8	1			T138	1		T188	1		T166	1
all_levels[57]	auto[1]	2	1			T272	2		-	-		-	-
all_levels[58]	auto[0]	11	1			T184	1		T176	1		T198	2
all_levels[58]	auto[1]	1	1			T273	1		-	-		-	-
all_levels[59]	auto[0]	5	1			T89	1		T199	1		T200	1
all_levels[60]	auto[0]	6	1			T17	1		T201	1		T202	1
all_levels[60]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[61]	auto[0]	4	1			T161	1		T201	1		T203	1
all_levels[61]	auto[1]	1	1			T255	1		-	-		-	-
all_levels[62]	auto[0]	6	1			T139	1		T204	2		T205	1
all_levels[62]	auto[1]	1	1			T205	1		-	-		-	-
all_levels[63]	auto[0]	11	1			T20	1		T206	1		T207	1
all_levels[64]	auto[0]	115	1			T5	1		T14	1		T17	1
all_levels[64]	auto[1]	28	1			T5	1		T138	1		T274	1