Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	114434	1			T1	27		T3	161		T4	32
all_pins[1]	114434	1			T1	27		T3	161		T4	32
all_pins[2]	114434	1			T1	27		T3	161		T4	32
all_pins[3]	114434	1			T1	27		T3	161		T4	32
all_pins[4]	114434	1			T1	27		T3	161		T4	32
all_pins[5]	114434	1			T1	27		T3	161		T4	32
all_pins[6]	114434	1			T1	27		T3	161		T4	32
all_pins[7]	114434	1			T1	27		T3	161		T4	32

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	884933	1			T1	180		T3	1284		T4	255
values[0x1]	30539	1			T1	36		T3	4		T4	1
transitions[0x0=>0x1]	29222	1			T1	36		T3	4		T4	1
transitions[0x1=>0x0]	28795	1			T1	35		T3	4		T4	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90608	1			T3	161		T4	32		T5	3
all_pins[0]	values[0x1]	23826	1			T1	27		T6	13		T7	1
all_pins[0]	transitions[0x0=>0x1]	23109	1			T1	27		T7	1		T8	3
all_pins[0]	transitions[0x1=>0x0]	1129	1			T38	10		T40	10		T17	4
all_pins[1]	values[0x0]	112588	1			T1	27		T3	161		T4	32
all_pins[1]	values[0x1]	1846	1			T6	13		T12	1		T35	1
all_pins[1]	transitions[0x0=>0x1]	1728	1			T6	10		T35	1		T38	10
all_pins[1]	transitions[0x1=>0x0]	2395	1			T3	4		T4	1		T5	2
all_pins[2]	values[0x0]	111921	1			T1	27		T3	157		T4	31
all_pins[2]	values[0x1]	2513	1			T3	4		T4	1		T5	2
all_pins[2]	transitions[0x0=>0x1]	2423	1			T3	4		T4	1		T5	2
all_pins[2]	transitions[0x1=>0x0]	273	1			T17	5		T21	2		T103	1
all_pins[3]	values[0x0]	114071	1			T1	27		T3	161		T4	32
all_pins[3]	values[0x1]	363	1			T12	1		T17	5		T42	2
all_pins[3]	transitions[0x0=>0x1]	318	1			T17	3		T42	2		T21	2
all_pins[3]	transitions[0x1=>0x0]	426	1			T1	9		T12	3		T17	1
all_pins[4]	values[0x0]	113963	1			T1	18		T3	161		T4	32
all_pins[4]	values[0x1]	471	1			T1	9		T12	4		T17	3
all_pins[4]	transitions[0x0=>0x1]	395	1			T1	9		T12	1		T17	1
all_pins[4]	transitions[0x1=>0x0]	193	1			T17	3		T21	2		T102	2
all_pins[5]	values[0x0]	114165	1			T1	27		T3	161		T4	32
all_pins[5]	values[0x1]	269	1			T12	3		T17	5		T21	2
all_pins[5]	transitions[0x0=>0x1]	212	1			T17	2		T21	2		T22	1
all_pins[5]	transitions[0x1=>0x0]	845	1			T38	2		T39	1		T14	1
all_pins[6]	values[0x0]	113532	1			T1	27		T3	161		T4	32
all_pins[6]	values[0x1]	902	1			T12	3		T38	2		T39	1
all_pins[6]	transitions[0x0=>0x1]	844	1			T12	3		T38	2		T39	1
all_pins[6]	transitions[0x1=>0x0]	291	1			T17	3		T153	1		T102	2
all_pins[7]	values[0x0]	114085	1			T1	27		T3	161		T4	32
all_pins[7]	values[0x1]	349	1			T17	4		T153	1		T102	2
all_pins[7]	transitions[0x0=>0x1]	193	1			T17	1		T153	1		T102	1
all_pins[7]	transitions[0x1=>0x0]	23243	1			T1	26		T6	13		T8	2