Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6242566	1			T1	8		T3	22		T5	3
all_levels[1]	1235813	1			T4	1		T5	2		T6	7
all_levels[2]	356562	1			T11	551		T12	1458		T36	2457
all_levels[3]	396546	1			T9	5		T11	551		T12	1351
all_levels[4]	307075	1			T3	1		T9	11		T11	550
all_levels[5]	216145	1			T6	1		T11	551		T12	1344
all_levels[6]	201595	1			T11	545		T12	1101		T36	2439
all_levels[7]	199246	1			T5	2		T11	552		T12	1059
all_levels[8]	333933	1			T3	5		T11	550		T12	1215
all_levels[9]	310354	1			T11	551		T12	1016		T36	1968
all_levels[10]	310933	1			T11	36600		T12	1150		T36	1968
all_levels[11]	260884	1			T11	551		T12	1338		T36	1963
all_levels[12]	242086	1			T11	548		T12	1509		T36	1966
all_levels[13]	195405	1			T11	550		T12	1587		T34	3
all_levels[14]	199670	1			T6	1		T11	551		T12	1557
all_levels[15]	286597	1			T11	552		T12	1534		T34	2
all_levels[16]	363308	1			T6	5		T11	537		T12	1451
all_levels[17]	190290	1			T6	2		T11	551		T12	1286
all_levels[18]	447510	1			T11	550		T12	1160		T35	2
all_levels[19]	453564	1			T3	12		T5	4		T11	551
all_levels[20]	355031	1			T11	552		T12	1396		T36	1944
all_levels[21]	243704	1			T11	549		T12	1426		T34	5
all_levels[22]	276518	1			T6	2		T11	551		T12	1255
all_levels[23]	288155	1			T11	551		T12	1115		T36	1956
all_levels[24]	273024	1			T4	4		T11	551		T12	1208
all_levels[25]	293476	1			T11	551		T12	1238		T35	1
all_levels[26]	312095	1			T11	527		T12	1395		T35	2
all_levels[27]	249961	1			T3	352		T11	551		T12	1656
all_levels[28]	337920	1			T3	186		T11	552		T12	1660
all_levels[29]	173795	1			T11	549		T12	1573		T36	1958
all_levels[30]	567133	1			T6	3		T11	550		T12	1787
all_levels[31]	539250	1			T11	553		T12	2504		T36	2048
all_levels[32]	11948133	1			T4	148		T7	311256		T8	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28603707

1

T3

568

T4

146

T5

7

auto[1]

4570

1

T1

8

T3

10

T4

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6240198	1			T3	19		T5	3		T6	15
all_levels[0]	auto[1]	2368	1			T1	8		T3	3		T6	2
all_levels[1]	auto[0]	1235438	1			T4	1		T5	1		T6	6
all_levels[1]	auto[1]	375	1			T5	1		T6	1		T35	1
all_levels[2]	auto[0]	356533	1			T11	551		T12	1458		T36	2457
all_levels[2]	auto[1]	29	1			T156	1		T160	1		T274	1
all_levels[3]	auto[0]	396344	1			T9	5		T11	551		T12	1351
all_levels[3]	auto[1]	202	1			T131	1		T152	1		T365	1
all_levels[4]	auto[0]	307038	1			T3	1		T9	11		T11	550
all_levels[4]	auto[1]	37	1			T133	1		T159	1		T320	3
all_levels[5]	auto[0]	216125	1			T6	1		T11	551		T12	1344
all_levels[5]	auto[1]	20	1			T155	1		T315	1		T180	1
all_levels[6]	auto[0]	201559	1			T11	545		T12	1101		T36	2439
all_levels[6]	auto[1]	36	1			T186	1		T206	1		T300	1
all_levels[7]	auto[0]	199032	1			T5	1		T11	552		T12	1059
all_levels[7]	auto[1]	214	1			T5	1		T103	18		T132	1
all_levels[8]	auto[0]	333898	1			T3	3		T11	550		T12	1215
all_levels[8]	auto[1]	35	1			T3	2		T161	1		T152	2
all_levels[9]	auto[0]	310320	1			T11	551		T12	1016		T36	1968
all_levels[9]	auto[1]	34	1			T48	3		T160	1		T164	1
all_levels[10]	auto[0]	310899	1			T11	36600		T12	1150		T36	1968
all_levels[10]	auto[1]	34	1			T187	1		T240	1		T158	1
all_levels[11]	auto[0]	260850	1			T11	551		T12	1338		T36	1963
all_levels[11]	auto[1]	34	1			T18	1		T295	1		T315	3
all_levels[12]	auto[0]	242059	1			T11	548		T12	1509		T36	1966
all_levels[12]	auto[1]	27	1			T157	2		T216	1		T263	2
all_levels[13]	auto[0]	195382	1			T11	550		T12	1587		T34	2
all_levels[13]	auto[1]	23	1			T34	1		T172	3		T366	1
all_levels[14]	auto[0]	199632	1			T6	1		T11	551		T12	1557
all_levels[14]	auto[1]	38	1			T24	1		T288	3		T304	3
all_levels[15]	auto[0]	286421	1			T11	552		T12	1534		T34	2
all_levels[15]	auto[1]	176	1			T280	4		T160	1		T164	1
all_levels[16]	auto[0]	363287	1			T6	3		T11	537		T12	1451
all_levels[16]	auto[1]	21	1			T6	2		T38	1		T216	1
all_levels[17]	auto[0]	190268	1			T6	2		T11	551		T12	1286
all_levels[17]	auto[1]	22	1			T212	2		T216	1		T367	1
all_levels[18]	auto[0]	447480	1			T11	550		T12	1160		T35	2
all_levels[18]	auto[1]	30	1			T48	1		T149	1		T311	1
all_levels[19]	auto[0]	453540	1			T3	10		T5	2		T11	551
all_levels[19]	auto[1]	24	1			T3	2		T5	2		T157	1
all_levels[20]	auto[0]	355000	1			T11	552		T12	1396		T36	1944
all_levels[20]	auto[1]	31	1			T228	1		T123	2		T184	2
all_levels[21]	auto[0]	243683	1			T11	549		T12	1426		T34	5
all_levels[21]	auto[1]	21	1			T14	1		T187	1		T368	1
all_levels[22]	auto[0]	276495	1			T6	2		T11	551		T12	1255
all_levels[22]	auto[1]	23	1			T38	1		T15	1		T351	1
all_levels[23]	auto[0]	288134	1			T11	551		T12	1115		T36	1956
all_levels[23]	auto[1]	21	1			T161	2		T160	1		T165	1
all_levels[24]	auto[0]	272994	1			T4	2		T11	551		T12	1208
all_levels[24]	auto[1]	30	1			T4	2		T155	1		T299	1
all_levels[25]	auto[0]	293451	1			T11	551		T12	1238		T35	1
all_levels[25]	auto[1]	25	1			T38	2		T156	1		T102	1
all_levels[26]	auto[0]	312085	1			T11	527		T12	1395		T35	2
all_levels[26]	auto[1]	10	1			T194	2		T218	2		T254	2
all_levels[27]	auto[0]	249939	1			T3	350		T11	551		T12	1656
all_levels[27]	auto[1]	22	1			T3	2		T14	3		T159	2
all_levels[28]	auto[0]	337899	1			T3	185		T11	552		T12	1660
all_levels[28]	auto[1]	21	1			T3	1		T38	2		T251	1
all_levels[29]	auto[0]	173770	1			T11	549		T12	1573		T36	1958
all_levels[29]	auto[1]	25	1			T240	4		T311	3		T147	1
all_levels[30]	auto[0]	567107	1			T6	2		T11	550		T12	1787
all_levels[30]	auto[1]	26	1			T6	1		T159	2		T157	4
all_levels[31]	auto[0]	539224	1			T11	553		T12	2504		T36	2048
all_levels[31]	auto[1]	26	1			T302	1		T208	1		T348	1
all_levels[32]	auto[0]	11947623	1			T4	143		T7	311255		T8	1
all_levels[32]	auto[1]	510	1			T4	5		T7	1		T8	1