Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	833	1			T12	4		T17	15		T102	4
all_values[1]	833	1			T12	4		T17	15		T102	4
all_values[2]	833	1			T12	4		T17	15		T102	4
all_values[3]	833	1			T12	4		T17	15		T102	4
all_values[4]	833	1			T12	4		T17	15		T102	4
all_values[5]	833	1			T12	4		T17	15		T102	4
all_values[6]	833	1			T12	4		T17	15		T102	4
all_values[7]	833	1			T12	4		T17	15		T102	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3604

1

T12

7

T17

68

T102

21

auto[1]

3060

1

T12

25

T17

52

T102

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2451

1

T12

13

T17

44

T102

15

auto[1]

4213

1

T12

19

T17

76

T102

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3897

1

T12

21

T17

73

T102

23

auto[1]

2767

1

T12

11

T17

47

T102

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	252	1			T12	1		T17	3		T102	2
all_values[0]	auto[0]	auto[1]	auto[1]	241	1			T12	3		T17	5		T33	3
all_values[0]	auto[1]	auto[0]	auto[1]	191	1			T17	4		T102	1		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T17	3		T102	1		T33	2
all_values[1]	auto[0]	auto[0]	auto[0]	251	1			T17	2		T102	3		T33	1
all_values[1]	auto[0]	auto[1]	auto[0]	243	1			T12	3		T17	6		T33	4
all_values[1]	auto[1]	auto[0]	auto[1]	181	1			T17	5		T102	1		T33	1
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T12	1		T17	2		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T17	5		T102	3		T33	2
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T17	3		T137	1		T145	1
all_values[2]	auto[0]	auto[1]	auto[0]	163	1			T12	2		T17	1		T102	1
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T137	2		T145	1		T49	3
all_values[2]	auto[1]	auto[0]	auto[1]	201	1			T17	6		T33	2		T146	3
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T12	2		T33	3		T137	2
all_values[3]	auto[0]	auto[0]	auto[0]	201	1			T12	1		T17	2		T102	2
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T17	2		T137	1		T147	1
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T12	2		T17	2		T102	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T17	4		T145	1		T146	1
all_values[3]	auto[1]	auto[0]	auto[1]	203	1			T17	3		T33	4		T137	2
all_values[3]	auto[1]	auto[1]	auto[1]	141	1			T12	1		T17	2		T137	1
all_values[4]	auto[0]	auto[0]	auto[0]	199	1			T17	3		T102	1		T33	3
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T17	1		T137	2		T145	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T17	5		T102	1		T137	1
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T12	2		T17	1		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T17	2		T102	1		T33	1
all_values[4]	auto[1]	auto[1]	auto[1]	145	1			T12	2		T17	3		T102	1
all_values[5]	auto[0]	auto[0]	auto[0]	178	1			T17	3		T33	1		T137	1
all_values[5]	auto[0]	auto[0]	auto[1]	88	1			T17	1		T102	1		T137	3
all_values[5]	auto[0]	auto[1]	auto[0]	137	1			T17	4		T137	1		T145	2
all_values[5]	auto[0]	auto[1]	auto[1]	78	1			T12	1		T17	1		T102	2
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T12	1		T17	2		T102	1
all_values[5]	auto[1]	auto[1]	auto[1]	177	1			T12	2		T17	4		T33	2
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T17	5		T33	1		T137	2
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T17	3		T102	2		T145	1
all_values[6]	auto[0]	auto[1]	auto[0]	167	1			T12	1		T17	2		T33	1
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T12	1		T17	1		T33	2
all_values[6]	auto[1]	auto[0]	auto[1]	205	1			T17	2		T102	1		T145	3
all_values[6]	auto[1]	auto[1]	auto[1]	141	1			T12	2		T17	2		T102	1
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T12	4		T17	3		T102	2
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T17	3		T146	2		T147	2
all_values[7]	auto[0]	auto[1]	auto[0]	125	1			T17	1		T33	1		T137	3
all_values[7]	auto[0]	auto[1]	auto[1]	98	1			T17	1		T102	1		T33	3
all_values[7]	auto[1]	auto[0]	auto[1]	179	1			T17	5		T33	1		T145	3
all_values[7]	auto[1]	auto[1]	auto[1]	172	1			T17	2		T102	1		T137	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal