Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.29 99.27 97.95 100.00 98.80 100.00 99.73


Total test records in report: 1319
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T1253 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.737310069 May 09 02:34:33 PM PDT 24 May 09 02:34:41 PM PDT 24 28070718 ps
T1254 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3988568262 May 09 02:34:23 PM PDT 24 May 09 02:34:29 PM PDT 24 107131416 ps
T1255 /workspace/coverage/cover_reg_top/13.uart_intr_test.3399967531 May 09 02:34:36 PM PDT 24 May 09 02:34:43 PM PDT 24 21499458 ps
T1256 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1259126929 May 09 02:34:28 PM PDT 24 May 09 02:34:35 PM PDT 24 190843191 ps
T1257 /workspace/coverage/cover_reg_top/40.uart_intr_test.876773843 May 09 02:34:48 PM PDT 24 May 09 02:34:54 PM PDT 24 14623521 ps
T1258 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2523286791 May 09 02:34:26 PM PDT 24 May 09 02:34:33 PM PDT 24 23857881 ps
T1259 /workspace/coverage/cover_reg_top/1.uart_intr_test.3711944827 May 09 02:34:26 PM PDT 24 May 09 02:34:31 PM PDT 24 14055556 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1135977991 May 09 02:34:31 PM PDT 24 May 09 02:34:39 PM PDT 24 22422006 ps
T1261 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3118473347 May 09 02:34:43 PM PDT 24 May 09 02:34:48 PM PDT 24 22887253 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1633134049 May 09 02:34:19 PM PDT 24 May 09 02:34:26 PM PDT 24 14277631 ps
T1263 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.81880391 May 09 02:34:37 PM PDT 24 May 09 02:34:44 PM PDT 24 30991111 ps
T1264 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3431221550 May 09 02:34:25 PM PDT 24 May 09 02:34:32 PM PDT 24 172515623 ps
T109 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.166399225 May 09 02:34:47 PM PDT 24 May 09 02:34:53 PM PDT 24 44559395 ps
T1265 /workspace/coverage/cover_reg_top/0.uart_intr_test.1294419839 May 09 02:34:38 PM PDT 24 May 09 02:34:44 PM PDT 24 39528528 ps
T1266 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4754712 May 09 02:34:27 PM PDT 24 May 09 02:34:33 PM PDT 24 87826687 ps
T1267 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4082244300 May 09 02:34:35 PM PDT 24 May 09 02:34:43 PM PDT 24 749741424 ps
T1268 /workspace/coverage/cover_reg_top/2.uart_csr_rw.4094993172 May 09 02:34:25 PM PDT 24 May 09 02:34:30 PM PDT 24 52264694 ps
T1269 /workspace/coverage/cover_reg_top/5.uart_intr_test.999692012 May 09 02:34:25 PM PDT 24 May 09 02:34:31 PM PDT 24 19120988 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3071178838 May 09 02:34:22 PM PDT 24 May 09 02:34:28 PM PDT 24 51106522 ps
T1271 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2631214576 May 09 02:34:42 PM PDT 24 May 09 02:34:47 PM PDT 24 23340763 ps
T1272 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1856318231 May 09 02:34:30 PM PDT 24 May 09 02:34:38 PM PDT 24 23923284 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_intr_test.3201381754 May 09 02:34:44 PM PDT 24 May 09 02:34:49 PM PDT 24 36277232 ps
T1274 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2714930621 May 09 02:34:23 PM PDT 24 May 09 02:34:28 PM PDT 24 26610189 ps
T1275 /workspace/coverage/cover_reg_top/16.uart_intr_test.284815002 May 09 02:34:37 PM PDT 24 May 09 02:34:44 PM PDT 24 38568452 ps
T1276 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1615225297 May 09 02:34:28 PM PDT 24 May 09 02:34:36 PM PDT 24 75953532 ps
T1277 /workspace/coverage/cover_reg_top/3.uart_tl_errors.837532868 May 09 02:34:24 PM PDT 24 May 09 02:34:31 PM PDT 24 57669066 ps
T1278 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4081679938 May 09 02:34:32 PM PDT 24 May 09 02:34:41 PM PDT 24 112985540 ps
T1279 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2889003375 May 09 02:34:39 PM PDT 24 May 09 02:34:46 PM PDT 24 89921910 ps
T1280 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3095783403 May 09 02:34:25 PM PDT 24 May 09 02:34:31 PM PDT 24 89392200 ps
T1281 /workspace/coverage/cover_reg_top/9.uart_intr_test.3229743508 May 09 02:34:33 PM PDT 24 May 09 02:34:41 PM PDT 24 112489269 ps
T1282 /workspace/coverage/cover_reg_top/49.uart_intr_test.2389733584 May 09 02:34:49 PM PDT 24 May 09 02:34:55 PM PDT 24 15443738 ps
T1283 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.888479409 May 09 02:34:32 PM PDT 24 May 09 02:34:40 PM PDT 24 91674528 ps
T1284 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1095848454 May 09 02:34:36 PM PDT 24 May 09 02:34:44 PM PDT 24 483791718 ps
T1285 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.47152007 May 09 02:34:29 PM PDT 24 May 09 02:34:37 PM PDT 24 57394384 ps
T73 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2790057268 May 09 02:34:28 PM PDT 24 May 09 02:34:37 PM PDT 24 1650040607 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_csr_rw.976055685 May 09 02:34:27 PM PDT 24 May 09 02:34:33 PM PDT 24 24880890 ps
T1287 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4083856428 May 09 02:34:23 PM PDT 24 May 09 02:34:29 PM PDT 24 49604256 ps
T1288 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3715612847 May 09 02:34:31 PM PDT 24 May 09 02:34:39 PM PDT 24 29226209 ps
T1289 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.978760843 May 09 02:34:14 PM PDT 24 May 09 02:34:22 PM PDT 24 165768776 ps
T1290 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.868753522 May 09 02:34:24 PM PDT 24 May 09 02:34:30 PM PDT 24 63477611 ps
T1291 /workspace/coverage/cover_reg_top/7.uart_intr_test.4271057550 May 09 02:34:27 PM PDT 24 May 09 02:34:34 PM PDT 24 17485494 ps
T1292 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1318692447 May 09 02:34:23 PM PDT 24 May 09 02:34:29 PM PDT 24 68250106 ps
T1293 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2152078934 May 09 02:34:22 PM PDT 24 May 09 02:34:29 PM PDT 24 34779925 ps
T1294 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.420822890 May 09 02:34:31 PM PDT 24 May 09 02:34:39 PM PDT 24 81232157 ps
T1295 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.693222993 May 09 02:34:38 PM PDT 24 May 09 02:34:45 PM PDT 24 105314434 ps
T1296 /workspace/coverage/cover_reg_top/37.uart_intr_test.2955305077 May 09 02:34:45 PM PDT 24 May 09 02:34:50 PM PDT 24 17009814 ps
T1297 /workspace/coverage/cover_reg_top/22.uart_intr_test.3027453641 May 09 02:34:49 PM PDT 24 May 09 02:34:55 PM PDT 24 13816219 ps
T1298 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3558409535 May 09 02:34:37 PM PDT 24 May 09 02:34:44 PM PDT 24 58641408 ps
T1299 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3175648319 May 09 02:34:23 PM PDT 24 May 09 02:34:29 PM PDT 24 191855546 ps
T1300 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1211756111 May 09 02:34:35 PM PDT 24 May 09 02:34:42 PM PDT 24 13918445 ps
T1301 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2953332842 May 09 02:34:19 PM PDT 24 May 09 02:34:28 PM PDT 24 79635322 ps
T1302 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2700561894 May 09 02:34:19 PM PDT 24 May 09 02:34:27 PM PDT 24 20303853 ps
T1303 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3643462437 May 09 02:34:23 PM PDT 24 May 09 02:34:29 PM PDT 24 54910706 ps
T1304 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.186133789 May 09 02:34:18 PM PDT 24 May 09 02:34:26 PM PDT 24 43236280 ps
T1305 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1225105239 May 09 02:34:27 PM PDT 24 May 09 02:34:33 PM PDT 24 49011434 ps
T1306 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2533086179 May 09 02:34:27 PM PDT 24 May 09 02:34:35 PM PDT 24 108463835 ps
T1307 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1861152047 May 09 02:34:39 PM PDT 24 May 09 02:34:45 PM PDT 24 37787209 ps
T1308 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.387165666 May 09 02:34:47 PM PDT 24 May 09 02:34:54 PM PDT 24 42661265 ps
T1309 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4222257555 May 09 02:34:28 PM PDT 24 May 09 02:34:36 PM PDT 24 18413585 ps
T1310 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2493465622 May 09 02:34:44 PM PDT 24 May 09 02:34:55 PM PDT 24 30975364 ps
T1311 /workspace/coverage/cover_reg_top/8.uart_tl_errors.87522662 May 09 02:34:16 PM PDT 24 May 09 02:34:25 PM PDT 24 56578404 ps
T1312 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3602734363 May 09 02:34:32 PM PDT 24 May 09 02:34:40 PM PDT 24 28204166 ps
T1313 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3077319178 May 09 02:34:31 PM PDT 24 May 09 02:34:40 PM PDT 24 463371737 ps
T1314 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1782431008 May 09 02:34:39 PM PDT 24 May 09 02:34:46 PM PDT 24 238466553 ps
T1315 /workspace/coverage/cover_reg_top/38.uart_intr_test.1250943067 May 09 02:34:45 PM PDT 24 May 09 02:34:50 PM PDT 24 11477526 ps
T1316 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3211446252 May 09 02:34:31 PM PDT 24 May 09 02:34:38 PM PDT 24 152312252 ps
T1317 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.896944243 May 09 02:34:30 PM PDT 24 May 09 02:34:37 PM PDT 24 24760003 ps
T1318 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.199457468 May 09 02:34:22 PM PDT 24 May 09 02:34:28 PM PDT 24 318171904 ps
T1319 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3416271751 May 09 02:34:32 PM PDT 24 May 09 02:34:40 PM PDT 24 907066769 ps

Test location /workspace/coverage/default/284.uart_fifo_reset.1468858467
Short name T6
Test name
Test status
Simulation time 15661099811 ps
CPU time 33.93 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:43:16 PM PDT 24
Peak memory 200228 kb
Host smart-b097d5ca-2871-4cd0-acf4-0028471e0812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468858467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1468858467
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3187301863
Short name T17
Test name
Test status
Simulation time 499337348255 ps
CPU time 893.12 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:54:21 PM PDT 24
Peak memory 225280 kb
Host smart-95ae20cc-4757-4bfd-9cbd-7ddbbb7f4aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187301863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3187301863
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2741936317
Short name T15
Test name
Test status
Simulation time 395937380168 ps
CPU time 955.44 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:54:46 PM PDT 24
Peak memory 229980 kb
Host smart-b2222dd6-4802-4af9-8d1f-da4f68231035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741936317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2741936317
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.22789137
Short name T188
Test name
Test status
Simulation time 124258222033 ps
CPU time 816.21 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:54:31 PM PDT 24
Peak memory 200456 kb
Host smart-4395b1d3-6dd3-49c5-b10b-c3f399165a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.22789137
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all.2835885910
Short name T153
Test name
Test status
Simulation time 123831398081 ps
CPU time 377.29 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:44:49 PM PDT 24
Peak memory 200404 kb
Host smart-f97aef57-80d8-458a-8d25-c421b7684452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835885910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2835885910
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.142913853
Short name T12
Test name
Test status
Simulation time 66297105519 ps
CPU time 316.15 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:46:44 PM PDT 24
Peak memory 215976 kb
Host smart-b2910206-f786-46c0-aea3-bc4303b56207
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142913853 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.142913853
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.3340846648
Short name T183
Test name
Test status
Simulation time 282027115020 ps
CPU time 359.51 seconds
Started May 09 02:38:38 PM PDT 24
Finished May 09 02:44:39 PM PDT 24
Peak memory 208872 kb
Host smart-ca538e6f-cfeb-4f9e-bad8-a3aa89a0d112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340846648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3340846648
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2074936200
Short name T25
Test name
Test status
Simulation time 188767452378 ps
CPU time 358.69 seconds
Started May 09 02:39:33 PM PDT 24
Finished May 09 02:45:33 PM PDT 24
Peak memory 216404 kb
Host smart-83c169c2-6f22-4f2a-bfcf-87cea2a8a28d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074936200 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2074936200
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.3013178376
Short name T18
Test name
Test status
Simulation time 232727116348 ps
CPU time 426.08 seconds
Started May 09 02:39:02 PM PDT 24
Finished May 09 02:46:09 PM PDT 24
Peak memory 208772 kb
Host smart-1fcd9099-8e84-4a1e-bba4-618e8170fa54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013178376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3013178376
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_full.27575271
Short name T43
Test name
Test status
Simulation time 385536959690 ps
CPU time 295.56 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:43:27 PM PDT 24
Peak memory 200460 kb
Host smart-89d36dc8-7fea-43e1-b5aa-db7448c24be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27575271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.27575271
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_alert_test.2601887620
Short name T13
Test name
Test status
Simulation time 21792810 ps
CPU time 0.6 seconds
Started May 09 02:40:28 PM PDT 24
Finished May 09 02:40:32 PM PDT 24
Peak memory 195816 kb
Host smart-aa300df0-5a42-480c-a80f-fbf43a7049c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601887620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2601887620
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3705989935
Short name T105
Test name
Test status
Simulation time 273001718 ps
CPU time 1.25 seconds
Started May 09 02:34:37 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 199592 kb
Host smart-973eef26-2393-4588-ac3a-e77c1c219b22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705989935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3705989935
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2525498076
Short name T122
Test name
Test status
Simulation time 210662404419 ps
CPU time 324.04 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:46:20 PM PDT 24
Peak memory 216880 kb
Host smart-59d6353b-fe7f-4b76-82c1-01f14ebc44cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525498076 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2525498076
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.3293572051
Short name T142
Test name
Test status
Simulation time 287129202838 ps
CPU time 176.34 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:42:36 PM PDT 24
Peak memory 200468 kb
Host smart-db015c3b-a2f8-45d3-b001-3e6744c71a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293572051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3293572051
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1284094000
Short name T289
Test name
Test status
Simulation time 113086964608 ps
CPU time 763.49 seconds
Started May 09 02:39:11 PM PDT 24
Finished May 09 02:51:55 PM PDT 24
Peak memory 200408 kb
Host smart-d1fb1a51-1abb-4a4c-823e-5a50e28e61c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284094000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1284094000
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.536228170
Short name T68
Test name
Test status
Simulation time 48860800 ps
CPU time 0.57 seconds
Started May 09 02:34:33 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 195716 kb
Host smart-9b1eb7ba-f026-46fc-99a5-82ce8ddd2463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536228170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.536228170
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.175630596
Short name T32
Test name
Test status
Simulation time 108258706659 ps
CPU time 340.72 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 216916 kb
Host smart-8b642579-279d-4b11-aad7-96c3f8897f08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175630596 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.175630596
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.4086555651
Short name T158
Test name
Test status
Simulation time 139229100398 ps
CPU time 210.85 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:42:41 PM PDT 24
Peak memory 200480 kb
Host smart-da8d35b8-50de-4611-8c2b-47adee5ae839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086555651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4086555651
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1168822128
Short name T28
Test name
Test status
Simulation time 217768117 ps
CPU time 0.83 seconds
Started May 09 02:38:01 PM PDT 24
Finished May 09 02:38:03 PM PDT 24
Peak memory 218632 kb
Host smart-40202879-449b-4833-8f37-3345582586cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168822128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1168822128
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/24.uart_stress_all.1469035394
Short name T335
Test name
Test status
Simulation time 274053843037 ps
CPU time 1102.31 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:57:51 PM PDT 24
Peak memory 200436 kb
Host smart-bd4e0699-6cb9-4535-8303-04d79ba4c687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469035394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1469035394
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3868179404
Short name T285
Test name
Test status
Simulation time 94595814862 ps
CPU time 763.34 seconds
Started May 09 02:38:24 PM PDT 24
Finished May 09 02:51:09 PM PDT 24
Peak memory 200424 kb
Host smart-d7bab154-6cc1-4d32-84bc-0a640d986958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868179404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3868179404
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4106143862
Short name T51
Test name
Test status
Simulation time 588010952818 ps
CPU time 687.68 seconds
Started May 09 02:39:09 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 225256 kb
Host smart-1cabadb1-324b-4b02-bf1a-fb3e91e28cfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106143862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4106143862
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1586899116
Short name T147
Test name
Test status
Simulation time 231746067211 ps
CPU time 747.59 seconds
Started May 09 02:39:12 PM PDT 24
Finished May 09 02:51:41 PM PDT 24
Peak memory 216932 kb
Host smart-1037d783-f19a-4535-837f-bcfa0d189f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586899116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1586899116
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3783884278
Short name T38
Test name
Test status
Simulation time 116245375213 ps
CPU time 145.96 seconds
Started May 09 02:39:18 PM PDT 24
Finished May 09 02:41:45 PM PDT 24
Peak memory 200396 kb
Host smart-2e5aeb7d-69cb-4d6e-a005-e1beb193033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783884278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3783884278
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2757756923
Short name T493
Test name
Test status
Simulation time 1118179928123 ps
CPU time 1376.06 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 03:02:59 PM PDT 24
Peak memory 225104 kb
Host smart-73e7fd94-8315-4b3d-a12f-fd8c81ca52ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757756923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2757756923
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.578876338
Short name T49
Test name
Test status
Simulation time 412489818242 ps
CPU time 631.19 seconds
Started May 09 02:38:17 PM PDT 24
Finished May 09 02:48:49 PM PDT 24
Peak memory 225356 kb
Host smart-057cee40-1856-4f25-81fb-af58faaac888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578876338 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.578876338
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3125560383
Short name T40
Test name
Test status
Simulation time 57838942822 ps
CPU time 25.06 seconds
Started May 09 02:41:40 PM PDT 24
Finished May 09 02:42:07 PM PDT 24
Peak memory 200376 kb
Host smart-f3c7ba1b-f9e9-49b6-831a-4b30c9fcda8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125560383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3125560383
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3305391685
Short name T184
Test name
Test status
Simulation time 99277211861 ps
CPU time 90.52 seconds
Started May 09 02:40:43 PM PDT 24
Finished May 09 02:42:15 PM PDT 24
Peak memory 200376 kb
Host smart-8cb264eb-4afe-45ea-bf2c-2845fb35ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305391685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3305391685
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2243360045
Short name T165
Test name
Test status
Simulation time 58876296550 ps
CPU time 58.28 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:42:14 PM PDT 24
Peak memory 200400 kb
Host smart-da40f9af-2dcf-4cd7-aa72-4868f3e776ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243360045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2243360045
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.10492051
Short name T390
Test name
Test status
Simulation time 152762597785 ps
CPU time 227.91 seconds
Started May 09 02:39:23 PM PDT 24
Finished May 09 02:43:12 PM PDT 24
Peak memory 200408 kb
Host smart-5807b6e7-c4fb-4661-ba10-bbf77834edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10492051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.10492051
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3206156359
Short name T220
Test name
Test status
Simulation time 381903376079 ps
CPU time 1174.79 seconds
Started May 09 02:40:46 PM PDT 24
Finished May 09 03:00:24 PM PDT 24
Peak memory 225124 kb
Host smart-8dc231eb-1f99-4508-b9d7-4d8ee35560f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206156359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3206156359
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1807301409
Short name T200
Test name
Test status
Simulation time 122821086019 ps
CPU time 1441.69 seconds
Started May 09 02:41:17 PM PDT 24
Finished May 09 03:05:20 PM PDT 24
Peak memory 232900 kb
Host smart-abce00df-6d5a-4b79-9032-e0d88e174320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807301409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1807301409
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.420822890
Short name T1294
Test name
Test status
Simulation time 81232157 ps
CPU time 1.27 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:39 PM PDT 24
Peak memory 199320 kb
Host smart-6ad4d175-588e-4a7e-8518-bd7418a2907a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420822890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.420822890
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1759858406
Short name T157
Test name
Test status
Simulation time 386146934916 ps
CPU time 97.48 seconds
Started May 09 02:41:54 PM PDT 24
Finished May 09 02:43:36 PM PDT 24
Peak memory 200344 kb
Host smart-7dbd72e7-c38e-40ef-8531-5e7e321d9586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759858406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1759858406
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2122278602
Short name T132
Test name
Test status
Simulation time 121232430695 ps
CPU time 96.21 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:41:13 PM PDT 24
Peak memory 200432 kb
Host smart-ed96eae8-6f6a-4e80-9c28-0e26bd852426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122278602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2122278602
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.642872163
Short name T291
Test name
Test status
Simulation time 152199870946 ps
CPU time 44.83 seconds
Started May 09 02:38:00 PM PDT 24
Finished May 09 02:38:45 PM PDT 24
Peak memory 200380 kb
Host smart-badd3712-88c4-40ef-8179-efab17f331a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642872163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.642872163
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3195702457
Short name T181
Test name
Test status
Simulation time 146739519025 ps
CPU time 95.39 seconds
Started May 09 02:41:34 PM PDT 24
Finished May 09 02:43:12 PM PDT 24
Peak memory 200392 kb
Host smart-68370ced-5b5e-4b87-9bc1-243b4df43ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195702457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3195702457
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2088031616
Short name T255
Test name
Test status
Simulation time 154179975590 ps
CPU time 118.52 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:43:38 PM PDT 24
Peak memory 200420 kb
Host smart-8b2f69e3-c601-426a-9746-35562b17c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088031616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2088031616
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3895828420
Short name T192
Test name
Test status
Simulation time 42766781884 ps
CPU time 37.88 seconds
Started May 09 02:42:21 PM PDT 24
Finished May 09 02:43:01 PM PDT 24
Peak memory 200452 kb
Host smart-70fd2b78-5c96-4006-8e36-cfb4c0566c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895828420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3895828420
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.3228272647
Short name T226
Test name
Test status
Simulation time 372500905693 ps
CPU time 313.4 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:43:17 PM PDT 24
Peak memory 208836 kb
Host smart-4746f4b2-9de3-4187-b016-6429951a0147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228272647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3228272647
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1999591749
Short name T260
Test name
Test status
Simulation time 395938897336 ps
CPU time 1111.91 seconds
Started May 09 02:38:12 PM PDT 24
Finished May 09 02:56:45 PM PDT 24
Peak memory 216960 kb
Host smart-3609ae73-7f42-4879-8271-7c4ece6ba0bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999591749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1999591749
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.599954011
Short name T269
Test name
Test status
Simulation time 102457068483 ps
CPU time 139.86 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:44:10 PM PDT 24
Peak memory 200476 kb
Host smart-9f5574d4-3712-4198-b781-a665c0bad501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599954011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.599954011
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1857890367
Short name T169
Test name
Test status
Simulation time 27026923824 ps
CPU time 47.75 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:42:57 PM PDT 24
Peak memory 200500 kb
Host smart-1653a235-89e5-4cb8-80e9-9a1d193cabcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857890367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1857890367
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1074650612
Short name T208
Test name
Test status
Simulation time 14626241620 ps
CPU time 34.65 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:43:06 PM PDT 24
Peak memory 200420 kb
Host smart-f3f58b9d-6c1e-4933-a1b9-40bcb0e4d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074650612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1074650612
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1416332991
Short name T205
Test name
Test status
Simulation time 37065148433 ps
CPU time 32.41 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:42:13 PM PDT 24
Peak memory 200352 kb
Host smart-1204ae4e-f151-4ade-828d-207f9cd8bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416332991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1416332991
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3987409650
Short name T283
Test name
Test status
Simulation time 89990018120 ps
CPU time 196.84 seconds
Started May 09 02:39:12 PM PDT 24
Finished May 09 02:42:30 PM PDT 24
Peak memory 200488 kb
Host smart-49d3ecb0-c3b7-41ee-8005-ca2af55779b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987409650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3987409650
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1571920448
Short name T604
Test name
Test status
Simulation time 119215654236 ps
CPU time 263.05 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 200424 kb
Host smart-01834f5f-49b8-4ca9-9854-ea4b5c6ad7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571920448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1571920448
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1825871782
Short name T159
Test name
Test status
Simulation time 43670302547 ps
CPU time 66.03 seconds
Started May 09 02:42:32 PM PDT 24
Finished May 09 02:43:41 PM PDT 24
Peak memory 200460 kb
Host smart-891b4c64-da07-4bf5-9cdf-57dd500cbd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825871782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1825871782
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.609196552
Short name T161
Test name
Test status
Simulation time 55839815123 ps
CPU time 41.01 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:42:29 PM PDT 24
Peak memory 200444 kb
Host smart-1a9d6e37-b9f2-4e90-afb5-257a080901ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609196552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.609196552
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1660812900
Short name T4
Test name
Test status
Simulation time 97896087402 ps
CPU time 86.6 seconds
Started May 09 02:39:00 PM PDT 24
Finished May 09 02:40:27 PM PDT 24
Peak memory 200376 kb
Host smart-96e9e610-e985-4134-a496-b9c6d69d2e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660812900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1660812900
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.12298085
Short name T238
Test name
Test status
Simulation time 160111500413 ps
CPU time 64.96 seconds
Started May 09 02:42:06 PM PDT 24
Finished May 09 02:43:12 PM PDT 24
Peak memory 200464 kb
Host smart-c1bb9e48-f37c-4b57-aff6-d95f6bc00ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12298085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.12298085
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2621695399
Short name T182
Test name
Test status
Simulation time 36755177933 ps
CPU time 51.26 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:37 PM PDT 24
Peak memory 200380 kb
Host smart-2d039000-08fd-4534-a31b-0d8751e1bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621695399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2621695399
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4155815300
Short name T277
Test name
Test status
Simulation time 169549645076 ps
CPU time 86.29 seconds
Started May 09 02:39:40 PM PDT 24
Finished May 09 02:41:08 PM PDT 24
Peak memory 200120 kb
Host smart-fc975f2e-f520-418a-996f-4ca097d7f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155815300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4155815300
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1860348344
Short name T194
Test name
Test status
Simulation time 135767585881 ps
CPU time 57.91 seconds
Started May 09 02:41:25 PM PDT 24
Finished May 09 02:42:24 PM PDT 24
Peak memory 200436 kb
Host smart-9c3e2180-637c-4689-a07b-3a033b89fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860348344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1860348344
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2086823728
Short name T449
Test name
Test status
Simulation time 94919036131 ps
CPU time 44.02 seconds
Started May 09 02:38:00 PM PDT 24
Finished May 09 02:38:45 PM PDT 24
Peak memory 200456 kb
Host smart-9b3dd188-2cdd-46a5-85c3-50b9a87ef420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086823728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2086823728
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1416836791
Short name T850
Test name
Test status
Simulation time 34320565676 ps
CPU time 15.26 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 199968 kb
Host smart-daf98c85-f163-451a-aef4-29ee489c44ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416836791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1416836791
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3715420392
Short name T256
Test name
Test status
Simulation time 65493321322 ps
CPU time 76.97 seconds
Started May 09 02:41:35 PM PDT 24
Finished May 09 02:42:55 PM PDT 24
Peak memory 200428 kb
Host smart-f80176c0-19cc-4db9-be78-b5caf3fc2490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715420392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3715420392
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3319962047
Short name T237
Test name
Test status
Simulation time 65074064027 ps
CPU time 36.2 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:42:16 PM PDT 24
Peak memory 200216 kb
Host smart-0484f26f-9ee2-4449-85d1-5ec3e89be402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319962047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3319962047
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1684758206
Short name T224
Test name
Test status
Simulation time 68474271355 ps
CPU time 60.88 seconds
Started May 09 02:41:37 PM PDT 24
Finished May 09 02:42:40 PM PDT 24
Peak memory 200504 kb
Host smart-313c3194-d7f7-47c3-acdd-3d6ec1d168a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684758206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1684758206
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2836753374
Short name T135
Test name
Test status
Simulation time 49634690004 ps
CPU time 13.38 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 200396 kb
Host smart-e7ff06e7-6329-4017-ba65-afad3ca6814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836753374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2836753374
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2734747073
Short name T246
Test name
Test status
Simulation time 31869642143 ps
CPU time 26.87 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:42:26 PM PDT 24
Peak memory 200424 kb
Host smart-6e190a4e-549f-43fc-afc6-e602438cb5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734747073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2734747073
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2587211974
Short name T156
Test name
Test status
Simulation time 39559508651 ps
CPU time 61.33 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:43:01 PM PDT 24
Peak memory 200432 kb
Host smart-df8572a7-8a37-4fda-8832-bfcc8335b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587211974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2587211974
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.820361785
Short name T262
Test name
Test status
Simulation time 34372105100 ps
CPU time 12.99 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:42:13 PM PDT 24
Peak memory 200332 kb
Host smart-7e04a78e-8065-4565-83e7-2fa1961220db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820361785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.820361785
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.4015272037
Short name T266
Test name
Test status
Simulation time 54947894065 ps
CPU time 28.82 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:29 PM PDT 24
Peak memory 200368 kb
Host smart-ab1af14b-2228-43ef-8d5a-adcf637bedeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015272037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4015272037
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.456745240
Short name T249
Test name
Test status
Simulation time 40592020300 ps
CPU time 73.16 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:43:12 PM PDT 24
Peak memory 200412 kb
Host smart-07b60925-12af-42a3-bc89-c1eccaf5313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456745240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.456745240
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.150221068
Short name T273
Test name
Test status
Simulation time 29913912412 ps
CPU time 19.11 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:19 PM PDT 24
Peak memory 200436 kb
Host smart-d4affca0-a7ee-4959-b5e4-9a41f43f2970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150221068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.150221068
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1778359009
Short name T252
Test name
Test status
Simulation time 79656160108 ps
CPU time 116.62 seconds
Started May 09 02:42:02 PM PDT 24
Finished May 09 02:44:01 PM PDT 24
Peak memory 200480 kb
Host smart-86644416-7125-4ea3-9604-421e14dd8867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778359009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1778359009
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2410662619
Short name T193
Test name
Test status
Simulation time 152391014270 ps
CPU time 251.9 seconds
Started May 09 02:42:09 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 200432 kb
Host smart-0b6ae11a-42c8-4736-ad17-5535c8a4944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410662619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2410662619
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3202469590
Short name T207
Test name
Test status
Simulation time 23945459004 ps
CPU time 11.03 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:42:34 PM PDT 24
Peak memory 200456 kb
Host smart-c026e852-e651-4dbd-b014-16e621c97fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202469590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3202469590
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3255664915
Short name T258
Test name
Test status
Simulation time 64871351090 ps
CPU time 10.24 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:42:43 PM PDT 24
Peak memory 200420 kb
Host smart-9f257097-24d5-417e-9f36-01caa9c997f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255664915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3255664915
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1110809297
Short name T259
Test name
Test status
Simulation time 82002045678 ps
CPU time 29.68 seconds
Started May 09 02:42:30 PM PDT 24
Finished May 09 02:43:03 PM PDT 24
Peak memory 200452 kb
Host smart-432747bd-d295-4390-98ce-6119c4898f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110809297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1110809297
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.613566840
Short name T271
Test name
Test status
Simulation time 37130939023 ps
CPU time 15.07 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:00 PM PDT 24
Peak memory 200476 kb
Host smart-cd7ed90e-ea54-4ac0-90b7-3497833cdae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613566840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.613566840
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.758869448
Short name T243
Test name
Test status
Simulation time 404153690787 ps
CPU time 98.76 seconds
Started May 09 02:39:33 PM PDT 24
Finished May 09 02:41:14 PM PDT 24
Peak memory 200428 kb
Host smart-ad6af2b4-5729-458d-940a-21c680125cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758869448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.758869448
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1207735114
Short name T272
Test name
Test status
Simulation time 52878914238 ps
CPU time 21.12 seconds
Started May 09 02:40:51 PM PDT 24
Finished May 09 02:41:14 PM PDT 24
Peak memory 200352 kb
Host smart-5a1c0354-3c9d-496e-9ae0-de0df68750b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207735114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1207735114
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3513571771
Short name T265
Test name
Test status
Simulation time 64015950275 ps
CPU time 54.94 seconds
Started May 09 02:41:24 PM PDT 24
Finished May 09 02:42:20 PM PDT 24
Peak memory 200380 kb
Host smart-cc6d40ed-5e39-4e06-99d9-1208fe801dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513571771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3513571771
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2341080535
Short name T254
Test name
Test status
Simulation time 127715564810 ps
CPU time 176.32 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:44:35 PM PDT 24
Peak memory 200476 kb
Host smart-3c62bd03-83ca-4e8d-9d91-dffdb4a09043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341080535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2341080535
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1005474732
Short name T1250
Test name
Test status
Simulation time 26572586 ps
CPU time 0.78 seconds
Started May 09 02:34:22 PM PDT 24
Finished May 09 02:34:28 PM PDT 24
Peak memory 196560 kb
Host smart-e2441424-4784-46b6-956a-e5d650c58802
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005474732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1005474732
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3906316136
Short name T71
Test name
Test status
Simulation time 225247456 ps
CPU time 1.42 seconds
Started May 09 02:34:29 PM PDT 24
Finished May 09 02:34:37 PM PDT 24
Peak memory 197880 kb
Host smart-80bf8737-33a2-4bcb-ba2e-b42b6927386a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906316136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3906316136
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1213101601
Short name T1217
Test name
Test status
Simulation time 14838447 ps
CPU time 0.6 seconds
Started May 09 02:34:18 PM PDT 24
Finished May 09 02:34:26 PM PDT 24
Peak memory 195744 kb
Host smart-9e285b60-a7da-4f89-93ae-90ffb704e088
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213101601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1213101601
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3095783403
Short name T1280
Test name
Test status
Simulation time 89392200 ps
CPU time 1.13 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 200384 kb
Host smart-057341ba-997a-4bbd-a170-1e30ee8dfef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095783403 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3095783403
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.976055685
Short name T1286
Test name
Test status
Simulation time 24880890 ps
CPU time 0.61 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:33 PM PDT 24
Peak memory 195732 kb
Host smart-545fe271-fb0a-489e-8c59-6d011e041e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976055685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.976055685
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1294419839
Short name T1265
Test name
Test status
Simulation time 39528528 ps
CPU time 0.55 seconds
Started May 09 02:34:38 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 194664 kb
Host smart-4c624b40-6c23-4c4a-aa79-632c8e088f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294419839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1294419839
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3804296723
Short name T1244
Test name
Test status
Simulation time 60471764 ps
CPU time 0.77 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 196828 kb
Host smart-7e48a999-88e1-425a-b6e3-96208e3571cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804296723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3804296723
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2953332842
Short name T1301
Test name
Test status
Simulation time 79635322 ps
CPU time 2.1 seconds
Started May 09 02:34:19 PM PDT 24
Finished May 09 02:34:28 PM PDT 24
Peak memory 200364 kb
Host smart-c3471f4b-a3bf-45f4-876c-8846fddee406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953332842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2953332842
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.978760843
Short name T1289
Test name
Test status
Simulation time 165768776 ps
CPU time 0.93 seconds
Started May 09 02:34:14 PM PDT 24
Finished May 09 02:34:22 PM PDT 24
Peak memory 199216 kb
Host smart-1644c856-05c3-489f-a87a-518a3f652a86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978760843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.978760843
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1069692523
Short name T92
Test name
Test status
Simulation time 46197830 ps
CPU time 0.79 seconds
Started May 09 02:34:30 PM PDT 24
Finished May 09 02:34:38 PM PDT 24
Peak memory 196692 kb
Host smart-4a31d4f4-5133-4255-b5b0-1c1a0ae1e2f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069692523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1069692523
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3957046313
Short name T1198
Test name
Test status
Simulation time 105158986 ps
CPU time 2.35 seconds
Started May 09 02:34:30 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 197940 kb
Host smart-667355ae-f0e3-4894-b467-8a6b5ea76d45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957046313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3957046313
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1211756111
Short name T1300
Test name
Test status
Simulation time 13918445 ps
CPU time 0.58 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 195724 kb
Host smart-ca64a626-73a8-4088-aed9-8f705af36e6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211756111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1211756111
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3602734363
Short name T1312
Test name
Test status
Simulation time 28204166 ps
CPU time 1.22 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 200180 kb
Host smart-a834dfa0-1b40-4e8e-97d3-90dcaf107a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602734363 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3602734363
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2714930621
Short name T1274
Test name
Test status
Simulation time 26610189 ps
CPU time 0.61 seconds
Started May 09 02:34:23 PM PDT 24
Finished May 09 02:34:28 PM PDT 24
Peak memory 195712 kb
Host smart-d9f81823-7677-4ff1-b30e-cf33a03efd5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714930621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2714930621
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3711944827
Short name T1259
Test name
Test status
Simulation time 14055556 ps
CPU time 0.58 seconds
Started May 09 02:34:26 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 194604 kb
Host smart-3aa8a73e-e8ea-43d2-a8fe-5369dbaf2f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711944827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3711944827
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.186133789
Short name T1304
Test name
Test status
Simulation time 43236280 ps
CPU time 0.71 seconds
Started May 09 02:34:18 PM PDT 24
Finished May 09 02:34:26 PM PDT 24
Peak memory 195832 kb
Host smart-ac0f41e3-7f61-43e0-b7a4-64a34698b31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186133789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.186133789
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3175648319
Short name T1299
Test name
Test status
Simulation time 191855546 ps
CPU time 1.17 seconds
Started May 09 02:34:23 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 200260 kb
Host smart-4ebf44ba-9ff3-4c21-a16b-06c19b5a7350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175648319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3175648319
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.311522633
Short name T104
Test name
Test status
Simulation time 42426128 ps
CPU time 0.95 seconds
Started May 09 02:34:39 PM PDT 24
Finished May 09 02:34:46 PM PDT 24
Peak memory 199268 kb
Host smart-5492d6c4-faa2-4130-a701-5bdd3ba7094d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311522633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.311522633
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.888479409
Short name T1283
Test name
Test status
Simulation time 91674528 ps
CPU time 0.84 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 200204 kb
Host smart-b71a774e-7122-4040-afa1-1074a8b61d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888479409 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.888479409
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.109425584
Short name T1182
Test name
Test status
Simulation time 22971039 ps
CPU time 0.57 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:43 PM PDT 24
Peak memory 194704 kb
Host smart-e2785067-dec0-4dfd-914f-f28889c01384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109425584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.109425584
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.283930134
Short name T95
Test name
Test status
Simulation time 100458227 ps
CPU time 0.63 seconds
Started May 09 02:34:28 PM PDT 24
Finished May 09 02:34:36 PM PDT 24
Peak memory 194920 kb
Host smart-0cc64847-2848-4dbe-b133-8aafb5ba137b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283930134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.283930134
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2533086179
Short name T1306
Test name
Test status
Simulation time 108463835 ps
CPU time 2.29 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:35 PM PDT 24
Peak memory 200612 kb
Host smart-541d3305-dda2-4c10-b79c-d5777a7ff7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533086179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2533086179
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.710681812
Short name T1252
Test name
Test status
Simulation time 165992915 ps
CPU time 0.91 seconds
Started May 09 02:34:22 PM PDT 24
Finished May 09 02:34:28 PM PDT 24
Peak memory 199196 kb
Host smart-7b63737b-91ac-42cb-987d-b06caf657ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710681812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.710681812
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.896944243
Short name T1317
Test name
Test status
Simulation time 24760003 ps
CPU time 0.78 seconds
Started May 09 02:34:30 PM PDT 24
Finished May 09 02:34:37 PM PDT 24
Peak memory 200108 kb
Host smart-7e6888d4-16ac-43ca-9de4-c6eb90ec816d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896944243 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.896944243
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1861152047
Short name T1307
Test name
Test status
Simulation time 37787209 ps
CPU time 0.63 seconds
Started May 09 02:34:39 PM PDT 24
Finished May 09 02:34:45 PM PDT 24
Peak memory 195860 kb
Host smart-f04fc83b-7cd1-4077-aea4-128548804ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861152047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1861152047
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4287747958
Short name T1243
Test name
Test status
Simulation time 11938566 ps
CPU time 0.6 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:38 PM PDT 24
Peak memory 194648 kb
Host smart-70756391-9e3f-4fac-b0e5-6306809582b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287747958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4287747958
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.310505515
Short name T1249
Test name
Test status
Simulation time 17933888 ps
CPU time 0.75 seconds
Started May 09 02:34:34 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 197848 kb
Host smart-ffd73069-6ccf-4831-89c0-7e5ba7c00bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310505515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.310505515
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1856318231
Short name T1272
Test name
Test status
Simulation time 23923284 ps
CPU time 1.23 seconds
Started May 09 02:34:30 PM PDT 24
Finished May 09 02:34:38 PM PDT 24
Peak memory 200320 kb
Host smart-3cab5ec2-09de-4445-8a89-03018168d81d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856318231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1856318231
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3416271751
Short name T1319
Test name
Test status
Simulation time 907066769 ps
CPU time 0.99 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 199324 kb
Host smart-5e2ae5aa-13c4-4f73-a04f-c816021f4313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416271751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3416271751
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2906736271
Short name T1235
Test name
Test status
Simulation time 30033372 ps
CPU time 0.87 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 200200 kb
Host smart-a48ef3a8-04e8-46b1-8b7d-16dabcec06f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906736271 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2906736271
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3852437570
Short name T70
Test name
Test status
Simulation time 89775921 ps
CPU time 0.59 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 195724 kb
Host smart-6e4e825c-56bc-4a0a-8eca-97be4f531b6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852437570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3852437570
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2421648462
Short name T1228
Test name
Test status
Simulation time 50412149 ps
CPU time 0.56 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 194636 kb
Host smart-73126d0b-208f-4af6-91ac-cebc5ff1f7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421648462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2421648462
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3715612847
Short name T1288
Test name
Test status
Simulation time 29226209 ps
CPU time 0.78 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:39 PM PDT 24
Peak memory 196364 kb
Host smart-e807ba56-a84d-4cc7-bbca-54e33ad5b346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715612847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3715612847
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3077319178
Short name T1313
Test name
Test status
Simulation time 463371737 ps
CPU time 2.33 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 200384 kb
Host smart-426f801c-336f-4c2a-8620-9a7258a565ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077319178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3077319178
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2208369322
Short name T108
Test name
Test status
Simulation time 311237966 ps
CPU time 1.25 seconds
Started May 09 02:34:33 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 199448 kb
Host smart-7a4340a0-773b-4ab7-8993-50c46be0af31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208369322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2208369322
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.81880391
Short name T1263
Test name
Test status
Simulation time 30991111 ps
CPU time 0.87 seconds
Started May 09 02:34:37 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 200416 kb
Host smart-b554f1dc-28c1-4ae5-a631-8f0946a0be29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81880391 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.81880391
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1624592526
Short name T1206
Test name
Test status
Simulation time 41020187 ps
CPU time 0.58 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 195628 kb
Host smart-36a79afb-8638-426b-b8cd-a4a39ec727a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624592526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1624592526
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3399967531
Short name T1255
Test name
Test status
Simulation time 21499458 ps
CPU time 0.57 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:43 PM PDT 24
Peak memory 194684 kb
Host smart-b789be61-f357-415f-8a59-7fbd1ea2e110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399967531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3399967531
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.101276674
Short name T1213
Test name
Test status
Simulation time 31104008 ps
CPU time 0.62 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 195964 kb
Host smart-69867062-46af-41c6-9ed7-77a9edd2cca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101276674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.101276674
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.121861874
Short name T1241
Test name
Test status
Simulation time 266693182 ps
CPU time 2.17 seconds
Started May 09 02:34:38 PM PDT 24
Finished May 09 02:34:46 PM PDT 24
Peak memory 200336 kb
Host smart-dadb1fa9-7c27-4aeb-bfd6-83106f06dd74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121861874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.121861874
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2964989004
Short name T1192
Test name
Test status
Simulation time 31406519 ps
CPU time 1.41 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 200372 kb
Host smart-f4ad3477-a95b-47cd-9638-ed8fb254a2e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964989004 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2964989004
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3543187887
Short name T1218
Test name
Test status
Simulation time 15286063 ps
CPU time 0.6 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 195608 kb
Host smart-a9dbc16c-4e69-4d59-b9a4-dc08e1c2c054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543187887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3543187887
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3520503731
Short name T1225
Test name
Test status
Simulation time 17223845 ps
CPU time 0.57 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:43 PM PDT 24
Peak memory 194712 kb
Host smart-e6b80e7c-c073-4042-9257-d103b13064ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520503731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3520503731
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2534240692
Short name T100
Test name
Test status
Simulation time 46136391 ps
CPU time 0.73 seconds
Started May 09 02:34:37 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 197424 kb
Host smart-42869f25-c622-468e-94d9-e5af69b9dbeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534240692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2534240692
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1095848454
Short name T1284
Test name
Test status
Simulation time 483791718 ps
CPU time 1.48 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 200364 kb
Host smart-36707cae-748c-4a4a-8b8e-151c4c30b3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095848454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1095848454
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4163444560
Short name T106
Test name
Test status
Simulation time 340978279 ps
CPU time 0.9 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 199160 kb
Host smart-709b3b6c-087a-4949-94c0-b9e023e29a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163444560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4163444560
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.693222993
Short name T1295
Test name
Test status
Simulation time 105314434 ps
CPU time 0.85 seconds
Started May 09 02:34:38 PM PDT 24
Finished May 09 02:34:45 PM PDT 24
Peak memory 200088 kb
Host smart-a669a393-b23b-40d6-91c1-30448f25d417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693222993 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.693222993
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1099422068
Short name T98
Test name
Test status
Simulation time 45761225 ps
CPU time 0.57 seconds
Started May 09 02:34:38 PM PDT 24
Finished May 09 02:34:45 PM PDT 24
Peak memory 195788 kb
Host smart-1a0fab94-7096-4de7-9bfe-433a8771bbe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099422068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1099422068
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2323796319
Short name T1186
Test name
Test status
Simulation time 43774849 ps
CPU time 0.55 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:42 PM PDT 24
Peak memory 194668 kb
Host smart-a7ee5c33-28ed-43d0-b925-6d00ffff085f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323796319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2323796319
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1009765108
Short name T94
Test name
Test status
Simulation time 101307203 ps
CPU time 0.75 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:43 PM PDT 24
Peak memory 196244 kb
Host smart-be404162-ad8b-4315-a396-7852bb5a4dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009765108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1009765108
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2662089159
Short name T1208
Test name
Test status
Simulation time 22250384 ps
CPU time 1.15 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:43 PM PDT 24
Peak memory 200324 kb
Host smart-2718e80d-01f1-4761-b4d9-e7fafab1281d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662089159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2662089159
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3159976931
Short name T1251
Test name
Test status
Simulation time 70356445 ps
CPU time 1.23 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 199476 kb
Host smart-e983ccd1-ca18-4d1f-9d19-2a736e98287c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159976931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3159976931
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2889003375
Short name T1279
Test name
Test status
Simulation time 89921910 ps
CPU time 0.77 seconds
Started May 09 02:34:39 PM PDT 24
Finished May 09 02:34:46 PM PDT 24
Peak memory 199360 kb
Host smart-844e2293-4667-4ba3-aba7-fef6237fd6f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889003375 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2889003375
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3211446252
Short name T1316
Test name
Test status
Simulation time 152312252 ps
CPU time 0.6 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:38 PM PDT 24
Peak memory 195868 kb
Host smart-5d35875b-49e5-43cb-8f82-c1d1ca37dd79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211446252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3211446252
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.284815002
Short name T1275
Test name
Test status
Simulation time 38568452 ps
CPU time 0.56 seconds
Started May 09 02:34:37 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 194672 kb
Host smart-c9b83f36-7c1b-44b6-9d0e-3bf51370a70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284815002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.284815002
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.737310069
Short name T1253
Test name
Test status
Simulation time 28070718 ps
CPU time 0.76 seconds
Started May 09 02:34:33 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 196512 kb
Host smart-3a9b38dc-d503-4156-9857-e80834c82997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737310069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.737310069
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.854725001
Short name T1219
Test name
Test status
Simulation time 30078338 ps
CPU time 1.47 seconds
Started May 09 02:34:33 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 200372 kb
Host smart-0aaa9e2a-70be-4774-a619-8a3a64c4ea1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854725001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.854725001
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.54442012
Short name T144
Test name
Test status
Simulation time 314379129 ps
CPU time 1.2 seconds
Started May 09 02:34:36 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 199364 kb
Host smart-b8c04f4f-a417-4335-b374-18c5283b5683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54442012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.54442012
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3977495352
Short name T1190
Test name
Test status
Simulation time 76716715 ps
CPU time 0.84 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:52 PM PDT 24
Peak memory 200220 kb
Host smart-9bbdac19-a02a-45f3-9d30-b38a00fcf9bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977495352 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3977495352
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2631214576
Short name T1271
Test name
Test status
Simulation time 23340763 ps
CPU time 0.58 seconds
Started May 09 02:34:42 PM PDT 24
Finished May 09 02:34:47 PM PDT 24
Peak memory 195728 kb
Host smart-c7836bbc-0a0d-48c7-8ad9-aad8bc6e2483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631214576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2631214576
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.298524827
Short name T1247
Test name
Test status
Simulation time 27851998 ps
CPU time 0.57 seconds
Started May 09 02:34:43 PM PDT 24
Finished May 09 02:34:48 PM PDT 24
Peak memory 194740 kb
Host smart-311f1ef9-1be4-4594-954a-d69a2a6ddf12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298524827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.298524827
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.951405061
Short name T1234
Test name
Test status
Simulation time 118937298 ps
CPU time 0.78 seconds
Started May 09 02:34:41 PM PDT 24
Finished May 09 02:34:47 PM PDT 24
Peak memory 196872 kb
Host smart-93818205-1f77-42b8-92ae-aa55aa8ad3d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951405061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.951405061
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2573101629
Short name T1199
Test name
Test status
Simulation time 97826248 ps
CPU time 2.06 seconds
Started May 09 02:34:38 PM PDT 24
Finished May 09 02:34:46 PM PDT 24
Peak memory 200436 kb
Host smart-b6f9687e-e784-49d4-bba2-3b3901f7168e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573101629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2573101629
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1782431008
Short name T1314
Test name
Test status
Simulation time 238466553 ps
CPU time 1.29 seconds
Started May 09 02:34:39 PM PDT 24
Finished May 09 02:34:46 PM PDT 24
Peak memory 199552 kb
Host smart-20fc0ea3-c47d-43c0-a3cc-e41f707e9dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782431008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1782431008
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.995308679
Short name T1227
Test name
Test status
Simulation time 38432109 ps
CPU time 1.05 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:50 PM PDT 24
Peak memory 200368 kb
Host smart-78272c04-8c9f-4b9b-b7ae-30e059e03afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995308679 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.995308679
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3118473347
Short name T1261
Test name
Test status
Simulation time 22887253 ps
CPU time 0.62 seconds
Started May 09 02:34:43 PM PDT 24
Finished May 09 02:34:48 PM PDT 24
Peak memory 195716 kb
Host smart-99d8159b-f729-4562-b0f4-95861aebc613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118473347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3118473347
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3201381754
Short name T1273
Test name
Test status
Simulation time 36277232 ps
CPU time 0.61 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194772 kb
Host smart-13d50fa2-43f1-4cc1-99be-f4e0a33cc485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201381754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3201381754
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.549161406
Short name T1242
Test name
Test status
Simulation time 39644961 ps
CPU time 0.65 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:53 PM PDT 24
Peak memory 195940 kb
Host smart-09761d2c-017d-4517-b89a-960d28dfc4c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549161406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.549161406
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3360702124
Short name T1248
Test name
Test status
Simulation time 57245402 ps
CPU time 1.69 seconds
Started May 09 02:34:43 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 200396 kb
Host smart-f3a2ac1e-bb9b-421a-9dd1-cb2f7dff1afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360702124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3360702124
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.387165666
Short name T1308
Test name
Test status
Simulation time 42661265 ps
CPU time 0.94 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:54 PM PDT 24
Peak memory 199240 kb
Host smart-56331fbd-fbf8-4713-9b67-d31bcf6f7e11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387165666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.387165666
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1564941469
Short name T1181
Test name
Test status
Simulation time 63337758 ps
CPU time 0.91 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:52 PM PDT 24
Peak memory 200184 kb
Host smart-e5bc6293-ef5e-4769-9760-fce25416223f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564941469 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1564941469
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3157278086
Short name T1239
Test name
Test status
Simulation time 11844126 ps
CPU time 0.61 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:53 PM PDT 24
Peak memory 195828 kb
Host smart-33757501-c375-451c-8c7c-56aa222e3bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157278086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3157278086
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.289473325
Short name T1237
Test name
Test status
Simulation time 13596333 ps
CPU time 0.57 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194760 kb
Host smart-84dcad90-ef6a-4077-9178-ad3e7be0b110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289473325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.289473325
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2493465622
Short name T1310
Test name
Test status
Simulation time 30975364 ps
CPU time 0.79 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:55 PM PDT 24
Peak memory 197160 kb
Host smart-6531f811-3923-419d-9ae1-be43fe59f1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493465622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2493465622
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2923986412
Short name T1240
Test name
Test status
Simulation time 167658519 ps
CPU time 2.87 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:52 PM PDT 24
Peak memory 200364 kb
Host smart-f4e35009-5a08-4bb6-aad5-43432f56af1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923986412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2923986412
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.166399225
Short name T109
Test name
Test status
Simulation time 44559395 ps
CPU time 0.98 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:53 PM PDT 24
Peak memory 199364 kb
Host smart-cae56d81-8d01-4ae2-89a5-a23cae0cc5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166399225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.166399225
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3884333889
Short name T1205
Test name
Test status
Simulation time 50665276 ps
CPU time 0.82 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:38 PM PDT 24
Peak memory 196728 kb
Host smart-8a0028a0-56e0-4e9d-b000-8b747bd13986
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884333889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3884333889
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2913706653
Short name T1224
Test name
Test status
Simulation time 451080070 ps
CPU time 2.41 seconds
Started May 09 02:34:26 PM PDT 24
Finished May 09 02:34:34 PM PDT 24
Peak memory 198008 kb
Host smart-27fac779-7918-471d-a93c-ca9d78295100
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913706653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2913706653
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1633134049
Short name T1262
Test name
Test status
Simulation time 14277631 ps
CPU time 0.58 seconds
Started May 09 02:34:19 PM PDT 24
Finished May 09 02:34:26 PM PDT 24
Peak memory 195720 kb
Host smart-8e16f858-993f-4d30-8038-6a6c59bca272
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633134049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1633134049
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3031027071
Short name T1184
Test name
Test status
Simulation time 195211597 ps
CPU time 1 seconds
Started May 09 02:34:38 PM PDT 24
Finished May 09 02:34:45 PM PDT 24
Peak memory 200168 kb
Host smart-681afab5-92a1-4e0a-831e-148412f829a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031027071 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3031027071
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4094993172
Short name T1268
Test name
Test status
Simulation time 52264694 ps
CPU time 0.56 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:30 PM PDT 24
Peak memory 195600 kb
Host smart-6e84f508-cb3b-46b4-a8f5-9121800c27b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094993172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4094993172
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4193904016
Short name T1207
Test name
Test status
Simulation time 13520470 ps
CPU time 0.62 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:34 PM PDT 24
Peak memory 194800 kb
Host smart-80850521-fa54-437b-9a88-e6444aaf7509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193904016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4193904016
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2710034343
Short name T101
Test name
Test status
Simulation time 23440808 ps
CPU time 0.8 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 196272 kb
Host smart-7780a51b-a7c8-41bc-bae0-84db1c93c163
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710034343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2710034343
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2152078934
Short name T1293
Test name
Test status
Simulation time 34779925 ps
CPU time 1.83 seconds
Started May 09 02:34:22 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 200416 kb
Host smart-51c7927f-3756-45e7-823e-a68ffcbd3834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152078934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2152078934
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1259126929
Short name T1256
Test name
Test status
Simulation time 190843191 ps
CPU time 1.33 seconds
Started May 09 02:34:28 PM PDT 24
Finished May 09 02:34:35 PM PDT 24
Peak memory 199816 kb
Host smart-eb9ae189-1606-43e2-b864-187f735c0172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259126929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1259126929
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2503384054
Short name T1193
Test name
Test status
Simulation time 18547637 ps
CPU time 0.56 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194708 kb
Host smart-c6b58b7d-0e78-4735-afeb-9cb860685420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503384054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2503384054
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1986746593
Short name T1203
Test name
Test status
Simulation time 10825038 ps
CPU time 0.56 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:48 PM PDT 24
Peak memory 194736 kb
Host smart-2ed3378a-0d73-4033-842b-a33aab20d55b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986746593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1986746593
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3027453641
Short name T1297
Test name
Test status
Simulation time 13816219 ps
CPU time 0.59 seconds
Started May 09 02:34:49 PM PDT 24
Finished May 09 02:34:55 PM PDT 24
Peak memory 194704 kb
Host smart-3a6872cf-1c5b-4a73-92fe-f1eddcdd1359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027453641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3027453641
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1241006287
Short name T1221
Test name
Test status
Simulation time 42333808 ps
CPU time 0.59 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194740 kb
Host smart-5b3c1596-9c67-4f88-a5f1-d2e26845e39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241006287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1241006287
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3654208975
Short name T1196
Test name
Test status
Simulation time 17459025 ps
CPU time 0.58 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:53 PM PDT 24
Peak memory 194672 kb
Host smart-19d35f99-95e9-4bb4-af59-5cb19b1ec692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654208975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3654208975
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1589546811
Short name T1204
Test name
Test status
Simulation time 13721582 ps
CPU time 0.58 seconds
Started May 09 02:34:48 PM PDT 24
Finished May 09 02:34:55 PM PDT 24
Peak memory 194736 kb
Host smart-88b38b42-f13a-45ee-8376-bcb253a179ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589546811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1589546811
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2386041341
Short name T1183
Test name
Test status
Simulation time 43656824 ps
CPU time 0.6 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194728 kb
Host smart-ec4d1a26-850b-4bae-b20c-6a45e5bdeb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386041341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2386041341
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3323678410
Short name T1216
Test name
Test status
Simulation time 12708555 ps
CPU time 0.61 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:48 PM PDT 24
Peak memory 194792 kb
Host smart-0652a44f-187b-494a-9940-5cb3a0cf3685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323678410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3323678410
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2960461859
Short name T1222
Test name
Test status
Simulation time 50034909 ps
CPU time 0.58 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194748 kb
Host smart-5fbc02bf-e3fa-420f-90c8-bc0cf81d4b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960461859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2960461859
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.893607301
Short name T1209
Test name
Test status
Simulation time 13956127 ps
CPU time 0.58 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:50 PM PDT 24
Peak memory 194756 kb
Host smart-c0e8702a-e4e7-4afc-915a-28a00ec57888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893607301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.893607301
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3292434121
Short name T93
Test name
Test status
Simulation time 21086533 ps
CPU time 0.72 seconds
Started May 09 02:34:24 PM PDT 24
Finished May 09 02:34:30 PM PDT 24
Peak memory 195292 kb
Host smart-c50ffb3c-b6f1-4750-a76f-5224df2eca09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292434121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3292434121
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2790057268
Short name T73
Test name
Test status
Simulation time 1650040607 ps
CPU time 2.54 seconds
Started May 09 02:34:28 PM PDT 24
Finished May 09 02:34:37 PM PDT 24
Peak memory 198288 kb
Host smart-599bb524-e8fa-4419-a5af-405d53496322
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790057268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2790057268
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3071178838
Short name T1270
Test name
Test status
Simulation time 51106522 ps
CPU time 0.61 seconds
Started May 09 02:34:22 PM PDT 24
Finished May 09 02:34:28 PM PDT 24
Peak memory 195720 kb
Host smart-7747d9d7-67c8-42e9-ba59-97844d161176
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071178838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3071178838
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1283574300
Short name T1195
Test name
Test status
Simulation time 72103167 ps
CPU time 0.73 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:39 PM PDT 24
Peak memory 199952 kb
Host smart-8eae6375-04b3-44a5-a0af-c48621a5bac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283574300 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1283574300
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.913550561
Short name T99
Test name
Test status
Simulation time 32554270 ps
CPU time 0.62 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 195632 kb
Host smart-bc532190-78d3-4dc2-9af0-d0ec76733e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913550561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.913550561
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3093620059
Short name T1236
Test name
Test status
Simulation time 49578601 ps
CPU time 0.58 seconds
Started May 09 02:34:20 PM PDT 24
Finished May 09 02:34:27 PM PDT 24
Peak memory 194700 kb
Host smart-48b4615f-ce4a-4671-97a5-c6b471961869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093620059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3093620059
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1012249230
Short name T97
Test name
Test status
Simulation time 76275994 ps
CPU time 0.87 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 198412 kb
Host smart-ca46aeff-faf8-4009-9848-2a2399081bcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012249230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1012249230
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.837532868
Short name T1277
Test name
Test status
Simulation time 57669066 ps
CPU time 1.46 seconds
Started May 09 02:34:24 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 200308 kb
Host smart-81c53fb7-aad0-4a0d-bd89-9b173dccb58f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837532868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.837532868
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3488686093
Short name T143
Test name
Test status
Simulation time 215726611 ps
CPU time 0.93 seconds
Started May 09 02:34:34 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 199172 kb
Host smart-d5cbcaec-8346-463d-aba9-1408b46f8776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488686093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3488686093
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.883983819
Short name T1191
Test name
Test status
Simulation time 38355294 ps
CPU time 0.56 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:50 PM PDT 24
Peak memory 194736 kb
Host smart-b98d7dfe-9ea7-4f5f-9569-cbcf8b7c4a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883983819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.883983819
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3370679521
Short name T1246
Test name
Test status
Simulation time 94232372 ps
CPU time 0.57 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:52 PM PDT 24
Peak memory 194752 kb
Host smart-72b5b307-3d01-4b20-b537-f6a02b2ee8bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370679521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3370679521
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2329308552
Short name T1215
Test name
Test status
Simulation time 34060825 ps
CPU time 0.58 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:52 PM PDT 24
Peak memory 194692 kb
Host smart-a0637c51-930a-4a2d-bd78-23f053390605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329308552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2329308552
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3026466887
Short name T1197
Test name
Test status
Simulation time 13349893 ps
CPU time 0.62 seconds
Started May 09 02:34:44 PM PDT 24
Finished May 09 02:34:49 PM PDT 24
Peak memory 194772 kb
Host smart-28b99ab4-f62c-4017-8c93-cd65a55517d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026466887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3026466887
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1279255760
Short name T1200
Test name
Test status
Simulation time 16802187 ps
CPU time 0.6 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:52 PM PDT 24
Peak memory 194784 kb
Host smart-d530af25-0add-42a0-af26-538b398e84e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279255760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1279255760
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3387714821
Short name T1214
Test name
Test status
Simulation time 12817790 ps
CPU time 0.58 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:51 PM PDT 24
Peak memory 194672 kb
Host smart-9c8f113b-8bc4-4ddd-916a-e4e9506a9d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387714821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3387714821
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.744554301
Short name T1226
Test name
Test status
Simulation time 45948379 ps
CPU time 0.54 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:50 PM PDT 24
Peak memory 194732 kb
Host smart-5436f504-c9af-41a0-aec7-4551f881e1e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744554301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.744554301
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2955305077
Short name T1296
Test name
Test status
Simulation time 17009814 ps
CPU time 0.61 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:50 PM PDT 24
Peak memory 194688 kb
Host smart-1c497dc1-be3f-4123-908d-365d97f715be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955305077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2955305077
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1250943067
Short name T1315
Test name
Test status
Simulation time 11477526 ps
CPU time 0.55 seconds
Started May 09 02:34:45 PM PDT 24
Finished May 09 02:34:50 PM PDT 24
Peak memory 194676 kb
Host smart-3c508b9a-58c5-464e-b2ec-b2ee67bc8b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250943067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1250943067
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4129983360
Short name T1201
Test name
Test status
Simulation time 15206489 ps
CPU time 0.59 seconds
Started May 09 02:34:50 PM PDT 24
Finished May 09 02:34:56 PM PDT 24
Peak memory 194764 kb
Host smart-a96f4f87-3630-44fc-8a46-4e9e4250c74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129983360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4129983360
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.47152007
Short name T1285
Test name
Test status
Simulation time 57394384 ps
CPU time 0.67 seconds
Started May 09 02:34:29 PM PDT 24
Finished May 09 02:34:37 PM PDT 24
Peak memory 195944 kb
Host smart-f5d1fd77-86bd-4efd-a81e-03f0a3d08ea3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47152007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.47152007
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4081679938
Short name T1278
Test name
Test status
Simulation time 112985540 ps
CPU time 2.24 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 198008 kb
Host smart-ef2f9553-6765-4473-a929-b5d86675bb4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081679938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4081679938
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.555075053
Short name T69
Test name
Test status
Simulation time 17710909 ps
CPU time 0.63 seconds
Started May 09 02:34:20 PM PDT 24
Finished May 09 02:34:26 PM PDT 24
Peak memory 195720 kb
Host smart-6f51f402-b8d4-4d36-8248-57ba3aa207a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555075053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.555075053
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1225105239
Short name T1305
Test name
Test status
Simulation time 49011434 ps
CPU time 0.87 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:33 PM PDT 24
Peak memory 200168 kb
Host smart-0d668ef7-b7b3-4f97-92dc-35be45e39897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225105239 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1225105239
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1254368943
Short name T67
Test name
Test status
Simulation time 14568402 ps
CPU time 0.62 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 195804 kb
Host smart-b02b3f7f-0d7e-4c75-83d0-65d459dccd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254368943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1254368943
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3956485010
Short name T1210
Test name
Test status
Simulation time 16370893 ps
CPU time 0.6 seconds
Started May 09 02:34:24 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 194736 kb
Host smart-ca63dbd2-29d3-4fd1-8821-901448e1af9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956485010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3956485010
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4222257555
Short name T1309
Test name
Test status
Simulation time 18413585 ps
CPU time 0.64 seconds
Started May 09 02:34:28 PM PDT 24
Finished May 09 02:34:36 PM PDT 24
Peak memory 195808 kb
Host smart-550e8ad0-5227-4a5a-8a4c-eb71dad58735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222257555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4222257555
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3988568262
Short name T1254
Test name
Test status
Simulation time 107131416 ps
CPU time 1.56 seconds
Started May 09 02:34:23 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 200392 kb
Host smart-28c98678-db92-4ec1-82cc-74afca10c48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988568262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3988568262
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.199457468
Short name T1318
Test name
Test status
Simulation time 318171904 ps
CPU time 1.31 seconds
Started May 09 02:34:22 PM PDT 24
Finished May 09 02:34:28 PM PDT 24
Peak memory 199612 kb
Host smart-f01a9aee-327d-40d4-a118-432d599eedc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199457468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.199457468
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.876773843
Short name T1257
Test name
Test status
Simulation time 14623521 ps
CPU time 0.57 seconds
Started May 09 02:34:48 PM PDT 24
Finished May 09 02:34:54 PM PDT 24
Peak memory 194696 kb
Host smart-04c8e084-4e7e-45bb-9190-b46c29d69a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876773843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.876773843
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2135029557
Short name T1220
Test name
Test status
Simulation time 15577002 ps
CPU time 0.55 seconds
Started May 09 02:34:49 PM PDT 24
Finished May 09 02:34:55 PM PDT 24
Peak memory 194468 kb
Host smart-0919e365-f369-4026-8665-b50a98375f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135029557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2135029557
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4094608701
Short name T1230
Test name
Test status
Simulation time 14241032 ps
CPU time 0.6 seconds
Started May 09 02:34:48 PM PDT 24
Finished May 09 02:34:54 PM PDT 24
Peak memory 194700 kb
Host smart-c0a9cc31-5bc1-4da9-87a6-691ec8d34fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094608701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4094608701
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.704430486
Short name T1211
Test name
Test status
Simulation time 55423146 ps
CPU time 0.55 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:51 PM PDT 24
Peak memory 194692 kb
Host smart-f002d942-ec1c-4836-85aa-92aea40002c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704430486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.704430486
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1710106566
Short name T1231
Test name
Test status
Simulation time 14733930 ps
CPU time 0.58 seconds
Started May 09 02:34:47 PM PDT 24
Finished May 09 02:34:53 PM PDT 24
Peak memory 194700 kb
Host smart-3408c3bb-685e-40ef-bc0d-ffd96cfae424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710106566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1710106566
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3398009523
Short name T1187
Test name
Test status
Simulation time 90116800 ps
CPU time 0.55 seconds
Started May 09 02:34:48 PM PDT 24
Finished May 09 02:34:55 PM PDT 24
Peak memory 194752 kb
Host smart-36f549c5-3115-4820-a95a-5efe5f260d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398009523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3398009523
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.441911219
Short name T1189
Test name
Test status
Simulation time 15902032 ps
CPU time 0.59 seconds
Started May 09 02:34:48 PM PDT 24
Finished May 09 02:34:54 PM PDT 24
Peak memory 194688 kb
Host smart-7f254325-4663-439c-a254-3feae0288ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441911219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.441911219
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3082363558
Short name T1188
Test name
Test status
Simulation time 27980161 ps
CPU time 0.6 seconds
Started May 09 02:34:46 PM PDT 24
Finished May 09 02:34:51 PM PDT 24
Peak memory 194700 kb
Host smart-13da5cf8-ae37-42c1-bb64-e2851b8e0171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082363558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3082363558
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3198818275
Short name T1194
Test name
Test status
Simulation time 14393339 ps
CPU time 0.58 seconds
Started May 09 02:34:49 PM PDT 24
Finished May 09 02:34:56 PM PDT 24
Peak memory 194768 kb
Host smart-82ecabb3-1b73-48d7-82cb-bdc3d323fbfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198818275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3198818275
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2389733584
Short name T1282
Test name
Test status
Simulation time 15443738 ps
CPU time 0.59 seconds
Started May 09 02:34:49 PM PDT 24
Finished May 09 02:34:55 PM PDT 24
Peak memory 194508 kb
Host smart-e7161267-1013-4d6d-9985-f0c0f69cfe63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389733584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2389733584
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4754712
Short name T1266
Test name
Test status
Simulation time 87826687 ps
CPU time 0.79 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:33 PM PDT 24
Peak memory 200164 kb
Host smart-178dcdac-a419-418f-849c-9101e8b0b71d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4754712 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4754712
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3824536533
Short name T1238
Test name
Test status
Simulation time 10838408 ps
CPU time 0.6 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:39 PM PDT 24
Peak memory 195728 kb
Host smart-bb53984b-aa79-469e-91ee-8f19f28b13fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824536533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3824536533
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.999692012
Short name T1269
Test name
Test status
Simulation time 19120988 ps
CPU time 0.58 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 194652 kb
Host smart-cec0b913-ff61-4b93-80b5-5358e9e3e40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999692012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.999692012
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1273432101
Short name T96
Test name
Test status
Simulation time 21215557 ps
CPU time 0.64 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:31 PM PDT 24
Peak memory 196284 kb
Host smart-e4dc3b64-1d05-4b07-9440-1c62c47251b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273432101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1273432101
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3643462437
Short name T1303
Test name
Test status
Simulation time 54910706 ps
CPU time 1.13 seconds
Started May 09 02:34:23 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 200396 kb
Host smart-de10f941-22df-4e00-94ec-86e7a90cc8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643462437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3643462437
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3696694505
Short name T110
Test name
Test status
Simulation time 149773080 ps
CPU time 1.28 seconds
Started May 09 02:34:32 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 199428 kb
Host smart-84255078-8677-4be8-b0f8-d6f77c69fd6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696694505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3696694505
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2700561894
Short name T1302
Test name
Test status
Simulation time 20303853 ps
CPU time 1 seconds
Started May 09 02:34:19 PM PDT 24
Finished May 09 02:34:27 PM PDT 24
Peak memory 200200 kb
Host smart-d8beb263-2b79-444b-a5f3-29bb68896bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700561894 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2700561894
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1135977991
Short name T1260
Test name
Test status
Simulation time 22422006 ps
CPU time 0.62 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:39 PM PDT 24
Peak memory 195716 kb
Host smart-7c9e4ddf-e4fe-49dc-8792-ef81bed448ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135977991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1135977991
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2179108133
Short name T1233
Test name
Test status
Simulation time 20505839 ps
CPU time 0.55 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:30 PM PDT 24
Peak memory 194660 kb
Host smart-d6668b15-6e13-4e64-878d-530e1f0ca591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179108133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2179108133
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3726699807
Short name T1232
Test name
Test status
Simulation time 88347691 ps
CPU time 0.71 seconds
Started May 09 02:34:24 PM PDT 24
Finished May 09 02:34:30 PM PDT 24
Peak memory 197212 kb
Host smart-234395ef-4856-4937-9e76-23700d6a0508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726699807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3726699807
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3839718483
Short name T1245
Test name
Test status
Simulation time 463732704 ps
CPU time 2.24 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:32 PM PDT 24
Peak memory 200244 kb
Host smart-5630914b-e6fd-401a-b4a3-9ae2f34f08c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839718483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3839718483
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4082244300
Short name T1267
Test name
Test status
Simulation time 749741424 ps
CPU time 0.96 seconds
Started May 09 02:34:35 PM PDT 24
Finished May 09 02:34:43 PM PDT 24
Peak memory 199112 kb
Host smart-8add0288-698b-4674-acb3-98fe079a7a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082244300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4082244300
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2186841062
Short name T1185
Test name
Test status
Simulation time 77063946 ps
CPU time 1.04 seconds
Started May 09 02:34:29 PM PDT 24
Finished May 09 02:34:36 PM PDT 24
Peak memory 200112 kb
Host smart-8b79e0b5-f23b-4a4a-9b37-d914336d429a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186841062 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2186841062
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3766359227
Short name T1223
Test name
Test status
Simulation time 45500174 ps
CPU time 0.57 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:39 PM PDT 24
Peak memory 195712 kb
Host smart-7baab83c-48ed-432b-8f00-2474aaff131c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766359227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3766359227
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.4271057550
Short name T1291
Test name
Test status
Simulation time 17485494 ps
CPU time 0.57 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:34 PM PDT 24
Peak memory 194720 kb
Host smart-fc35efcb-a382-4da9-b833-3bf9314f57a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271057550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4271057550
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3558409535
Short name T1298
Test name
Test status
Simulation time 58641408 ps
CPU time 0.77 seconds
Started May 09 02:34:37 PM PDT 24
Finished May 09 02:34:44 PM PDT 24
Peak memory 196480 kb
Host smart-336688e8-96e8-409e-a6ea-3c22210a3258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558409535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3558409535
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2704209150
Short name T1229
Test name
Test status
Simulation time 169807326 ps
CPU time 2 seconds
Started May 09 02:34:31 PM PDT 24
Finished May 09 02:34:40 PM PDT 24
Peak memory 200428 kb
Host smart-5a4ad07c-2c01-46a0-9307-f151dbca71f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704209150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2704209150
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3431221550
Short name T1264
Test name
Test status
Simulation time 172515623 ps
CPU time 1.33 seconds
Started May 09 02:34:25 PM PDT 24
Finished May 09 02:34:32 PM PDT 24
Peak memory 199768 kb
Host smart-08a231e8-07b6-4155-993a-2d72a6b86215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431221550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3431221550
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4083856428
Short name T1287
Test name
Test status
Simulation time 49604256 ps
CPU time 0.65 seconds
Started May 09 02:34:23 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 197968 kb
Host smart-64503856-d90c-4198-bad8-729625ffc3f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083856428 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4083856428
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1615225297
Short name T1276
Test name
Test status
Simulation time 75953532 ps
CPU time 0.59 seconds
Started May 09 02:34:28 PM PDT 24
Finished May 09 02:34:36 PM PDT 24
Peak memory 195684 kb
Host smart-9915e7ea-1259-4c0f-8aef-8b01bc8f2875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615225297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1615225297
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2825283931
Short name T1202
Test name
Test status
Simulation time 24221311 ps
CPU time 0.57 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:34 PM PDT 24
Peak memory 194696 kb
Host smart-19a7c46c-8bf1-471f-a80d-677538681871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825283931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2825283931
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2523286791
Short name T1258
Test name
Test status
Simulation time 23857881 ps
CPU time 0.66 seconds
Started May 09 02:34:26 PM PDT 24
Finished May 09 02:34:33 PM PDT 24
Peak memory 195216 kb
Host smart-6beae71e-2d0f-4b1d-97d0-3150535bae55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523286791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2523286791
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.87522662
Short name T1311
Test name
Test status
Simulation time 56578404 ps
CPU time 1.4 seconds
Started May 09 02:34:16 PM PDT 24
Finished May 09 02:34:25 PM PDT 24
Peak memory 200344 kb
Host smart-3b8b93fb-87a1-49ac-9075-22aa8b446c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87522662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.87522662
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2094632344
Short name T107
Test name
Test status
Simulation time 95768271 ps
CPU time 1.22 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:34 PM PDT 24
Peak memory 199548 kb
Host smart-682d79a9-815a-43ca-a4df-25d3d8789e43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094632344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2094632344
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1318692447
Short name T1292
Test name
Test status
Simulation time 68250106 ps
CPU time 0.97 seconds
Started May 09 02:34:23 PM PDT 24
Finished May 09 02:34:29 PM PDT 24
Peak memory 200420 kb
Host smart-b629970c-2092-4a71-b0ff-0570a8c72f52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318692447 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1318692447
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2436563596
Short name T72
Test name
Test status
Simulation time 17046262 ps
CPU time 0.65 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:34 PM PDT 24
Peak memory 196104 kb
Host smart-967e3f8f-d983-4c7c-9b5f-9366a49cc20f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436563596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2436563596
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3229743508
Short name T1281
Test name
Test status
Simulation time 112489269 ps
CPU time 0.57 seconds
Started May 09 02:34:33 PM PDT 24
Finished May 09 02:34:41 PM PDT 24
Peak memory 194728 kb
Host smart-77c510a6-af4b-46b8-912c-15f4745f0835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229743508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3229743508
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.868753522
Short name T1290
Test name
Test status
Simulation time 63477611 ps
CPU time 0.68 seconds
Started May 09 02:34:24 PM PDT 24
Finished May 09 02:34:30 PM PDT 24
Peak memory 195064 kb
Host smart-3efe645b-6cee-4b23-915d-ebd770625600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868753522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.868753522
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.461367729
Short name T1212
Test name
Test status
Simulation time 358383195 ps
CPU time 1.65 seconds
Started May 09 02:34:27 PM PDT 24
Finished May 09 02:34:35 PM PDT 24
Peak memory 200420 kb
Host smart-02537e03-1e80-4030-8d29-64c118a5bfcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461367729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.461367729
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.1993593507
Short name T136
Test name
Test status
Simulation time 23304619 ps
CPU time 0.54 seconds
Started May 09 02:38:02 PM PDT 24
Finished May 09 02:38:03 PM PDT 24
Peak memory 194820 kb
Host smart-73a5537b-3019-4b95-9d45-8f9b0efed48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993593507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1993593507
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3029952686
Short name T823
Test name
Test status
Simulation time 19173562893 ps
CPU time 9.48 seconds
Started May 09 02:38:04 PM PDT 24
Finished May 09 02:38:15 PM PDT 24
Peak memory 200372 kb
Host smart-bd4146a8-49dd-471b-a467-da6dcd7fdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029952686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3029952686
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.599756476
Short name T859
Test name
Test status
Simulation time 121445860533 ps
CPU time 26.04 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:38:30 PM PDT 24
Peak memory 200448 kb
Host smart-23b6ed32-c700-4493-a8dd-29e8b33bd813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599756476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.599756476
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.2597838401
Short name T1015
Test name
Test status
Simulation time 11756246464 ps
CPU time 5.79 seconds
Started May 09 02:37:57 PM PDT 24
Finished May 09 02:38:04 PM PDT 24
Peak memory 196416 kb
Host smart-46da6a62-30a8-4671-bb0a-f0f3d18aaa1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597838401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2597838401
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3134538239
Short name T1175
Test name
Test status
Simulation time 331864207495 ps
CPU time 244.73 seconds
Started May 09 02:38:09 PM PDT 24
Finished May 09 02:42:14 PM PDT 24
Peak memory 200376 kb
Host smart-4a53352c-3591-4d60-b9c3-eac41cdb6975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134538239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3134538239
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.489973353
Short name T844
Test name
Test status
Simulation time 8408193192 ps
CPU time 16.25 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:38:21 PM PDT 24
Peak memory 199572 kb
Host smart-f2393e1f-1bbf-4f01-85e5-6ebac1b2d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489973353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.489973353
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.658478485
Short name T875
Test name
Test status
Simulation time 23272490178 ps
CPU time 8.78 seconds
Started May 09 02:37:59 PM PDT 24
Finished May 09 02:38:09 PM PDT 24
Peak memory 198808 kb
Host smart-1dda6096-765c-4731-a754-81f9b26c148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658478485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.658478485
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2615156867
Short name T676
Test name
Test status
Simulation time 14722588502 ps
CPU time 231.06 seconds
Started May 09 02:38:02 PM PDT 24
Finished May 09 02:41:54 PM PDT 24
Peak memory 200384 kb
Host smart-d25ee011-a155-4e8d-9184-c72112e61157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615156867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2615156867
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4244007462
Short name T411
Test name
Test status
Simulation time 5529130909 ps
CPU time 11.17 seconds
Started May 09 02:37:56 PM PDT 24
Finished May 09 02:38:09 PM PDT 24
Peak memory 198668 kb
Host smart-32cda4c8-b312-4607-8e6c-82d20ac0ed9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244007462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4244007462
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.664968500
Short name T796
Test name
Test status
Simulation time 91725587079 ps
CPU time 80.43 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:39:25 PM PDT 24
Peak memory 200444 kb
Host smart-c2d1e4e2-9075-4a84-9d01-7be3b50371c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664968500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.664968500
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.826544606
Short name T871
Test name
Test status
Simulation time 1741093383 ps
CPU time 1.99 seconds
Started May 09 02:37:59 PM PDT 24
Finished May 09 02:38:07 PM PDT 24
Peak memory 196064 kb
Host smart-57e3724f-72dc-43d1-9fc3-6e972abcd4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826544606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.826544606
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3796742093
Short name T752
Test name
Test status
Simulation time 478707010 ps
CPU time 1.32 seconds
Started May 09 02:38:05 PM PDT 24
Finished May 09 02:38:07 PM PDT 24
Peak memory 199248 kb
Host smart-1ca1418e-f536-4a15-9671-3668e788c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796742093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3796742093
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2840909573
Short name T615
Test name
Test status
Simulation time 212128040364 ps
CPU time 544.41 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 225416 kb
Host smart-bd7cce9a-516c-4d7c-b067-7628a7f4debb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840909573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2840909573
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2526859741
Short name T974
Test name
Test status
Simulation time 714207181 ps
CPU time 2.21 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:38:07 PM PDT 24
Peak memory 199156 kb
Host smart-87bc3a6b-740c-4731-a13b-9b68bac2ee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526859741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2526859741
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.688627213
Short name T620
Test name
Test status
Simulation time 46727504110 ps
CPU time 54.76 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:38:59 PM PDT 24
Peak memory 200468 kb
Host smart-b749540b-4793-4903-82af-4d01bf5eb962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688627213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.688627213
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4198552394
Short name T83
Test name
Test status
Simulation time 32285181 ps
CPU time 0.56 seconds
Started May 09 02:38:02 PM PDT 24
Finished May 09 02:38:03 PM PDT 24
Peak memory 195828 kb
Host smart-07d251c3-fd01-4419-9e62-aa41f07a4b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198552394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4198552394
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.14869975
Short name T77
Test name
Test status
Simulation time 20085520577 ps
CPU time 31.03 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:38:39 PM PDT 24
Peak memory 200444 kb
Host smart-a79ddcfb-bbde-4b33-8153-dd52582bd754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14869975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.14869975
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2844094311
Short name T240
Test name
Test status
Simulation time 146397664754 ps
CPU time 78.23 seconds
Started May 09 02:38:05 PM PDT 24
Finished May 09 02:39:24 PM PDT 24
Peak memory 200460 kb
Host smart-9b63bb2b-d212-4d59-acdd-8e36f2c52d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844094311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2844094311
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.397291328
Short name T977
Test name
Test status
Simulation time 9544026957 ps
CPU time 2.81 seconds
Started May 09 02:38:11 PM PDT 24
Finished May 09 02:38:15 PM PDT 24
Peak memory 200428 kb
Host smart-ebea3eef-a546-43e1-8da2-aba5ea0b3fea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397291328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.397291328
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1099448333
Short name T394
Test name
Test status
Simulation time 129339426778 ps
CPU time 1043.25 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:55:28 PM PDT 24
Peak memory 200388 kb
Host smart-1b39fe54-dd38-49d7-b18e-81f719b5e489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099448333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1099448333
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2368433261
Short name T559
Test name
Test status
Simulation time 8118480116 ps
CPU time 5.73 seconds
Started May 09 02:38:05 PM PDT 24
Finished May 09 02:38:11 PM PDT 24
Peak memory 199272 kb
Host smart-e9107756-9f72-45f0-ab0e-3d5f939d2490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368433261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2368433261
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1974953688
Short name T924
Test name
Test status
Simulation time 141207330013 ps
CPU time 68.67 seconds
Started May 09 02:38:22 PM PDT 24
Finished May 09 02:39:32 PM PDT 24
Peak memory 208496 kb
Host smart-4bb0976b-98fb-4d12-88c3-9c883f777f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974953688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1974953688
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3083356066
Short name T424
Test name
Test status
Simulation time 16990202412 ps
CPU time 941.68 seconds
Started May 09 02:38:05 PM PDT 24
Finished May 09 02:53:47 PM PDT 24
Peak memory 200388 kb
Host smart-73a21b62-1350-4f95-afc6-ab9baf5331b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083356066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3083356066
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1693825159
Short name T848
Test name
Test status
Simulation time 5186710427 ps
CPU time 3.85 seconds
Started May 09 02:38:01 PM PDT 24
Finished May 09 02:38:06 PM PDT 24
Peak memory 199148 kb
Host smart-255537f7-9e65-445e-8cf2-2866d5a7c389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693825159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1693825159
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1069102781
Short name T139
Test name
Test status
Simulation time 178171590311 ps
CPU time 28.49 seconds
Started May 09 02:38:01 PM PDT 24
Finished May 09 02:38:31 PM PDT 24
Peak memory 200440 kb
Host smart-3eb99e0f-ece1-45c9-b513-ec8f4501065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069102781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1069102781
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2233867723
Short name T1173
Test name
Test status
Simulation time 526488360 ps
CPU time 1.22 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:38:05 PM PDT 24
Peak memory 195756 kb
Host smart-d8e8ced3-5ec3-4ee8-a3fa-fef127f43890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233867723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2233867723
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.592352501
Short name T112
Test name
Test status
Simulation time 51112202 ps
CPU time 0.79 seconds
Started May 09 02:38:11 PM PDT 24
Finished May 09 02:38:13 PM PDT 24
Peak memory 218424 kb
Host smart-83fe8588-216b-493e-9212-fed2edc5e092
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592352501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.592352501
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3918097590
Short name T831
Test name
Test status
Simulation time 530572870 ps
CPU time 4.42 seconds
Started May 09 02:37:59 PM PDT 24
Finished May 09 02:38:04 PM PDT 24
Peak memory 199200 kb
Host smart-ed7e7e17-1fd3-46b0-b1d4-362ab2ffdadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918097590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3918097590
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.979044242
Short name T239
Test name
Test status
Simulation time 312732688830 ps
CPU time 1219.95 seconds
Started May 09 02:38:09 PM PDT 24
Finished May 09 02:58:30 PM PDT 24
Peak memory 200508 kb
Host smart-0763aadd-e871-4944-9561-adfe32ab9eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979044242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.979044242
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2111562124
Short name T481
Test name
Test status
Simulation time 405798993 ps
CPU time 1.4 seconds
Started May 09 02:38:04 PM PDT 24
Finished May 09 02:38:06 PM PDT 24
Peak memory 198516 kb
Host smart-d6d028bd-27e3-4f2f-95d5-f8a62773ddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111562124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2111562124
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2617572395
Short name T442
Test name
Test status
Simulation time 126843564957 ps
CPU time 28.96 seconds
Started May 09 02:38:07 PM PDT 24
Finished May 09 02:38:37 PM PDT 24
Peak memory 200368 kb
Host smart-5b724f7c-0b35-4fa0-9e86-804c793c6cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617572395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2617572395
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1626189112
Short name T536
Test name
Test status
Simulation time 23392923 ps
CPU time 0.55 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:38:39 PM PDT 24
Peak memory 195844 kb
Host smart-541d5b3e-3383-4d09-8565-f1ab31ac692c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626189112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1626189112
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3751164815
Short name T1143
Test name
Test status
Simulation time 26082707908 ps
CPU time 25.75 seconds
Started May 09 02:38:48 PM PDT 24
Finished May 09 02:39:15 PM PDT 24
Peak memory 200356 kb
Host smart-b2aa4596-fb99-49d2-9bee-7b68891cebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751164815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3751164815
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.394806054
Short name T42
Test name
Test status
Simulation time 31282413009 ps
CPU time 13.3 seconds
Started May 09 02:38:31 PM PDT 24
Finished May 09 02:38:46 PM PDT 24
Peak memory 200436 kb
Host smart-583b07b4-815c-43c2-ac2f-ea051b350936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394806054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.394806054
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1950086230
Short name T1170
Test name
Test status
Simulation time 39458857208 ps
CPU time 41.18 seconds
Started May 09 02:38:51 PM PDT 24
Finished May 09 02:39:33 PM PDT 24
Peak memory 200372 kb
Host smart-1e082765-9a17-4b15-9958-4a8af5faddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950086230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1950086230
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1617566299
Short name T1059
Test name
Test status
Simulation time 6263912377 ps
CPU time 10.68 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:38:49 PM PDT 24
Peak memory 197228 kb
Host smart-b43922f1-3bf6-456e-ba96-ba6f18456c15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617566299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1617566299
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4039688186
Short name T453
Test name
Test status
Simulation time 184222841538 ps
CPU time 260.07 seconds
Started May 09 02:38:39 PM PDT 24
Finished May 09 02:43:00 PM PDT 24
Peak memory 200480 kb
Host smart-fa7cf439-b1da-49b0-ad49-021dfdd39b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039688186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4039688186
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3613750002
Short name T454
Test name
Test status
Simulation time 10793680514 ps
CPU time 11.45 seconds
Started May 09 02:38:50 PM PDT 24
Finished May 09 02:39:03 PM PDT 24
Peak memory 200468 kb
Host smart-2b88195a-a266-4617-9766-0089916b54cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613750002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3613750002
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.563301777
Short name T916
Test name
Test status
Simulation time 87653438797 ps
CPU time 164.21 seconds
Started May 09 02:38:36 PM PDT 24
Finished May 09 02:41:21 PM PDT 24
Peak memory 200584 kb
Host smart-05939ed0-db04-4122-bcc7-ece38d02f53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563301777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.563301777
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.597228670
Short name T307
Test name
Test status
Simulation time 2826456787 ps
CPU time 45.32 seconds
Started May 09 02:38:36 PM PDT 24
Finished May 09 02:39:22 PM PDT 24
Peak memory 200428 kb
Host smart-012eead1-a4b0-4704-be34-fe4af8845ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597228670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.597228670
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4180881125
Short name T926
Test name
Test status
Simulation time 1481123011 ps
CPU time 6.54 seconds
Started May 09 02:38:45 PM PDT 24
Finished May 09 02:38:52 PM PDT 24
Peak memory 198696 kb
Host smart-a3c81f82-1437-4003-ba13-2953febacb80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180881125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4180881125
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3987968613
Short name T1003
Test name
Test status
Simulation time 31356792163 ps
CPU time 49.63 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:39:34 PM PDT 24
Peak memory 200344 kb
Host smart-741e0e6f-cd0f-4d75-9e59-f9ff08f5d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987968613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3987968613
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3514439164
Short name T590
Test name
Test status
Simulation time 19983681747 ps
CPU time 2.67 seconds
Started May 09 02:38:53 PM PDT 24
Finished May 09 02:38:57 PM PDT 24
Peak memory 196712 kb
Host smart-fa988d2f-bbb5-4515-9a93-f1c3357637c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514439164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3514439164
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2702474737
Short name T383
Test name
Test status
Simulation time 627002968 ps
CPU time 3.13 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:38:53 PM PDT 24
Peak memory 198580 kb
Host smart-44e5a07b-176e-4e69-93fc-317736606f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702474737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2702474737
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2259594250
Short name T498
Test name
Test status
Simulation time 51776328581 ps
CPU time 44.18 seconds
Started May 09 02:38:48 PM PDT 24
Finished May 09 02:39:33 PM PDT 24
Peak memory 200432 kb
Host smart-ccdae40e-6ef8-4b8e-99f5-5ffbb28fb85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259594250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2259594250
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3623639721
Short name T477
Test name
Test status
Simulation time 1166725564 ps
CPU time 3.74 seconds
Started May 09 02:38:45 PM PDT 24
Finished May 09 02:38:50 PM PDT 24
Peak memory 198908 kb
Host smart-262971e5-4348-44af-b278-a1543670ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623639721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3623639721
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2310991484
Short name T566
Test name
Test status
Simulation time 334001976094 ps
CPU time 31.78 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:39:22 PM PDT 24
Peak memory 200240 kb
Host smart-d13aba21-6cd0-41e5-b052-f2b3632c848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310991484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2310991484
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2930454090
Short name T930
Test name
Test status
Simulation time 9830169122 ps
CPU time 24.08 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:42:02 PM PDT 24
Peak memory 200424 kb
Host smart-885cd63f-5bad-41fc-ab2e-a2ca27bfdf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930454090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2930454090
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3473248426
Short name T1125
Test name
Test status
Simulation time 55415762211 ps
CPU time 25.1 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:42:03 PM PDT 24
Peak memory 200376 kb
Host smart-3d6cca53-a5dd-467a-b440-f162a1bb04ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473248426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3473248426
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3990156740
Short name T3
Test name
Test status
Simulation time 193540333488 ps
CPU time 263.1 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 200256 kb
Host smart-834867bc-7921-4230-8a14-0cc2e0d54994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990156740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3990156740
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3667706157
Short name T336
Test name
Test status
Simulation time 58649200829 ps
CPU time 88.16 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:43:16 PM PDT 24
Peak memory 200240 kb
Host smart-8e29608c-95c2-4e9b-9b33-de955c00f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667706157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3667706157
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1215896007
Short name T824
Test name
Test status
Simulation time 13191624666 ps
CPU time 22.36 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:42:00 PM PDT 24
Peak memory 200336 kb
Host smart-30404cbf-fbe3-488a-903c-f02db0a0b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215896007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1215896007
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2294396863
Short name T841
Test name
Test status
Simulation time 126273073258 ps
CPU time 189.37 seconds
Started May 09 02:41:42 PM PDT 24
Finished May 09 02:44:53 PM PDT 24
Peak memory 200256 kb
Host smart-aa37b441-c27f-4aa2-8d12-dd29d63e7170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294396863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2294396863
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3936353047
Short name T1031
Test name
Test status
Simulation time 103949882894 ps
CPU time 174.11 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:44:42 PM PDT 24
Peak memory 199892 kb
Host smart-c36fb1f0-8c1f-4e4d-ba39-cf1ceb8bf437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936353047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3936353047
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.218552600
Short name T209
Test name
Test status
Simulation time 33227463746 ps
CPU time 53.11 seconds
Started May 09 02:41:37 PM PDT 24
Finished May 09 02:42:33 PM PDT 24
Peak memory 200392 kb
Host smart-ee223c2e-2197-4169-ad9f-3cdaea62d04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218552600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.218552600
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2631019096
Short name T786
Test name
Test status
Simulation time 13054319 ps
CPU time 0.55 seconds
Started May 09 02:38:43 PM PDT 24
Finished May 09 02:38:44 PM PDT 24
Peak memory 195300 kb
Host smart-7c842439-2ef8-4c19-b305-40458447a2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631019096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2631019096
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4116235617
Short name T1122
Test name
Test status
Simulation time 80808742790 ps
CPU time 48.87 seconds
Started May 09 02:38:50 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 200448 kb
Host smart-e91d56b8-e687-48c4-a7bd-a2a916eaf666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116235617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4116235617
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1691818752
Short name T419
Test name
Test status
Simulation time 146940120032 ps
CPU time 71.49 seconds
Started May 09 02:38:48 PM PDT 24
Finished May 09 02:40:01 PM PDT 24
Peak memory 200428 kb
Host smart-4f0100e2-8579-4eb1-92f9-7e3503b287c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691818752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1691818752
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2302120466
Short name T605
Test name
Test status
Simulation time 62436912633 ps
CPU time 99.47 seconds
Started May 09 02:38:35 PM PDT 24
Finished May 09 02:40:15 PM PDT 24
Peak memory 200412 kb
Host smart-c4c806ae-d8d5-4948-80c4-6ef60a488858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302120466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2302120466
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2345391033
Short name T140
Test name
Test status
Simulation time 29771287934 ps
CPU time 43.14 seconds
Started May 09 02:38:39 PM PDT 24
Finished May 09 02:39:23 PM PDT 24
Peak memory 198912 kb
Host smart-e81e733f-9a4a-4096-8acc-61776c94dfdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345391033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2345391033
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1493819006
Short name T423
Test name
Test status
Simulation time 218474980721 ps
CPU time 156.91 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:41:22 PM PDT 24
Peak memory 200464 kb
Host smart-4b752f32-c667-4cb1-8075-8f3468a7624c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493819006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1493819006
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2502616106
Short name T834
Test name
Test status
Simulation time 5472278772 ps
CPU time 3.05 seconds
Started May 09 02:38:42 PM PDT 24
Finished May 09 02:38:45 PM PDT 24
Peak memory 196580 kb
Host smart-3f64bfa3-58ca-4e9d-830f-296df28643a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502616106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2502616106
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1417171638
Short name T881
Test name
Test status
Simulation time 180143194497 ps
CPU time 78.37 seconds
Started May 09 02:38:38 PM PDT 24
Finished May 09 02:39:58 PM PDT 24
Peak memory 200192 kb
Host smart-fac31e27-0fba-4726-8343-686030ec8445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417171638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1417171638
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3798663175
Short name T877
Test name
Test status
Simulation time 8700154105 ps
CPU time 275.68 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:43:23 PM PDT 24
Peak memory 200472 kb
Host smart-1f731746-a2e3-47e2-b0a4-d3ebc20d5283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798663175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3798663175
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4022379083
Short name T1036
Test name
Test status
Simulation time 3685413450 ps
CPU time 29.41 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:39:17 PM PDT 24
Peak memory 199244 kb
Host smart-f317204d-658b-44cf-b89e-5fa7b5432fc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022379083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4022379083
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1273990034
Short name T464
Test name
Test status
Simulation time 135573432191 ps
CPU time 231.24 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:42:44 PM PDT 24
Peak memory 200404 kb
Host smart-320d9e53-fe37-480d-bc28-006a727852ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273990034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1273990034
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1918692946
Short name T561
Test name
Test status
Simulation time 1750229176 ps
CPU time 3.53 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:38:49 PM PDT 24
Peak memory 196124 kb
Host smart-7c11310d-8939-405d-8ffb-17dcb41e94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918692946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1918692946
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2562572259
Short name T1050
Test name
Test status
Simulation time 6147899297 ps
CPU time 7.13 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:38:55 PM PDT 24
Peak memory 200300 kb
Host smart-665c49d8-a201-4c3c-a267-c1ad948e0c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562572259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2562572259
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1114650206
Short name T867
Test name
Test status
Simulation time 111497342740 ps
CPU time 225.04 seconds
Started May 09 02:38:51 PM PDT 24
Finished May 09 02:42:38 PM PDT 24
Peak memory 200436 kb
Host smart-36231405-7985-455f-9da6-ce093dea0ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114650206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1114650206
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2084674638
Short name T650
Test name
Test status
Simulation time 36754827092 ps
CPU time 546.63 seconds
Started May 09 02:38:42 PM PDT 24
Finished May 09 02:47:49 PM PDT 24
Peak memory 217124 kb
Host smart-daa924bd-cfe6-409c-8a7d-183bc844eab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084674638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2084674638
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.285083657
Short name T62
Test name
Test status
Simulation time 6515619223 ps
CPU time 29.4 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:39:20 PM PDT 24
Peak memory 200364 kb
Host smart-ca13f0f0-81f4-4c0c-80e4-076806e3b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285083657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.285083657
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3103107270
Short name T1174
Test name
Test status
Simulation time 17758200822 ps
CPU time 27.67 seconds
Started May 09 02:38:41 PM PDT 24
Finished May 09 02:39:10 PM PDT 24
Peak memory 200204 kb
Host smart-f5825cbc-9f40-452d-988f-9775d5725cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103107270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3103107270
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2187614784
Short name T915
Test name
Test status
Simulation time 70127582921 ps
CPU time 34.98 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:42:16 PM PDT 24
Peak memory 200492 kb
Host smart-8c4e7b0b-fdcf-44fe-a4a6-212efb7a5bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187614784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2187614784
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3570702182
Short name T580
Test name
Test status
Simulation time 90029227089 ps
CPU time 39.23 seconds
Started May 09 02:41:37 PM PDT 24
Finished May 09 02:42:18 PM PDT 24
Peak memory 200412 kb
Host smart-4124f117-4a15-4896-8237-efb6cb55da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570702182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3570702182
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3903053838
Short name T1104
Test name
Test status
Simulation time 14530595819 ps
CPU time 25.08 seconds
Started May 09 02:41:35 PM PDT 24
Finished May 09 02:42:02 PM PDT 24
Peak memory 200216 kb
Host smart-5e91b160-da31-4649-9304-75b6c613c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903053838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3903053838
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3672042270
Short name T35
Test name
Test status
Simulation time 233787613690 ps
CPU time 62.3 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:42:43 PM PDT 24
Peak memory 200416 kb
Host smart-8b47d772-84f3-430f-b290-8871e0b8ca87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672042270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3672042270
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3367947785
Short name T14
Test name
Test status
Simulation time 111126239894 ps
CPU time 9.54 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:41:48 PM PDT 24
Peak memory 200084 kb
Host smart-91e03acf-4853-4473-9257-6271ddfbbf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367947785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3367947785
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1790049634
Short name T918
Test name
Test status
Simulation time 190540106205 ps
CPU time 85.6 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:43:07 PM PDT 24
Peak memory 200340 kb
Host smart-fa1d5e3f-c9cb-4330-ade1-050d597bbda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790049634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1790049634
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2069989227
Short name T58
Test name
Test status
Simulation time 167976268035 ps
CPU time 63.88 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:42:45 PM PDT 24
Peak memory 200340 kb
Host smart-64a91124-7a7a-4856-b284-b4e3c75866d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069989227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2069989227
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3693508418
Short name T118
Test name
Test status
Simulation time 36024744 ps
CPU time 0.54 seconds
Started May 09 02:38:51 PM PDT 24
Finished May 09 02:38:52 PM PDT 24
Peak memory 195188 kb
Host smart-c023659e-3d08-4e20-8ff9-74dd57759dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693508418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3693508418
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.888129793
Short name T1045
Test name
Test status
Simulation time 76203615834 ps
CPU time 88.36 seconds
Started May 09 02:38:36 PM PDT 24
Finished May 09 02:40:06 PM PDT 24
Peak memory 200420 kb
Host smart-9a5bd5fe-55bb-41b6-9055-fbf17a662b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888129793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.888129793
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1891623378
Short name T903
Test name
Test status
Simulation time 91335180272 ps
CPU time 78.9 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:40:06 PM PDT 24
Peak memory 200428 kb
Host smart-1cf0d0f7-6d22-4749-91e0-a0e9f6f151ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891623378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1891623378
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1253255587
Short name T133
Test name
Test status
Simulation time 98204321771 ps
CPU time 686.1 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 200408 kb
Host smart-52f0b8c9-7fae-4f6e-bb75-f563b8e82fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253255587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1253255587
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4091497998
Short name T519
Test name
Test status
Simulation time 30666021597 ps
CPU time 12.25 seconds
Started May 09 02:39:00 PM PDT 24
Finished May 09 02:39:14 PM PDT 24
Peak memory 200032 kb
Host smart-b3b749d7-bfcb-4430-88be-a197064399ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091497998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4091497998
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2259594297
Short name T1078
Test name
Test status
Simulation time 85941551290 ps
CPU time 252.92 seconds
Started May 09 02:38:50 PM PDT 24
Finished May 09 02:43:04 PM PDT 24
Peak memory 200476 kb
Host smart-bd61032a-d536-4d54-83d3-6d5cf8972caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259594297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2259594297
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2117963245
Short name T557
Test name
Test status
Simulation time 695668486 ps
CPU time 1.61 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:38:49 PM PDT 24
Peak memory 197876 kb
Host smart-c70a63e9-bff4-47aa-ae48-8e34d0659875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117963245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2117963245
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3901734730
Short name T793
Test name
Test status
Simulation time 192465586910 ps
CPU time 88.73 seconds
Started May 09 02:38:50 PM PDT 24
Finished May 09 02:40:20 PM PDT 24
Peak memory 200568 kb
Host smart-84c3c737-d0fe-402c-a249-9cfd45444288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901734730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3901734730
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.338252689
Short name T60
Test name
Test status
Simulation time 13727799809 ps
CPU time 385.27 seconds
Started May 09 02:38:45 PM PDT 24
Finished May 09 02:45:12 PM PDT 24
Peak memory 200384 kb
Host smart-d6a1e78a-77e4-45ce-8800-d5b06012ae12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338252689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.338252689
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1690747656
Short name T712
Test name
Test status
Simulation time 3718284387 ps
CPU time 4.37 seconds
Started May 09 02:38:53 PM PDT 24
Finished May 09 02:38:58 PM PDT 24
Peak memory 198788 kb
Host smart-47c4816a-c690-4ddd-8f58-09fcc3a7b656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690747656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1690747656
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1109109100
Short name T1004
Test name
Test status
Simulation time 32484460172 ps
CPU time 60.12 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:39:50 PM PDT 24
Peak memory 200412 kb
Host smart-e0b41c69-e8ef-43da-9dad-9a7cf7e25fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109109100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1109109100
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1326301121
Short name T972
Test name
Test status
Simulation time 29365217909 ps
CPU time 11.35 seconds
Started May 09 02:38:54 PM PDT 24
Finished May 09 02:39:07 PM PDT 24
Peak memory 196728 kb
Host smart-d0184877-13c4-4432-b3f7-34e5ea95abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326301121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1326301121
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1604984144
Short name T782
Test name
Test status
Simulation time 499917374 ps
CPU time 1.99 seconds
Started May 09 02:38:38 PM PDT 24
Finished May 09 02:38:41 PM PDT 24
Peak memory 198668 kb
Host smart-b4a14d6b-0693-4b38-8dfd-1e235686af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604984144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1604984144
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1125534026
Short name T658
Test name
Test status
Simulation time 19120697649 ps
CPU time 7.87 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:38:55 PM PDT 24
Peak memory 198124 kb
Host smart-f8b28faf-956f-4e94-97e5-726ee42e1d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125534026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1125534026
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3480890448
Short name T933
Test name
Test status
Simulation time 82321290262 ps
CPU time 1224.91 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:59:13 PM PDT 24
Peak memory 225484 kb
Host smart-78f8746c-1f20-45c0-9744-2e870e9820f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480890448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3480890448
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3607667131
Short name T691
Test name
Test status
Simulation time 665874065 ps
CPU time 1.91 seconds
Started May 09 02:38:43 PM PDT 24
Finished May 09 02:38:46 PM PDT 24
Peak memory 199212 kb
Host smart-111a7352-e9f7-4f2a-b325-fd56ece62a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607667131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3607667131
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.634339628
Short name T318
Test name
Test status
Simulation time 107284631718 ps
CPU time 43.37 seconds
Started May 09 02:38:41 PM PDT 24
Finished May 09 02:39:25 PM PDT 24
Peak memory 200400 kb
Host smart-7636082b-4f47-4195-b475-44523f7e2a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634339628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.634339628
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3725778039
Short name T210
Test name
Test status
Simulation time 129384240650 ps
CPU time 49.13 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:42:38 PM PDT 24
Peak memory 199512 kb
Host smart-5e36b6b1-fcd0-4137-ab0b-7f488ba3d7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725778039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3725778039
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3108084025
Short name T993
Test name
Test status
Simulation time 190540477170 ps
CPU time 81.02 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:43:11 PM PDT 24
Peak memory 200436 kb
Host smart-0b4e199c-8d8b-4fd9-9fd2-9e9cb1d764d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108084025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3108084025
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1900317335
Short name T173
Test name
Test status
Simulation time 15991844761 ps
CPU time 44.78 seconds
Started May 09 02:41:50 PM PDT 24
Finished May 09 02:42:38 PM PDT 24
Peak memory 200416 kb
Host smart-24657fce-a09f-4d46-810c-2cc08466cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900317335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1900317335
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2740380312
Short name T495
Test name
Test status
Simulation time 50495905831 ps
CPU time 83.9 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:43:12 PM PDT 24
Peak memory 200436 kb
Host smart-afcf782e-98ac-4b38-ad70-3004568aa34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740380312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2740380312
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1821655798
Short name T150
Test name
Test status
Simulation time 97012492646 ps
CPU time 41.5 seconds
Started May 09 02:41:49 PM PDT 24
Finished May 09 02:42:34 PM PDT 24
Peak memory 200400 kb
Host smart-c08e00bf-ccfa-4394-a265-1bf3e78f254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821655798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1821655798
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2964054424
Short name T1119
Test name
Test status
Simulation time 120232360650 ps
CPU time 187.8 seconds
Started May 09 02:41:44 PM PDT 24
Finished May 09 02:44:56 PM PDT 24
Peak memory 200460 kb
Host smart-26469eba-3788-4b9c-9a58-86e192e19512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964054424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2964054424
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1875191631
Short name T743
Test name
Test status
Simulation time 211856294647 ps
CPU time 369.77 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:47:59 PM PDT 24
Peak memory 200312 kb
Host smart-74cc3363-7f23-4161-b9ee-450c3086c1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875191631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1875191631
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2188364965
Short name T1055
Test name
Test status
Simulation time 11917880 ps
CPU time 0.55 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:38:51 PM PDT 24
Peak memory 195852 kb
Host smart-16fb128c-9a2a-491f-a5ac-88448d3aa93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188364965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2188364965
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1943725338
Short name T940
Test name
Test status
Simulation time 50023411981 ps
CPU time 42.43 seconds
Started May 09 02:38:40 PM PDT 24
Finished May 09 02:39:23 PM PDT 24
Peak memory 200416 kb
Host smart-30079a66-c5b0-4864-942b-708466799750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943725338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1943725338
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2651418417
Short name T792
Test name
Test status
Simulation time 102201676198 ps
CPU time 124.35 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:40:52 PM PDT 24
Peak memory 200384 kb
Host smart-0cec941a-dbdf-4d23-95cc-b78fad5d6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651418417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2651418417
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.3780261833
Short name T1137
Test name
Test status
Simulation time 56535912129 ps
CPU time 35.89 seconds
Started May 09 02:39:05 PM PDT 24
Finished May 09 02:39:41 PM PDT 24
Peak memory 200436 kb
Host smart-7b801148-9595-404d-b3e1-5bcb6872e5a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780261833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3780261833
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.845819475
Short name T397
Test name
Test status
Simulation time 63704395107 ps
CPU time 577.03 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 200460 kb
Host smart-938a12a0-fc42-44aa-86f9-aa68bb144b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845819475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.845819475
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1629510869
Short name T389
Test name
Test status
Simulation time 6699703622 ps
CPU time 12.29 seconds
Started May 09 02:38:56 PM PDT 24
Finished May 09 02:39:09 PM PDT 24
Peak memory 199072 kb
Host smart-84943e9d-e576-4d39-b4ec-8793772256ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629510869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1629510869
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.710764630
Short name T893
Test name
Test status
Simulation time 83939105121 ps
CPU time 135.07 seconds
Started May 09 02:38:43 PM PDT 24
Finished May 09 02:40:59 PM PDT 24
Peak memory 198536 kb
Host smart-b342867a-c328-4b61-81a9-a84f7e27e78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710764630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.710764630
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4036357129
Short name T90
Test name
Test status
Simulation time 1826985749 ps
CPU time 105.8 seconds
Started May 09 02:38:48 PM PDT 24
Finished May 09 02:40:35 PM PDT 24
Peak memory 200372 kb
Host smart-5c426229-c55d-4aee-a7c3-827b869031dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036357129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4036357129
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2259896482
Short name T375
Test name
Test status
Simulation time 4934684137 ps
CPU time 44.68 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:39:38 PM PDT 24
Peak memory 199732 kb
Host smart-73a1c880-3a55-47a8-8db5-226e41fe8be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259896482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2259896482
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1481760782
Short name T680
Test name
Test status
Simulation time 35030258255 ps
CPU time 16.46 seconds
Started May 09 02:38:56 PM PDT 24
Finished May 09 02:39:13 PM PDT 24
Peak memory 200352 kb
Host smart-a7ca76c4-d5ab-4109-8b61-9d90a8f3a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481760782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1481760782
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2388984869
Short name T460
Test name
Test status
Simulation time 35323177718 ps
CPU time 52.93 seconds
Started May 09 02:38:45 PM PDT 24
Finished May 09 02:39:39 PM PDT 24
Peak memory 196176 kb
Host smart-e150d23b-a28d-4c90-91f7-15b2e58d0601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388984869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2388984869
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3109011263
Short name T717
Test name
Test status
Simulation time 5751587580 ps
CPU time 9.38 seconds
Started May 09 02:39:02 PM PDT 24
Finished May 09 02:39:12 PM PDT 24
Peak memory 200184 kb
Host smart-9c792b5f-2df0-43f3-bc9a-1a9551d7333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109011263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3109011263
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.170170145
Short name T1007
Test name
Test status
Simulation time 78787569962 ps
CPU time 402.78 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:45:33 PM PDT 24
Peak memory 200496 kb
Host smart-27f08725-dd4e-4ef6-850b-23f04b3563ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170170145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.170170145
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1285064099
Short name T33
Test name
Test status
Simulation time 15333622744 ps
CPU time 217.49 seconds
Started May 09 02:38:55 PM PDT 24
Finished May 09 02:42:33 PM PDT 24
Peak memory 216740 kb
Host smart-129a5f39-6ddc-41f7-80cf-c15659c19d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285064099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1285064099
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4016575691
Short name T957
Test name
Test status
Simulation time 13349000116 ps
CPU time 18.53 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:39:06 PM PDT 24
Peak memory 200264 kb
Host smart-bee0e17f-2b9c-400d-9e9d-c016049b06c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016575691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4016575691
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1103432196
Short name T594
Test name
Test status
Simulation time 46905490961 ps
CPU time 20.33 seconds
Started May 09 02:39:02 PM PDT 24
Finished May 09 02:39:23 PM PDT 24
Peak memory 200408 kb
Host smart-bb466f6b-a10e-4221-b1a1-e1ce4a91dd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103432196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1103432196
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1115876995
Short name T569
Test name
Test status
Simulation time 47751666746 ps
CPU time 16.41 seconds
Started May 09 02:41:49 PM PDT 24
Finished May 09 02:42:09 PM PDT 24
Peak memory 200444 kb
Host smart-bd15a5cc-6a3a-48d3-ae05-d0251eed08d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115876995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1115876995
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.470949602
Short name T361
Test name
Test status
Simulation time 11736491284 ps
CPU time 9.73 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:41:59 PM PDT 24
Peak memory 200436 kb
Host smart-cd0bd3f0-c2f0-46e6-b689-c27377d254c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470949602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.470949602
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1138815164
Short name T747
Test name
Test status
Simulation time 50929097341 ps
CPU time 82.04 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:43:13 PM PDT 24
Peak memory 200324 kb
Host smart-069706e1-76b8-42b0-9c50-e6ad364cda37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138815164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1138815164
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3438673230
Short name T525
Test name
Test status
Simulation time 70566656932 ps
CPU time 58.05 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 200408 kb
Host smart-0c3eaa2f-ed1c-4a0a-a22d-519160190d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438673230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3438673230
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1085764213
Short name T381
Test name
Test status
Simulation time 85193270141 ps
CPU time 148.45 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:44:18 PM PDT 24
Peak memory 200128 kb
Host smart-7f7167d9-5903-4511-8328-7da40bc12083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085764213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1085764213
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2451799302
Short name T694
Test name
Test status
Simulation time 55159464373 ps
CPU time 42.58 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:42:33 PM PDT 24
Peak memory 200432 kb
Host smart-5be931f9-036f-44a4-a4b5-c05b688d9801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451799302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2451799302
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.409022740
Short name T967
Test name
Test status
Simulation time 36532308758 ps
CPU time 23.86 seconds
Started May 09 02:41:44 PM PDT 24
Finished May 09 02:42:12 PM PDT 24
Peak memory 200472 kb
Host smart-d33197d6-6829-4dda-bf15-94652e698dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409022740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.409022740
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3780007455
Short name T724
Test name
Test status
Simulation time 35709160057 ps
CPU time 122.96 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:43:51 PM PDT 24
Peak memory 200384 kb
Host smart-8ecb51bd-b57b-4042-917b-f5ee4f909713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780007455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3780007455
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3207876982
Short name T278
Test name
Test status
Simulation time 165830104502 ps
CPU time 25.15 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:42:13 PM PDT 24
Peak memory 200436 kb
Host smart-a2a38622-390b-4b0e-8108-2f1a750ef5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207876982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3207876982
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2792627932
Short name T482
Test name
Test status
Simulation time 23670551202 ps
CPU time 10.05 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:42:01 PM PDT 24
Peak memory 200424 kb
Host smart-ca71a78e-4b5d-4303-be9a-135b68af11c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792627932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2792627932
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3837535051
Short name T776
Test name
Test status
Simulation time 27256601 ps
CPU time 0.57 seconds
Started May 09 02:39:00 PM PDT 24
Finished May 09 02:39:01 PM PDT 24
Peak memory 195848 kb
Host smart-0ea85d33-0704-4cfc-975c-c7ba64ee2648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837535051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3837535051
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2924201368
Short name T766
Test name
Test status
Simulation time 38955899550 ps
CPU time 79.38 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:40:13 PM PDT 24
Peak memory 200412 kb
Host smart-55c0c71f-2005-4b60-b0dd-41c8a3594ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924201368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2924201368
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2720970061
Short name T1026
Test name
Test status
Simulation time 104581925029 ps
CPU time 172.67 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:41:46 PM PDT 24
Peak memory 200416 kb
Host smart-a83bf6e5-76f8-4cb7-bf7a-87ceeaf5bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720970061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2720970061
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4127571758
Short name T420
Test name
Test status
Simulation time 44155092865 ps
CPU time 20.43 seconds
Started May 09 02:38:50 PM PDT 24
Finished May 09 02:39:11 PM PDT 24
Peak memory 200476 kb
Host smart-2bf11d29-1db4-46bc-926f-e636c62c04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127571758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4127571758
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3995019631
Short name T736
Test name
Test status
Simulation time 52222939941 ps
CPU time 76.46 seconds
Started May 09 02:38:41 PM PDT 24
Finished May 09 02:39:59 PM PDT 24
Peak memory 199868 kb
Host smart-b3f090e4-b078-41aa-bf0a-4912cbcdf9cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995019631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3995019631
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2316816396
Short name T645
Test name
Test status
Simulation time 158252356171 ps
CPU time 445.48 seconds
Started May 09 02:39:03 PM PDT 24
Finished May 09 02:46:29 PM PDT 24
Peak memory 200444 kb
Host smart-b2a127e6-da1e-4890-aba5-28f1293f82f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316816396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2316816396
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2665992419
Short name T731
Test name
Test status
Simulation time 4530385737 ps
CPU time 7.08 seconds
Started May 09 02:38:59 PM PDT 24
Finished May 09 02:39:07 PM PDT 24
Peak memory 200004 kb
Host smart-8f17eca1-956e-4f1a-9518-aab0c07d0b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665992419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2665992419
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1778811492
Short name T497
Test name
Test status
Simulation time 24763947025 ps
CPU time 60 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:39:58 PM PDT 24
Peak memory 198740 kb
Host smart-f3f095a7-ae7b-45ae-89df-0f0019bc77ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778811492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1778811492
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.440465278
Short name T1029
Test name
Test status
Simulation time 19828657224 ps
CPU time 1069.91 seconds
Started May 09 02:38:56 PM PDT 24
Finished May 09 02:56:47 PM PDT 24
Peak memory 200444 kb
Host smart-c4fa458f-5660-4881-82f2-cf3b5e79de73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440465278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.440465278
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1480761077
Short name T738
Test name
Test status
Simulation time 6818571966 ps
CPU time 34.22 seconds
Started May 09 02:39:05 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 198552 kb
Host smart-f68f6ad9-03bc-4c89-8824-b4627e2abd60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480761077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1480761077
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3466478498
Short name T204
Test name
Test status
Simulation time 112464102364 ps
CPU time 235.3 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:42:49 PM PDT 24
Peak memory 200376 kb
Host smart-03b6f0c6-7840-43ad-b3bc-81dc8f206fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466478498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3466478498
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.922398916
Short name T450
Test name
Test status
Simulation time 2756681351 ps
CPU time 5.15 seconds
Started May 09 02:38:51 PM PDT 24
Finished May 09 02:38:57 PM PDT 24
Peak memory 196164 kb
Host smart-4701dd11-5c89-417e-9118-2f15f86a49bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922398916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.922398916
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3347987884
Short name T1106
Test name
Test status
Simulation time 652287017 ps
CPU time 1.73 seconds
Started May 09 02:39:05 PM PDT 24
Finished May 09 02:39:07 PM PDT 24
Peak memory 200392 kb
Host smart-6953d2d6-09b3-4dc7-845d-97349866192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347987884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3347987884
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.871551762
Short name T980
Test name
Test status
Simulation time 402883182330 ps
CPU time 382.06 seconds
Started May 09 02:38:54 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 217112 kb
Host smart-7a1398aa-4cc1-4735-8281-aa652f6cfde1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871551762 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.871551762
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.470063393
Short name T413
Test name
Test status
Simulation time 5670177040 ps
CPU time 1.42 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:38:55 PM PDT 24
Peak memory 199152 kb
Host smart-8106c0cc-2f03-4247-8d85-0c67d286be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470063393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.470063393
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1055494188
Short name T321
Test name
Test status
Simulation time 77727449036 ps
CPU time 129.92 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:41:03 PM PDT 24
Peak memory 200408 kb
Host smart-aa202e60-8b1f-47c5-9d55-7b2721887ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055494188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1055494188
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.428168294
Short name T227
Test name
Test status
Simulation time 8677665410 ps
CPU time 12.2 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:42:03 PM PDT 24
Peak memory 200428 kb
Host smart-04474459-e5d2-463c-a0f6-e740f0c717be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428168294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.428168294
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2881734450
Short name T225
Test name
Test status
Simulation time 232650921959 ps
CPU time 87.67 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:43:19 PM PDT 24
Peak memory 200508 kb
Host smart-06d4d95a-a59d-4c8e-a373-b325cd2fd09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881734450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2881734450
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2918954568
Short name T939
Test name
Test status
Simulation time 86337896804 ps
CPU time 60.08 seconds
Started May 09 02:41:48 PM PDT 24
Finished May 09 02:42:52 PM PDT 24
Peak memory 200428 kb
Host smart-77cbd801-7060-4de1-9a0d-39d5e43f4828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918954568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2918954568
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3066754429
Short name T245
Test name
Test status
Simulation time 14208837385 ps
CPU time 8.15 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:41:56 PM PDT 24
Peak memory 200476 kb
Host smart-7e4f7dce-8784-4d8e-8be6-f3380e4d3dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066754429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3066754429
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3205405687
Short name T521
Test name
Test status
Simulation time 64749425522 ps
CPU time 132.43 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:44:04 PM PDT 24
Peak memory 200464 kb
Host smart-d511a1ea-436e-48d9-a0d9-7a5ea68b1a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205405687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3205405687
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.366199671
Short name T119
Test name
Test status
Simulation time 42270789217 ps
CPU time 8.93 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:41:57 PM PDT 24
Peak memory 200456 kb
Host smart-fae5abf2-3fdf-4a0f-a391-e72359d7f19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366199671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.366199671
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.4209347308
Short name T288
Test name
Test status
Simulation time 31999917482 ps
CPU time 31.91 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:42:23 PM PDT 24
Peak memory 200460 kb
Host smart-9587c0aa-f241-44d1-93e0-96b2b7d6bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209347308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.4209347308
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1039672538
Short name T556
Test name
Test status
Simulation time 147389874574 ps
CPU time 63.21 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:42:54 PM PDT 24
Peak memory 200456 kb
Host smart-0d5029ae-4222-4ce6-bb0a-79af14bee71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039672538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1039672538
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.238299968
Short name T622
Test name
Test status
Simulation time 136929029211 ps
CPU time 194.46 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:45:04 PM PDT 24
Peak memory 200404 kb
Host smart-b889369f-6f59-4b38-9ffe-05faa2b1bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238299968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.238299968
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.844620881
Short name T230
Test name
Test status
Simulation time 89532145505 ps
CPU time 42.65 seconds
Started May 09 02:41:48 PM PDT 24
Finished May 09 02:42:35 PM PDT 24
Peak memory 200416 kb
Host smart-43c857f9-1298-41eb-98a1-460ca48e0203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844620881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.844620881
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1289867454
Short name T433
Test name
Test status
Simulation time 29977992 ps
CPU time 0.57 seconds
Started May 09 02:39:04 PM PDT 24
Finished May 09 02:39:05 PM PDT 24
Peak memory 195836 kb
Host smart-8361d42e-af39-4058-ac3e-0ef5978070e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289867454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1289867454
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2952186203
Short name T297
Test name
Test status
Simulation time 204416079872 ps
CPU time 212.06 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:42:41 PM PDT 24
Peak memory 200420 kb
Host smart-01e99b2e-8c86-48d8-8086-8a083b22a742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952186203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2952186203
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2692593558
Short name T686
Test name
Test status
Simulation time 24878517070 ps
CPU time 45.05 seconds
Started May 09 02:39:01 PM PDT 24
Finished May 09 02:39:47 PM PDT 24
Peak memory 200372 kb
Host smart-5d10f0df-13a1-4057-89ac-d65c71cb0761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692593558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2692593558
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.987052972
Short name T48
Test name
Test status
Simulation time 133375907852 ps
CPU time 32.34 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:39:30 PM PDT 24
Peak memory 200448 kb
Host smart-0bebd88c-6158-4979-baa3-24995ddd9970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987052972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.987052972
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2749617792
Short name T459
Test name
Test status
Simulation time 45465892073 ps
CPU time 18.47 seconds
Started May 09 02:39:13 PM PDT 24
Finished May 09 02:39:33 PM PDT 24
Peak memory 200472 kb
Host smart-34b42dcc-7df4-4baf-a466-a238470a3edb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749617792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2749617792
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3538505356
Short name T290
Test name
Test status
Simulation time 57131264640 ps
CPU time 152.28 seconds
Started May 09 02:39:04 PM PDT 24
Finished May 09 02:41:37 PM PDT 24
Peak memory 200400 kb
Host smart-2023fea3-9d8a-4a2a-ab09-7d0fb43b0347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538505356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3538505356
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1549794512
Short name T372
Test name
Test status
Simulation time 5385016841 ps
CPU time 10.79 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:39:04 PM PDT 24
Peak memory 199948 kb
Host smart-1f61113f-cdbc-4ae4-8c05-0f7cf46b736b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549794512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1549794512
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3022114724
Short name T679
Test name
Test status
Simulation time 75920475226 ps
CPU time 28.22 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:38 PM PDT 24
Peak memory 200580 kb
Host smart-bb82da12-ad6e-4af0-bde0-7796895b90a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022114724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3022114724
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1531199428
Short name T47
Test name
Test status
Simulation time 7808822139 ps
CPU time 106.68 seconds
Started May 09 02:38:51 PM PDT 24
Finished May 09 02:40:39 PM PDT 24
Peak memory 200308 kb
Host smart-ab0a1af2-8968-4266-8ef1-4f0ceb52da13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531199428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1531199428
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2445430709
Short name T730
Test name
Test status
Simulation time 1205386906 ps
CPU time 0.96 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:38:59 PM PDT 24
Peak memory 195884 kb
Host smart-a64ac365-92f1-4ebc-9af4-d6f2a3cae95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445430709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2445430709
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1204877155
Short name T1129
Test name
Test status
Simulation time 114818262855 ps
CPU time 172.69 seconds
Started May 09 02:38:59 PM PDT 24
Finished May 09 02:41:52 PM PDT 24
Peak memory 200412 kb
Host smart-da00ec36-df71-45a0-8e45-d738475035c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204877155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1204877155
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.787550046
Short name T412
Test name
Test status
Simulation time 1763527918 ps
CPU time 3.56 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:13 PM PDT 24
Peak memory 196084 kb
Host smart-e4e14cdf-8085-48f4-adf3-2c637f2f6cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787550046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.787550046
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1649921455
Short name T880
Test name
Test status
Simulation time 265920505 ps
CPU time 1.52 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:38:59 PM PDT 24
Peak memory 200284 kb
Host smart-f0d6faf2-826a-469e-8043-e01ab4c60d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649921455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1649921455
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1604575699
Short name T1005
Test name
Test status
Simulation time 112483770497 ps
CPU time 253.29 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 216800 kb
Host smart-e85da8c0-356c-40e8-b9ed-2d8e2a0431fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604575699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1604575699
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2326076589
Short name T1096
Test name
Test status
Simulation time 168431574571 ps
CPU time 175.92 seconds
Started May 09 02:38:59 PM PDT 24
Finished May 09 02:41:55 PM PDT 24
Peak memory 217108 kb
Host smart-f9de3274-6caa-416c-8755-c98d0b5d32db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326076589 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2326076589
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2130682961
Short name T1117
Test name
Test status
Simulation time 9066816147 ps
CPU time 10.06 seconds
Started May 09 02:39:12 PM PDT 24
Finished May 09 02:39:23 PM PDT 24
Peak memory 200292 kb
Host smart-f96198ba-b010-44bb-8103-baeeffa93f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130682961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2130682961
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2702035950
Short name T1060
Test name
Test status
Simulation time 23737404951 ps
CPU time 39.42 seconds
Started May 09 02:39:11 PM PDT 24
Finished May 09 02:39:51 PM PDT 24
Peak memory 200364 kb
Host smart-232459b0-6f94-4098-9691-959503a023d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702035950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2702035950
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.848077950
Short name T690
Test name
Test status
Simulation time 12989151624 ps
CPU time 21.85 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:42:13 PM PDT 24
Peak memory 200416 kb
Host smart-8dae2396-d88d-4e5c-8d32-e1e428cdaff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848077950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.848077950
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.825682868
Short name T216
Test name
Test status
Simulation time 29880093204 ps
CPU time 48.43 seconds
Started May 09 02:41:47 PM PDT 24
Finished May 09 02:42:40 PM PDT 24
Peak memory 200432 kb
Host smart-b68bd292-f15e-4f1d-a6b8-d6ded8d4aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825682868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.825682868
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.616703353
Short name T953
Test name
Test status
Simulation time 37882150511 ps
CPU time 19.41 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:42:08 PM PDT 24
Peak memory 200176 kb
Host smart-6d8b4389-d95c-46fb-be53-d3169f355c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616703353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.616703353
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.116636797
Short name T206
Test name
Test status
Simulation time 32430310574 ps
CPU time 15.4 seconds
Started May 09 02:41:46 PM PDT 24
Finished May 09 02:42:05 PM PDT 24
Peak memory 200444 kb
Host smart-ee010e15-17ae-4ee4-9141-087aa7a81dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116636797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.116636797
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1852961664
Short name T295
Test name
Test status
Simulation time 79241529234 ps
CPU time 88.36 seconds
Started May 09 02:41:45 PM PDT 24
Finished May 09 02:43:18 PM PDT 24
Peak memory 200460 kb
Host smart-e5c5357c-c19f-4339-b4d7-ecf7c6641b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852961664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1852961664
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2835252158
Short name T395
Test name
Test status
Simulation time 74936359890 ps
CPU time 116.82 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:43:57 PM PDT 24
Peak memory 200264 kb
Host smart-d74470aa-e507-48d2-8b98-937575015add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835252158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2835252158
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.903207759
Short name T911
Test name
Test status
Simulation time 163408121748 ps
CPU time 260.95 seconds
Started May 09 02:42:02 PM PDT 24
Finished May 09 02:46:26 PM PDT 24
Peak memory 200360 kb
Host smart-7782e17d-64e2-4971-81ca-630111c88ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903207759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.903207759
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3776140979
Short name T670
Test name
Test status
Simulation time 12660007 ps
CPU time 0.55 seconds
Started May 09 02:39:12 PM PDT 24
Finished May 09 02:39:13 PM PDT 24
Peak memory 194828 kb
Host smart-e7d86ff1-07f3-4327-9017-24878f5a9a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776140979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3776140979
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2444641032
Short name T1077
Test name
Test status
Simulation time 131838362640 ps
CPU time 109.53 seconds
Started May 09 02:39:12 PM PDT 24
Finished May 09 02:41:03 PM PDT 24
Peak memory 200408 kb
Host smart-d0169b04-e8ae-44f2-a1d7-7fe09a73f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444641032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2444641032
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3435033499
Short name T349
Test name
Test status
Simulation time 20162424461 ps
CPU time 19.64 seconds
Started May 09 02:39:02 PM PDT 24
Finished May 09 02:39:23 PM PDT 24
Peak memory 200200 kb
Host smart-dde3c8a4-3c1a-4e76-b29f-d90a6fb0535b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435033499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3435033499
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2799327681
Short name T213
Test name
Test status
Simulation time 42119944589 ps
CPU time 51.82 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:40:10 PM PDT 24
Peak memory 200452 kb
Host smart-2717f2f8-e816-4c9a-bff9-e487c1337b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799327681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2799327681
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2256427288
Short name T1167
Test name
Test status
Simulation time 36176469433 ps
CPU time 38.46 seconds
Started May 09 02:39:07 PM PDT 24
Finished May 09 02:39:46 PM PDT 24
Peak memory 200396 kb
Host smart-1e6fd645-bd6c-4803-b05a-9f6d67a432d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256427288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2256427288
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3777044934
Short name T985
Test name
Test status
Simulation time 65977572561 ps
CPU time 575.48 seconds
Started May 09 02:38:53 PM PDT 24
Finished May 09 02:48:34 PM PDT 24
Peak memory 200424 kb
Host smart-2ea2efb8-8850-430b-b5aa-9efd15f34091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777044934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3777044934
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1814349243
Short name T86
Test name
Test status
Simulation time 2332158914 ps
CPU time 3.59 seconds
Started May 09 02:39:05 PM PDT 24
Finished May 09 02:39:10 PM PDT 24
Peak memory 198824 kb
Host smart-88a9595a-2cfa-406e-9974-c527e15a6dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814349243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1814349243
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2527070133
Short name T333
Test name
Test status
Simulation time 12019020582 ps
CPU time 21.28 seconds
Started May 09 02:39:07 PM PDT 24
Finished May 09 02:39:29 PM PDT 24
Peak memory 198976 kb
Host smart-47b2e56f-ba97-4305-a8d4-f8a64fd65724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527070133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2527070133
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2627542085
Short name T987
Test name
Test status
Simulation time 22947880428 ps
CPU time 317.31 seconds
Started May 09 02:38:53 PM PDT 24
Finished May 09 02:44:12 PM PDT 24
Peak memory 200400 kb
Host smart-eab84c43-aea1-425a-b076-bbc487611f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627542085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2627542085
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1442767224
Short name T637
Test name
Test status
Simulation time 6943797745 ps
CPU time 7.25 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:16 PM PDT 24
Peak memory 199140 kb
Host smart-4c0ee6bd-0be4-404a-b9fc-9ca92da58664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442767224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1442767224
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1561233942
Short name T171
Test name
Test status
Simulation time 47287885168 ps
CPU time 20.29 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:39:18 PM PDT 24
Peak memory 200240 kb
Host smart-44c6ff3d-f360-49a0-b97a-efc81011b770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561233942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1561233942
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1145552450
Short name T1166
Test name
Test status
Simulation time 1326826161 ps
CPU time 2.9 seconds
Started May 09 02:39:03 PM PDT 24
Finished May 09 02:39:07 PM PDT 24
Peak memory 195792 kb
Host smart-d868d954-663a-437b-a691-a2f8338c9b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145552450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1145552450
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1264222391
Short name T778
Test name
Test status
Simulation time 468843676 ps
CPU time 2.45 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:38:55 PM PDT 24
Peak memory 199644 kb
Host smart-10cb0f8a-d8dd-44c2-9bbe-422b97ace8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264222391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1264222391
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3563692973
Short name T534
Test name
Test status
Simulation time 253890308218 ps
CPU time 2826.06 seconds
Started May 09 02:38:54 PM PDT 24
Finished May 09 03:26:01 PM PDT 24
Peak memory 200364 kb
Host smart-e9d9c83f-59fb-4e6d-9b19-260ec7a6358c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563692973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3563692973
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3197461050
Short name T356
Test name
Test status
Simulation time 50897627990 ps
CPU time 142.71 seconds
Started May 09 02:39:01 PM PDT 24
Finished May 09 02:41:25 PM PDT 24
Peak memory 212468 kb
Host smart-6c4042d4-49c4-4eb2-8437-8c5db1e126dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197461050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3197461050
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1629437581
Short name T341
Test name
Test status
Simulation time 362657907 ps
CPU time 1.3 seconds
Started May 09 02:38:58 PM PDT 24
Finished May 09 02:39:00 PM PDT 24
Peak memory 197664 kb
Host smart-ff5243c9-d720-44c1-aa97-f5862413b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629437581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1629437581
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1804256109
Short name T1061
Test name
Test status
Simulation time 72435863962 ps
CPU time 149.65 seconds
Started May 09 02:38:56 PM PDT 24
Finished May 09 02:41:27 PM PDT 24
Peak memory 200440 kb
Host smart-9cac0cdf-d39d-485d-ba51-b1f14d73fa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804256109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1804256109
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1566770085
Short name T1130
Test name
Test status
Simulation time 36440528572 ps
CPU time 17.23 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:17 PM PDT 24
Peak memory 200388 kb
Host smart-76f3decd-f877-44b9-8133-d67d6d448898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566770085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1566770085
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3612858930
Short name T979
Test name
Test status
Simulation time 67022489266 ps
CPU time 93.75 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 200416 kb
Host smart-965c18fb-32e1-4d89-9870-7c503895e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612858930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3612858930
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3691615763
Short name T175
Test name
Test status
Simulation time 77544443420 ps
CPU time 122.04 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:44:02 PM PDT 24
Peak memory 200488 kb
Host smart-4b0b9590-84e7-4963-9dbd-2fcce52749a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691615763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3691615763
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.229201621
Short name T1064
Test name
Test status
Simulation time 88212410673 ps
CPU time 31.22 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:31 PM PDT 24
Peak memory 200480 kb
Host smart-65cbf7a5-8680-4dc5-b4ed-fbe3aa7501fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229201621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.229201621
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1070412517
Short name T152
Test name
Test status
Simulation time 25467089722 ps
CPU time 46.6 seconds
Started May 09 02:41:57 PM PDT 24
Finished May 09 02:42:47 PM PDT 24
Peak memory 200408 kb
Host smart-ace7dead-d7ae-4ae0-8b15-0361c5bd4371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070412517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1070412517
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2765888249
Short name T187
Test name
Test status
Simulation time 61362352413 ps
CPU time 22.8 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:42:22 PM PDT 24
Peak memory 200412 kb
Host smart-c222fd04-03b3-4d8c-a8df-bcbc326ba352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765888249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2765888249
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4146254742
Short name T1123
Test name
Test status
Simulation time 34482625370 ps
CPU time 17.92 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:18 PM PDT 24
Peak memory 200456 kb
Host smart-e42fee13-cc59-4e5e-b1ee-f59edb94b7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146254742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4146254742
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1969583056
Short name T1067
Test name
Test status
Simulation time 47891154431 ps
CPU time 79.9 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:43:19 PM PDT 24
Peak memory 200360 kb
Host smart-c565f9ae-a9b8-42e6-81d0-cf8b33fd2b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969583056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1969583056
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.763899227
Short name T387
Test name
Test status
Simulation time 21509355 ps
CPU time 0.56 seconds
Started May 09 02:39:07 PM PDT 24
Finished May 09 02:39:09 PM PDT 24
Peak memory 195808 kb
Host smart-a37f1c47-a1e5-46bc-978a-24222bade1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763899227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.763899227
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.907369329
Short name T352
Test name
Test status
Simulation time 35380788279 ps
CPU time 58.48 seconds
Started May 09 02:38:52 PM PDT 24
Finished May 09 02:39:52 PM PDT 24
Peak memory 200396 kb
Host smart-783312dd-6e84-43ac-a307-d90092385b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907369329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.907369329
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.635104075
Short name T914
Test name
Test status
Simulation time 31793686766 ps
CPU time 13.65 seconds
Started May 09 02:38:56 PM PDT 24
Finished May 09 02:39:10 PM PDT 24
Peak memory 200472 kb
Host smart-28ae41ee-25c5-4dc6-9f51-f9c4c430b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635104075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.635104075
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3278635079
Short name T473
Test name
Test status
Simulation time 113375084203 ps
CPU time 132.81 seconds
Started May 09 02:39:11 PM PDT 24
Finished May 09 02:41:25 PM PDT 24
Peak memory 200460 kb
Host smart-20cb5052-0880-46b6-9477-aef3836d6ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278635079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3278635079
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1152588925
Short name T889
Test name
Test status
Simulation time 34992282728 ps
CPU time 66.7 seconds
Started May 09 02:38:56 PM PDT 24
Finished May 09 02:40:04 PM PDT 24
Peak memory 200432 kb
Host smart-9cc1f585-cc70-4090-8392-e688b8598db1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152588925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1152588925
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_loopback.3784911137
Short name T66
Test name
Test status
Simulation time 1440885730 ps
CPU time 4.02 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:39:02 PM PDT 24
Peak memory 198916 kb
Host smart-f2a28cde-fe2c-429a-8482-fabba060b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784911137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3784911137
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3607358724
Short name T794
Test name
Test status
Simulation time 25419892714 ps
CPU time 9.75 seconds
Started May 09 02:39:02 PM PDT 24
Finished May 09 02:39:13 PM PDT 24
Peak memory 195024 kb
Host smart-ce6638d6-d727-4783-9a91-e3edfd2a46d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607358724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3607358724
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4164308216
Short name T601
Test name
Test status
Simulation time 9810197909 ps
CPU time 545.65 seconds
Started May 09 02:39:04 PM PDT 24
Finished May 09 02:48:11 PM PDT 24
Peak memory 200432 kb
Host smart-5f307432-800d-4346-868b-34a30e7e33e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164308216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4164308216
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2110594997
Short name T88
Test name
Test status
Simulation time 4327782953 ps
CPU time 28.84 seconds
Started May 09 02:39:06 PM PDT 24
Finished May 09 02:39:35 PM PDT 24
Peak memory 199460 kb
Host smart-32f639c0-6fab-4e69-93f2-bdf134a975ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110594997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2110594997
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1789669721
Short name T826
Test name
Test status
Simulation time 37214875357 ps
CPU time 63.3 seconds
Started May 09 02:39:06 PM PDT 24
Finished May 09 02:40:10 PM PDT 24
Peak memory 200420 kb
Host smart-36106b83-ae96-403b-93b3-9ea771df6312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789669721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1789669721
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.148916497
Short name T1046
Test name
Test status
Simulation time 3559400529 ps
CPU time 3.3 seconds
Started May 09 02:39:14 PM PDT 24
Finished May 09 02:39:18 PM PDT 24
Peak memory 196756 kb
Host smart-ceab32e9-9811-433d-8cab-387f692d9f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148916497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.148916497
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1942031725
Short name T586
Test name
Test status
Simulation time 6057098001 ps
CPU time 25.42 seconds
Started May 09 02:38:53 PM PDT 24
Finished May 09 02:39:19 PM PDT 24
Peak memory 200412 kb
Host smart-72e9040c-ca2d-46f7-b025-2715733335be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942031725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1942031725
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2499028312
Short name T555
Test name
Test status
Simulation time 131384421701 ps
CPU time 243.41 seconds
Started May 09 02:38:57 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200412 kb
Host smart-4572f7a3-8c26-4cf4-b9fb-c9cf093748c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499028312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2499028312
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2644568786
Short name T1100
Test name
Test status
Simulation time 31181198299 ps
CPU time 149.77 seconds
Started May 09 02:39:13 PM PDT 24
Finished May 09 02:41:44 PM PDT 24
Peak memory 217096 kb
Host smart-da0ab43f-9e72-4855-96c9-55e7e0f690b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644568786 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2644568786
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3367567351
Short name T780
Test name
Test status
Simulation time 6136813701 ps
CPU time 13.63 seconds
Started May 09 02:38:54 PM PDT 24
Finished May 09 02:39:08 PM PDT 24
Peak memory 200300 kb
Host smart-5d60c811-4583-48b2-9bb7-2f7c422dd198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367567351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3367567351
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3678359951
Short name T549
Test name
Test status
Simulation time 214928283528 ps
CPU time 98.19 seconds
Started May 09 02:41:54 PM PDT 24
Finished May 09 02:43:37 PM PDT 24
Peak memory 200472 kb
Host smart-5a721989-f929-484e-8740-2e865fa6ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678359951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3678359951
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3506162609
Short name T455
Test name
Test status
Simulation time 17161086110 ps
CPU time 26.94 seconds
Started May 09 02:42:02 PM PDT 24
Finished May 09 02:42:32 PM PDT 24
Peak memory 200416 kb
Host smart-3b300006-9b03-46cc-b41a-75d94285f0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506162609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3506162609
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.86535293
Short name T1063
Test name
Test status
Simulation time 21744908296 ps
CPU time 58.51 seconds
Started May 09 02:41:58 PM PDT 24
Finished May 09 02:43:00 PM PDT 24
Peak memory 200420 kb
Host smart-fe07a349-e47a-4122-b8c8-4b15dc8e2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86535293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.86535293
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.4293934930
Short name T501
Test name
Test status
Simulation time 107092857065 ps
CPU time 661.42 seconds
Started May 09 02:41:57 PM PDT 24
Finished May 09 02:53:02 PM PDT 24
Peak memory 200440 kb
Host smart-37dde7c6-5402-41a6-9c28-ff81761a6bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293934930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4293934930
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1615927591
Short name T302
Test name
Test status
Simulation time 41337530230 ps
CPU time 21.85 seconds
Started May 09 02:42:02 PM PDT 24
Finished May 09 02:42:27 PM PDT 24
Peak memory 200392 kb
Host smart-bbb278e5-e10e-48ac-87d8-25836acc61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615927591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1615927591
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3874381847
Short name T532
Test name
Test status
Simulation time 132676090422 ps
CPU time 40.71 seconds
Started May 09 02:41:59 PM PDT 24
Finished May 09 02:42:43 PM PDT 24
Peak memory 200444 kb
Host smart-58bb01a7-2873-45fb-b649-527f177a5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874381847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3874381847
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3260254764
Short name T805
Test name
Test status
Simulation time 38753998544 ps
CPU time 15.84 seconds
Started May 09 02:41:59 PM PDT 24
Finished May 09 02:42:18 PM PDT 24
Peak memory 200448 kb
Host smart-3821df9a-0ace-4486-9c6e-d6ec7b035a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260254764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3260254764
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3723171363
Short name T406
Test name
Test status
Simulation time 33080604 ps
CPU time 0.56 seconds
Started May 09 02:39:19 PM PDT 24
Finished May 09 02:39:20 PM PDT 24
Peak memory 195800 kb
Host smart-e2b0be5a-098b-4a4b-a7c6-e6913c57e5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723171363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3723171363
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.47057930
Short name T393
Test name
Test status
Simulation time 41416050973 ps
CPU time 65.11 seconds
Started May 09 02:38:54 PM PDT 24
Finished May 09 02:40:00 PM PDT 24
Peak memory 200448 kb
Host smart-59a221e3-0417-4488-b4cb-9a77f9dbe92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47057930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.47057930
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1039280403
Short name T517
Test name
Test status
Simulation time 115647680454 ps
CPU time 189.84 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:42:19 PM PDT 24
Peak memory 200372 kb
Host smart-436fbd20-2dd0-4b21-876f-2aa9f06627a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039280403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1039280403
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1284021545
Short name T523
Test name
Test status
Simulation time 90569181473 ps
CPU time 42.39 seconds
Started May 09 02:39:01 PM PDT 24
Finished May 09 02:39:44 PM PDT 24
Peak memory 200408 kb
Host smart-e8c8ac04-1eb2-4b3c-b692-79e1c9460778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284021545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1284021545
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.381969037
Short name T103
Test name
Test status
Simulation time 32808835981 ps
CPU time 58.82 seconds
Started May 09 02:39:07 PM PDT 24
Finished May 09 02:40:07 PM PDT 24
Peak memory 200444 kb
Host smart-2add851d-b4d4-4759-89d7-276f4e1c1f14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381969037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.381969037
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1739655674
Short name T783
Test name
Test status
Simulation time 64514825536 ps
CPU time 538.65 seconds
Started May 09 02:39:14 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 200412 kb
Host smart-163eaa21-385c-414a-aaeb-9c05e1c2794f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739655674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1739655674
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1531999044
Short name T446
Test name
Test status
Simulation time 5066346928 ps
CPU time 2.92 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:21 PM PDT 24
Peak memory 195996 kb
Host smart-0f4f6c52-8513-49d7-ba3b-abb68c3c3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531999044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1531999044
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3992735971
Short name T960
Test name
Test status
Simulation time 246367139338 ps
CPU time 62.35 seconds
Started May 09 02:39:09 PM PDT 24
Finished May 09 02:40:13 PM PDT 24
Peak memory 216896 kb
Host smart-4dc5e790-410b-4eda-8cfb-2055b3011862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992735971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3992735971
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3515259154
Short name T11
Test name
Test status
Simulation time 21208928513 ps
CPU time 221.16 seconds
Started May 09 02:39:06 PM PDT 24
Finished May 09 02:42:48 PM PDT 24
Peak memory 200420 kb
Host smart-4ae2c13c-1e55-4019-b1d3-0344727eaad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515259154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3515259154
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.798960745
Short name T403
Test name
Test status
Simulation time 6448236001 ps
CPU time 16.9 seconds
Started May 09 02:38:54 PM PDT 24
Finished May 09 02:39:12 PM PDT 24
Peak memory 199276 kb
Host smart-0adfe88e-0e28-44a6-bf15-cff3039b17d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798960745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.798960745
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2879761668
Short name T82
Test name
Test status
Simulation time 13657023661 ps
CPU time 24.05 seconds
Started May 09 02:39:13 PM PDT 24
Finished May 09 02:39:38 PM PDT 24
Peak memory 199664 kb
Host smart-d222e6e7-8c32-44f9-b565-3ca655c97167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879761668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2879761668
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.770329812
Short name T339
Test name
Test status
Simulation time 42195995171 ps
CPU time 10.48 seconds
Started May 09 02:39:03 PM PDT 24
Finished May 09 02:39:14 PM PDT 24
Peak memory 196644 kb
Host smart-a3b1b6c5-c184-4087-afcd-1c7fa82988fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770329812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.770329812
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3136498193
Short name T345
Test name
Test status
Simulation time 777288852 ps
CPU time 1.38 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:39:19 PM PDT 24
Peak memory 200064 kb
Host smart-b10e2af1-9d2b-4ee7-826d-bef5f004395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136498193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3136498193
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.757230069
Short name T934
Test name
Test status
Simulation time 422968756 ps
CPU time 1.49 seconds
Started May 09 02:39:13 PM PDT 24
Finished May 09 02:39:15 PM PDT 24
Peak memory 197408 kb
Host smart-cd3eecf4-1c15-41f5-b6f2-2150d0a3bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757230069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.757230069
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.823966501
Short name T614
Test name
Test status
Simulation time 47418494319 ps
CPU time 69.71 seconds
Started May 09 02:39:05 PM PDT 24
Finished May 09 02:40:15 PM PDT 24
Peak memory 200452 kb
Host smart-83efae47-d442-46d0-9ae0-94c397ee5080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823966501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.823966501
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3607985368
Short name T771
Test name
Test status
Simulation time 38367665396 ps
CPU time 33.22 seconds
Started May 09 02:41:57 PM PDT 24
Finished May 09 02:42:34 PM PDT 24
Peak memory 200344 kb
Host smart-e116ec18-f051-4121-959e-b2fe3fd1c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607985368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3607985368
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1874488332
Short name T908
Test name
Test status
Simulation time 12102556953 ps
CPU time 17.96 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:18 PM PDT 24
Peak memory 200436 kb
Host smart-7303d04b-9ac7-4beb-9923-74547b3fa4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874488332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1874488332
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2984189524
Short name T231
Test name
Test status
Simulation time 40049054129 ps
CPU time 14.8 seconds
Started May 09 02:41:59 PM PDT 24
Finished May 09 02:42:17 PM PDT 24
Peak memory 200388 kb
Host smart-3bc93e62-8155-4b9d-a85f-48a01cfa3123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984189524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2984189524
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1860326980
Short name T1002
Test name
Test status
Simulation time 14161767763 ps
CPU time 25.61 seconds
Started May 09 02:41:56 PM PDT 24
Finished May 09 02:42:26 PM PDT 24
Peak memory 200432 kb
Host smart-458d7094-ab99-4d5a-8ba0-bbdee73eea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860326980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1860326980
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1583782489
Short name T969
Test name
Test status
Simulation time 21061332821 ps
CPU time 42.68 seconds
Started May 09 02:41:54 PM PDT 24
Finished May 09 02:42:41 PM PDT 24
Peak memory 200488 kb
Host smart-c12a0243-724b-4f63-92bb-131692847cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583782489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1583782489
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2702509531
Short name T735
Test name
Test status
Simulation time 107541176279 ps
CPU time 181.51 seconds
Started May 09 02:41:55 PM PDT 24
Finished May 09 02:45:01 PM PDT 24
Peak memory 200448 kb
Host smart-500d6047-af21-437f-acf9-c99184118774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702509531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2702509531
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.207307176
Short name T719
Test name
Test status
Simulation time 57902664964 ps
CPU time 90.87 seconds
Started May 09 02:41:58 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 200460 kb
Host smart-9b0c4caf-febd-4505-8dee-9487c513888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207307176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.207307176
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2301993339
Short name T376
Test name
Test status
Simulation time 11997900 ps
CPU time 0.58 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:39:11 PM PDT 24
Peak memory 194864 kb
Host smart-d38c8a47-0cd9-4008-9b28-d3a988b6bac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301993339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2301993339
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1138357707
Short name T1108
Test name
Test status
Simulation time 85576094449 ps
CPU time 148.56 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:41:40 PM PDT 24
Peak memory 200460 kb
Host smart-18552653-60ca-4113-9185-c11f5c6a6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138357707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1138357707
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.337094789
Short name T199
Test name
Test status
Simulation time 59958807797 ps
CPU time 15.71 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:34 PM PDT 24
Peak memory 199816 kb
Host smart-5e07b8d4-45fc-491a-b25b-5f7a17808f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337094789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.337094789
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.897438186
Short name T478
Test name
Test status
Simulation time 44724204351 ps
CPU time 19.47 seconds
Started May 09 02:39:04 PM PDT 24
Finished May 09 02:39:24 PM PDT 24
Peak memory 200472 kb
Host smart-6f665f67-c116-4fb9-9fba-2bb59b9d5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897438186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.897438186
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2399380234
Short name T1066
Test name
Test status
Simulation time 17509815765 ps
CPU time 15.59 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:25 PM PDT 24
Peak memory 199752 kb
Host smart-68b2d75b-5479-444b-bc4f-b2a5d1dcbc61
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399380234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2399380234
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2273614354
Short name T858
Test name
Test status
Simulation time 48592901556 ps
CPU time 200.55 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:42:32 PM PDT 24
Peak memory 200220 kb
Host smart-6c5a2f10-e34a-4290-bfde-f5a98bde7d85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273614354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2273614354
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.845569480
Short name T436
Test name
Test status
Simulation time 4698126723 ps
CPU time 4.75 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:39:16 PM PDT 24
Peak memory 200168 kb
Host smart-8f57c6d7-4e07-482f-b79d-d1c78651c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845569480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.845569480
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.954852145
Short name T1024
Test name
Test status
Simulation time 38320067048 ps
CPU time 21.62 seconds
Started May 09 02:39:19 PM PDT 24
Finished May 09 02:39:42 PM PDT 24
Peak memory 195084 kb
Host smart-1350177e-a673-47e5-b6e9-57075b2dcf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954852145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.954852145
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1225050198
Short name T784
Test name
Test status
Simulation time 8895953367 ps
CPU time 120.05 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:41:18 PM PDT 24
Peak memory 200424 kb
Host smart-b44db6ec-f34d-4f5b-ab54-25ab43b9c126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225050198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1225050198
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3234798914
Short name T438
Test name
Test status
Simulation time 5362741361 ps
CPU time 15.76 seconds
Started May 09 02:39:09 PM PDT 24
Finished May 09 02:39:26 PM PDT 24
Peak memory 198572 kb
Host smart-48ed90f9-6bba-4421-b2b0-f4d82d015bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234798914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3234798914
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2540181837
Short name T1065
Test name
Test status
Simulation time 78634961040 ps
CPU time 143.75 seconds
Started May 09 02:39:11 PM PDT 24
Finished May 09 02:41:36 PM PDT 24
Peak memory 200380 kb
Host smart-4f467acf-7141-486a-890f-add3cf74fbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540181837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2540181837
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4204828437
Short name T562
Test name
Test status
Simulation time 44013545054 ps
CPU time 19.94 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:30 PM PDT 24
Peak memory 196464 kb
Host smart-05cfa2c9-1f0e-4eb6-9410-d5c49fa9a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204828437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4204828437
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2458831556
Short name T1075
Test name
Test status
Simulation time 730641529 ps
CPU time 1.9 seconds
Started May 09 02:39:11 PM PDT 24
Finished May 09 02:39:14 PM PDT 24
Peak memory 199084 kb
Host smart-7341372e-fa46-4bff-b6fe-da0312af9ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458831556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2458831556
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2665345148
Short name T629
Test name
Test status
Simulation time 123101738105 ps
CPU time 1106.17 seconds
Started May 09 02:39:04 PM PDT 24
Finished May 09 02:57:31 PM PDT 24
Peak memory 200356 kb
Host smart-e2265498-436f-400e-b045-9c1036d7bce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665345148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2665345148
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1975978985
Short name T723
Test name
Test status
Simulation time 13020997779 ps
CPU time 6.23 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:39:18 PM PDT 24
Peak memory 200416 kb
Host smart-33e09331-443b-4c4a-82a7-da7b8c97b797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975978985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1975978985
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1537197574
Short name T851
Test name
Test status
Simulation time 9209177598 ps
CPU time 7.96 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:39:19 PM PDT 24
Peak memory 197452 kb
Host smart-bc2cdc9a-47b7-425f-b7d5-3d20101920ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537197574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1537197574
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3131032852
Short name T1098
Test name
Test status
Simulation time 17269826923 ps
CPU time 18.69 seconds
Started May 09 02:41:57 PM PDT 24
Finished May 09 02:42:19 PM PDT 24
Peak memory 200348 kb
Host smart-79b0c6dd-6150-4560-a96b-c5dd57ac9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131032852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3131032852
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2338432658
Short name T904
Test name
Test status
Simulation time 40483807664 ps
CPU time 58.72 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:43:07 PM PDT 24
Peak memory 200412 kb
Host smart-e6c1d08f-1c60-4fe4-bfba-4722e439e9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338432658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2338432658
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1570051235
Short name T248
Test name
Test status
Simulation time 19821113257 ps
CPU time 37.57 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 200436 kb
Host smart-f74c5df0-3a6b-4721-9364-b834b8f3959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570051235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1570051235
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.542909643
Short name T711
Test name
Test status
Simulation time 59947754885 ps
CPU time 49.91 seconds
Started May 09 02:42:06 PM PDT 24
Finished May 09 02:42:57 PM PDT 24
Peak memory 200472 kb
Host smart-bcdfbb52-e60d-4793-b830-97515c357e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542909643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.542909643
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1052841263
Short name T263
Test name
Test status
Simulation time 22018459438 ps
CPU time 52 seconds
Started May 09 02:42:08 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200396 kb
Host smart-5dd791ac-c8a4-47c5-92da-ffbc8600e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052841263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1052841263
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.588769416
Short name T474
Test name
Test status
Simulation time 79486033878 ps
CPU time 115.54 seconds
Started May 09 02:42:06 PM PDT 24
Finished May 09 02:44:03 PM PDT 24
Peak memory 200228 kb
Host smart-2cd9af28-721a-4ffb-8930-4a20bad01107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588769416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.588769416
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1315471284
Short name T1150
Test name
Test status
Simulation time 95228119868 ps
CPU time 82.86 seconds
Started May 09 02:42:10 PM PDT 24
Finished May 09 02:43:34 PM PDT 24
Peak memory 200348 kb
Host smart-d90e603b-67d3-4756-b972-9fb7ae0b48ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315471284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1315471284
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3960729026
Short name T149
Test name
Test status
Simulation time 40395778167 ps
CPU time 10.68 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:42:19 PM PDT 24
Peak memory 200464 kb
Host smart-6764aaaf-56a2-4f49-b4ec-43840ef4d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960729026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3960729026
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.922083314
Short name T223
Test name
Test status
Simulation time 18320966941 ps
CPU time 33.61 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:42:42 PM PDT 24
Peak memory 200396 kb
Host smart-9ccf5a18-00c7-4f62-943a-33e14277b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922083314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.922083314
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1553706020
Short name T431
Test name
Test status
Simulation time 20653176 ps
CPU time 0.58 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:38:09 PM PDT 24
Peak memory 195800 kb
Host smart-e7762dc0-24b7-4e84-8bca-8f26bd83ee0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553706020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1553706020
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2119230643
Short name T925
Test name
Test status
Simulation time 45142696358 ps
CPU time 19.17 seconds
Started May 09 02:38:12 PM PDT 24
Finished May 09 02:38:37 PM PDT 24
Peak memory 200428 kb
Host smart-2ecaefb4-e289-4da3-a2a4-ca992fb17ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119230643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2119230643
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1274016454
Short name T342
Test name
Test status
Simulation time 56388701864 ps
CPU time 31.07 seconds
Started May 09 02:38:22 PM PDT 24
Finished May 09 02:38:54 PM PDT 24
Peak memory 200448 kb
Host smart-3405889b-b5d1-4fc2-9d4e-c3de4c8fc45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274016454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1274016454
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4018635873
Short name T217
Test name
Test status
Simulation time 111991511090 ps
CPU time 189.34 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:41:18 PM PDT 24
Peak memory 200340 kb
Host smart-abef8b4d-f498-40c0-b767-21eb824274d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018635873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4018635873
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3732939295
Short name T722
Test name
Test status
Simulation time 27488175215 ps
CPU time 15.44 seconds
Started May 09 02:38:16 PM PDT 24
Finished May 09 02:38:32 PM PDT 24
Peak memory 199832 kb
Host smart-c1829b54-a0d6-49d4-8f26-e7ab0ed4ee23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732939295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3732939295
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.138384018
Short name T422
Test name
Test status
Simulation time 62120539095 ps
CPU time 358.7 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:44:25 PM PDT 24
Peak memory 200432 kb
Host smart-e4d12023-d808-493d-b3cf-98ccfa2366d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138384018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.138384018
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.764865888
Short name T1147
Test name
Test status
Simulation time 6730203015 ps
CPU time 13.74 seconds
Started May 09 02:38:15 PM PDT 24
Finished May 09 02:38:29 PM PDT 24
Peak memory 200424 kb
Host smart-7c9d3829-8f85-449c-9d50-0ba504ebd308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764865888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.764865888
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.472555854
Short name T635
Test name
Test status
Simulation time 75669069632 ps
CPU time 69.04 seconds
Started May 09 02:38:15 PM PDT 24
Finished May 09 02:39:25 PM PDT 24
Peak memory 199916 kb
Host smart-dc475cf9-3317-4b4f-9127-ce532face50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472555854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.472555854
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4016384160
Short name T986
Test name
Test status
Simulation time 25473273209 ps
CPU time 259.37 seconds
Started May 09 02:38:07 PM PDT 24
Finished May 09 02:42:27 PM PDT 24
Peak memory 200424 kb
Host smart-93a50499-d293-4f20-be39-3a9c1ed3b6f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016384160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4016384160
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.4280798488
Short name T998
Test name
Test status
Simulation time 3396905002 ps
CPU time 25.78 seconds
Started May 09 02:38:11 PM PDT 24
Finished May 09 02:38:38 PM PDT 24
Peak memory 198872 kb
Host smart-a8f185ee-c377-4ece-aece-10d306a3fd05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280798488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4280798488
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2414022961
Short name T547
Test name
Test status
Simulation time 46365883152 ps
CPU time 75.57 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:39:20 PM PDT 24
Peak memory 200604 kb
Host smart-422dfe7c-df0c-45f7-ab77-860d364bf80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414022961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2414022961
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2036876832
Short name T524
Test name
Test status
Simulation time 6333752100 ps
CPU time 5.72 seconds
Started May 09 02:38:03 PM PDT 24
Finished May 09 02:38:10 PM PDT 24
Peak memory 196756 kb
Host smart-2374ebdb-11a1-4954-a8e5-9b29bff625db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036876832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2036876832
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.479041350
Short name T29
Test name
Test status
Simulation time 577971676 ps
CPU time 0.85 seconds
Started May 09 02:38:12 PM PDT 24
Finished May 09 02:38:14 PM PDT 24
Peak memory 218800 kb
Host smart-af5b26f3-9fdd-4917-a032-019dbec75109
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479041350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.479041350
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1412874333
Short name T591
Test name
Test status
Simulation time 880206914 ps
CPU time 3.27 seconds
Started May 09 02:38:06 PM PDT 24
Finished May 09 02:38:10 PM PDT 24
Peak memory 200304 kb
Host smart-42bfc7d4-a585-4439-b1ac-d9eaa9874adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412874333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1412874333
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.53122096
Short name T492
Test name
Test status
Simulation time 126543213265 ps
CPU time 110.36 seconds
Started May 09 02:38:20 PM PDT 24
Finished May 09 02:40:12 PM PDT 24
Peak memory 217012 kb
Host smart-7fc75b7a-432e-4278-93c2-308d057f57e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53122096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.53122096
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2702278160
Short name T954
Test name
Test status
Simulation time 257275720943 ps
CPU time 653.06 seconds
Started May 09 02:38:02 PM PDT 24
Finished May 09 02:48:56 PM PDT 24
Peak memory 216796 kb
Host smart-6270f7f9-65b1-45f1-965f-ebcb26ade3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702278160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2702278160
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.214158566
Short name T902
Test name
Test status
Simulation time 1150065782 ps
CPU time 2.28 seconds
Started May 09 02:38:16 PM PDT 24
Finished May 09 02:38:19 PM PDT 24
Peak memory 199168 kb
Host smart-029ad2b7-5ef6-4358-9e3e-3beb03fe7c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214158566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.214158566
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.671245357
Short name T470
Test name
Test status
Simulation time 23549883119 ps
CPU time 10.05 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:38:19 PM PDT 24
Peak memory 200396 kb
Host smart-ae3846bd-3cbd-4a80-a1f9-1f65bd4cd2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671245357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.671245357
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3706419824
Short name T988
Test name
Test status
Simulation time 44497130 ps
CPU time 0.59 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:19 PM PDT 24
Peak memory 195820 kb
Host smart-7d237abf-56d5-4a6b-b35e-39d1a3632892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706419824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3706419824
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3579030608
Short name T448
Test name
Test status
Simulation time 85097147489 ps
CPU time 38.19 seconds
Started May 09 02:39:04 PM PDT 24
Finished May 09 02:39:43 PM PDT 24
Peak memory 200364 kb
Host smart-459a2c3f-38bd-4735-8f78-e4e17ec6fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579030608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3579030608
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3924678484
Short name T427
Test name
Test status
Simulation time 115833575996 ps
CPU time 121.73 seconds
Started May 09 02:39:12 PM PDT 24
Finished May 09 02:41:15 PM PDT 24
Peak memory 200240 kb
Host smart-36d2dea7-1793-4339-ac8d-39a99ae68415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924678484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3924678484
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1589859112
Short name T1101
Test name
Test status
Simulation time 53389362937 ps
CPU time 72.81 seconds
Started May 09 02:39:05 PM PDT 24
Finished May 09 02:40:19 PM PDT 24
Peak memory 200368 kb
Host smart-570d5ee7-3aa2-4a9a-8c28-512702d3d9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589859112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1589859112
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.4112662211
Short name T806
Test name
Test status
Simulation time 53723785511 ps
CPU time 99.56 seconds
Started May 09 02:39:03 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 200484 kb
Host smart-1eb31dd6-1588-416a-b05a-7d9a501bf851
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112662211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4112662211
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.140703586
Short name T384
Test name
Test status
Simulation time 100882135563 ps
CPU time 836.25 seconds
Started May 09 02:39:09 PM PDT 24
Finished May 09 02:53:06 PM PDT 24
Peak memory 200456 kb
Host smart-507a9f63-4142-41b9-adc9-e7930c264acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140703586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.140703586
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2302318458
Short name T1134
Test name
Test status
Simulation time 11857877965 ps
CPU time 9.81 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:19 PM PDT 24
Peak memory 200420 kb
Host smart-ae9679b6-c0bf-4186-887a-507dc1d76d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302318458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2302318458
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2127117707
Short name T483
Test name
Test status
Simulation time 28633865170 ps
CPU time 27.24 seconds
Started May 09 02:39:09 PM PDT 24
Finished May 09 02:39:37 PM PDT 24
Peak memory 199704 kb
Host smart-87f6ebfa-c577-4b39-b896-e3d22ffb7681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127117707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2127117707
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4292512268
Short name T833
Test name
Test status
Simulation time 14979759071 ps
CPU time 178.81 seconds
Started May 09 02:39:06 PM PDT 24
Finished May 09 02:42:06 PM PDT 24
Peak memory 200468 kb
Host smart-efcec0eb-882b-4c1b-95a7-85c3e8eee913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292512268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4292512268
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2378959187
Short name T548
Test name
Test status
Simulation time 6444181376 ps
CPU time 29.88 seconds
Started May 09 02:39:10 PM PDT 24
Finished May 09 02:39:41 PM PDT 24
Peak memory 199172 kb
Host smart-4ed1daf8-eeb9-4628-b952-53b51239bd34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378959187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2378959187
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2698365223
Short name T300
Test name
Test status
Simulation time 66506864010 ps
CPU time 8.11 seconds
Started May 09 02:39:18 PM PDT 24
Finished May 09 02:39:27 PM PDT 24
Peak memory 200456 kb
Host smart-4639edf0-441a-4eba-b969-b1535825db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698365223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2698365223
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3471558973
Short name T1139
Test name
Test status
Simulation time 1817171843 ps
CPU time 1.47 seconds
Started May 09 02:39:22 PM PDT 24
Finished May 09 02:39:25 PM PDT 24
Peak memory 196124 kb
Host smart-167b8fbf-8591-4de9-b53f-2b019c30c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471558973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3471558973
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3530040601
Short name T923
Test name
Test status
Simulation time 534031755 ps
CPU time 2.02 seconds
Started May 09 02:39:15 PM PDT 24
Finished May 09 02:39:18 PM PDT 24
Peak memory 200312 kb
Host smart-5d556f0f-253f-4b85-b724-b76743692a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530040601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3530040601
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.4278476051
Short name T968
Test name
Test status
Simulation time 247518836712 ps
CPU time 781.69 seconds
Started May 09 02:39:23 PM PDT 24
Finished May 09 02:52:26 PM PDT 24
Peak memory 200408 kb
Host smart-d0e22a8c-4231-40ca-af0f-60bc2c94dbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278476051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4278476051
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.674092276
Short name T613
Test name
Test status
Simulation time 25370304590 ps
CPU time 343.58 seconds
Started May 09 02:39:09 PM PDT 24
Finished May 09 02:44:54 PM PDT 24
Peak memory 217168 kb
Host smart-6ed3bd4f-3e22-4429-a436-bbc1c1e909f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674092276 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.674092276
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.838971632
Short name T684
Test name
Test status
Simulation time 1272962343 ps
CPU time 5.53 seconds
Started May 09 02:39:21 PM PDT 24
Finished May 09 02:39:27 PM PDT 24
Peak memory 199228 kb
Host smart-e5884068-62e8-4330-8431-af75993f09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838971632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.838971632
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.696870502
Short name T34
Test name
Test status
Simulation time 42520897411 ps
CPU time 17.91 seconds
Started May 09 02:39:08 PM PDT 24
Finished May 09 02:39:27 PM PDT 24
Peak memory 200436 kb
Host smart-ae3d93fa-fa15-45ca-9360-0d89af2e9ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696870502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.696870502
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3273702254
Short name T257
Test name
Test status
Simulation time 157792928722 ps
CPU time 94.57 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:43:43 PM PDT 24
Peak memory 200396 kb
Host smart-ee31fa0a-b348-4eae-993a-2f04257efea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273702254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3273702254
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4012780198
Short name T229
Test name
Test status
Simulation time 13502275777 ps
CPU time 22.88 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:42:32 PM PDT 24
Peak memory 200396 kb
Host smart-7b08fe9d-02f4-402a-813b-1c5521d2ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012780198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4012780198
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.666817699
Short name T276
Test name
Test status
Simulation time 79675550213 ps
CPU time 43.92 seconds
Started May 09 02:42:05 PM PDT 24
Finished May 09 02:42:51 PM PDT 24
Peak memory 200412 kb
Host smart-870a2a06-60db-4df8-8004-24795e4f9a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666817699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.666817699
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.361488628
Short name T695
Test name
Test status
Simulation time 34643283614 ps
CPU time 29.38 seconds
Started May 09 02:42:10 PM PDT 24
Finished May 09 02:42:41 PM PDT 24
Peak memory 200392 kb
Host smart-33201ee1-2d0d-40e7-a18e-5f6a3b3bde40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361488628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.361488628
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1903371506
Short name T910
Test name
Test status
Simulation time 212034466502 ps
CPU time 310.53 seconds
Started May 09 02:42:09 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 200188 kb
Host smart-80f04fde-c40a-43f5-8c51-4cabc4a43ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903371506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1903371506
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.779408689
Short name T641
Test name
Test status
Simulation time 100958897159 ps
CPU time 35.03 seconds
Started May 09 02:42:06 PM PDT 24
Finished May 09 02:42:42 PM PDT 24
Peak memory 200276 kb
Host smart-f22e9eea-1125-452d-85a2-9ec1889ec830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779408689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.779408689
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3621535717
Short name T287
Test name
Test status
Simulation time 81530954347 ps
CPU time 279.93 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:46:49 PM PDT 24
Peak memory 200472 kb
Host smart-2c55d35c-a647-442b-a553-096a2e34f8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621535717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3621535717
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.353225468
Short name T726
Test name
Test status
Simulation time 21718643766 ps
CPU time 10.29 seconds
Started May 09 02:42:08 PM PDT 24
Finished May 09 02:42:20 PM PDT 24
Peak memory 199256 kb
Host smart-1d122521-decc-461c-983f-73fec7ab037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353225468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.353225468
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1221839357
Short name T628
Test name
Test status
Simulation time 56801142 ps
CPU time 0.6 seconds
Started May 09 02:39:15 PM PDT 24
Finished May 09 02:39:16 PM PDT 24
Peak memory 195240 kb
Host smart-0b612f6e-1703-4c96-91ac-c9fbce64acbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221839357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1221839357
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3787491918
Short name T462
Test name
Test status
Simulation time 124346917819 ps
CPU time 332.07 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:45:00 PM PDT 24
Peak memory 200200 kb
Host smart-5929ed14-8f8e-43e8-80ac-28a9f8a7ebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787491918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3787491918
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1301563361
Short name T1178
Test name
Test status
Simulation time 54837313423 ps
CPU time 8.84 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:28 PM PDT 24
Peak memory 200440 kb
Host smart-9429f049-5864-4da1-bd69-2a5e84056b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301563361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1301563361
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4116629857
Short name T1177
Test name
Test status
Simulation time 69696153289 ps
CPU time 31.04 seconds
Started May 09 02:39:22 PM PDT 24
Finished May 09 02:39:54 PM PDT 24
Peak memory 200404 kb
Host smart-2a3a0215-107a-457d-8e6b-56a1c548d67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116629857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4116629857
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.669041020
Short name T970
Test name
Test status
Simulation time 49851050243 ps
CPU time 25.51 seconds
Started May 09 02:39:24 PM PDT 24
Finished May 09 02:39:50 PM PDT 24
Peak memory 200224 kb
Host smart-f774b3be-bd57-450e-8585-e1df878cdc11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669041020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.669041020
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.267283184
Short name T541
Test name
Test status
Simulation time 147541562494 ps
CPU time 185.05 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:42:31 PM PDT 24
Peak memory 200416 kb
Host smart-dd325f2c-32a6-4835-8ffe-2e5f56bec3d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267283184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.267283184
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3318369585
Short name T693
Test name
Test status
Simulation time 11535348179 ps
CPU time 7.13 seconds
Started May 09 02:39:18 PM PDT 24
Finished May 09 02:39:26 PM PDT 24
Peak memory 199152 kb
Host smart-5c1b087a-6c23-4299-8f70-3714ca92ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318369585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3318369585
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3944971945
Short name T671
Test name
Test status
Simulation time 2203874777 ps
CPU time 1.25 seconds
Started May 09 02:39:20 PM PDT 24
Finished May 09 02:39:22 PM PDT 24
Peak memory 196480 kb
Host smart-85a55947-5850-47b6-8485-1f06b5d4245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944971945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3944971945
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1332409883
Short name T849
Test name
Test status
Simulation time 7889072070 ps
CPU time 162.82 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:42:12 PM PDT 24
Peak memory 200420 kb
Host smart-2bf02610-511c-432e-ba8b-9a7251bf72c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332409883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1332409883
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3052482604
Short name T837
Test name
Test status
Simulation time 3665398317 ps
CPU time 6.51 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:39:35 PM PDT 24
Peak memory 198720 kb
Host smart-d9fb6ca7-3739-46ad-8ad8-921415e1cc58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052482604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3052482604
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.484718914
Short name T1132
Test name
Test status
Simulation time 36335474917 ps
CPU time 29.67 seconds
Started May 09 02:39:21 PM PDT 24
Finished May 09 02:39:52 PM PDT 24
Peak memory 196784 kb
Host smart-4c28cfb2-fb7e-4b09-afaa-af4f4b437153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484718914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.484718914
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3585310638
Short name T714
Test name
Test status
Simulation time 742544123 ps
CPU time 1.35 seconds
Started May 09 02:39:19 PM PDT 24
Finished May 09 02:39:22 PM PDT 24
Peak memory 198616 kb
Host smart-fd00a8ad-eb9f-4619-8d86-b013f93e8c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585310638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3585310638
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1127222860
Short name T917
Test name
Test status
Simulation time 223533610922 ps
CPU time 130.18 seconds
Started May 09 02:39:28 PM PDT 24
Finished May 09 02:41:40 PM PDT 24
Peak memory 200332 kb
Host smart-0d6e4ade-aa26-4257-9f88-fd07488b6c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127222860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1127222860
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.452517406
Short name T53
Test name
Test status
Simulation time 67651549533 ps
CPU time 803.47 seconds
Started May 09 02:39:15 PM PDT 24
Finished May 09 02:52:40 PM PDT 24
Peak memory 225316 kb
Host smart-9d586396-3095-4362-83f8-d7da34e6c76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452517406 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.452517406
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3290903738
Short name T434
Test name
Test status
Simulation time 515219734 ps
CPU time 2.27 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:39:19 PM PDT 24
Peak memory 198824 kb
Host smart-915e96a0-7cce-4817-a97d-e1cfab97c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290903738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3290903738
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2724750496
Short name T350
Test name
Test status
Simulation time 131742433210 ps
CPU time 90.95 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 200484 kb
Host smart-10c81693-15d0-42fb-ab4c-b3bfd9f063ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724750496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2724750496
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3522492724
Short name T138
Test name
Test status
Simulation time 151870335419 ps
CPU time 80.2 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:43:29 PM PDT 24
Peak memory 200224 kb
Host smart-adf507c5-ce0b-45b8-b55e-6b627ff5c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522492724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3522492724
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2588996171
Short name T862
Test name
Test status
Simulation time 54104794824 ps
CPU time 18.87 seconds
Started May 09 02:42:07 PM PDT 24
Finished May 09 02:42:27 PM PDT 24
Peak memory 200176 kb
Host smart-30411bc1-c461-41d7-93ad-240163bbabd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588996171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2588996171
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2607094454
Short name T899
Test name
Test status
Simulation time 333207036583 ps
CPU time 94.64 seconds
Started May 09 02:42:10 PM PDT 24
Finished May 09 02:43:46 PM PDT 24
Peak memory 200412 kb
Host smart-f92599ea-d54a-493b-a950-364ddb887bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607094454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2607094454
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2174279655
Short name T825
Test name
Test status
Simulation time 46494875708 ps
CPU time 6.44 seconds
Started May 09 02:42:09 PM PDT 24
Finished May 09 02:42:17 PM PDT 24
Peak memory 200452 kb
Host smart-65899cfa-18bd-4587-abc9-619b1a843d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174279655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2174279655
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1931191681
Short name T219
Test name
Test status
Simulation time 62493274828 ps
CPU time 146.21 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:44:49 PM PDT 24
Peak memory 200408 kb
Host smart-27ba50ef-4ed4-4af9-a44d-c833a9028791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931191681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1931191681
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1698766902
Short name T640
Test name
Test status
Simulation time 9100288028 ps
CPU time 14.82 seconds
Started May 09 02:42:20 PM PDT 24
Finished May 09 02:42:38 PM PDT 24
Peak memory 200228 kb
Host smart-def37850-fbb9-4cf0-9d4a-0dfca2f71773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698766902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1698766902
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1158310061
Short name T1073
Test name
Test status
Simulation time 17840655629 ps
CPU time 28.1 seconds
Started May 09 02:42:23 PM PDT 24
Finished May 09 02:42:53 PM PDT 24
Peak memory 200240 kb
Host smart-d892a910-0a18-4c44-a503-27351b089836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158310061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1158310061
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3715502856
Short name T732
Test name
Test status
Simulation time 226192827046 ps
CPU time 108.25 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:44:10 PM PDT 24
Peak memory 200424 kb
Host smart-e405a0fa-99c2-44a9-b3b8-dc9a83e35a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715502856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3715502856
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2153077006
Short name T1103
Test name
Test status
Simulation time 190179598313 ps
CPU time 588.76 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:52:11 PM PDT 24
Peak memory 200472 kb
Host smart-6c1530df-c66f-41c9-b487-35e23b9e0b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153077006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2153077006
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2433863510
Short name T186
Test name
Test status
Simulation time 14762826219 ps
CPU time 12.05 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:42:34 PM PDT 24
Peak memory 200484 kb
Host smart-ae7ab6c9-5e07-4376-8aba-f0291b54e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433863510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2433863510
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2578467535
Short name T370
Test name
Test status
Simulation time 24623322 ps
CPU time 0.55 seconds
Started May 09 02:39:14 PM PDT 24
Finished May 09 02:39:16 PM PDT 24
Peak memory 195224 kb
Host smart-06a4a7b5-36dd-45f6-a4dc-bc8fed8aac41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578467535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2578467535
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2285415090
Short name T1180
Test name
Test status
Simulation time 61214894675 ps
CPU time 24.93 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:39:53 PM PDT 24
Peak memory 200216 kb
Host smart-54da7701-560e-430b-8a3b-45fbbb00936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285415090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2285415090
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3858596658
Short name T154
Test name
Test status
Simulation time 37578308431 ps
CPU time 13.68 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:39:31 PM PDT 24
Peak memory 200360 kb
Host smart-714ac976-5e3d-42f7-aa21-9699bca236a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858596658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3858596658
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3038407311
Short name T811
Test name
Test status
Simulation time 32335727861 ps
CPU time 16.03 seconds
Started May 09 02:39:15 PM PDT 24
Finished May 09 02:39:32 PM PDT 24
Peak memory 200448 kb
Host smart-a60b314a-d233-4eae-9b3e-fd865b4e731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038407311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3038407311
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3400342378
Short name T978
Test name
Test status
Simulation time 514030195728 ps
CPU time 197.28 seconds
Started May 09 02:39:18 PM PDT 24
Finished May 09 02:42:37 PM PDT 24
Peak memory 199272 kb
Host smart-ec419265-61d6-450a-9899-a7a0a9c4179a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400342378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3400342378
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3081520081
Short name T781
Test name
Test status
Simulation time 34959105681 ps
CPU time 170.81 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:42:08 PM PDT 24
Peak memory 200472 kb
Host smart-97d8f040-ee87-45c3-a7af-ca5af7c6dbf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081520081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3081520081
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.435035420
Short name T23
Test name
Test status
Simulation time 3605239096 ps
CPU time 2.69 seconds
Started May 09 02:39:21 PM PDT 24
Finished May 09 02:39:25 PM PDT 24
Peak memory 199180 kb
Host smart-0a492bee-7d4c-4c14-9f8a-638850c92070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435035420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.435035420
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2947977222
Short name T299
Test name
Test status
Simulation time 96763851101 ps
CPU time 88.06 seconds
Started May 09 02:39:23 PM PDT 24
Finished May 09 02:40:53 PM PDT 24
Peak memory 200264 kb
Host smart-0844078a-659f-498f-87e8-080c2b36c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947977222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2947977222
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.975812929
Short name T1113
Test name
Test status
Simulation time 10209856728 ps
CPU time 595.57 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 200644 kb
Host smart-8a2daa7f-1e9e-47e2-a148-da5146a786e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975812929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.975812929
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4236050259
Short name T702
Test name
Test status
Simulation time 5873830308 ps
CPU time 26.99 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:39:56 PM PDT 24
Peak memory 199552 kb
Host smart-b21262dd-dfa9-4bb5-b234-aab133c86701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236050259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4236050259
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2208260416
Short name T292
Test name
Test status
Simulation time 105147017083 ps
CPU time 139.5 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:41:38 PM PDT 24
Peak memory 200400 kb
Host smart-b2588692-b3af-4afc-9c44-62369563859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208260416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2208260416
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1495893958
Short name T1161
Test name
Test status
Simulation time 3079100064 ps
CPU time 2.33 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:21 PM PDT 24
Peak memory 196456 kb
Host smart-50476419-62e8-4041-9af0-fd4e6ab39e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495893958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1495893958
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2719278243
Short name T756
Test name
Test status
Simulation time 5566807870 ps
CPU time 17.56 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:39:35 PM PDT 24
Peak memory 200216 kb
Host smart-e790c3e5-0b53-4b98-af5c-d71f762826bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719278243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2719278243
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2379332041
Short name T344
Test name
Test status
Simulation time 165269132882 ps
CPU time 474.54 seconds
Started May 09 02:39:18 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 200356 kb
Host smart-e6305c17-c631-4f57-8806-fc456c92abdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379332041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2379332041
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.77709063
Short name T530
Test name
Test status
Simulation time 54282002621 ps
CPU time 714.74 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:51:12 PM PDT 24
Peak memory 216964 kb
Host smart-88e552cd-09d9-4b38-8be8-39c86f014a58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77709063 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.77709063
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.107331655
Short name T827
Test name
Test status
Simulation time 2135014876 ps
CPU time 2.3 seconds
Started May 09 02:39:22 PM PDT 24
Finished May 09 02:39:26 PM PDT 24
Peak memory 200536 kb
Host smart-77563120-dc14-42c3-999f-f3a3433380b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107331655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.107331655
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4248878271
Short name T828
Test name
Test status
Simulation time 6735898774 ps
CPU time 11.58 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:30 PM PDT 24
Peak memory 197284 kb
Host smart-1a2b2651-14d4-457d-9e84-681eed885057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248878271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4248878271
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1425569650
Short name T5
Test name
Test status
Simulation time 24854051103 ps
CPU time 23.72 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 200408 kb
Host smart-03bb7c24-b5f5-467b-acf6-4a696a0dfb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425569650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1425569650
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2745632453
Short name T233
Test name
Test status
Simulation time 23317700327 ps
CPU time 35.88 seconds
Started May 09 02:42:20 PM PDT 24
Finished May 09 02:42:59 PM PDT 24
Peak memory 200416 kb
Host smart-a580f21d-3ca9-41c2-8208-5a2586b07a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745632453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2745632453
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2768560597
Short name T687
Test name
Test status
Simulation time 49026792230 ps
CPU time 83.49 seconds
Started May 09 02:42:18 PM PDT 24
Finished May 09 02:43:45 PM PDT 24
Peak memory 200384 kb
Host smart-f8b55a2e-a59a-4dfd-b7f8-c91c8a6a7bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768560597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2768560597
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.182409834
Short name T365
Test name
Test status
Simulation time 57106586125 ps
CPU time 23.84 seconds
Started May 09 02:42:18 PM PDT 24
Finished May 09 02:42:45 PM PDT 24
Peak memory 200432 kb
Host smart-eb16d082-33e5-4cb6-be96-a168c6fc2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182409834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.182409834
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1310448991
Short name T332
Test name
Test status
Simulation time 53973355200 ps
CPU time 127.63 seconds
Started May 09 02:42:20 PM PDT 24
Finished May 09 02:44:30 PM PDT 24
Peak memory 200440 kb
Host smart-20a217a3-1cd1-4add-8640-a69905dd43e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310448991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1310448991
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.891857853
Short name T683
Test name
Test status
Simulation time 87196613606 ps
CPU time 336.39 seconds
Started May 09 02:42:18 PM PDT 24
Finished May 09 02:47:58 PM PDT 24
Peak memory 200424 kb
Host smart-740e171a-8f77-476c-8b0b-bc959fc85c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891857853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.891857853
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1686636763
Short name T749
Test name
Test status
Simulation time 22008520774 ps
CPU time 21.11 seconds
Started May 09 02:42:20 PM PDT 24
Finished May 09 02:42:44 PM PDT 24
Peak memory 200416 kb
Host smart-0bbe7dcf-79f4-43b7-b4e4-f8ca8b076b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686636763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1686636763
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.269137666
Short name T583
Test name
Test status
Simulation time 132185947202 ps
CPU time 101.5 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:44:04 PM PDT 24
Peak memory 200468 kb
Host smart-ba337f8b-9dec-4baf-9d07-871f4ae5f883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269137666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.269137666
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1146844718
Short name T936
Test name
Test status
Simulation time 83980279642 ps
CPU time 85.12 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:43:47 PM PDT 24
Peak memory 200476 kb
Host smart-1c2f9194-ce91-4bea-b752-a0d470ea83a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146844718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1146844718
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.201345028
Short name T373
Test name
Test status
Simulation time 14912985 ps
CPU time 0.56 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:39:28 PM PDT 24
Peak memory 195836 kb
Host smart-46b50ffa-838c-4124-94fd-f809626c868b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201345028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.201345028
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2529774246
Short name T952
Test name
Test status
Simulation time 39532287333 ps
CPU time 12.6 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:39:30 PM PDT 24
Peak memory 200440 kb
Host smart-2d87ba86-0461-4652-8bef-0c65c2862df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529774246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2529774246
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.685935516
Short name T768
Test name
Test status
Simulation time 113582537115 ps
CPU time 51.34 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:40:09 PM PDT 24
Peak memory 200504 kb
Host smart-23b9fab9-3365-4c0f-9f3d-00edae1ef484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685935516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.685935516
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.1647798687
Short name T531
Test name
Test status
Simulation time 176592353700 ps
CPU time 69.86 seconds
Started May 09 02:39:19 PM PDT 24
Finished May 09 02:40:30 PM PDT 24
Peak memory 198232 kb
Host smart-c3a3db77-0cc1-4d2b-9dcb-bb309a07be84
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647798687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1647798687
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1372990758
Short name T927
Test name
Test status
Simulation time 97305810566 ps
CPU time 869.49 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:53:57 PM PDT 24
Peak memory 200396 kb
Host smart-ddb032b5-a4e1-4fda-8807-6820a8cb234b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372990758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1372990758
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2590430402
Short name T669
Test name
Test status
Simulation time 1461451938 ps
CPU time 2.84 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:39:37 PM PDT 24
Peak memory 196344 kb
Host smart-2c5348c7-d30c-4023-85cb-45f1f2310311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590430402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2590430402
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2781090259
Short name T130
Test name
Test status
Simulation time 44567312416 ps
CPU time 70.19 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:40:29 PM PDT 24
Peak memory 199796 kb
Host smart-a2c5c76f-2932-47e5-95d2-9aa90e1aa806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781090259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2781090259
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3449507190
Short name T7
Test name
Test status
Simulation time 6595099714 ps
CPU time 408.66 seconds
Started May 09 02:39:28 PM PDT 24
Finished May 09 02:46:19 PM PDT 24
Peak memory 200316 kb
Host smart-7b7d1988-e4ca-4c72-aa68-56eeecff4279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449507190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3449507190
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4069073891
Short name T1038
Test name
Test status
Simulation time 3185391950 ps
CPU time 11.87 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 198272 kb
Host smart-edfab988-7564-4aa8-ab1f-fe8c0241ee57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069073891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4069073891
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2021759258
Short name T190
Test name
Test status
Simulation time 15687252127 ps
CPU time 13.92 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:39:42 PM PDT 24
Peak memory 199952 kb
Host smart-68ece4f6-fc2b-4454-b3d3-d40bde976400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021759258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2021759258
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1430621253
Short name T456
Test name
Test status
Simulation time 46303975054 ps
CPU time 21.75 seconds
Started May 09 02:39:20 PM PDT 24
Finished May 09 02:39:43 PM PDT 24
Peak memory 196452 kb
Host smart-5e6263d3-63c0-4321-97ee-4295c600ceee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430621253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1430621253
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4100711053
Short name T529
Test name
Test status
Simulation time 492289462 ps
CPU time 1.4 seconds
Started May 09 02:39:17 PM PDT 24
Finished May 09 02:39:20 PM PDT 24
Peak memory 200024 kb
Host smart-3b849e65-db6c-405d-ae9b-f7a5c8f2296e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100711053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4100711053
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1818377880
Short name T115
Test name
Test status
Simulation time 161437527507 ps
CPU time 70.5 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:40:47 PM PDT 24
Peak memory 200444 kb
Host smart-4a1cfc8a-b1a7-4fa0-940d-c57b746481aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818377880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1818377880
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.836116582
Short name T170
Test name
Test status
Simulation time 134895272421 ps
CPU time 450.23 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 228176 kb
Host smart-9b94f15e-a338-425d-a2cb-6da40e8fb767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836116582 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.836116582
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1132317441
Short name T298
Test name
Test status
Simulation time 2159688585 ps
CPU time 2.07 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:39:30 PM PDT 24
Peak memory 198924 kb
Host smart-4b50dd6b-c4c5-416f-ba38-96e42bf401eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132317441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1132317441
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1489420935
Short name T327
Test name
Test status
Simulation time 33084343626 ps
CPU time 36.12 seconds
Started May 09 02:39:16 PM PDT 24
Finished May 09 02:39:54 PM PDT 24
Peak memory 200364 kb
Host smart-d2d2207e-911b-4ad5-8414-1f975ab0164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489420935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1489420935
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.160245694
Short name T368
Test name
Test status
Simulation time 80165824411 ps
CPU time 162.59 seconds
Started May 09 02:42:18 PM PDT 24
Finished May 09 02:45:04 PM PDT 24
Peak memory 200472 kb
Host smart-ad7e2978-4012-4384-8bec-d2425ea2399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160245694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.160245694
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.30067572
Short name T1160
Test name
Test status
Simulation time 43249121069 ps
CPU time 46.63 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:43:42 PM PDT 24
Peak memory 200440 kb
Host smart-12f09aab-e599-4aed-8984-ad24cb3843e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30067572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.30067572
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3190547901
Short name T505
Test name
Test status
Simulation time 43010608881 ps
CPU time 20.04 seconds
Started May 09 02:42:18 PM PDT 24
Finished May 09 02:42:41 PM PDT 24
Peak memory 200384 kb
Host smart-375d2b88-581e-4a61-b2cc-ca7656a5663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190547901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3190547901
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2942086162
Short name T241
Test name
Test status
Simulation time 63554136537 ps
CPU time 23.4 seconds
Started May 09 02:42:21 PM PDT 24
Finished May 09 02:42:47 PM PDT 24
Peak memory 200428 kb
Host smart-c5aea036-3ab0-49d9-b547-3ac7b060c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942086162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2942086162
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2111535656
Short name T185
Test name
Test status
Simulation time 18288963601 ps
CPU time 32.14 seconds
Started May 09 02:42:22 PM PDT 24
Finished May 09 02:42:56 PM PDT 24
Peak memory 200432 kb
Host smart-7a50c72b-7c87-4658-81d8-ce2981db301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111535656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2111535656
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2489915052
Short name T808
Test name
Test status
Simulation time 16277881211 ps
CPU time 96.56 seconds
Started May 09 02:42:21 PM PDT 24
Finished May 09 02:44:00 PM PDT 24
Peak memory 200472 kb
Host smart-63d145ae-ecde-4c06-bb31-2611ea4f20cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489915052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2489915052
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.269267875
Short name T578
Test name
Test status
Simulation time 342609473506 ps
CPU time 138.2 seconds
Started May 09 02:42:19 PM PDT 24
Finished May 09 02:44:40 PM PDT 24
Peak memory 200452 kb
Host smart-7d7a2457-a775-4620-b874-a75bff4943b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269267875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.269267875
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1599197468
Short name T221
Test name
Test status
Simulation time 28327323417 ps
CPU time 46.89 seconds
Started May 09 02:42:20 PM PDT 24
Finished May 09 02:43:10 PM PDT 24
Peak memory 200392 kb
Host smart-09e93942-2186-4aaf-af94-da00fec3134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599197468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1599197468
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.454123942
Short name T759
Test name
Test status
Simulation time 102432339934 ps
CPU time 22.32 seconds
Started May 09 02:42:18 PM PDT 24
Finished May 09 02:42:44 PM PDT 24
Peak memory 200388 kb
Host smart-e62e10b3-b38f-49f6-8880-afe3a26eddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454123942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.454123942
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3201782102
Short name T938
Test name
Test status
Simulation time 23745303 ps
CPU time 0.57 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:39:29 PM PDT 24
Peak memory 195808 kb
Host smart-1bcaac76-b55a-4a2d-8280-b7764b8c51f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201782102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3201782102
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1558050242
Short name T518
Test name
Test status
Simulation time 61938415865 ps
CPU time 27.39 seconds
Started May 09 02:39:24 PM PDT 24
Finished May 09 02:39:53 PM PDT 24
Peak memory 200472 kb
Host smart-e2c83d92-7d0f-4923-9153-05ec86ac106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558050242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1558050242
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4092137661
Short name T286
Test name
Test status
Simulation time 54899410064 ps
CPU time 96.73 seconds
Started May 09 02:39:33 PM PDT 24
Finished May 09 02:41:12 PM PDT 24
Peak memory 200468 kb
Host smart-dec07d8b-989a-4dbd-b075-7893bbe1223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092137661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4092137661
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1124050498
Short name T235
Test name
Test status
Simulation time 28766460482 ps
CPU time 46.61 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:40:15 PM PDT 24
Peak memory 200428 kb
Host smart-86e7fd2c-9053-4fff-9a09-c0c72adebdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124050498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1124050498
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.384439371
Short name T835
Test name
Test status
Simulation time 7765693821 ps
CPU time 4.02 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:39:38 PM PDT 24
Peak memory 198208 kb
Host smart-f2b13f08-2e8f-4834-8c59-02a8a780adbc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384439371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.384439371
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3894035524
Short name T1179
Test name
Test status
Simulation time 109567024393 ps
CPU time 998.7 seconds
Started May 09 02:39:31 PM PDT 24
Finished May 09 02:56:12 PM PDT 24
Peak memory 200192 kb
Host smart-52c86116-9c31-4574-aaa4-5a26f833aa67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894035524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3894035524
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3937486932
Short name T437
Test name
Test status
Simulation time 8377450081 ps
CPU time 16.4 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:39:43 PM PDT 24
Peak memory 198888 kb
Host smart-4018ab11-f2cc-4b42-b404-401afc7a1f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937486932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3937486932
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2346680060
Short name T275
Test name
Test status
Simulation time 156820271081 ps
CPU time 97.91 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:41:06 PM PDT 24
Peak memory 199560 kb
Host smart-f0852f31-d031-4c23-a880-4109d337a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346680060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2346680060
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2304601537
Short name T485
Test name
Test status
Simulation time 12891130383 ps
CPU time 349.8 seconds
Started May 09 02:39:28 PM PDT 24
Finished May 09 02:45:19 PM PDT 24
Peak memory 200392 kb
Host smart-ca8272eb-2c1d-4462-a4bb-82c8b015350d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304601537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2304601537
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2110605951
Short name T472
Test name
Test status
Simulation time 1602876269 ps
CPU time 1.84 seconds
Started May 09 02:39:33 PM PDT 24
Finished May 09 02:39:36 PM PDT 24
Peak memory 197236 kb
Host smart-f36b6d7c-a9a5-4421-8c47-7a1c347ace6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110605951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2110605951
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2230797823
Short name T198
Test name
Test status
Simulation time 189965136635 ps
CPU time 396.87 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:46:05 PM PDT 24
Peak memory 200476 kb
Host smart-5f0829d8-bbff-4fcb-8fe5-8a79a8a501ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230797823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2230797823
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1367184387
Short name T129
Test name
Test status
Simulation time 3617760959 ps
CPU time 6.98 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:39:35 PM PDT 24
Peak memory 196764 kb
Host smart-6c83451f-d900-4440-9094-e73e2da1b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367184387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1367184387
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.286587007
Short name T490
Test name
Test status
Simulation time 933191640 ps
CPU time 4.04 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:39:32 PM PDT 24
Peak memory 198776 kb
Host smart-f4bf2b24-383f-4d7b-81f0-8d7a8e29a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286587007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.286587007
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.4230025681
Short name T19
Test name
Test status
Simulation time 533008087 ps
CPU time 1.89 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:39:36 PM PDT 24
Peak memory 198844 kb
Host smart-d20463f2-c6e5-4ea9-98aa-63b85d4c9cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230025681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4230025681
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2227940026
Short name T984
Test name
Test status
Simulation time 103556815606 ps
CPU time 36.91 seconds
Started May 09 02:39:24 PM PDT 24
Finished May 09 02:40:02 PM PDT 24
Peak memory 200396 kb
Host smart-738c414a-92cd-4c56-b89d-4463f99f5049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227940026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2227940026
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2910261235
Short name T944
Test name
Test status
Simulation time 210492672450 ps
CPU time 372.96 seconds
Started May 09 02:42:31 PM PDT 24
Finished May 09 02:48:47 PM PDT 24
Peak memory 200440 kb
Host smart-af34c512-c619-43fa-a16e-c53971adcd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910261235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2910261235
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2963510423
Short name T1102
Test name
Test status
Simulation time 19719698083 ps
CPU time 11.6 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:42:43 PM PDT 24
Peak memory 200448 kb
Host smart-cb9583e8-e62c-4542-b4d9-4ffef92ad17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963510423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2963510423
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2662993238
Short name T705
Test name
Test status
Simulation time 224530941953 ps
CPU time 333.84 seconds
Started May 09 02:42:28 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 200220 kb
Host smart-2aae65f1-0620-4237-82b9-6bf60bafd453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662993238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2662993238
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3035350559
Short name T334
Test name
Test status
Simulation time 65163811226 ps
CPU time 198.71 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 200348 kb
Host smart-3975d6a1-0c81-43bf-a862-7cff73d2751a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035350559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3035350559
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3711647118
Short name T661
Test name
Test status
Simulation time 169319364526 ps
CPU time 75.89 seconds
Started May 09 02:42:32 PM PDT 24
Finished May 09 02:43:51 PM PDT 24
Peak memory 200464 kb
Host smart-9bdef959-c8c0-40cd-8d71-2cb0d23bec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711647118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3711647118
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3311121633
Short name T215
Test name
Test status
Simulation time 159007493606 ps
CPU time 15.39 seconds
Started May 09 02:42:28 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 199692 kb
Host smart-48460816-bf23-4a2d-87b6-7ef3b2e5e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311121633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3311121633
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1941468783
Short name T886
Test name
Test status
Simulation time 48970766788 ps
CPU time 38.66 seconds
Started May 09 02:42:32 PM PDT 24
Finished May 09 02:43:14 PM PDT 24
Peak memory 200376 kb
Host smart-0bece1ae-0b2a-412a-b83d-22a85f4d2fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941468783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1941468783
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1152027082
Short name T396
Test name
Test status
Simulation time 13684105 ps
CPU time 0.54 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:39:31 PM PDT 24
Peak memory 195816 kb
Host smart-771524a3-1021-4cfa-9a13-102964261f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152027082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1152027082
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2959790041
Short name T1088
Test name
Test status
Simulation time 54508246140 ps
CPU time 93.71 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:41:00 PM PDT 24
Peak memory 200504 kb
Host smart-c5e99c15-ed13-4148-8076-620003ac9b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959790041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2959790041
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2431359396
Short name T163
Test name
Test status
Simulation time 188504800734 ps
CPU time 44.36 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:40:12 PM PDT 24
Peak memory 200440 kb
Host smart-1a6dd2e3-6a99-4cec-bb4b-c1a50ee228ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431359396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2431359396
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.160704176
Short name T160
Test name
Test status
Simulation time 52192167159 ps
CPU time 82.32 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 200420 kb
Host smart-69337a53-58e8-4723-b1c7-b538481afcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160704176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.160704176
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1837126472
Short name T488
Test name
Test status
Simulation time 42409075943 ps
CPU time 69 seconds
Started May 09 02:39:27 PM PDT 24
Finished May 09 02:40:38 PM PDT 24
Peak memory 197068 kb
Host smart-083b3414-b541-49a6-941b-65242ed09bd2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837126472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1837126472
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4077556416
Short name T928
Test name
Test status
Simulation time 129955925314 ps
CPU time 154.5 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:42:10 PM PDT 24
Peak memory 200412 kb
Host smart-18d72528-e721-4511-ae4a-7627641d0a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077556416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4077556416
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.373495224
Short name T508
Test name
Test status
Simulation time 7317669924 ps
CPU time 5.2 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:39:31 PM PDT 24
Peak memory 199176 kb
Host smart-9db732ef-c16d-4355-84d4-8f57cb963019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373495224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.373495224
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1667496052
Short name T746
Test name
Test status
Simulation time 38690415515 ps
CPU time 72.06 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:40:42 PM PDT 24
Peak memory 200660 kb
Host smart-b8fd2819-ebee-4a79-8c38-49c51e9a4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667496052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1667496052
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2934481988
Short name T1089
Test name
Test status
Simulation time 8119320459 ps
CPU time 120.12 seconds
Started May 09 02:39:31 PM PDT 24
Finished May 09 02:41:33 PM PDT 24
Peak memory 200368 kb
Host smart-b48c5ed9-4b92-4400-b2a3-9179593d6517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934481988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2934481988
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.892480693
Short name T1027
Test name
Test status
Simulation time 3648235970 ps
CPU time 14.05 seconds
Started May 09 02:39:24 PM PDT 24
Finished May 09 02:39:39 PM PDT 24
Peak memory 198552 kb
Host smart-34fe0573-f217-4ed7-9508-7dc4971ed4ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892480693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.892480693
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3494016812
Short name T935
Test name
Test status
Simulation time 73118371614 ps
CPU time 72.28 seconds
Started May 09 02:39:23 PM PDT 24
Finished May 09 02:40:36 PM PDT 24
Peak memory 200480 kb
Host smart-b1f4b6ea-1508-4895-a02d-3a884363aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494016812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3494016812
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4181836804
Short name T1169
Test name
Test status
Simulation time 1964757983 ps
CPU time 2.23 seconds
Started May 09 02:39:28 PM PDT 24
Finished May 09 02:39:32 PM PDT 24
Peak memory 196096 kb
Host smart-3f455c7f-21b1-42b3-a449-b37b0bf6170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181836804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4181836804
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3337168306
Short name T10
Test name
Test status
Simulation time 700287221 ps
CPU time 2.15 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:39:33 PM PDT 24
Peak memory 199260 kb
Host smart-5c0a30c7-e8db-4bdb-89dd-aff37e0da72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337168306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3337168306
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1978833359
Short name T912
Test name
Test status
Simulation time 419164447725 ps
CPU time 747.24 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:52:05 PM PDT 24
Peak memory 216944 kb
Host smart-5e2212c2-7721-4121-8782-6847e248dbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978833359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1978833359
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3045881468
Short name T432
Test name
Test status
Simulation time 242230562 ps
CPU time 1.13 seconds
Started May 09 02:39:25 PM PDT 24
Finished May 09 02:39:28 PM PDT 24
Peak memory 197572 kb
Host smart-1bfddfc0-f9e6-4e0a-9105-619679a26a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045881468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3045881468
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1660797034
Short name T325
Test name
Test status
Simulation time 140017082592 ps
CPU time 60.96 seconds
Started May 09 02:39:26 PM PDT 24
Finished May 09 02:40:28 PM PDT 24
Peak memory 200472 kb
Host smart-4947a901-9302-4603-82c6-724cac893a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660797034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1660797034
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2433776683
Short name T1022
Test name
Test status
Simulation time 31696744056 ps
CPU time 29.08 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:43:01 PM PDT 24
Peak memory 200416 kb
Host smart-b617ff78-1724-4686-be6d-5b23b74fcb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433776683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2433776683
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.986192164
Short name T253
Test name
Test status
Simulation time 69435578431 ps
CPU time 27.99 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:42:59 PM PDT 24
Peak memory 200312 kb
Host smart-1fd0e3d8-cf1f-4ae9-860e-46c83c5cc939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986192164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.986192164
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.416608255
Short name T311
Test name
Test status
Simulation time 42783762316 ps
CPU time 96 seconds
Started May 09 02:42:28 PM PDT 24
Finished May 09 02:44:07 PM PDT 24
Peak memory 200376 kb
Host smart-b5d91382-fb61-4bfe-bba1-fa9a4ee38480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416608255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.416608255
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4114368465
Short name T949
Test name
Test status
Simulation time 80053687043 ps
CPU time 38.94 seconds
Started May 09 02:42:28 PM PDT 24
Finished May 09 02:43:09 PM PDT 24
Peak memory 200308 kb
Host smart-2856deff-2b3c-4ec0-b134-8ccdbbf2cb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114368465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4114368465
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.219112590
Short name T166
Test name
Test status
Simulation time 104807622169 ps
CPU time 55.15 seconds
Started May 09 02:42:31 PM PDT 24
Finished May 09 02:43:29 PM PDT 24
Peak memory 200340 kb
Host smart-c6c6db0e-c357-4420-bf1e-4b269a7bed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219112590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.219112590
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3651735447
Short name T920
Test name
Test status
Simulation time 46313780146 ps
CPU time 62 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 200452 kb
Host smart-54c1f7c4-5fe8-4d50-8b97-e3914a9cd0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651735447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3651735447
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1271045036
Short name T632
Test name
Test status
Simulation time 32480948705 ps
CPU time 16.8 seconds
Started May 09 02:42:32 PM PDT 24
Finished May 09 02:42:52 PM PDT 24
Peak memory 200456 kb
Host smart-80c82212-9b59-472d-aee3-54025c7acb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271045036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1271045036
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2584647570
Short name T268
Test name
Test status
Simulation time 211205604216 ps
CPU time 44.51 seconds
Started May 09 02:42:31 PM PDT 24
Finished May 09 02:43:19 PM PDT 24
Peak memory 200376 kb
Host smart-03c5f257-be7d-4e8b-97c8-2beb7637eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584647570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2584647570
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2577777400
Short name T638
Test name
Test status
Simulation time 102092397742 ps
CPU time 141.04 seconds
Started May 09 02:42:31 PM PDT 24
Finished May 09 02:44:56 PM PDT 24
Peak memory 200368 kb
Host smart-0fe21bf7-7985-43c6-987d-0dda8d48a911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577777400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2577777400
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2670069095
Short name T367
Test name
Test status
Simulation time 90675328005 ps
CPU time 129.5 seconds
Started May 09 02:42:33 PM PDT 24
Finished May 09 02:44:45 PM PDT 24
Peak memory 200400 kb
Host smart-3b831967-58f8-4ce2-bfa6-3be8e547f3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670069095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2670069095
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.741849202
Short name T623
Test name
Test status
Simulation time 16170163 ps
CPU time 0.54 seconds
Started May 09 02:39:38 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 195844 kb
Host smart-53ee1970-f675-4735-8de4-c2b485cb6660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741849202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.741849202
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3816940622
Short name T568
Test name
Test status
Simulation time 472407932176 ps
CPU time 157.79 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:42:14 PM PDT 24
Peak memory 200480 kb
Host smart-adab647d-6629-482b-9de8-99b5f987eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816940622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3816940622
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2316359748
Short name T606
Test name
Test status
Simulation time 164016161329 ps
CPU time 71.8 seconds
Started May 09 02:39:30 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 200356 kb
Host smart-8f708c74-b865-441b-ab08-74fe0218da38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316359748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2316359748
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1602134298
Short name T1165
Test name
Test status
Simulation time 76190884460 ps
CPU time 34.52 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:40:05 PM PDT 24
Peak memory 200500 kb
Host smart-1d28e14e-d631-4770-88a9-d349e245ac47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602134298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1602134298
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2696054819
Short name T22
Test name
Test status
Simulation time 18152659381 ps
CPU time 32.91 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:40:04 PM PDT 24
Peak memory 200160 kb
Host smart-e336f278-2ee9-4947-98fe-16a1584b7948
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696054819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2696054819
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4102125300
Short name T1048
Test name
Test status
Simulation time 218470302031 ps
CPU time 341.21 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:45:16 PM PDT 24
Peak memory 200436 kb
Host smart-2b706c2c-49ca-46fa-8cb3-679f371ace22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102125300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4102125300
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2353267072
Short name T399
Test name
Test status
Simulation time 4835714278 ps
CPU time 8.85 seconds
Started May 09 02:39:31 PM PDT 24
Finished May 09 02:39:41 PM PDT 24
Peak memory 198988 kb
Host smart-850c27ae-a1a9-4371-bea4-add4b484a3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353267072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2353267072
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3041779120
Short name T527
Test name
Test status
Simulation time 125460170798 ps
CPU time 103.68 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:41:20 PM PDT 24
Peak memory 200600 kb
Host smart-e30fdf64-bc2a-4cae-84cb-51306ebf3654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041779120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3041779120
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2679312715
Short name T885
Test name
Test status
Simulation time 16024305398 ps
CPU time 708.3 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:51:22 PM PDT 24
Peak memory 200368 kb
Host smart-45b75224-7cab-4476-89e9-132e46a15075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679312715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2679312715
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.458443548
Short name T500
Test name
Test status
Simulation time 2207806310 ps
CPU time 12.71 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:39:43 PM PDT 24
Peak memory 198928 kb
Host smart-fbb6deac-8364-472c-9692-bdcac9d0e146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458443548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.458443548
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1849730463
Short name T1006
Test name
Test status
Simulation time 227540229661 ps
CPU time 837.42 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:53:31 PM PDT 24
Peak memory 200416 kb
Host smart-677c742b-a8e2-4f9c-b453-b1b4c32e79bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849730463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1849730463
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2961817712
Short name T643
Test name
Test status
Simulation time 5479038062 ps
CPU time 9.86 seconds
Started May 09 02:39:29 PM PDT 24
Finished May 09 02:39:41 PM PDT 24
Peak memory 196712 kb
Host smart-8bf3de15-e22b-4061-90e3-fd277512c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961817712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2961817712
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1088843863
Short name T533
Test name
Test status
Simulation time 6059994307 ps
CPU time 13.6 seconds
Started May 09 02:39:30 PM PDT 24
Finished May 09 02:39:45 PM PDT 24
Peak memory 200416 kb
Host smart-802bfb4b-494d-41e7-bcb0-f355d334215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088843863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1088843863
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1975567634
Short name T405
Test name
Test status
Simulation time 1797514010 ps
CPU time 2.93 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:39:37 PM PDT 24
Peak memory 199200 kb
Host smart-43c2a4e4-e959-42af-866a-e05e94759343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975567634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1975567634
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3137227297
Short name T520
Test name
Test status
Simulation time 82499682731 ps
CPU time 32.43 seconds
Started May 09 02:42:30 PM PDT 24
Finished May 09 02:43:06 PM PDT 24
Peak memory 200460 kb
Host smart-39af2a8b-0ab4-4c5a-a682-7e4d73bc9379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137227297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3137227297
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3641609605
Short name T85
Test name
Test status
Simulation time 23226826257 ps
CPU time 48.69 seconds
Started May 09 02:42:32 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 200384 kb
Host smart-7fabae54-15aa-4d6e-baef-159e4955c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641609605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3641609605
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2548951639
Short name T280
Test name
Test status
Simulation time 18830355834 ps
CPU time 7.55 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:42:39 PM PDT 24
Peak memory 200400 kb
Host smart-890cb0e7-4baf-4dee-b723-21d0442f3a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548951639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2548951639
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3167379428
Short name T890
Test name
Test status
Simulation time 50518998981 ps
CPU time 32.92 seconds
Started May 09 02:42:30 PM PDT 24
Finished May 09 02:43:07 PM PDT 24
Peak memory 200500 kb
Host smart-f0db6d94-a897-4e05-9e1e-b494ef6c76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167379428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3167379428
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2949535697
Short name T164
Test name
Test status
Simulation time 111577071732 ps
CPU time 235.56 seconds
Started May 09 02:42:31 PM PDT 24
Finished May 09 02:46:30 PM PDT 24
Peak memory 200404 kb
Host smart-76f4b94e-f0eb-4f65-bfbd-f7927c3444c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949535697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2949535697
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4050170476
Short name T211
Test name
Test status
Simulation time 5103129267 ps
CPU time 9.32 seconds
Started May 09 02:42:29 PM PDT 24
Finished May 09 02:42:41 PM PDT 24
Peak memory 200152 kb
Host smart-cf4f20b1-a253-4d5f-8f83-85344173b1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050170476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4050170476
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3667855892
Short name T236
Test name
Test status
Simulation time 27136705025 ps
CPU time 22.81 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:08 PM PDT 24
Peak memory 200504 kb
Host smart-6b635b74-4579-40d1-9cbd-b8818dfbae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667855892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3667855892
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3414443598
Short name T167
Test name
Test status
Simulation time 150737966564 ps
CPU time 63.19 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:43:45 PM PDT 24
Peak memory 200448 kb
Host smart-9f7af022-18ee-4331-b7f1-b88510ad26d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414443598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3414443598
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3903556894
Short name T943
Test name
Test status
Simulation time 20984901 ps
CPU time 0.57 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:39:36 PM PDT 24
Peak memory 195280 kb
Host smart-f140bfed-7aab-4be7-a509-f98d2e48d5f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903556894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3903556894
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.154279404
Short name T475
Test name
Test status
Simulation time 68550939294 ps
CPU time 46.92 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:40:24 PM PDT 24
Peak memory 200304 kb
Host smart-fa8a579d-a617-49e8-8006-870b942a2316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154279404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.154279404
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1478001675
Short name T842
Test name
Test status
Simulation time 208686950127 ps
CPU time 90.8 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:41:08 PM PDT 24
Peak memory 200436 kb
Host smart-806de9e5-f269-4785-ad4b-6cb6deded574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478001675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1478001675
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1069643945
Short name T191
Test name
Test status
Simulation time 66011067385 ps
CPU time 8.52 seconds
Started May 09 02:39:36 PM PDT 24
Finished May 09 02:39:47 PM PDT 24
Peak memory 200428 kb
Host smart-bea41ebf-1b1c-4b94-bbcb-7d009ae27e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069643945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1069643945
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1880856464
Short name T141
Test name
Test status
Simulation time 123775628050 ps
CPU time 101.25 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:41:20 PM PDT 24
Peak memory 196656 kb
Host smart-049ab06b-611d-4e0e-b217-5fda3f27265e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880856464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1880856464
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4186459596
Short name T651
Test name
Test status
Simulation time 92986326479 ps
CPU time 519 seconds
Started May 09 02:39:42 PM PDT 24
Finished May 09 02:48:23 PM PDT 24
Peak memory 200452 kb
Host smart-39af300c-a625-4c8a-b6ba-748454541191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186459596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4186459596
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.650241096
Short name T1092
Test name
Test status
Simulation time 25859854 ps
CPU time 0.58 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:39:36 PM PDT 24
Peak memory 196208 kb
Host smart-c5112a42-3deb-4e1d-a4fc-12ee60db587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650241096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.650241096
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3374218968
Short name T664
Test name
Test status
Simulation time 41620330462 ps
CPU time 75.72 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:40:55 PM PDT 24
Peak memory 200592 kb
Host smart-fec29f63-f0b7-4d82-bf48-c99c4838af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374218968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3374218968
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2326912141
Short name T329
Test name
Test status
Simulation time 22095729505 ps
CPU time 282.25 seconds
Started May 09 02:39:39 PM PDT 24
Finished May 09 02:44:23 PM PDT 24
Peak memory 200472 kb
Host smart-507faed5-6439-427e-8dee-07a967b42eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326912141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2326912141
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1464959254
Short name T599
Test name
Test status
Simulation time 6603198247 ps
CPU time 17.05 seconds
Started May 09 02:39:33 PM PDT 24
Finished May 09 02:39:52 PM PDT 24
Peak memory 198288 kb
Host smart-9a7d7005-ed64-4021-85d5-1e557981341e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464959254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1464959254
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2625486684
Short name T63
Test name
Test status
Simulation time 102841260917 ps
CPU time 17.13 seconds
Started May 09 02:39:40 PM PDT 24
Finished May 09 02:39:58 PM PDT 24
Peak memory 200388 kb
Host smart-5f3d434d-8d87-4714-afb5-877942b34f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625486684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2625486684
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2349614063
Short name T392
Test name
Test status
Simulation time 642961730 ps
CPU time 0.93 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:39 PM PDT 24
Peak memory 195272 kb
Host smart-20cba7b8-e33e-46b3-99f6-54f9f9779c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349614063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2349614063
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.998921928
Short name T1142
Test name
Test status
Simulation time 550096492 ps
CPU time 3.73 seconds
Started May 09 02:39:36 PM PDT 24
Finished May 09 02:39:42 PM PDT 24
Peak memory 199444 kb
Host smart-1955ddcd-355a-4490-a745-e167378f4c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998921928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.998921928
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1852615661
Short name T809
Test name
Test status
Simulation time 96866374519 ps
CPU time 416.53 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:46:34 PM PDT 24
Peak memory 200568 kb
Host smart-aee2be39-0fc6-41cb-a057-1942465d05d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852615661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1852615661
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1513856187
Short name T120
Test name
Test status
Simulation time 155025894207 ps
CPU time 371.11 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:45:47 PM PDT 24
Peak memory 217036 kb
Host smart-75d21bc2-e8fe-4b1b-800b-fb6fb4347f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513856187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1513856187
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1997758137
Short name T991
Test name
Test status
Simulation time 6198461557 ps
CPU time 11.93 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:49 PM PDT 24
Peak memory 199724 kb
Host smart-a6840575-24fd-4d70-a840-c41f3be7c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997758137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1997758137
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2873697091
Short name T863
Test name
Test status
Simulation time 23296314514 ps
CPU time 19.88 seconds
Started May 09 02:39:39 PM PDT 24
Finished May 09 02:40:00 PM PDT 24
Peak memory 200080 kb
Host smart-2f81b4e8-85cd-4c7e-9c09-4a0d181cd736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873697091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2873697091
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.596602213
Short name T304
Test name
Test status
Simulation time 124996741616 ps
CPU time 13.4 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:42:56 PM PDT 24
Peak memory 200476 kb
Host smart-1695f770-5baa-4580-8685-07c05bd3878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596602213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.596602213
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1254459930
Short name T1115
Test name
Test status
Simulation time 50253263332 ps
CPU time 23.31 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:43:05 PM PDT 24
Peak memory 200476 kb
Host smart-7b6f2bde-7a13-4558-b670-8e9274d01af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254459930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1254459930
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1705454826
Short name T879
Test name
Test status
Simulation time 5407215553 ps
CPU time 11.93 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:42:57 PM PDT 24
Peak memory 200448 kb
Host smart-64a9b726-441c-443c-bf6f-48621c6aa5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705454826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1705454826
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3896076967
Short name T596
Test name
Test status
Simulation time 90364271891 ps
CPU time 12.72 seconds
Started May 09 02:42:38 PM PDT 24
Finished May 09 02:42:54 PM PDT 24
Peak memory 200444 kb
Host smart-e33803ea-e999-414e-af18-d64d2ce5e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896076967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3896076967
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.823622683
Short name T366
Test name
Test status
Simulation time 45669810362 ps
CPU time 180.14 seconds
Started May 09 02:42:43 PM PDT 24
Finished May 09 02:45:46 PM PDT 24
Peak memory 200456 kb
Host smart-5fa431d4-ceea-489e-857f-6217161486d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823622683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.823622683
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2753998389
Short name T320
Test name
Test status
Simulation time 49235890690 ps
CPU time 20.89 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:43:04 PM PDT 24
Peak memory 200448 kb
Host smart-e99df624-c2bc-4a7f-a353-d3a71b1678c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753998389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2753998389
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.682183116
Short name T1042
Test name
Test status
Simulation time 252837251481 ps
CPU time 1005.22 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:59:29 PM PDT 24
Peak memory 200388 kb
Host smart-2d3b1ec8-3fa7-4a96-afe5-04a8ea41325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682183116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.682183116
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3852537681
Short name T172
Test name
Test status
Simulation time 51914620413 ps
CPU time 26.84 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:11 PM PDT 24
Peak memory 200608 kb
Host smart-cca823e1-5c27-4554-8364-face95c7206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852537681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3852537681
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1172503630
Short name T251
Test name
Test status
Simulation time 53635562318 ps
CPU time 39.97 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 200392 kb
Host smart-b0617846-defc-4228-bc1e-31431aa17efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172503630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1172503630
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.860412280
Short name T162
Test name
Test status
Simulation time 14921984296 ps
CPU time 23.76 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:43:08 PM PDT 24
Peak memory 200308 kb
Host smart-6bd2f22e-ae09-4998-9130-b44309e6f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860412280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.860412280
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2055271706
Short name T947
Test name
Test status
Simulation time 39211688 ps
CPU time 0.56 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 195832 kb
Host smart-694cfb33-9f75-400b-bb4e-29451f768b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055271706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2055271706
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2886424009
Short name T795
Test name
Test status
Simulation time 36078026997 ps
CPU time 20.62 seconds
Started May 09 02:39:41 PM PDT 24
Finished May 09 02:40:03 PM PDT 24
Peak memory 200396 kb
Host smart-3197f5a7-4d50-4619-b6a1-99d5236e5425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886424009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2886424009
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.168749683
Short name T64
Test name
Test status
Simulation time 39601295440 ps
CPU time 48.97 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:40:28 PM PDT 24
Peak memory 199700 kb
Host smart-4d646298-c215-420c-9410-737504315f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168749683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.168749683
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1716432856
Short name T1081
Test name
Test status
Simulation time 194332327616 ps
CPU time 24.78 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:40:02 PM PDT 24
Peak memory 200440 kb
Host smart-712b78e5-53b1-4a58-97fb-6ac0f55b06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716432856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1716432856
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4032171774
Short name T1091
Test name
Test status
Simulation time 6725819670 ps
CPU time 3.12 seconds
Started May 09 02:39:40 PM PDT 24
Finished May 09 02:39:45 PM PDT 24
Peak memory 197132 kb
Host smart-b7de1a24-63b3-4df7-814e-39f9211e7205
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032171774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4032171774
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.824234986
Short name T587
Test name
Test status
Simulation time 122757355082 ps
CPU time 1148.61 seconds
Started May 09 02:39:36 PM PDT 24
Finished May 09 02:58:47 PM PDT 24
Peak memory 200432 kb
Host smart-428e3574-ef89-4a97-8847-dcfc70fcfb18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824234986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.824234986
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2296353054
Short name T1095
Test name
Test status
Simulation time 8218842270 ps
CPU time 17.46 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:39:56 PM PDT 24
Peak memory 200448 kb
Host smart-5b27fb08-e9a9-4c3a-96cf-25f65bb3908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296353054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2296353054
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.1426704929
Short name T821
Test name
Test status
Simulation time 25869647853 ps
CPU time 314.13 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:44:50 PM PDT 24
Peak memory 200416 kb
Host smart-d1e3f632-8d91-4f93-834d-d054768d381b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426704929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1426704929
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2584954523
Short name T855
Test name
Test status
Simulation time 1713881542 ps
CPU time 2.08 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 198832 kb
Host smart-471eeb7b-893d-4aab-9c87-7a163a93b7e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584954523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2584954523
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.448494923
Short name T678
Test name
Test status
Simulation time 70183939889 ps
CPU time 115.61 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:41:31 PM PDT 24
Peak memory 200472 kb
Host smart-4cd6cfd9-4c23-465e-8a9c-4845f3f51826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448494923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.448494923
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1204964518
Short name T319
Test name
Test status
Simulation time 34521447440 ps
CPU time 16.28 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:53 PM PDT 24
Peak memory 196472 kb
Host smart-7fd6d11c-5b29-4818-aac4-8943ada69ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204964518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1204964518
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2295710026
Short name T511
Test name
Test status
Simulation time 657789927 ps
CPU time 1.69 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:39:38 PM PDT 24
Peak memory 198736 kb
Host smart-f251b3e8-bfd0-4f41-a50a-ddeec5237e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295710026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2295710026
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1166740595
Short name T882
Test name
Test status
Simulation time 181133044107 ps
CPU time 861.84 seconds
Started May 09 02:39:38 PM PDT 24
Finished May 09 02:54:02 PM PDT 24
Peak memory 200452 kb
Host smart-22d0f496-f135-4d3b-8afe-d7ded4f06d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166740595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1166740595
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.772296320
Short name T56
Test name
Test status
Simulation time 90427020535 ps
CPU time 225 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 200668 kb
Host smart-d4fa84fd-f584-4696-becc-c7c25f8ce857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772296320 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.772296320
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1105228148
Short name T1079
Test name
Test status
Simulation time 708751519 ps
CPU time 2.3 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:39:39 PM PDT 24
Peak memory 199092 kb
Host smart-c9d3da9b-d93d-45fd-9a62-4cc916fd305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105228148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1105228148
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.995483367
Short name T1040
Test name
Test status
Simulation time 125291718884 ps
CPU time 82.7 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:41:02 PM PDT 24
Peak memory 200224 kb
Host smart-a89fe64d-775b-4135-95a4-1ff359598a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995483367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.995483367
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2552912792
Short name T994
Test name
Test status
Simulation time 53581918071 ps
CPU time 27.27 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:43:11 PM PDT 24
Peak memory 200524 kb
Host smart-6203d2db-61d1-4d23-bb67-3a504bbb53b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552912792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2552912792
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1963040643
Short name T315
Test name
Test status
Simulation time 56305766754 ps
CPU time 26.87 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:43:09 PM PDT 24
Peak memory 200388 kb
Host smart-20c8d1cd-048f-441d-ba7e-45e502e9974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963040643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1963040643
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.361175302
Short name T754
Test name
Test status
Simulation time 14888474997 ps
CPU time 7.21 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:42:53 PM PDT 24
Peak memory 200452 kb
Host smart-0d356948-c12a-468a-8a4b-0f0e6d977b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361175302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.361175302
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.687029677
Short name T600
Test name
Test status
Simulation time 35105172441 ps
CPU time 61.96 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:43:45 PM PDT 24
Peak memory 200428 kb
Host smart-49b88bfd-43f8-4122-ae29-9ccd32953584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687029677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.687029677
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2190245917
Short name T228
Test name
Test status
Simulation time 89453218906 ps
CPU time 165.75 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:45:30 PM PDT 24
Peak memory 200412 kb
Host smart-42251b78-8830-4491-9196-e27381fdb8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190245917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2190245917
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1552372657
Short name T212
Test name
Test status
Simulation time 40397912250 ps
CPU time 37.34 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:43:20 PM PDT 24
Peak memory 200464 kb
Host smart-c58bfacf-d05a-402d-b38a-5d201943af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552372657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1552372657
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2556770127
Short name T218
Test name
Test status
Simulation time 75095466402 ps
CPU time 59.77 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:44 PM PDT 24
Peak memory 200424 kb
Host smart-b1592c78-fa53-46a5-b404-0efce0f7cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556770127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2556770127
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3913029887
Short name T75
Test name
Test status
Simulation time 215156563843 ps
CPU time 310.58 seconds
Started May 09 02:42:40 PM PDT 24
Finished May 09 02:47:55 PM PDT 24
Peak memory 200392 kb
Host smart-3236503c-d8c3-47f7-bc93-1eb7f2c1c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913029887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3913029887
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2291064311
Short name T733
Test name
Test status
Simulation time 15436753 ps
CPU time 0.54 seconds
Started May 09 02:39:39 PM PDT 24
Finished May 09 02:39:41 PM PDT 24
Peak memory 195808 kb
Host smart-779939c9-8cb5-489c-9aa8-7b0148a7c421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291064311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2291064311
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3146444920
Short name T1110
Test name
Test status
Simulation time 57981366903 ps
CPU time 96.32 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:41:16 PM PDT 24
Peak memory 200332 kb
Host smart-8892ba7b-4788-4a59-9a66-a4913920c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146444920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3146444920
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4064988625
Short name T506
Test name
Test status
Simulation time 13755458626 ps
CPU time 13.35 seconds
Started May 09 02:39:36 PM PDT 24
Finished May 09 02:39:52 PM PDT 24
Peak memory 200384 kb
Host smart-f421404a-6647-41bc-b0af-e0706f44f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064988625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4064988625
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2754479852
Short name T588
Test name
Test status
Simulation time 85164578971 ps
CPU time 38.1 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:40:16 PM PDT 24
Peak memory 199788 kb
Host smart-ce7c42b1-1756-47e6-bf83-c1529ed5df17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754479852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2754479852
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1914845963
Short name T777
Test name
Test status
Simulation time 33953788448 ps
CPU time 56.25 seconds
Started May 09 02:39:39 PM PDT 24
Finished May 09 02:40:37 PM PDT 24
Peak memory 198332 kb
Host smart-704bed60-9c57-4c9d-a40e-123c52363e8b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914845963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1914845963
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2785191852
Short name T117
Test name
Test status
Simulation time 69198623753 ps
CPU time 257.23 seconds
Started May 09 02:39:41 PM PDT 24
Finished May 09 02:44:00 PM PDT 24
Peak memory 200408 kb
Host smart-cad7b614-2793-4586-b0fd-212c2a75cfb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785191852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2785191852
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2857879850
Short name T540
Test name
Test status
Simulation time 2714424680 ps
CPU time 5.19 seconds
Started May 09 02:39:32 PM PDT 24
Finished May 09 02:39:39 PM PDT 24
Peak memory 198392 kb
Host smart-d34a0b5f-d71b-455e-9ea0-439d628283a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857879850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2857879850
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4132540736
Short name T891
Test name
Test status
Simulation time 41003569997 ps
CPU time 71.78 seconds
Started May 09 02:39:42 PM PDT 24
Finished May 09 02:40:55 PM PDT 24
Peak memory 200580 kb
Host smart-242bfb53-13b5-44d0-b655-693b8743d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132540736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4132540736
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2760227184
Short name T36
Test name
Test status
Simulation time 6420378509 ps
CPU time 184.92 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:42:42 PM PDT 24
Peak memory 200444 kb
Host smart-42427617-be57-4a9a-b6f0-cba490420677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760227184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2760227184
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2053609549
Short name T745
Test name
Test status
Simulation time 2960189357 ps
CPU time 6.45 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:44 PM PDT 24
Peak memory 198568 kb
Host smart-0c5b243d-2fc3-4963-95ff-b654177f2329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053609549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2053609549
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2905521021
Short name T1018
Test name
Test status
Simulation time 12762674234 ps
CPU time 20.56 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:39:57 PM PDT 24
Peak memory 200044 kb
Host smart-bc9e9538-1f24-4c87-b181-09a7901a38e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905521021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2905521021
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1507135304
Short name T385
Test name
Test status
Simulation time 4067713773 ps
CPU time 1.43 seconds
Started May 09 02:39:39 PM PDT 24
Finished May 09 02:39:42 PM PDT 24
Peak memory 196704 kb
Host smart-318955d3-110c-40aa-bf2d-f00eaedc1eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507135304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1507135304
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.4119490904
Short name T312
Test name
Test status
Simulation time 710079698 ps
CPU time 2.1 seconds
Started May 09 02:39:37 PM PDT 24
Finished May 09 02:39:41 PM PDT 24
Peak memory 199184 kb
Host smart-7457c4da-cc55-48af-94fe-047a123b76dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119490904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4119490904
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2620633144
Short name T895
Test name
Test status
Simulation time 188657909617 ps
CPU time 594.37 seconds
Started May 09 02:39:34 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 216896 kb
Host smart-80ea3423-3b29-43f1-b2f2-f352edf4f486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620633144 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2620633144
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3368655027
Short name T820
Test name
Test status
Simulation time 541259564 ps
CPU time 1.79 seconds
Started May 09 02:39:40 PM PDT 24
Finished May 09 02:39:43 PM PDT 24
Peak memory 198872 kb
Host smart-7f809176-60dc-4eca-ba78-e80216873a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368655027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3368655027
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2251511299
Short name T39
Test name
Test status
Simulation time 12281803878 ps
CPU time 9.27 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:47 PM PDT 24
Peak memory 200452 kb
Host smart-b867a461-e593-49ca-87b4-7bbcb18f15db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251511299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2251511299
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1970901902
Short name T1097
Test name
Test status
Simulation time 56092817181 ps
CPU time 54.09 seconds
Started May 09 02:42:41 PM PDT 24
Finished May 09 02:43:39 PM PDT 24
Peak memory 200400 kb
Host smart-aa3ff0cb-b3ba-4027-947e-79671ef8c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970901902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1970901902
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2271490936
Short name T496
Test name
Test status
Simulation time 163899358701 ps
CPU time 20.19 seconds
Started May 09 02:42:39 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200484 kb
Host smart-b47e1252-929d-4ace-917a-e469d2ba2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271490936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2271490936
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1144533638
Short name T8
Test name
Test status
Simulation time 12521484681 ps
CPU time 8.61 seconds
Started May 09 02:42:52 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200224 kb
Host smart-09d664ec-04da-4ae0-86dc-d78b17cddbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144533638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1144533638
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.711412320
Short name T961
Test name
Test status
Simulation time 103222004419 ps
CPU time 72.88 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:44:07 PM PDT 24
Peak memory 200484 kb
Host smart-88264ead-4f56-484f-a464-33c3eada9fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711412320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.711412320
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3309517705
Short name T232
Test name
Test status
Simulation time 21988829328 ps
CPU time 34.62 seconds
Started May 09 02:42:50 PM PDT 24
Finished May 09 02:43:27 PM PDT 24
Peak memory 200412 kb
Host smart-cd5ac9aa-679f-4253-9183-9263bb912ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309517705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3309517705
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2178390514
Short name T990
Test name
Test status
Simulation time 144774735617 ps
CPU time 130.76 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:45:06 PM PDT 24
Peak memory 200464 kb
Host smart-b23c4c35-9208-4eff-8d26-50418649a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178390514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2178390514
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.414659259
Short name T1010
Test name
Test status
Simulation time 147252412518 ps
CPU time 58.52 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:43:51 PM PDT 24
Peak memory 200480 kb
Host smart-c675ed5e-1832-44c8-9b56-a782019ad28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414659259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.414659259
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.982511771
Short name T45
Test name
Test status
Simulation time 76666020493 ps
CPU time 111.39 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:44:45 PM PDT 24
Peak memory 200472 kb
Host smart-eecd8e07-4035-45ad-94a5-4c2686575647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982511771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.982511771
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3685924119
Short name T76
Test name
Test status
Simulation time 101594431059 ps
CPU time 152.17 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 200292 kb
Host smart-b7262cf1-0ece-41be-8f92-deeda9b11e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685924119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3685924119
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.510773582
Short name T654
Test name
Test status
Simulation time 150272562570 ps
CPU time 149.86 seconds
Started May 09 02:42:54 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 200316 kb
Host smart-5e51997b-e894-47c4-bbd2-f8044d5673e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510773582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.510773582
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1994080830
Short name T713
Test name
Test status
Simulation time 13464454 ps
CPU time 0.56 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:38:26 PM PDT 24
Peak memory 195704 kb
Host smart-3a22ca4b-3e41-43cc-b6a4-ed5bf3fe3cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994080830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1994080830
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2916179459
Short name T567
Test name
Test status
Simulation time 17199023447 ps
CPU time 27.82 seconds
Started May 09 02:38:17 PM PDT 24
Finished May 09 02:38:46 PM PDT 24
Peak memory 200388 kb
Host smart-066ac490-6db5-4c41-8736-063c9a5ade63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916179459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2916179459
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2543627522
Short name T770
Test name
Test status
Simulation time 55700021506 ps
CPU time 25.19 seconds
Started May 09 02:38:17 PM PDT 24
Finished May 09 02:38:43 PM PDT 24
Peak memory 200468 kb
Host smart-c7afb71d-dc52-496d-aeb4-6e1d3a9a3032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543627522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2543627522
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3938043202
Short name T151
Test name
Test status
Simulation time 12480643047 ps
CPU time 19 seconds
Started May 09 02:38:34 PM PDT 24
Finished May 09 02:38:54 PM PDT 24
Peak memory 200216 kb
Host smart-642a703b-624a-4acd-8a81-dfcaa7dbd5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938043202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3938043202
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3594435013
Short name T21
Test name
Test status
Simulation time 28825245298 ps
CPU time 8.78 seconds
Started May 09 02:38:21 PM PDT 24
Finished May 09 02:38:31 PM PDT 24
Peak memory 198948 kb
Host smart-1a9e6f47-78a0-40e2-a090-b40f8dac2523
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594435013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3594435013
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1761818605
Short name T1163
Test name
Test status
Simulation time 87297767564 ps
CPU time 117.09 seconds
Started May 09 02:38:10 PM PDT 24
Finished May 09 02:40:08 PM PDT 24
Peak memory 200416 kb
Host smart-acec0f49-b833-4834-b183-0ab17ebf97cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761818605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1761818605
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3555047329
Short name T673
Test name
Test status
Simulation time 11581735208 ps
CPU time 28.57 seconds
Started May 09 02:38:10 PM PDT 24
Finished May 09 02:38:39 PM PDT 24
Peak memory 200400 kb
Host smart-405656b4-758b-4d1a-b619-4cdcf73eac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555047329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3555047329
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.261570813
Short name T589
Test name
Test status
Simulation time 363600323260 ps
CPU time 217.31 seconds
Started May 09 02:38:02 PM PDT 24
Finished May 09 02:41:40 PM PDT 24
Peak memory 208968 kb
Host smart-85a718d7-de8d-43f0-bb15-49d820bd65ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261570813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.261570813
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2537079570
Short name T351
Test name
Test status
Simulation time 13938140548 ps
CPU time 211.99 seconds
Started May 09 02:38:14 PM PDT 24
Finished May 09 02:41:47 PM PDT 24
Peak memory 200396 kb
Host smart-2aa1e4a9-2196-48bf-a145-80b9e2e209e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537079570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2537079570
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1251288193
Short name T989
Test name
Test status
Simulation time 7064348792 ps
CPU time 65.96 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:39:36 PM PDT 24
Peak memory 198956 kb
Host smart-85bfe931-ca4a-4031-b3dc-4f8a9370a6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251288193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1251288193
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.457177641
Short name T665
Test name
Test status
Simulation time 167411413227 ps
CPU time 92.65 seconds
Started May 09 02:38:02 PM PDT 24
Finished May 09 02:39:36 PM PDT 24
Peak memory 200476 kb
Host smart-52617999-a5f6-4253-bde8-ca635ec0f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457177641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.457177641
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.565396926
Short name T798
Test name
Test status
Simulation time 4470610386 ps
CPU time 7.97 seconds
Started May 09 02:38:26 PM PDT 24
Finished May 09 02:38:41 PM PDT 24
Peak memory 196424 kb
Host smart-e94cbffc-df73-4380-9f24-cc425981f405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565396926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.565396926
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1960373101
Short name T27
Test name
Test status
Simulation time 284301920 ps
CPU time 0.78 seconds
Started May 09 02:38:13 PM PDT 24
Finished May 09 02:38:15 PM PDT 24
Peak memory 218500 kb
Host smart-3d1242cb-7cf2-41ba-8745-c1290254a54b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960373101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1960373101
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1282251763
Short name T721
Test name
Test status
Simulation time 289898718 ps
CPU time 1 seconds
Started May 09 02:38:10 PM PDT 24
Finished May 09 02:38:12 PM PDT 24
Peak memory 200360 kb
Host smart-730d3bbb-79d9-4a01-80ef-35cc996552f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282251763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1282251763
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.906007730
Short name T1083
Test name
Test status
Simulation time 136781048293 ps
CPU time 258.67 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:42:27 PM PDT 24
Peak memory 200384 kb
Host smart-6110d959-7045-41bf-a818-d2ef77f783e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906007730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.906007730
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.249438816
Short name T127
Test name
Test status
Simulation time 121535621200 ps
CPU time 295.1 seconds
Started May 09 02:38:28 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 217084 kb
Host smart-1a2916c2-ec32-4178-b980-e381f1fe42ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249438816 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.249438816
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1438128231
Short name T697
Test name
Test status
Simulation time 6901845002 ps
CPU time 25.05 seconds
Started May 09 02:38:23 PM PDT 24
Finished May 09 02:38:49 PM PDT 24
Peak memory 200292 kb
Host smart-1d0dfbd2-42c4-4a42-a59d-83aaaff71cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438128231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1438128231
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3323234135
Short name T461
Test name
Test status
Simulation time 44187105193 ps
CPU time 81.52 seconds
Started May 09 02:38:22 PM PDT 24
Finished May 09 02:39:44 PM PDT 24
Peak memory 200388 kb
Host smart-9fe01a7d-8e2f-41cd-9526-cffefbeb6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323234135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3323234135
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3681645869
Short name T812
Test name
Test status
Simulation time 42318072 ps
CPU time 0.6 seconds
Started May 09 02:39:48 PM PDT 24
Finished May 09 02:39:49 PM PDT 24
Peak memory 195828 kb
Host smart-b51a4f48-dc67-4f12-9b16-f21049240fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681645869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3681645869
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4156932760
Short name T1144
Test name
Test status
Simulation time 84323874361 ps
CPU time 74.96 seconds
Started May 09 02:39:43 PM PDT 24
Finished May 09 02:40:59 PM PDT 24
Peak memory 200384 kb
Host smart-9395e968-7403-420b-a468-73322cead2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156932760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4156932760
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2882901758
Short name T888
Test name
Test status
Simulation time 156149650702 ps
CPU time 220.1 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 200480 kb
Host smart-8a1e51f9-5fab-4f7e-8921-2150099ce629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882901758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2882901758
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2318549372
Short name T80
Test name
Test status
Simulation time 80303628786 ps
CPU time 72.52 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:40:58 PM PDT 24
Peak memory 200444 kb
Host smart-c843ed21-9b07-45e6-8db0-71411f7048c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318549372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2318549372
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1959842984
Short name T305
Test name
Test status
Simulation time 61443733396 ps
CPU time 102.67 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:41:30 PM PDT 24
Peak memory 200448 kb
Host smart-3a3fae35-398f-4f18-b613-8af4c52613e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959842984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1959842984
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2399876549
Short name T997
Test name
Test status
Simulation time 117478665305 ps
CPU time 492.76 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:47:58 PM PDT 24
Peak memory 200416 kb
Host smart-aa37b6c8-9ccb-4e2d-bc1e-11735baaa687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399876549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2399876549
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1253546600
Short name T704
Test name
Test status
Simulation time 10485439895 ps
CPU time 18.29 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:40:03 PM PDT 24
Peak memory 199792 kb
Host smart-32b13328-c1f4-4c95-928d-e58580491248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253546600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1253546600
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2502451143
Short name T815
Test name
Test status
Simulation time 200876190322 ps
CPU time 104.05 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:41:29 PM PDT 24
Peak memory 200236 kb
Host smart-8a58a770-4b81-4a6c-abbc-66e33bfadaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502451143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2502451143
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3962126052
Short name T681
Test name
Test status
Simulation time 20971487464 ps
CPU time 962.97 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:55:51 PM PDT 24
Peak memory 200436 kb
Host smart-cf5f7dbe-eb32-4fae-98c2-47672f1b82c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962126052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3962126052
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.568370912
Short name T1021
Test name
Test status
Simulation time 3789892607 ps
CPU time 30.4 seconds
Started May 09 02:39:48 PM PDT 24
Finished May 09 02:40:19 PM PDT 24
Peak memory 198820 kb
Host smart-e15dab0c-f005-45cf-a6e3-85b9abb1465a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568370912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.568370912
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.440363328
Short name T503
Test name
Test status
Simulation time 216870153851 ps
CPU time 658.42 seconds
Started May 09 02:39:48 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 200460 kb
Host smart-e8872574-6ff5-40dc-b5fd-3513ccfc9aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440363328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.440363328
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.859041030
Short name T769
Test name
Test status
Simulation time 36576274531 ps
CPU time 13.48 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:40:02 PM PDT 24
Peak memory 196148 kb
Host smart-a088ea97-7707-47b4-b8ae-0ec660b0c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859041030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.859041030
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3455364671
Short name T343
Test name
Test status
Simulation time 502865027 ps
CPU time 2.28 seconds
Started May 09 02:39:35 PM PDT 24
Finished May 09 02:39:40 PM PDT 24
Peak memory 198628 kb
Host smart-470ebf1a-5d92-4ced-b9eb-98675fd5ec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455364671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3455364671
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.202902918
Short name T1146
Test name
Test status
Simulation time 310498078855 ps
CPU time 240.63 seconds
Started May 09 02:39:45 PM PDT 24
Finished May 09 02:43:47 PM PDT 24
Peak memory 200364 kb
Host smart-9fdbb442-84c6-48d4-9792-aebc655eb324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202902918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.202902918
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.4059506911
Short name T999
Test name
Test status
Simulation time 28175588486 ps
CPU time 74.78 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:41:00 PM PDT 24
Peak memory 216268 kb
Host smart-5455d369-e089-4546-9475-a0b95d176dd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059506911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4059506911
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1061813927
Short name T306
Test name
Test status
Simulation time 6729722098 ps
CPU time 9.88 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:39:58 PM PDT 24
Peak memory 199844 kb
Host smart-ca42d527-4b93-4df7-8061-8d5c1d21696d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061813927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1061813927
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3476693574
Short name T1107
Test name
Test status
Simulation time 39370646245 ps
CPU time 74.18 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:41:02 PM PDT 24
Peak memory 200340 kb
Host smart-3b219d5d-bf5f-40f3-b12f-c99ba4cff6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476693574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3476693574
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2136240282
Short name T380
Test name
Test status
Simulation time 12381232 ps
CPU time 0.55 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:39:47 PM PDT 24
Peak memory 194800 kb
Host smart-a913ea4a-472a-45ef-85d4-02225f05c9aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136240282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2136240282
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.506219315
Short name T494
Test name
Test status
Simulation time 171653286298 ps
CPU time 89.56 seconds
Started May 09 02:39:45 PM PDT 24
Finished May 09 02:41:16 PM PDT 24
Peak memory 200432 kb
Host smart-82edf78c-d727-41ab-a85d-0c5d48fd11e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506219315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.506219315
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.613740547
Short name T293
Test name
Test status
Simulation time 24651587828 ps
CPU time 39.35 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:40:25 PM PDT 24
Peak memory 200416 kb
Host smart-e98edc12-81b7-44fd-acef-7bf6e4fe13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613740547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.613740547
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1917544000
Short name T1176
Test name
Test status
Simulation time 41709369364 ps
CPU time 66.97 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:40:54 PM PDT 24
Peak memory 200480 kb
Host smart-67a72c2c-029e-413f-93c7-97de170688ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917544000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1917544000
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2125900490
Short name T1058
Test name
Test status
Simulation time 116351428433 ps
CPU time 103.43 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:41:29 PM PDT 24
Peak memory 200432 kb
Host smart-8da85672-55aa-4728-9417-a2d0557c4f37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125900490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2125900490
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4131761001
Short name T1140
Test name
Test status
Simulation time 108940677739 ps
CPU time 267.99 seconds
Started May 09 02:39:43 PM PDT 24
Finished May 09 02:44:13 PM PDT 24
Peak memory 200424 kb
Host smart-51d29e31-1d92-492d-910e-793e5d361556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131761001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4131761001
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.411190333
Short name T818
Test name
Test status
Simulation time 9665029548 ps
CPU time 21.08 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:40:09 PM PDT 24
Peak memory 200456 kb
Host smart-1759055a-71dc-4912-97ff-0df57896936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411190333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.411190333
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.755450721
Short name T838
Test name
Test status
Simulation time 76291452528 ps
CPU time 113.03 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:41:39 PM PDT 24
Peak memory 200692 kb
Host smart-3ff881c9-38ae-4529-b423-633a9a6d9740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755450721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.755450721
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3191987559
Short name T597
Test name
Test status
Simulation time 13915770980 ps
CPU time 196.29 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200412 kb
Host smart-37cf6603-c6ed-4a4e-9c15-3bf1862c4c16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191987559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3191987559
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.702286349
Short name T1074
Test name
Test status
Simulation time 6278198425 ps
CPU time 9.85 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:39:55 PM PDT 24
Peak memory 198564 kb
Host smart-5fda9e8f-e824-4a01-9c32-6fac339845ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702286349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.702286349
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.572329738
Short name T866
Test name
Test status
Simulation time 50777240243 ps
CPU time 20.59 seconds
Started May 09 02:39:49 PM PDT 24
Finished May 09 02:40:11 PM PDT 24
Peak memory 200452 kb
Host smart-ed4b88b7-54da-4af6-ac12-ab7730178dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572329738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.572329738
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2433391593
Short name T800
Test name
Test status
Simulation time 3898710698 ps
CPU time 7.37 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:39:55 PM PDT 24
Peak memory 196436 kb
Host smart-20ae9784-42d2-40ed-b780-be7f47f1f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433391593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2433391593
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3633485705
Short name T869
Test name
Test status
Simulation time 5354049291 ps
CPU time 9.65 seconds
Started May 09 02:39:43 PM PDT 24
Finished May 09 02:39:54 PM PDT 24
Peak memory 200420 kb
Host smart-2e3836da-9d80-4890-ae15-6a0a2fced5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633485705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3633485705
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1891441369
Short name T137
Test name
Test status
Simulation time 39938936567 ps
CPU time 702.1 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:51:30 PM PDT 24
Peak memory 200480 kb
Host smart-31c9c033-824c-4b73-a334-99a9397e5956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891441369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1891441369
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1684378225
Short name T791
Test name
Test status
Simulation time 88682080556 ps
CPU time 223.27 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:43:29 PM PDT 24
Peak memory 216980 kb
Host smart-cb398180-aeee-4a10-b4e2-419de95c0088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684378225 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1684378225
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2994769174
Short name T404
Test name
Test status
Simulation time 7351885173 ps
CPU time 7.61 seconds
Started May 09 02:39:48 PM PDT 24
Finished May 09 02:39:57 PM PDT 24
Peak memory 200312 kb
Host smart-d4ad9d7e-f8b9-4c5d-97a5-09c760c14cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994769174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2994769174
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3972982615
Short name T326
Test name
Test status
Simulation time 59479058818 ps
CPU time 49.23 seconds
Started May 09 02:39:45 PM PDT 24
Finished May 09 02:40:35 PM PDT 24
Peak memory 200444 kb
Host smart-2accc4c5-94cc-499b-bce8-3a85596a6721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972982615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3972982615
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.452479665
Short name T582
Test name
Test status
Simulation time 13514294 ps
CPU time 0.53 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:39:54 PM PDT 24
Peak memory 195812 kb
Host smart-33b77757-f096-47f3-a9bc-87b7fe45e9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452479665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.452479665
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3096116969
Short name T663
Test name
Test status
Simulation time 146244609236 ps
CPU time 59.14 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:40:45 PM PDT 24
Peak memory 200396 kb
Host smart-8684298e-73e1-47cc-aa01-99bb5ad902e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096116969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3096116969
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2631114470
Short name T338
Test name
Test status
Simulation time 266364050030 ps
CPU time 44.85 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:40:33 PM PDT 24
Peak memory 200416 kb
Host smart-86767e79-3176-437e-a803-4a1923343517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631114470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2631114470
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1096445132
Short name T662
Test name
Test status
Simulation time 114425196285 ps
CPU time 173.04 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:42:39 PM PDT 24
Peak memory 200248 kb
Host smart-9184117c-3a29-4373-a4b3-8a4dccf05bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096445132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1096445132
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3013765386
Short name T672
Test name
Test status
Simulation time 356724768390 ps
CPU time 514.01 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:48:22 PM PDT 24
Peak memory 200368 kb
Host smart-b2f0719a-30a0-4d35-9478-961be60f58e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013765386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3013765386
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1265543892
Short name T696
Test name
Test status
Simulation time 128643214345 ps
CPU time 936.84 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:55:32 PM PDT 24
Peak memory 200640 kb
Host smart-c7525b30-20e1-41fd-bf83-4506bb1e5dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265543892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1265543892
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3367808672
Short name T602
Test name
Test status
Simulation time 11451742556 ps
CPU time 13.12 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:40:08 PM PDT 24
Peak memory 200428 kb
Host smart-ec1a9f8d-04e6-4080-8002-0ab9e1e51893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367808672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3367808672
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3472254657
Short name T655
Test name
Test status
Simulation time 118052049671 ps
CPU time 61.82 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 199764 kb
Host smart-8e475299-fa69-4c54-87b3-9ad617cd51ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472254657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3472254657
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1390289536
Short name T740
Test name
Test status
Simulation time 14859466369 ps
CPU time 501.38 seconds
Started May 09 02:39:52 PM PDT 24
Finished May 09 02:48:14 PM PDT 24
Peak memory 200452 kb
Host smart-b1b32676-fb86-4f1a-b13e-42bce0e30ef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390289536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1390289536
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3829485081
Short name T699
Test name
Test status
Simulation time 6792451953 ps
CPU time 61.25 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 199796 kb
Host smart-25ceedd6-dcf6-4979-af17-86d608917cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829485081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3829485081
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2462883098
Short name T1051
Test name
Test status
Simulation time 7078405156 ps
CPU time 11.69 seconds
Started May 09 02:39:47 PM PDT 24
Finished May 09 02:40:00 PM PDT 24
Peak memory 200380 kb
Host smart-4ebe9171-0e24-4d5d-bb28-492b69fc6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462883098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2462883098
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4081632079
Short name T764
Test name
Test status
Simulation time 3448150887 ps
CPU time 5.91 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:39:53 PM PDT 24
Peak memory 196284 kb
Host smart-919be39a-b4a1-4395-9bfc-285a0dfe8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081632079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4081632079
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2984309400
Short name T878
Test name
Test status
Simulation time 494607730 ps
CPU time 1.54 seconds
Started May 09 02:39:46 PM PDT 24
Finished May 09 02:39:49 PM PDT 24
Peak memory 198992 kb
Host smart-94338d78-9ab4-4d9b-8751-a77ad533fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984309400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2984309400
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.34799071
Short name T864
Test name
Test status
Simulation time 98510079702 ps
CPU time 48.74 seconds
Started May 09 02:39:51 PM PDT 24
Finished May 09 02:40:41 PM PDT 24
Peak memory 200424 kb
Host smart-2b90c3d5-a250-43ca-94e9-d09ebec86cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.34799071
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1491814605
Short name T466
Test name
Test status
Simulation time 98626886303 ps
CPU time 811.53 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:53:27 PM PDT 24
Peak memory 225384 kb
Host smart-da14a3e2-fdc0-45d8-af91-ccb3050b5eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491814605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1491814605
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2319365997
Short name T802
Test name
Test status
Simulation time 8826555990 ps
CPU time 8.57 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:40:04 PM PDT 24
Peak memory 200364 kb
Host smart-f1127c3f-1977-49a5-b7c7-89fef2fdaefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319365997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2319365997
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.942932280
Short name T873
Test name
Test status
Simulation time 38402847817 ps
CPU time 63.77 seconds
Started May 09 02:39:44 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 200476 kb
Host smart-27156194-f237-43ff-accf-ffd5add88554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942932280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.942932280
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2210270950
Short name T408
Test name
Test status
Simulation time 12976234 ps
CPU time 0.62 seconds
Started May 09 02:40:12 PM PDT 24
Finished May 09 02:40:14 PM PDT 24
Peak memory 195800 kb
Host smart-626a70b0-a127-49a8-a4c9-6629f8d58401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210270950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2210270950
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3510837507
Short name T409
Test name
Test status
Simulation time 22617955910 ps
CPU time 34.92 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 200376 kb
Host smart-799c6706-25ad-47c0-89c7-a9ba72359d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510837507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3510837507
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3044812475
Short name T630
Test name
Test status
Simulation time 120582915772 ps
CPU time 191.41 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 200128 kb
Host smart-2eebbeeb-bff9-44b5-a578-dcb8697a37a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044812475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3044812475
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1316927047
Short name T91
Test name
Test status
Simulation time 205108389790 ps
CPU time 164.93 seconds
Started May 09 02:39:56 PM PDT 24
Finished May 09 02:42:43 PM PDT 24
Peak memory 200308 kb
Host smart-0b6a7e77-8c20-4720-ba92-e1d8f5b0d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316927047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1316927047
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1761347737
Short name T840
Test name
Test status
Simulation time 139890485267 ps
CPU time 234.83 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:44:08 PM PDT 24
Peak memory 200124 kb
Host smart-72c3d845-368c-463a-983b-a03d0129cac5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761347737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1761347737
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3102207559
Short name T374
Test name
Test status
Simulation time 204979271977 ps
CPU time 132.73 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:42:26 PM PDT 24
Peak memory 200316 kb
Host smart-875fe36f-3fae-44e4-8a5c-b140a5f7c724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102207559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3102207559
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4216070037
Short name T708
Test name
Test status
Simulation time 10822592570 ps
CPU time 18.63 seconds
Started May 09 02:39:51 PM PDT 24
Finished May 09 02:40:11 PM PDT 24
Peak memory 200388 kb
Host smart-4a02a2da-62f9-4855-b4d8-2b509f65cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216070037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4216070037
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.407333018
Short name T322
Test name
Test status
Simulation time 7180070219 ps
CPU time 7.03 seconds
Started May 09 02:39:52 PM PDT 24
Finished May 09 02:40:00 PM PDT 24
Peak memory 200408 kb
Host smart-e403ec8b-b01d-4399-9f02-b7dd33c38d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407333018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.407333018
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3011516277
Short name T1012
Test name
Test status
Simulation time 12020484474 ps
CPU time 126.67 seconds
Started May 09 02:39:56 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 200448 kb
Host smart-7a2875d5-98cd-4131-9d91-ea20c8599a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011516277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3011516277
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3161580172
Short name T16
Test name
Test status
Simulation time 4733327911 ps
CPU time 37.02 seconds
Started May 09 02:39:51 PM PDT 24
Finished May 09 02:40:30 PM PDT 24
Peak memory 199688 kb
Host smart-6d5af79c-428a-4f68-82cd-d8e10cbc68a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161580172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3161580172
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2547927317
Short name T347
Test name
Test status
Simulation time 18240340726 ps
CPU time 34.21 seconds
Started May 09 02:39:52 PM PDT 24
Finished May 09 02:40:28 PM PDT 24
Peak memory 200336 kb
Host smart-cc1fac2d-ec2e-4076-8a49-7e8ac6497336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547927317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2547927317
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2385317886
Short name T469
Test name
Test status
Simulation time 1811882160 ps
CPU time 3.63 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:17 PM PDT 24
Peak memory 195772 kb
Host smart-7c6b8538-53ea-4977-a16d-aea7edce10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385317886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2385317886
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1607310573
Short name T574
Test name
Test status
Simulation time 102881201 ps
CPU time 0.93 seconds
Started May 09 02:39:57 PM PDT 24
Finished May 09 02:39:59 PM PDT 24
Peak memory 197436 kb
Host smart-8277f163-bc70-41f3-a403-0b18694f0e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607310573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1607310573
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3768179732
Short name T992
Test name
Test status
Simulation time 129468607088 ps
CPU time 469.69 seconds
Started May 09 02:39:55 PM PDT 24
Finished May 09 02:47:47 PM PDT 24
Peak memory 200368 kb
Host smart-f47c0bb0-76d5-4e73-9ce0-4e256ab244e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768179732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3768179732
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.198788568
Short name T55
Test name
Test status
Simulation time 118384592584 ps
CPU time 888.42 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:54:44 PM PDT 24
Peak memory 232908 kb
Host smart-e87f2987-c07c-4cbe-ba1b-ea99b62fb166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198788568 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.198788568
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1029101413
Short name T573
Test name
Test status
Simulation time 1116075248 ps
CPU time 1.17 seconds
Started May 09 02:39:51 PM PDT 24
Finished May 09 02:39:52 PM PDT 24
Peak memory 197652 kb
Host smart-50cf481e-9f97-4855-b9aa-8d379df60a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029101413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1029101413
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3163345200
Short name T452
Test name
Test status
Simulation time 15640107248 ps
CPU time 25.58 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:40:21 PM PDT 24
Peak memory 200412 kb
Host smart-ba60a7ee-e846-479a-86db-c327abca6dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163345200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3163345200
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3797460674
Short name T603
Test name
Test status
Simulation time 46493108 ps
CPU time 0.56 seconds
Started May 09 02:40:05 PM PDT 24
Finished May 09 02:40:07 PM PDT 24
Peak memory 195836 kb
Host smart-722ee083-801e-4f58-be2a-0e8a136d0392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797460674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3797460674
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1482245994
Short name T178
Test name
Test status
Simulation time 39532488707 ps
CPU time 12.36 seconds
Started May 09 02:39:57 PM PDT 24
Finished May 09 02:40:11 PM PDT 24
Peak memory 200428 kb
Host smart-f9c052bb-a0c0-415f-8ac8-755f44317222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482245994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1482245994
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.263196789
Short name T131
Test name
Test status
Simulation time 103580617227 ps
CPU time 238.47 seconds
Started May 09 02:39:52 PM PDT 24
Finished May 09 02:43:51 PM PDT 24
Peak memory 200500 kb
Host smart-8a6223c5-c9f0-4956-8376-6a6ba1d5079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263196789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.263196789
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4086584360
Short name T267
Test name
Test status
Simulation time 155233123852 ps
CPU time 134.25 seconds
Started May 09 02:39:55 PM PDT 24
Finished May 09 02:42:11 PM PDT 24
Peak memory 200348 kb
Host smart-5d74efce-8070-42c6-b571-63931aa1a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086584360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4086584360
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.923262832
Short name T1069
Test name
Test status
Simulation time 46862853536 ps
CPU time 21.54 seconds
Started May 09 02:39:52 PM PDT 24
Finished May 09 02:40:15 PM PDT 24
Peak memory 200480 kb
Host smart-15feb16f-ac71-4301-a6a8-9a05bdf3ea79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923262832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.923262832
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1465644103
Short name T913
Test name
Test status
Simulation time 55323879679 ps
CPU time 109.9 seconds
Started May 09 02:40:00 PM PDT 24
Finished May 09 02:41:52 PM PDT 24
Peak memory 200476 kb
Host smart-a56200dc-ab60-4e6a-a724-268ac682cf22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465644103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1465644103
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.969486152
Short name T425
Test name
Test status
Simulation time 1238123998 ps
CPU time 1.68 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:40:08 PM PDT 24
Peak memory 197784 kb
Host smart-aff07ecb-d31a-4282-b2ff-7b9ff5fdc9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969486152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.969486152
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1984478924
Short name T616
Test name
Test status
Simulation time 254048183535 ps
CPU time 166.53 seconds
Started May 09 02:39:57 PM PDT 24
Finished May 09 02:42:45 PM PDT 24
Peak memory 200548 kb
Host smart-42ab4afc-65dc-46fd-92fc-c5231849b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984478924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1984478924
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3139646816
Short name T330
Test name
Test status
Simulation time 16238884639 ps
CPU time 653.6 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:50:57 PM PDT 24
Peak memory 200424 kb
Host smart-3f3a83cb-04c5-480c-86c9-988bcc582eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139646816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3139646816
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.4171395096
Short name T371
Test name
Test status
Simulation time 4005646351 ps
CPU time 2.44 seconds
Started May 09 02:39:54 PM PDT 24
Finished May 09 02:39:59 PM PDT 24
Peak memory 198368 kb
Host smart-8e42aeec-e8db-4a63-ac03-a63069056994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171395096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4171395096
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4043567177
Short name T37
Test name
Test status
Simulation time 153434331908 ps
CPU time 167.19 seconds
Started May 09 02:39:56 PM PDT 24
Finished May 09 02:42:44 PM PDT 24
Peak memory 200484 kb
Host smart-33a33da4-7f9b-4301-8235-4bc0eff9aec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043567177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4043567177
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3967003810
Short name T739
Test name
Test status
Simulation time 43690894708 ps
CPU time 73.86 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:41:27 PM PDT 24
Peak memory 196424 kb
Host smart-55b9bd52-a734-47ba-a630-32e9004ccd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967003810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3967003810
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3239992791
Short name T491
Test name
Test status
Simulation time 452428741 ps
CPU time 2.29 seconds
Started May 09 02:39:51 PM PDT 24
Finished May 09 02:39:55 PM PDT 24
Peak memory 200180 kb
Host smart-a3e0b654-8a1f-4563-91ef-08843326ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239992791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3239992791
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.135184105
Short name T1141
Test name
Test status
Simulation time 86064611404 ps
CPU time 168.88 seconds
Started May 09 02:40:06 PM PDT 24
Finished May 09 02:42:56 PM PDT 24
Peak memory 200412 kb
Host smart-ca5aa60e-4237-48d1-81ad-12d028d709ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135184105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.135184105
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.115216466
Short name T84
Test name
Test status
Simulation time 6940130317 ps
CPU time 7.9 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:21 PM PDT 24
Peak memory 199604 kb
Host smart-2be407cf-10ed-4f5d-be8d-5c098fa44f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115216466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.115216466
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.501992597
Short name T929
Test name
Test status
Simulation time 134848218543 ps
CPU time 98.81 seconds
Started May 09 02:39:53 PM PDT 24
Finished May 09 02:41:35 PM PDT 24
Peak memory 200440 kb
Host smart-de992f19-56eb-4e67-83f6-5fba3348116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501992597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.501992597
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.658503317
Short name T950
Test name
Test status
Simulation time 19372960 ps
CPU time 0.6 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:04 PM PDT 24
Peak memory 195816 kb
Host smart-74fa8d89-a583-4271-9c5c-af20a1a33d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658503317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.658503317
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3854428960
Short name T168
Test name
Test status
Simulation time 156157279351 ps
CPU time 64.47 seconds
Started May 09 02:40:03 PM PDT 24
Finished May 09 02:41:10 PM PDT 24
Peak memory 200412 kb
Host smart-c993f2a4-1419-4d9a-97a0-d45af3295db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854428960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3854428960
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3288014052
Short name T773
Test name
Test status
Simulation time 98218589441 ps
CPU time 33.11 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:37 PM PDT 24
Peak memory 200344 kb
Host smart-3d4037a5-4b14-4bbf-a5d4-a35bffbbede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288014052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3288014052
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2674831312
Short name T435
Test name
Test status
Simulation time 176350018663 ps
CPU time 28.46 seconds
Started May 09 02:40:00 PM PDT 24
Finished May 09 02:40:30 PM PDT 24
Peak memory 200456 kb
Host smart-7fcedde1-ba33-4032-a24b-28346269f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674831312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2674831312
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.929300954
Short name T829
Test name
Test status
Simulation time 50416981895 ps
CPU time 42.89 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:46 PM PDT 24
Peak memory 200396 kb
Host smart-4db7beaa-f5c9-4b0b-abce-f66198d2aec5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929300954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.929300954
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4140718034
Short name T1152
Test name
Test status
Simulation time 104825743350 ps
CPU time 684.83 seconds
Started May 09 02:40:02 PM PDT 24
Finished May 09 02:51:29 PM PDT 24
Peak memory 200472 kb
Host smart-fa3490c2-88eb-483e-9e85-a6d135926f88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140718034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4140718034
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1097250105
Short name T647
Test name
Test status
Simulation time 8150340544 ps
CPU time 31.14 seconds
Started May 09 02:40:02 PM PDT 24
Finished May 09 02:40:35 PM PDT 24
Peak memory 199544 kb
Host smart-027a192b-c7eb-4c8e-b43b-ff72553d54bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097250105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1097250105
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3654242442
Short name T410
Test name
Test status
Simulation time 27962531261 ps
CPU time 46.46 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:40:52 PM PDT 24
Peak memory 198768 kb
Host smart-4a5d556a-7d09-472f-9bc5-f831904bdc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654242442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3654242442
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.4013221033
Short name T748
Test name
Test status
Simulation time 8271247141 ps
CPU time 252.99 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 200416 kb
Host smart-ad2eeba8-b0f8-4e6f-b892-56fe71f1c67d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013221033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4013221033
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.663179754
Short name T571
Test name
Test status
Simulation time 4502066094 ps
CPU time 39.46 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 199776 kb
Host smart-b5f6e439-523c-4b4e-b13e-67815d523a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663179754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.663179754
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.740878642
Short name T803
Test name
Test status
Simulation time 36876046795 ps
CPU time 64.3 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:41:10 PM PDT 24
Peak memory 200368 kb
Host smart-62f96d86-3666-496a-bf64-6d7e65df18f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740878642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.740878642
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.18380487
Short name T575
Test name
Test status
Simulation time 705900499 ps
CPU time 0.86 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:40:07 PM PDT 24
Peak memory 195808 kb
Host smart-e44a7b17-9a25-4159-995e-26015a9f819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18380487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.18380487
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1282344133
Short name T751
Test name
Test status
Simulation time 666503576 ps
CPU time 4.67 seconds
Started May 09 02:40:02 PM PDT 24
Finished May 09 02:40:09 PM PDT 24
Peak memory 199276 kb
Host smart-d421d69f-4e6b-4258-8b32-09511a069a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282344133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1282344133
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3373754121
Short name T788
Test name
Test status
Simulation time 393608011562 ps
CPU time 163.28 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:42:47 PM PDT 24
Peak memory 200472 kb
Host smart-812caf05-db77-42c8-bcbf-e571b7454292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373754121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3373754121
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2003784189
Short name T692
Test name
Test status
Simulation time 44061441608 ps
CPU time 421.67 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 208856 kb
Host smart-16dd21b9-64a8-467a-a6a1-41a83e617b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003784189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2003784189
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3038380470
Short name T378
Test name
Test status
Simulation time 634987503 ps
CPU time 3 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:06 PM PDT 24
Peak memory 199032 kb
Host smart-97f9cd95-4822-4c61-9ea9-900d7df76c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038380470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3038380470
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2952218039
Short name T941
Test name
Test status
Simulation time 28811213374 ps
CPU time 56.79 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:41:03 PM PDT 24
Peak memory 200408 kb
Host smart-8609caa1-d5ee-499b-a272-74799b236f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952218039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2952218039
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2592742645
Short name T610
Test name
Test status
Simulation time 15031179 ps
CPU time 0.58 seconds
Started May 09 02:40:06 PM PDT 24
Finished May 09 02:40:08 PM PDT 24
Peak memory 195848 kb
Host smart-b452d995-9e0d-48ed-8e40-d10569f00d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592742645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2592742645
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.756194461
Short name T1028
Test name
Test status
Simulation time 168694607620 ps
CPU time 20.83 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:24 PM PDT 24
Peak memory 200336 kb
Host smart-ca581206-4dbd-42a3-b1ca-9e5d82a3950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756194461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.756194461
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.674855592
Short name T303
Test name
Test status
Simulation time 63640946473 ps
CPU time 110.03 seconds
Started May 09 02:40:02 PM PDT 24
Finished May 09 02:41:54 PM PDT 24
Peak memory 200416 kb
Host smart-b8920da8-4a68-41b3-ac0d-39147dc59e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674855592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.674855592
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.471803925
Short name T741
Test name
Test status
Simulation time 26330791917 ps
CPU time 45.38 seconds
Started May 09 02:40:00 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 200428 kb
Host smart-4730ffdb-ce5d-422e-800e-6c1a088a3678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471803925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.471803925
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1800279724
Short name T1156
Test name
Test status
Simulation time 5418188193 ps
CPU time 10.16 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:40:16 PM PDT 24
Peak memory 200576 kb
Host smart-9f0ae78d-21bf-4371-81c7-2a18844d16f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800279724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1800279724
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1692179606
Short name T87
Test name
Test status
Simulation time 129765532724 ps
CPU time 357.14 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:46:00 PM PDT 24
Peak memory 200468 kb
Host smart-5b8beac2-a0f2-4131-b520-fa2d5d28a6fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692179606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1692179606
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.132170005
Short name T644
Test name
Test status
Simulation time 1047962412 ps
CPU time 1.15 seconds
Started May 09 02:40:02 PM PDT 24
Finished May 09 02:40:05 PM PDT 24
Peak memory 196424 kb
Host smart-f7dfcd7a-0b8e-4b50-b4d9-2376a1f4744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132170005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.132170005
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2996164209
Short name T61
Test name
Test status
Simulation time 59277812249 ps
CPU time 48.46 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:52 PM PDT 24
Peak memory 199828 kb
Host smart-8c34b2cd-89d0-4ff8-b74d-86f6a93bbcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996164209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2996164209
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2020196349
Short name T963
Test name
Test status
Simulation time 20242379703 ps
CPU time 189.01 seconds
Started May 09 02:40:12 PM PDT 24
Finished May 09 02:43:23 PM PDT 24
Peak memory 200424 kb
Host smart-4354bfc9-8904-4f6c-a789-2f655ad82ded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020196349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2020196349
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2779741103
Short name T544
Test name
Test status
Simulation time 7699788963 ps
CPU time 19.59 seconds
Started May 09 02:40:05 PM PDT 24
Finished May 09 02:40:26 PM PDT 24
Peak memory 199812 kb
Host smart-91ca4631-50a8-487e-a8d5-19cfa5b76b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779741103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2779741103
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.714217637
Short name T116
Test name
Test status
Simulation time 26954780335 ps
CPU time 44.4 seconds
Started May 09 02:40:01 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 200236 kb
Host smart-1831e363-e5c4-432a-a6c1-aefb7eea2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714217637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.714217637
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.449690626
Short name T317
Test name
Test status
Simulation time 44745337245 ps
CPU time 26.97 seconds
Started May 09 02:40:00 PM PDT 24
Finished May 09 02:40:29 PM PDT 24
Peak memory 196484 kb
Host smart-456a7243-943d-42f2-be8e-d0dbf04ea5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449690626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.449690626
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2651301416
Short name T876
Test name
Test status
Simulation time 5533318726 ps
CPU time 15.36 seconds
Started May 09 02:40:03 PM PDT 24
Finished May 09 02:40:20 PM PDT 24
Peak memory 200380 kb
Host smart-5f524b26-96e5-425f-96e3-a2f34a507e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651301416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2651301416
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.844147974
Short name T1034
Test name
Test status
Simulation time 224345676565 ps
CPU time 117.41 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:42:03 PM PDT 24
Peak memory 200368 kb
Host smart-3eec93b6-7ed1-4310-9c04-d1b3a4be4141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844147974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.844147974
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1679570330
Short name T853
Test name
Test status
Simulation time 18580959984 ps
CPU time 188.66 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:43:15 PM PDT 24
Peak memory 215988 kb
Host smart-e4107d91-ed25-4f8b-8bb1-6d610efca1f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679570330 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1679570330
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1436398340
Short name T479
Test name
Test status
Simulation time 6701191002 ps
CPU time 17.47 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:40:23 PM PDT 24
Peak memory 199476 kb
Host smart-0ff526c2-e54a-42b1-8cc7-608a95778184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436398340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1436398340
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1429546343
Short name T709
Test name
Test status
Simulation time 137221485869 ps
CPU time 167.14 seconds
Started May 09 03:13:21 PM PDT 24
Finished May 09 03:16:09 PM PDT 24
Peak memory 200392 kb
Host smart-0cc94bd1-54ee-47f1-99c2-ed50aaef1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429546343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1429546343
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3899369758
Short name T611
Test name
Test status
Simulation time 12598481 ps
CPU time 0.56 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:18 PM PDT 24
Peak memory 195780 kb
Host smart-d5b4342f-a8d4-413f-8c85-bad60c87ecb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899369758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3899369758
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.440355368
Short name T44
Test name
Test status
Simulation time 115230289498 ps
CPU time 179.61 seconds
Started May 09 02:40:05 PM PDT 24
Finished May 09 02:43:06 PM PDT 24
Peak memory 200484 kb
Host smart-4ac24057-577d-4e1c-b165-2fd5830bb98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440355368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.440355368
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3041027366
Short name T1149
Test name
Test status
Simulation time 117298981421 ps
CPU time 51.69 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:41:04 PM PDT 24
Peak memory 200432 kb
Host smart-ba535469-3771-4e0c-8eaa-ae1ad8c5af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041027366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3041027366
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.804414435
Short name T113
Test name
Test status
Simulation time 54570033011 ps
CPU time 24.66 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:42 PM PDT 24
Peak memory 200440 kb
Host smart-547ce952-a2e2-4e5c-8f03-e1ac576539b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804414435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.804414435
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1353600720
Short name T535
Test name
Test status
Simulation time 24569601902 ps
CPU time 11.73 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:24 PM PDT 24
Peak memory 200460 kb
Host smart-ba097013-3eca-4eb4-988e-cc9bb9d8ec49
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353600720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1353600720
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1672035655
Short name T565
Test name
Test status
Simulation time 83834035453 ps
CPU time 718.89 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:52:16 PM PDT 24
Peak memory 200380 kb
Host smart-017ed48f-6e36-41a5-8412-9a3d8751becd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672035655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1672035655
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2755733345
Short name T421
Test name
Test status
Simulation time 2280576792 ps
CPU time 1.84 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:40:19 PM PDT 24
Peak memory 195896 kb
Host smart-735272dc-0826-4e0f-863b-e77a06dcc77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755733345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2755733345
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.657427971
Short name T909
Test name
Test status
Simulation time 36789371855 ps
CPU time 58.19 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:41:11 PM PDT 24
Peak memory 200664 kb
Host smart-64495953-3bde-4ed3-95ad-18f9b4ce938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657427971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.657427971
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3863712500
Short name T1037
Test name
Test status
Simulation time 4579486543 ps
CPU time 226.1 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:44:03 PM PDT 24
Peak memory 200400 kb
Host smart-993739aa-6011-47e0-b66e-04af518cabd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863712500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3863712500
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3328561164
Short name T685
Test name
Test status
Simulation time 3778356570 ps
CPU time 29.36 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 199604 kb
Host smart-b52e9705-9d8f-4d75-a7bc-f32600caba10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328561164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3328561164
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1711968339
Short name T310
Test name
Test status
Simulation time 28918779283 ps
CPU time 51.48 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:41:10 PM PDT 24
Peak memory 200420 kb
Host smart-3886f46e-1873-4487-8691-5a8a9b416e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711968339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1711968339
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.349038232
Short name T625
Test name
Test status
Simulation time 7086511683 ps
CPU time 2.7 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:20 PM PDT 24
Peak memory 196472 kb
Host smart-21e74ba6-752a-4026-bf89-48844965712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349038232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.349038232
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2244383017
Short name T907
Test name
Test status
Simulation time 6091161144 ps
CPU time 12.61 seconds
Started May 09 02:40:02 PM PDT 24
Finished May 09 02:40:17 PM PDT 24
Peak memory 200240 kb
Host smart-d2c4ff21-a056-43a9-8e25-fe5786997498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244383017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2244383017
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.866762249
Short name T1153
Test name
Test status
Simulation time 200613078652 ps
CPU time 815.1 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:53:52 PM PDT 24
Peak memory 200476 kb
Host smart-04e2b1ce-aa49-4ac5-82f4-8d95550b60b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866762249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.866762249
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.119194370
Short name T1151
Test name
Test status
Simulation time 67495913279 ps
CPU time 289.16 seconds
Started May 09 02:40:15 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 217112 kb
Host smart-c821917f-e447-432f-85ee-10468740532d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119194370 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.119194370
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3718360442
Short name T416
Test name
Test status
Simulation time 8103931351 ps
CPU time 11.43 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:40:28 PM PDT 24
Peak memory 200400 kb
Host smart-e97af338-15b0-4873-819c-cd7c04d292eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718360442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3718360442
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2984876676
Short name T660
Test name
Test status
Simulation time 43035053454 ps
CPU time 39.06 seconds
Started May 09 02:40:04 PM PDT 24
Finished May 09 02:40:45 PM PDT 24
Peak memory 200368 kb
Host smart-aded48a7-7985-42da-9c03-8235f4e15be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984876676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2984876676
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1303634244
Short name T906
Test name
Test status
Simulation time 17368063 ps
CPU time 0.61 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:18 PM PDT 24
Peak memory 195836 kb
Host smart-3de32663-cace-4485-afd2-45881cb9eaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303634244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1303634244
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2062009530
Short name T1136
Test name
Test status
Simulation time 137641991092 ps
CPU time 92.47 seconds
Started May 09 02:40:15 PM PDT 24
Finished May 09 02:41:51 PM PDT 24
Peak memory 200236 kb
Host smart-c18dd1d3-4257-483f-8220-dd08f26639d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062009530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2062009530
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.314291035
Short name T526
Test name
Test status
Simulation time 129020384393 ps
CPU time 244.85 seconds
Started May 09 02:40:15 PM PDT 24
Finished May 09 02:44:23 PM PDT 24
Peak memory 200480 kb
Host smart-41f11f29-7768-4b34-9528-0c7794845c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314291035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.314291035
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.737161017
Short name T270
Test name
Test status
Simulation time 66679576264 ps
CPU time 18.89 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:31 PM PDT 24
Peak memory 200392 kb
Host smart-dc5442fc-3e7b-45ba-86dc-b2bae039be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737161017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.737161017
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.655888950
Short name T1
Test name
Test status
Simulation time 7427940510 ps
CPU time 10.87 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:24 PM PDT 24
Peak memory 197732 kb
Host smart-6d0cf5f0-39e8-4be4-9009-a8a82648defe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655888950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.655888950
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.304889695
Short name T447
Test name
Test status
Simulation time 177059424670 ps
CPU time 326.64 seconds
Started May 09 02:40:15 PM PDT 24
Finished May 09 02:45:45 PM PDT 24
Peak memory 200480 kb
Host smart-171bb3be-1c6d-4782-899f-a8ce4243cb17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304889695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.304889695
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.639365453
Short name T471
Test name
Test status
Simulation time 9007018496 ps
CPU time 19.32 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:38 PM PDT 24
Peak memory 200408 kb
Host smart-8d5ed3c5-2447-4996-89f2-7386c0544d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639365453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.639365453
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.516883519
Short name T1017
Test name
Test status
Simulation time 6197667979 ps
CPU time 12.43 seconds
Started May 09 02:40:10 PM PDT 24
Finished May 09 02:40:24 PM PDT 24
Peak memory 197184 kb
Host smart-44ef0b97-8c15-46e3-ad06-4a647f0b0308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516883519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.516883519
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4283820921
Short name T965
Test name
Test status
Simulation time 18128454444 ps
CPU time 83.76 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:41:36 PM PDT 24
Peak memory 200472 kb
Host smart-250e3154-1333-4630-bd70-1b5cdea14fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283820921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4283820921
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1786874052
Short name T698
Test name
Test status
Simulation time 3482667170 ps
CPU time 7.08 seconds
Started May 09 02:40:14 PM PDT 24
Finished May 09 02:40:24 PM PDT 24
Peak memory 199320 kb
Host smart-6751951b-e770-4fdd-b0c4-a1bd4ec7906f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786874052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1786874052
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.392210822
Short name T932
Test name
Test status
Simulation time 146638996287 ps
CPU time 16.86 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:29 PM PDT 24
Peak memory 200476 kb
Host smart-d82ecc6b-9625-4172-9362-46ada2f30f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392210822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.392210822
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2982277530
Short name T458
Test name
Test status
Simulation time 3554074932 ps
CPU time 5.46 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:40:21 PM PDT 24
Peak memory 196344 kb
Host smart-0f0526ce-6db8-4c83-bf58-026fa289f2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982277530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2982277530
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3637728475
Short name T710
Test name
Test status
Simulation time 737428427 ps
CPU time 2.14 seconds
Started May 09 02:40:15 PM PDT 24
Finished May 09 02:40:21 PM PDT 24
Peak memory 199856 kb
Host smart-52f78494-6aff-40e6-952c-b772e7b5dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637728475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3637728475
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2989922326
Short name T1105
Test name
Test status
Simulation time 24980106851 ps
CPU time 150.2 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 200472 kb
Host smart-da240237-fb79-48c4-bf6d-ae4fa01288a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989922326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2989922326
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.621930969
Short name T123
Test name
Test status
Simulation time 72845552868 ps
CPU time 677.18 seconds
Started May 09 02:40:12 PM PDT 24
Finished May 09 02:51:31 PM PDT 24
Peak memory 216856 kb
Host smart-2fd431a8-b6b3-4d70-ae05-4e4e1e06fd4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621930969 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.621930969
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.232581006
Short name T1124
Test name
Test status
Simulation time 2384952594 ps
CPU time 1.22 seconds
Started May 09 02:40:12 PM PDT 24
Finished May 09 02:40:15 PM PDT 24
Peak memory 199200 kb
Host smart-7b57c011-587d-4ae8-9003-3f709901977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232581006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.232581006
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.685962568
Short name T348
Test name
Test status
Simulation time 14982090189 ps
CPU time 23.58 seconds
Started May 09 02:40:12 PM PDT 24
Finished May 09 02:40:39 PM PDT 24
Peak memory 200420 kb
Host smart-5802febe-4fff-46c2-ba5c-afc0b509554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685962568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.685962568
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2712131834
Short name T975
Test name
Test status
Simulation time 39814000 ps
CPU time 0.56 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:40:27 PM PDT 24
Peak memory 195816 kb
Host smart-857e6391-86c1-4a80-8dce-5c7afe5a381b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712131834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2712131834
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.88193430
Short name T551
Test name
Test status
Simulation time 32461682563 ps
CPU time 16.19 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:40:32 PM PDT 24
Peak memory 200332 kb
Host smart-c039418b-2d1b-4840-abfe-4d857003eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88193430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.88193430
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2169636226
Short name T1035
Test name
Test status
Simulation time 22286531108 ps
CPU time 33.11 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 200436 kb
Host smart-d96ce5ac-8af6-477b-aecc-e9d38093491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169636226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2169636226
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2548576158
Short name T155
Test name
Test status
Simulation time 41328812958 ps
CPU time 54.33 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:41:07 PM PDT 24
Peak memory 200348 kb
Host smart-13879c18-d46f-43a6-8fb0-01b1f17b90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548576158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2548576158
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3116876370
Short name T653
Test name
Test status
Simulation time 3615658246 ps
CPU time 8.23 seconds
Started May 09 02:40:15 PM PDT 24
Finished May 09 02:40:27 PM PDT 24
Peak memory 200124 kb
Host smart-d5c09c78-6d67-42d2-a7e3-99b87d848918
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116876370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3116876370
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1834113618
Short name T417
Test name
Test status
Simulation time 145315464577 ps
CPU time 281.35 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:45:07 PM PDT 24
Peak memory 200452 kb
Host smart-aac0330d-59c8-40ce-9f3b-3193de791ab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834113618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1834113618
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1218318448
Short name T1025
Test name
Test status
Simulation time 5012231630 ps
CPU time 9.79 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:40:39 PM PDT 24
Peak memory 199148 kb
Host smart-39018e63-22b3-4511-9635-7533eed3b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218318448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1218318448
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1909040553
Short name T775
Test name
Test status
Simulation time 447652384322 ps
CPU time 84.94 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:41:50 PM PDT 24
Peak memory 208604 kb
Host smart-55289454-a37d-4993-b78b-d2f730ab8f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909040553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1909040553
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.163621819
Short name T757
Test name
Test status
Simulation time 2976961497 ps
CPU time 79.18 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:41:46 PM PDT 24
Peak memory 200448 kb
Host smart-f8e2244e-8b6a-4863-8551-da7587e8973a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163621819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.163621819
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.531524197
Short name T634
Test name
Test status
Simulation time 5656730178 ps
CPU time 23.98 seconds
Started May 09 02:40:13 PM PDT 24
Finished May 09 02:40:40 PM PDT 24
Peak memory 199668 kb
Host smart-6d93e723-ad5d-4222-8a2d-ddbeb0b1d07f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531524197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.531524197
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2738261835
Short name T639
Test name
Test status
Simulation time 161212871740 ps
CPU time 92.97 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:42:01 PM PDT 24
Peak memory 200092 kb
Host smart-9a909b7e-1c38-4d46-a4a6-9290654f754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738261835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2738261835
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1600133539
Short name T618
Test name
Test status
Simulation time 26972931284 ps
CPU time 10.63 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:40:37 PM PDT 24
Peak memory 196192 kb
Host smart-63d8c439-d280-46d2-9c3e-dc69fe7c2599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600133539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1600133539
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2004057161
Short name T674
Test name
Test status
Simulation time 11582952861 ps
CPU time 17.73 seconds
Started May 09 02:40:11 PM PDT 24
Finished May 09 02:40:31 PM PDT 24
Peak memory 200380 kb
Host smart-fcc09fd5-bdf5-4e3b-ac79-6adf597598c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004057161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2004057161
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.4199076544
Short name T468
Test name
Test status
Simulation time 429611891150 ps
CPU time 161.46 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:43:09 PM PDT 24
Peak memory 216096 kb
Host smart-a07287a2-9add-4e45-bf82-4efee99e522e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199076544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4199076544
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4054775169
Short name T54
Test name
Test status
Simulation time 117674826670 ps
CPU time 411.17 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 213884 kb
Host smart-142ac1db-c5e9-43a1-abd7-fa7fe3a51b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054775169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4054775169
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.272634523
Short name T595
Test name
Test status
Simulation time 2994126775 ps
CPU time 1.86 seconds
Started May 09 02:40:20 PM PDT 24
Finished May 09 02:40:25 PM PDT 24
Peak memory 199200 kb
Host smart-96f1f140-ed0a-4bd1-850f-72aaee4d46e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272634523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.272634523
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2542945849
Short name T703
Test name
Test status
Simulation time 39064276487 ps
CPU time 39.27 seconds
Started May 09 02:40:12 PM PDT 24
Finished May 09 02:40:54 PM PDT 24
Peak memory 200312 kb
Host smart-2e05b28a-a912-49cd-b0ea-31ddc5c826e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542945849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2542945849
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1946803551
Short name T26
Test name
Test status
Simulation time 11804572 ps
CPU time 0.56 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:38:31 PM PDT 24
Peak memory 195780 kb
Host smart-29dcc02b-4f69-4810-a725-61897eed3962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946803551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1946803551
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2606728662
Short name T1154
Test name
Test status
Simulation time 132122924019 ps
CPU time 270.26 seconds
Started May 09 02:38:26 PM PDT 24
Finished May 09 02:42:58 PM PDT 24
Peak memory 200156 kb
Host smart-c2369597-1dbe-41cc-82d5-c0dd123cdb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606728662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2606728662
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1449553039
Short name T700
Test name
Test status
Simulation time 32099318311 ps
CPU time 47.85 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:38:56 PM PDT 24
Peak memory 200392 kb
Host smart-0f797090-f4e6-4f0f-8900-f45e8f0cb15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449553039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1449553039
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2428535742
Short name T847
Test name
Test status
Simulation time 155355120782 ps
CPU time 90.89 seconds
Started May 09 02:38:10 PM PDT 24
Finished May 09 02:39:42 PM PDT 24
Peak memory 200420 kb
Host smart-4a7583bf-7b74-437d-9f49-4d38c942acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428535742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2428535742
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2858165245
Short name T668
Test name
Test status
Simulation time 21848678415 ps
CPU time 7.6 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:38:46 PM PDT 24
Peak memory 197404 kb
Host smart-ecccd867-071d-4a97-8888-c2d1ac6c5cf7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858165245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2858165245
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1516282686
Short name T572
Test name
Test status
Simulation time 91827660751 ps
CPU time 282.07 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:43:13 PM PDT 24
Peak memory 200404 kb
Host smart-6d59f1e4-4e66-41fa-9e97-cc897eca7e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516282686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1516282686
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4027052822
Short name T400
Test name
Test status
Simulation time 861552572 ps
CPU time 0.75 seconds
Started May 09 02:38:12 PM PDT 24
Finished May 09 02:38:14 PM PDT 24
Peak memory 196524 kb
Host smart-70e17af3-77db-4fcd-a96e-583031763eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027052822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4027052822
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3932627872
Short name T1126
Test name
Test status
Simulation time 44903171551 ps
CPU time 36.05 seconds
Started May 09 02:38:17 PM PDT 24
Finished May 09 02:38:54 PM PDT 24
Peak memory 200648 kb
Host smart-3f812366-7e7f-4412-b3a6-de39bfafc92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932627872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3932627872
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1489742733
Short name T884
Test name
Test status
Simulation time 12355062360 ps
CPU time 708.05 seconds
Started May 09 02:38:10 PM PDT 24
Finished May 09 02:49:59 PM PDT 24
Peak memory 200424 kb
Host smart-f34870f7-f05c-4d2a-bafa-485467fefe18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489742733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1489742733
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1835364497
Short name T515
Test name
Test status
Simulation time 5487602025 ps
CPU time 44.81 seconds
Started May 09 02:38:09 PM PDT 24
Finished May 09 02:38:55 PM PDT 24
Peak memory 199564 kb
Host smart-3302a7db-617c-490f-94cb-9ffd9f64eb36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835364497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1835364497
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2087825391
Short name T443
Test name
Test status
Simulation time 26603750114 ps
CPU time 11.73 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:38:38 PM PDT 24
Peak memory 199088 kb
Host smart-5d537b90-caa8-42b6-a85e-4139e5c2d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087825391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2087825391
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.278521151
Short name T440
Test name
Test status
Simulation time 5049160439 ps
CPU time 4.84 seconds
Started May 09 02:38:08 PM PDT 24
Finished May 09 02:38:14 PM PDT 24
Peak memory 196752 kb
Host smart-6d5b5e39-3efc-4660-a6bf-0dada729d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278521151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.278521151
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3966512231
Short name T111
Test name
Test status
Simulation time 129104522 ps
CPU time 0.83 seconds
Started May 09 02:38:23 PM PDT 24
Finished May 09 02:38:25 PM PDT 24
Peak memory 218668 kb
Host smart-c5e97efd-01ed-422e-8825-ffd7b05f93e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966512231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3966512231
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2464641979
Short name T279
Test name
Test status
Simulation time 488546206 ps
CPU time 1.07 seconds
Started May 09 02:38:22 PM PDT 24
Finished May 09 02:38:24 PM PDT 24
Peak memory 198492 kb
Host smart-79939085-bab7-4b6d-a3ed-ec74089d70a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464641979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2464641979
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.172397006
Short name T983
Test name
Test status
Simulation time 310513598273 ps
CPU time 1082.27 seconds
Started May 09 02:38:32 PM PDT 24
Finished May 09 02:56:36 PM PDT 24
Peak memory 200404 kb
Host smart-5178b63c-7f4e-488c-9176-f90c500c83e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172397006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.172397006
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.573182327
Short name T810
Test name
Test status
Simulation time 8056974640 ps
CPU time 8.07 seconds
Started May 09 02:38:09 PM PDT 24
Finished May 09 02:38:18 PM PDT 24
Peak memory 199792 kb
Host smart-6b733400-e50c-48e8-b6cb-5c5cc78b463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573182327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.573182327
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1384426115
Short name T328
Test name
Test status
Simulation time 94426551354 ps
CPU time 26.31 seconds
Started May 09 02:38:13 PM PDT 24
Finished May 09 02:38:40 PM PDT 24
Peak memory 200440 kb
Host smart-d746d4f4-6871-460e-bc7e-51af1a0137f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384426115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1384426115
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1651673838
Short name T467
Test name
Test status
Simulation time 38492614966 ps
CPU time 30.36 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:40:59 PM PDT 24
Peak memory 200232 kb
Host smart-498cb75b-6c12-4a7e-8458-1211579f04ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651673838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1651673838
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2298498554
Short name T189
Test name
Test status
Simulation time 70122376093 ps
CPU time 98.51 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:42:08 PM PDT 24
Peak memory 200396 kb
Host smart-298a1b1d-829b-4466-bdca-0b40803651e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298498554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2298498554
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2716518460
Short name T1030
Test name
Test status
Simulation time 80274251194 ps
CPU time 135.15 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:42:40 PM PDT 24
Peak memory 200372 kb
Host smart-ecdcd4e9-9ce7-4d3c-bda8-886b61c10238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716518460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2716518460
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.686006852
Short name T755
Test name
Test status
Simulation time 28877709047 ps
CPU time 15.31 seconds
Started May 09 02:40:26 PM PDT 24
Finished May 09 02:40:45 PM PDT 24
Peak memory 200160 kb
Host smart-a00de78a-cf29-4b91-a9d5-d8e3bc28e487
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686006852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.686006852
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2200601706
Short name T1094
Test name
Test status
Simulation time 176456611142 ps
CPU time 121.29 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:42:30 PM PDT 24
Peak memory 200424 kb
Host smart-23602731-9fbf-4c66-b6ea-2df37e472903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200601706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2200601706
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1561504239
Short name T822
Test name
Test status
Simulation time 4779224837 ps
CPU time 5.23 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:40:35 PM PDT 24
Peak memory 198764 kb
Host smart-e2045de5-c8d0-4ab4-b706-dbc55b391023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561504239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1561504239
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2368898632
Short name T624
Test name
Test status
Simulation time 36043071502 ps
CPU time 16.45 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:40:44 PM PDT 24
Peak memory 198724 kb
Host smart-aa6b83ba-2cf1-48f4-8e25-6ee54ea4ea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368898632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2368898632
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2313490636
Short name T507
Test name
Test status
Simulation time 10835111802 ps
CPU time 588.38 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 200444 kb
Host smart-b449c39b-5f72-496d-a8d0-7c180f4cc631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313490636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2313490636
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.963241543
Short name T856
Test name
Test status
Simulation time 6279541808 ps
CPU time 29.58 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:40:55 PM PDT 24
Peak memory 198344 kb
Host smart-cdffeb5f-3bee-454b-bd07-a3af313325f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963241543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.963241543
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2145069123
Short name T308
Test name
Test status
Simulation time 11689268316 ps
CPU time 21.34 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 200452 kb
Host smart-3994b747-2717-45fd-8e58-e02a5a180233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145069123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2145069123
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3383158895
Short name T401
Test name
Test status
Simulation time 1913462683 ps
CPU time 2.07 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:40:27 PM PDT 24
Peak memory 195828 kb
Host smart-adbd8503-bbe0-4ce6-8788-47d8bbf6bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383158895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3383158895
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3901041454
Short name T1019
Test name
Test status
Simulation time 246946448 ps
CPU time 1.69 seconds
Started May 09 02:40:28 PM PDT 24
Finished May 09 02:40:33 PM PDT 24
Peak memory 200296 kb
Host smart-7f54eb58-c1da-449b-aa35-578ae2ada664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901041454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3901041454
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.251609954
Short name T801
Test name
Test status
Simulation time 89681433157 ps
CPU time 36.28 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:41:04 PM PDT 24
Peak memory 200404 kb
Host smart-b9bab5cb-1155-457b-b048-db53d5aa94fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251609954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.251609954
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1880335741
Short name T765
Test name
Test status
Simulation time 96198673825 ps
CPU time 1186.68 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 03:00:14 PM PDT 24
Peak memory 225300 kb
Host smart-a44525b6-6dc7-4c92-b4e2-286c805d6c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880335741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1880335741
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2409738671
Short name T439
Test name
Test status
Simulation time 1718585008 ps
CPU time 2.65 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:40:30 PM PDT 24
Peak memory 200264 kb
Host smart-c5467095-874d-4904-b803-4d78edb4e449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409738671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2409738671
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1505807276
Short name T1056
Test name
Test status
Simulation time 51540204896 ps
CPU time 58.65 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:41:24 PM PDT 24
Peak memory 200404 kb
Host smart-6f8070bd-ddd4-4159-b51c-39a9db682c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505807276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1505807276
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2637503258
Short name T772
Test name
Test status
Simulation time 10389474 ps
CPU time 0.53 seconds
Started May 09 02:40:27 PM PDT 24
Finished May 09 02:40:31 PM PDT 24
Peak memory 195824 kb
Host smart-7214e437-330f-40fc-82d8-c8eb392b3d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637503258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2637503258
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.970522038
Short name T688
Test name
Test status
Simulation time 167593432697 ps
CPU time 263.29 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:44:49 PM PDT 24
Peak memory 200508 kb
Host smart-0c4e6686-c286-462b-b79b-82ef36477f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970522038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.970522038
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3745404341
Short name T1009
Test name
Test status
Simulation time 81282314292 ps
CPU time 38.08 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:41:05 PM PDT 24
Peak memory 200384 kb
Host smart-da07cba2-3f5e-4722-9c83-1198d63885c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745404341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3745404341
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3761706190
Short name T234
Test name
Test status
Simulation time 20177545804 ps
CPU time 40.54 seconds
Started May 09 02:40:20 PM PDT 24
Finished May 09 02:41:04 PM PDT 24
Peak memory 200420 kb
Host smart-4622972e-f181-401a-8920-50b3d95d55db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761706190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3761706190
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2433421986
Short name T813
Test name
Test status
Simulation time 43658324285 ps
CPU time 72.36 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:41:39 PM PDT 24
Peak memory 200448 kb
Host smart-e1df52b7-a178-4743-941c-74d13fe963f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433421986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2433421986
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2240609938
Short name T1008
Test name
Test status
Simulation time 81191100397 ps
CPU time 542.36 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 200480 kb
Host smart-2301e258-51d0-46bd-9ea7-aca6022bb48a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240609938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2240609938
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3092345470
Short name T363
Test name
Test status
Simulation time 4529707900 ps
CPU time 3.63 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:40:32 PM PDT 24
Peak memory 198884 kb
Host smart-a2c8bdb2-117f-43b9-9848-5fd7218b787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092345470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3092345470
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2622184507
Short name T480
Test name
Test status
Simulation time 25956992563 ps
CPU time 42.99 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:41:10 PM PDT 24
Peak memory 198552 kb
Host smart-41db0125-1167-4843-bea2-865c0445446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622184507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2622184507
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3233416184
Short name T1000
Test name
Test status
Simulation time 11905773011 ps
CPU time 583.57 seconds
Started May 09 02:40:26 PM PDT 24
Finished May 09 02:50:14 PM PDT 24
Peak memory 200380 kb
Host smart-942a70c5-e77f-4e02-b61b-74befa3f20c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233416184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3233416184
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3712353441
Short name T484
Test name
Test status
Simulation time 3906431647 ps
CPU time 28.6 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:40:54 PM PDT 24
Peak memory 198428 kb
Host smart-902b828a-15e4-4c1c-855b-69fb81e9a10d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712353441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3712353441
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1841531336
Short name T836
Test name
Test status
Simulation time 18113995343 ps
CPU time 27.93 seconds
Started May 09 02:40:28 PM PDT 24
Finished May 09 02:40:59 PM PDT 24
Peak memory 200404 kb
Host smart-05c3bb89-c441-4256-9ec1-b6389ad5732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841531336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1841531336
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.562025487
Short name T570
Test name
Test status
Simulation time 3405775967 ps
CPU time 2.03 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:40:31 PM PDT 24
Peak memory 196452 kb
Host smart-3e41d49a-06dd-44cd-ab0c-e93a88a60f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562025487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.562025487
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2998515660
Short name T1039
Test name
Test status
Simulation time 489222719 ps
CPU time 1.03 seconds
Started May 09 02:40:22 PM PDT 24
Finished May 09 02:40:26 PM PDT 24
Peak memory 198960 kb
Host smart-a95a4db4-d2be-4496-b87b-5207f68d5bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998515660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2998515660
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3921125801
Short name T608
Test name
Test status
Simulation time 143857024184 ps
CPU time 872.3 seconds
Started May 09 02:40:26 PM PDT 24
Finished May 09 02:55:02 PM PDT 24
Peak memory 200464 kb
Host smart-2f627bd9-9b4e-4c0c-b842-ce7eed4d4e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921125801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3921125801
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1373385592
Short name T585
Test name
Test status
Simulation time 646874326379 ps
CPU time 531.15 seconds
Started May 09 02:40:26 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 227768 kb
Host smart-90b9fd2d-1515-4a02-a8bd-116e4a4b1e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373385592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1373385592
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3562498807
Short name T579
Test name
Test status
Simulation time 6352548572 ps
CPU time 12.27 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:40:41 PM PDT 24
Peak memory 200268 kb
Host smart-6557f141-6891-4466-83ae-47f66bf280fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562498807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3562498807
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2370609559
Short name T316
Test name
Test status
Simulation time 82309437765 ps
CPU time 138.67 seconds
Started May 09 02:40:21 PM PDT 24
Finished May 09 02:42:43 PM PDT 24
Peak memory 200480 kb
Host smart-733cd4c6-7a57-4cfa-a498-d9ab9f664f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370609559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2370609559
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1379602166
Short name T1118
Test name
Test status
Simulation time 28342326 ps
CPU time 0.55 seconds
Started May 09 02:40:33 PM PDT 24
Finished May 09 02:40:36 PM PDT 24
Peak memory 195796 kb
Host smart-d9508e8f-a5ec-4d56-98f1-e1f16f280c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379602166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1379602166
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.144969171
Short name T553
Test name
Test status
Simulation time 211056862749 ps
CPU time 134.21 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:42:42 PM PDT 24
Peak memory 200376 kb
Host smart-3553bbc4-8c2b-4e10-8b67-39fbcecdd298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144969171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.144969171
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3804102808
Short name T429
Test name
Test status
Simulation time 140660264047 ps
CPU time 62.69 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:41:31 PM PDT 24
Peak memory 200368 kb
Host smart-f71ced26-b531-4d52-80b4-e9b05308b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804102808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3804102808
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.413477756
Short name T883
Test name
Test status
Simulation time 66163533906 ps
CPU time 65.31 seconds
Started May 09 02:40:26 PM PDT 24
Finished May 09 02:41:35 PM PDT 24
Peak memory 200404 kb
Host smart-d6af039e-8d20-42ee-a556-717ad22a241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413477756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.413477756
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.748814520
Short name T528
Test name
Test status
Simulation time 39262847061 ps
CPU time 17.83 seconds
Started May 09 02:40:25 PM PDT 24
Finished May 09 02:40:47 PM PDT 24
Peak memory 200256 kb
Host smart-d5565b61-5aaf-4e95-8127-e3cc1429718e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748814520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.748814520
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2813673615
Short name T1114
Test name
Test status
Simulation time 376945883741 ps
CPU time 212.23 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:44:07 PM PDT 24
Peak memory 200420 kb
Host smart-75c14644-70a7-4f17-8dd6-71a319fb2555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813673615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2813673615
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3011527899
Short name T894
Test name
Test status
Simulation time 1572940185 ps
CPU time 3.51 seconds
Started May 09 02:40:34 PM PDT 24
Finished May 09 02:40:40 PM PDT 24
Peak memory 199872 kb
Host smart-f968f06e-8700-4464-9b68-cf0e3e735892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011527899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3011527899
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.779562051
Short name T734
Test name
Test status
Simulation time 45494463909 ps
CPU time 14.43 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 200396 kb
Host smart-64774a3b-252f-49d4-98f9-a8f323498aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779562051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.779562051
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.999616236
Short name T379
Test name
Test status
Simulation time 8829157547 ps
CPU time 341.99 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:46:17 PM PDT 24
Peak memory 200280 kb
Host smart-d48aa651-58c1-4d3a-b47b-ec5df7ee05de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999616236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.999616236
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2873505122
Short name T951
Test name
Test status
Simulation time 6858090569 ps
CPU time 61.47 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:41:29 PM PDT 24
Peak memory 198680 kb
Host smart-a0593fa4-bab2-4d52-85c5-6e9104f9004e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873505122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2873505122
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1424340760
Short name T1072
Test name
Test status
Simulation time 31211177720 ps
CPU time 57.67 seconds
Started May 09 02:40:26 PM PDT 24
Finished May 09 02:41:28 PM PDT 24
Peak memory 200400 kb
Host smart-cd1e5092-3972-461a-81f7-a61d29215e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424340760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1424340760
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.295074321
Short name T1082
Test name
Test status
Simulation time 37668586207 ps
CPU time 14.47 seconds
Started May 09 02:40:24 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 196732 kb
Host smart-ac2a7950-c79b-474c-a6eb-6f11a1d7a2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295074321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.295074321
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1925627175
Short name T922
Test name
Test status
Simulation time 6194375859 ps
CPU time 12.76 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:40:40 PM PDT 24
Peak memory 200296 kb
Host smart-b3476809-48a5-41b1-a8f3-ac231469d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925627175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1925627175
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1619089544
Short name T486
Test name
Test status
Simulation time 250111580341 ps
CPU time 194.72 seconds
Started May 09 02:40:33 PM PDT 24
Finished May 09 02:43:51 PM PDT 24
Peak memory 216864 kb
Host smart-d518bf74-5675-477a-86d5-7ff0a376e7e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619089544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1619089544
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1511709435
Short name T121
Test name
Test status
Simulation time 54970068126 ps
CPU time 751.84 seconds
Started May 09 02:40:33 PM PDT 24
Finished May 09 02:53:08 PM PDT 24
Peak memory 216812 kb
Host smart-64718c02-5034-4bf6-9cad-d116a442e58b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511709435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1511709435
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2122112933
Short name T414
Test name
Test status
Simulation time 703958777 ps
CPU time 2.67 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:40:38 PM PDT 24
Peak memory 200296 kb
Host smart-03e4f606-7572-4a35-a2e3-b4c509169840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122112933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2122112933
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.418401837
Short name T1158
Test name
Test status
Simulation time 34167363572 ps
CPU time 19.76 seconds
Started May 09 02:40:23 PM PDT 24
Finished May 09 02:40:47 PM PDT 24
Peak memory 200520 kb
Host smart-bbd50cd5-60f9-4b91-9174-235576af234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418401837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.418401837
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2710739342
Short name T1168
Test name
Test status
Simulation time 18835999 ps
CPU time 0.54 seconds
Started May 09 02:40:35 PM PDT 24
Finished May 09 02:40:38 PM PDT 24
Peak memory 195824 kb
Host smart-1713c018-d2d6-44ca-b503-69a724a7fd14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710739342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2710739342
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1186956977
Short name T9
Test name
Test status
Simulation time 105274542146 ps
CPU time 143.35 seconds
Started May 09 02:40:35 PM PDT 24
Finished May 09 02:43:00 PM PDT 24
Peak memory 200424 kb
Host smart-42ae0f43-a4a4-4ef3-b2c1-9c85c4eed197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186956977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1186956977
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3145470185
Short name T1121
Test name
Test status
Simulation time 124858374037 ps
CPU time 81.51 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:41:56 PM PDT 24
Peak memory 200508 kb
Host smart-b85e5a1b-bf7f-42df-b0f1-c64bab25cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145470185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3145470185
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.685352333
Short name T1052
Test name
Test status
Simulation time 14752455758 ps
CPU time 31.6 seconds
Started May 09 02:40:32 PM PDT 24
Finished May 09 02:41:07 PM PDT 24
Peak memory 200420 kb
Host smart-a4d26a00-f8db-49a1-868a-3d2db715498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685352333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.685352333
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3380168949
Short name T489
Test name
Test status
Simulation time 31522241181 ps
CPU time 56.64 seconds
Started May 09 02:40:34 PM PDT 24
Finished May 09 02:41:33 PM PDT 24
Peak memory 200412 kb
Host smart-5df5e3e2-6b4e-4a6a-ac81-6e8b75a96b9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380168949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3380168949
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.590452206
Short name T323
Test name
Test status
Simulation time 108853348481 ps
CPU time 1080.63 seconds
Started May 09 02:40:32 PM PDT 24
Finished May 09 02:58:36 PM PDT 24
Peak memory 200456 kb
Host smart-87ba5c4f-1654-4cae-b4a4-77bbba8dcf59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590452206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.590452206
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2442181383
Short name T358
Test name
Test status
Simulation time 5877340943 ps
CPU time 6.22 seconds
Started May 09 02:40:34 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 198512 kb
Host smart-7927b754-9a2a-49e1-943e-9d82489a17cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442181383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2442181383
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3318832569
Short name T675
Test name
Test status
Simulation time 96842073150 ps
CPU time 67.75 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:41:42 PM PDT 24
Peak memory 200608 kb
Host smart-95d7e0d0-5aa2-463c-aa38-f9f651b0a002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318832569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3318832569
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2639480612
Short name T1041
Test name
Test status
Simulation time 7634836742 ps
CPU time 410.58 seconds
Started May 09 02:40:32 PM PDT 24
Finished May 09 02:47:26 PM PDT 24
Peak memory 200480 kb
Host smart-89f641eb-23a0-4a19-b9c4-6fdad0c05834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639480612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2639480612
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.94415654
Short name T369
Test name
Test status
Simulation time 2844513990 ps
CPU time 5.57 seconds
Started May 09 02:40:30 PM PDT 24
Finished May 09 02:40:39 PM PDT 24
Peak memory 199128 kb
Host smart-7b16feae-5ab9-474e-bcde-906d8f925d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94415654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.94415654
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.28219653
Short name T74
Test name
Test status
Simulation time 16298030290 ps
CPU time 33.84 seconds
Started May 09 02:40:33 PM PDT 24
Finished May 09 02:41:10 PM PDT 24
Peak memory 200144 kb
Host smart-d73da838-f4f7-4032-bb87-7d66f30c1b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28219653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.28219653
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4193046250
Short name T973
Test name
Test status
Simulation time 4880108715 ps
CPU time 7.6 seconds
Started May 09 02:40:33 PM PDT 24
Finished May 09 02:40:43 PM PDT 24
Peak memory 196436 kb
Host smart-1dbc3308-3034-4bb8-a01b-302eb58f6bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193046250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4193046250
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.714604305
Short name T346
Test name
Test status
Simulation time 6313704997 ps
CPU time 5.99 seconds
Started May 09 02:40:32 PM PDT 24
Finished May 09 02:40:42 PM PDT 24
Peak memory 200244 kb
Host smart-fa786dd7-418e-40e8-8eb2-55f433eb4763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714604305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.714604305
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.845292306
Short name T716
Test name
Test status
Simulation time 249681540325 ps
CPU time 1187.3 seconds
Started May 09 02:40:35 PM PDT 24
Finished May 09 03:00:24 PM PDT 24
Peak memory 200480 kb
Host smart-6a57a80c-f4ee-41f7-9dbb-a444abb8b3a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845292306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.845292306
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2461017812
Short name T50
Test name
Test status
Simulation time 33295969297 ps
CPU time 84.16 seconds
Started May 09 02:40:32 PM PDT 24
Finished May 09 02:42:00 PM PDT 24
Peak memory 216080 kb
Host smart-8818c6b0-c0d5-4610-96a6-c8ff7d72b74f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461017812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2461017812
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.922028311
Short name T649
Test name
Test status
Simulation time 1035088669 ps
CPU time 2.1 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:40:37 PM PDT 24
Peak memory 198976 kb
Host smart-76259dd9-f9ed-4515-8e60-a6996193f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922028311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.922028311
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3815903667
Short name T689
Test name
Test status
Simulation time 30243852155 ps
CPU time 28.05 seconds
Started May 09 02:40:34 PM PDT 24
Finished May 09 02:41:05 PM PDT 24
Peak memory 200404 kb
Host smart-94801a7b-8f58-490b-a5b5-112af3043035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815903667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3815903667
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3348645324
Short name T377
Test name
Test status
Simulation time 19980482 ps
CPU time 0.54 seconds
Started May 09 02:40:43 PM PDT 24
Finished May 09 02:40:45 PM PDT 24
Peak memory 195788 kb
Host smart-3102d6f3-3e07-47fc-9ae9-14abb6c065b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348645324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3348645324
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.684904882
Short name T134
Test name
Test status
Simulation time 180509984008 ps
CPU time 271.33 seconds
Started May 09 02:40:31 PM PDT 24
Finished May 09 02:45:06 PM PDT 24
Peak memory 200412 kb
Host smart-14838272-43cc-47d5-bf4d-a9bd6fa50ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684904882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.684904882
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.395642238
Short name T148
Test name
Test status
Simulation time 17980146115 ps
CPU time 32.67 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:41:17 PM PDT 24
Peak memory 200336 kb
Host smart-688bef2b-daff-4ec3-9062-1cde7d4d4320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395642238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.395642238
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.2666987481
Short name T391
Test name
Test status
Simulation time 74530488326 ps
CPU time 24.29 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:41:11 PM PDT 24
Peak memory 200332 kb
Host smart-afe406b3-3c84-4dca-a7e1-89c6dbd95a95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666987481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2666987481
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3903218628
Short name T46
Test name
Test status
Simulation time 59652623218 ps
CPU time 451.12 seconds
Started May 09 02:40:43 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 200400 kb
Host smart-396056fe-eb98-4af3-8551-c1e37b0e86aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903218628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3903218628
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2546884380
Short name T1109
Test name
Test status
Simulation time 5196418742 ps
CPU time 6.69 seconds
Started May 09 02:40:43 PM PDT 24
Finished May 09 02:40:51 PM PDT 24
Peak memory 200164 kb
Host smart-d462b139-4120-4b17-9485-da1ffbe95459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546884380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2546884380
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.187909448
Short name T1128
Test name
Test status
Simulation time 40049913576 ps
CPU time 32.04 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:41:16 PM PDT 24
Peak memory 198124 kb
Host smart-3291c909-3b18-4a39-b04d-bbcae5947240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187909448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.187909448
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3832722098
Short name T857
Test name
Test status
Simulation time 13832861785 ps
CPU time 666.04 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:51:50 PM PDT 24
Peak memory 200480 kb
Host smart-946e74f7-b65d-460d-a069-30a5172b32ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832722098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3832722098
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.355982111
Short name T554
Test name
Test status
Simulation time 4309047045 ps
CPU time 23.97 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:41:07 PM PDT 24
Peak memory 199180 kb
Host smart-fa25da0a-6ce7-4e26-8cb3-ed7c53a0f784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355982111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.355982111
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.654573496
Short name T179
Test name
Test status
Simulation time 35399744969 ps
CPU time 20.53 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:41:08 PM PDT 24
Peak memory 200408 kb
Host smart-fde15cfb-291c-44e5-8173-ef35f0671aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654573496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.654573496
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.722783416
Short name T1159
Test name
Test status
Simulation time 3195163114 ps
CPU time 2.41 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 196260 kb
Host smart-b74b0ad8-befa-4a50-b727-e44334f597c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722783416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.722783416
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.539277217
Short name T659
Test name
Test status
Simulation time 658783604 ps
CPU time 1.75 seconds
Started May 09 02:40:34 PM PDT 24
Finished May 09 02:40:38 PM PDT 24
Peak memory 199340 kb
Host smart-a7be5b9a-a371-4a50-8b02-e04758e7f6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539277217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.539277217
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1153512704
Short name T264
Test name
Test status
Simulation time 572243832073 ps
CPU time 102.82 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:42:28 PM PDT 24
Peak memory 200580 kb
Host smart-0e38010c-de26-4fd2-874d-00ee12e16d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153512704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1153512704
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1623480712
Short name T197
Test name
Test status
Simulation time 82709953111 ps
CPU time 289.81 seconds
Started May 09 02:40:43 PM PDT 24
Finished May 09 02:45:35 PM PDT 24
Peak memory 215292 kb
Host smart-9d5053b7-9c43-44e6-a973-699ee35fa67c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623480712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1623480712
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.233413624
Short name T463
Test name
Test status
Simulation time 1722077208 ps
CPU time 1.8 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:40:45 PM PDT 24
Peak memory 199080 kb
Host smart-6aef3f7f-5106-4357-88fc-5e4f79c22825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233413624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.233413624
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2544486999
Short name T296
Test name
Test status
Simulation time 15151106733 ps
CPU time 14.52 seconds
Started May 09 02:40:34 PM PDT 24
Finished May 09 02:40:51 PM PDT 24
Peak memory 200244 kb
Host smart-bb324fe2-44ac-426b-9d89-faa452a2c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544486999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2544486999
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1972159353
Short name T386
Test name
Test status
Simulation time 42327732 ps
CPU time 0.56 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:40:48 PM PDT 24
Peak memory 195836 kb
Host smart-9f46c4c8-2a52-480e-9076-1a2d9d56720a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972159353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1972159353
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1651912583
Short name T707
Test name
Test status
Simulation time 91980607938 ps
CPU time 161.24 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:43:29 PM PDT 24
Peak memory 200392 kb
Host smart-06ccf9e9-32a5-4a5f-b673-5f0c5c21517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651912583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1651912583
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.26494584
Short name T581
Test name
Test status
Simulation time 9619549280 ps
CPU time 7.67 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:54 PM PDT 24
Peak memory 198996 kb
Host smart-d34ca2bd-ec5e-40a8-a6b1-35e36831a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26494584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.26494584
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3765077968
Short name T760
Test name
Test status
Simulation time 226650225927 ps
CPU time 137.46 seconds
Started May 09 02:40:43 PM PDT 24
Finished May 09 02:43:03 PM PDT 24
Peak memory 200416 kb
Host smart-02afaa27-5ade-4ff5-bbea-54472fbda5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765077968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3765077968
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.4166882211
Short name T937
Test name
Test status
Simulation time 53066865581 ps
CPU time 93.15 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:42:16 PM PDT 24
Peak memory 200416 kb
Host smart-016182d0-7ec9-4caf-998d-f32ae5d82186
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166882211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.4166882211
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.3791198665
Short name T799
Test name
Test status
Simulation time 7838159245 ps
CPU time 8.04 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:55 PM PDT 24
Peak memory 199724 kb
Host smart-9d0a2270-f2a9-4666-96f6-3565b4cddd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791198665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3791198665
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3959964713
Short name T128
Test name
Test status
Simulation time 23273604139 ps
CPU time 37.43 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:41:20 PM PDT 24
Peak memory 199008 kb
Host smart-7b3d2e2e-f0c3-46e1-beb3-fb57d1fa34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959964713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3959964713
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.923021637
Short name T382
Test name
Test status
Simulation time 10521968994 ps
CPU time 166.33 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:43:34 PM PDT 24
Peak memory 200396 kb
Host smart-d4b3ae74-6596-438f-b0e6-8d5e54c87905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923021637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.923021637
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2126958577
Short name T982
Test name
Test status
Simulation time 3079328134 ps
CPU time 10.2 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:40:57 PM PDT 24
Peak memory 199360 kb
Host smart-acf8aacd-18e1-4924-a32d-a23afcb22038
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126958577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2126958577
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2344997912
Short name T804
Test name
Test status
Simulation time 87123085580 ps
CPU time 32.89 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:41:20 PM PDT 24
Peak memory 200428 kb
Host smart-d3c3d14e-fda6-4a73-b858-e71c7ba56e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344997912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2344997912
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2582744733
Short name T1112
Test name
Test status
Simulation time 3989154491 ps
CPU time 3.83 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:50 PM PDT 24
Peak memory 196424 kb
Host smart-fb060cbb-4ac3-4e91-af04-595b9647b617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582744733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2582744733
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2448511710
Short name T1172
Test name
Test status
Simulation time 884092274 ps
CPU time 3.44 seconds
Started May 09 02:40:42 PM PDT 24
Finished May 09 02:40:47 PM PDT 24
Peak memory 198748 kb
Host smart-7242c787-0317-482a-8aa5-6abed67f0c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448511710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2448511710
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1364261029
Short name T797
Test name
Test status
Simulation time 258762593211 ps
CPU time 395.97 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 208780 kb
Host smart-e11dcc74-4dc5-4dda-b30a-a1531964c23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364261029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1364261029
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1209379267
Short name T843
Test name
Test status
Simulation time 2360020426 ps
CPU time 2.24 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 198980 kb
Host smart-66d438b5-f079-4c7a-8818-d272506c4295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209379267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1209379267
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.493307518
Short name T1090
Test name
Test status
Simulation time 42850027299 ps
CPU time 9.36 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:55 PM PDT 24
Peak memory 198356 kb
Host smart-eca82e27-9794-4c7e-af12-2dff0af41725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493307518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.493307518
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.244310046
Short name T428
Test name
Test status
Simulation time 44171907 ps
CPU time 0.58 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:40:54 PM PDT 24
Peak memory 196012 kb
Host smart-f24a9182-87f4-43b7-a035-63382829ddc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244310046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.244310046
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.434818517
Short name T779
Test name
Test status
Simulation time 93459862504 ps
CPU time 44.32 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:41:42 PM PDT 24
Peak memory 200396 kb
Host smart-c12f11a2-0693-48b0-bbe5-98745a2b3e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434818517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.434818517
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.499555493
Short name T921
Test name
Test status
Simulation time 78356260911 ps
CPU time 153.76 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:43:29 PM PDT 24
Peak memory 200380 kb
Host smart-96252c45-3ab3-4038-ac94-68c8d7093a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499555493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.499555493
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1606292443
Short name T845
Test name
Test status
Simulation time 55236482279 ps
CPU time 22.03 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:41:19 PM PDT 24
Peak memory 199352 kb
Host smart-eff9eaea-0dd7-447e-a59d-85fda1bec089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606292443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1606292443
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2164476508
Short name T744
Test name
Test status
Simulation time 16209763142 ps
CPU time 29.72 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:41:24 PM PDT 24
Peak memory 200456 kb
Host smart-c6cd8640-5b1e-41c6-8f46-5e79ec57873b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164476508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2164476508
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.697480328
Short name T445
Test name
Test status
Simulation time 79283990680 ps
CPU time 611.12 seconds
Started May 09 02:40:57 PM PDT 24
Finished May 09 02:51:10 PM PDT 24
Peak memory 200468 kb
Host smart-b760dbc7-96e7-421d-99ab-a22e012ba389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697480328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.697480328
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3814643102
Short name T59
Test name
Test status
Simulation time 2157127483 ps
CPU time 4.46 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:41:02 PM PDT 24
Peak memory 196532 kb
Host smart-d2322136-b8b6-4cfe-b511-f887a77fb820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814643102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3814643102
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1425630357
Short name T646
Test name
Test status
Simulation time 12667637736 ps
CPU time 20.01 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:41:15 PM PDT 24
Peak memory 198100 kb
Host smart-c28e6148-30e0-443f-af5b-cdc34aca4329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425630357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1425630357
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2779348072
Short name T846
Test name
Test status
Simulation time 8650309990 ps
CPU time 329.63 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:46:27 PM PDT 24
Peak memory 200412 kb
Host smart-0ef2fb0a-49f9-4ef6-9827-aeb50bfb4eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779348072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2779348072
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1186438528
Short name T617
Test name
Test status
Simulation time 5750277806 ps
CPU time 12.2 seconds
Started May 09 02:40:59 PM PDT 24
Finished May 09 02:41:12 PM PDT 24
Peak memory 198308 kb
Host smart-a1fa2d18-58c2-42be-ae03-9e5df04dafa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186438528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1186438528
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1728136642
Short name T898
Test name
Test status
Simulation time 169993619872 ps
CPU time 67.98 seconds
Started May 09 02:40:54 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 200452 kb
Host smart-ac46d04d-1898-4df2-a464-6e86912c5632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728136642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1728136642
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3738394072
Short name T294
Test name
Test status
Simulation time 3508003745 ps
CPU time 6.17 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:41:04 PM PDT 24
Peak memory 196448 kb
Host smart-6a94c870-af32-42c4-97ab-18361aa80eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738394072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3738394072
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3096170337
Short name T852
Test name
Test status
Simulation time 711062356 ps
CPU time 2.64 seconds
Started May 09 02:40:44 PM PDT 24
Finished May 09 02:40:49 PM PDT 24
Peak memory 198996 kb
Host smart-1d0eabef-b2fd-4df3-ba6c-6ef2c551eb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096170337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3096170337
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3381506911
Short name T354
Test name
Test status
Simulation time 24418204057 ps
CPU time 294.55 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:45:49 PM PDT 24
Peak memory 217128 kb
Host smart-213406f4-5143-48e6-be9c-30e1138f076b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381506911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3381506911
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2444334018
Short name T1033
Test name
Test status
Simulation time 987408026 ps
CPU time 1.98 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:40:57 PM PDT 24
Peak memory 199044 kb
Host smart-fc5e480b-54a3-4079-ab4f-ef37c615a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444334018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2444334018
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1537836668
Short name T814
Test name
Test status
Simulation time 47119092316 ps
CPU time 72.8 seconds
Started May 09 02:40:45 PM PDT 24
Finished May 09 02:42:00 PM PDT 24
Peak memory 200472 kb
Host smart-957d8467-2f10-46d1-8be3-65db3022c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537836668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1537836668
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2697101769
Short name T1087
Test name
Test status
Simulation time 11452904 ps
CPU time 0.55 seconds
Started May 09 02:40:54 PM PDT 24
Finished May 09 02:40:57 PM PDT 24
Peak memory 194812 kb
Host smart-3c3f984d-2a21-4d0a-abfe-ca623036e779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697101769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2697101769
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.408514710
Short name T762
Test name
Test status
Simulation time 57156591978 ps
CPU time 84.09 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:42:20 PM PDT 24
Peak memory 200372 kb
Host smart-04828d5f-35e6-49ea-9fbc-a6947320af2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408514710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.408514710
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1758081964
Short name T174
Test name
Test status
Simulation time 154357034005 ps
CPU time 294.46 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 200484 kb
Host smart-f8d01f0b-c0eb-4df2-83e1-7bbe29460ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758081964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1758081964
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.609963506
Short name T1001
Test name
Test status
Simulation time 280708973968 ps
CPU time 535.92 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:49:51 PM PDT 24
Peak memory 200368 kb
Host smart-80401b83-732b-4a9e-a7d8-6e8c823af65d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609963506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.609963506
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3683447034
Short name T284
Test name
Test status
Simulation time 54599101890 ps
CPU time 357.21 seconds
Started May 09 02:40:54 PM PDT 24
Finished May 09 02:46:54 PM PDT 24
Peak memory 200388 kb
Host smart-40fe1e3b-5c58-4ee5-842d-806b625013f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683447034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3683447034
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1400689466
Short name T563
Test name
Test status
Simulation time 3542188088 ps
CPU time 2.58 seconds
Started May 09 02:40:51 PM PDT 24
Finished May 09 02:40:56 PM PDT 24
Peak memory 199252 kb
Host smart-eb64b2fe-4fa6-4853-9e84-1297ad4ffb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400689466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1400689466
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3114572725
Short name T887
Test name
Test status
Simulation time 3244635985 ps
CPU time 6.25 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:41:02 PM PDT 24
Peak memory 195328 kb
Host smart-387c7813-aab9-44a3-b260-d90fce436835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114572725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3114572725
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1155135289
Short name T861
Test name
Test status
Simulation time 1819940222 ps
CPU time 72.56 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:42:08 PM PDT 24
Peak memory 200388 kb
Host smart-957b3e8e-6c85-447e-ac28-0b015e3adaa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155135289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1155135289
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2759254697
Short name T360
Test name
Test status
Simulation time 5342541428 ps
CPU time 22.9 seconds
Started May 09 02:40:59 PM PDT 24
Finished May 09 02:41:23 PM PDT 24
Peak memory 199652 kb
Host smart-90f347b6-b2ba-4cda-a990-b9fb44ec1fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759254697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2759254697
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.851606414
Short name T282
Test name
Test status
Simulation time 49322409931 ps
CPU time 57.71 seconds
Started May 09 02:40:55 PM PDT 24
Finished May 09 02:41:55 PM PDT 24
Peak memory 200424 kb
Host smart-dd4f6212-17f1-4ef4-b2e0-44b89dd6f1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851606414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.851606414
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3704645026
Short name T905
Test name
Test status
Simulation time 6129844688 ps
CPU time 3.46 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:41:00 PM PDT 24
Peak memory 196476 kb
Host smart-fe292c6f-ddb7-4cdd-bc95-c7c23682a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704645026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3704645026
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3789049656
Short name T854
Test name
Test status
Simulation time 688431732 ps
CPU time 2.47 seconds
Started May 09 02:40:59 PM PDT 24
Finished May 09 02:41:03 PM PDT 24
Peak memory 200328 kb
Host smart-642dadc9-6672-4ed6-9c9e-854fb4d6033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789049656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3789049656
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1788612738
Short name T514
Test name
Test status
Simulation time 244514235559 ps
CPU time 341.46 seconds
Started May 09 02:40:53 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 208768 kb
Host smart-61d8b0bc-b5ee-4bf0-9938-aa696d3f2b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788612738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1788612738
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.945698981
Short name T1057
Test name
Test status
Simulation time 1003602986 ps
CPU time 1.34 seconds
Started May 09 02:40:54 PM PDT 24
Finished May 09 02:40:58 PM PDT 24
Peak memory 199064 kb
Host smart-d980b516-2877-4233-a1e5-ae7e9d23a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945698981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.945698981
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1772927240
Short name T1086
Test name
Test status
Simulation time 47464324769 ps
CPU time 17.88 seconds
Started May 09 02:40:51 PM PDT 24
Finished May 09 02:41:11 PM PDT 24
Peak memory 200208 kb
Host smart-56c95ee4-4d31-4559-9ded-ab04853b1d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772927240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1772927240
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.794859835
Short name T2
Test name
Test status
Simulation time 39484313 ps
CPU time 0.57 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:41:05 PM PDT 24
Peak memory 194792 kb
Host smart-903b3ba1-9f61-4473-90e0-256d0a958d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794859835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.794859835
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1336857864
Short name T642
Test name
Test status
Simulation time 18056513121 ps
CPU time 13.9 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:41:19 PM PDT 24
Peak memory 200444 kb
Host smart-028ced14-f070-4f54-8419-f701196527f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336857864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1336857864
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.838478048
Short name T196
Test name
Test status
Simulation time 28478064624 ps
CPU time 27.74 seconds
Started May 09 02:41:07 PM PDT 24
Finished May 09 02:41:36 PM PDT 24
Peak memory 200396 kb
Host smart-b97f0dc4-ad79-456d-a26c-6aba77bb1497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838478048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.838478048
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1341925035
Short name T1023
Test name
Test status
Simulation time 20746576685 ps
CPU time 33.36 seconds
Started May 09 02:41:02 PM PDT 24
Finished May 09 02:41:37 PM PDT 24
Peak memory 200448 kb
Host smart-3e7174ae-ec7b-4a03-8987-41b2ce7fd409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341925035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1341925035
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2419436905
Short name T742
Test name
Test status
Simulation time 29236550068 ps
CPU time 17.52 seconds
Started May 09 02:41:07 PM PDT 24
Finished May 09 02:41:26 PM PDT 24
Peak memory 200424 kb
Host smart-0f861298-985b-423c-8bc2-21972651e163
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419436905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2419436905
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2665179304
Short name T729
Test name
Test status
Simulation time 61121997053 ps
CPU time 432.75 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 200384 kb
Host smart-90796511-44b8-4eb0-a6ef-7e6bac0fba89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665179304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2665179304
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1912258846
Short name T537
Test name
Test status
Simulation time 446834996 ps
CPU time 1.51 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:41:06 PM PDT 24
Peak memory 197772 kb
Host smart-c37b376a-0d12-4457-a15a-f03297f1a401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912258846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1912258846
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2228406786
Short name T868
Test name
Test status
Simulation time 351845640489 ps
CPU time 116.99 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200564 kb
Host smart-083ac19e-3e7b-4fe6-803a-6ad2cbaa953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228406786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2228406786
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3757864289
Short name T451
Test name
Test status
Simulation time 4907639213 ps
CPU time 77.81 seconds
Started May 09 02:41:04 PM PDT 24
Finished May 09 02:42:24 PM PDT 24
Peak memory 200464 kb
Host smart-fe357bec-a8d0-449d-8198-ef170cd16e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757864289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3757864289
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.801085423
Short name T402
Test name
Test status
Simulation time 4949887912 ps
CPU time 12.02 seconds
Started May 09 02:41:04 PM PDT 24
Finished May 09 02:41:18 PM PDT 24
Peak memory 199140 kb
Host smart-60621d9a-312c-4510-93c8-d45fc1537879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801085423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.801085423
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.564833603
Short name T955
Test name
Test status
Simulation time 5398864760 ps
CPU time 8.94 seconds
Started May 09 02:41:01 PM PDT 24
Finished May 09 02:41:11 PM PDT 24
Peak memory 200416 kb
Host smart-9acf67f8-1aa2-4d6c-bb48-dcad2a4e8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564833603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.564833603
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1235943750
Short name T324
Test name
Test status
Simulation time 4322463377 ps
CPU time 8.11 seconds
Started May 09 02:41:07 PM PDT 24
Finished May 09 02:41:16 PM PDT 24
Peak memory 196456 kb
Host smart-dc4c0658-ddcf-4549-b74a-d681019428a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235943750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1235943750
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3136333360
Short name T761
Test name
Test status
Simulation time 666058321 ps
CPU time 2.77 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:40:58 PM PDT 24
Peak memory 198872 kb
Host smart-4bc8466b-a143-4b5b-9890-e09ffbbc980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136333360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3136333360
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.863171966
Short name T1157
Test name
Test status
Simulation time 617132978853 ps
CPU time 236.45 seconds
Started May 09 02:41:09 PM PDT 24
Finished May 09 02:45:07 PM PDT 24
Peak memory 200424 kb
Host smart-04cc6ccb-1f9a-4fed-b69b-b4e14f7dfe01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863171966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.863171966
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2638463426
Short name T550
Test name
Test status
Simulation time 35436601326 ps
CPU time 418.91 seconds
Started May 09 02:41:04 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 216844 kb
Host smart-53b69bca-1212-4925-b5f1-2f90b8d2a319
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638463426 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2638463426
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1026851512
Short name T763
Test name
Test status
Simulation time 1492801114 ps
CPU time 1.93 seconds
Started May 09 02:41:01 PM PDT 24
Finished May 09 02:41:05 PM PDT 24
Peak memory 199900 kb
Host smart-3a6f8dd7-6d9e-4a5e-86c8-c17e4340665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026851512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1026851512
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2435885182
Short name T667
Test name
Test status
Simulation time 339007409713 ps
CPU time 80.13 seconds
Started May 09 02:40:52 PM PDT 24
Finished May 09 02:42:14 PM PDT 24
Peak memory 200464 kb
Host smart-435f6ae3-c291-4812-8a38-bb8915e54d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435885182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2435885182
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4246139006
Short name T1084
Test name
Test status
Simulation time 56085322 ps
CPU time 0.65 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:41:17 PM PDT 24
Peak memory 195168 kb
Host smart-f91184d8-8711-43c6-9cd9-f3810686cfd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246139006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4246139006
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1908522178
Short name T195
Test name
Test status
Simulation time 54727252846 ps
CPU time 36.84 seconds
Started May 09 02:41:10 PM PDT 24
Finished May 09 02:41:48 PM PDT 24
Peak memory 200468 kb
Host smart-d3e4e145-1fda-441d-a99e-bf2ea7f833b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908522178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1908522178
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3566945148
Short name T65
Test name
Test status
Simulation time 412849738786 ps
CPU time 42.86 seconds
Started May 09 02:41:10 PM PDT 24
Finished May 09 02:41:55 PM PDT 24
Peak memory 200464 kb
Host smart-295b3705-5dc8-4036-9cc7-edbaa330c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566945148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3566945148
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.64424199
Short name T958
Test name
Test status
Simulation time 111978909334 ps
CPU time 37.53 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:41:43 PM PDT 24
Peak memory 200408 kb
Host smart-b8ec63c4-eb4e-4512-995a-a925659bcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64424199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.64424199
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3678958710
Short name T619
Test name
Test status
Simulation time 3554634212 ps
CPU time 1.04 seconds
Started May 09 02:41:04 PM PDT 24
Finished May 09 02:41:07 PM PDT 24
Peak memory 197036 kb
Host smart-12de5e60-866e-424a-9f1c-eded2df0cb40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678958710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3678958710
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2927200933
Short name T430
Test name
Test status
Simulation time 119610429023 ps
CPU time 918.78 seconds
Started May 09 02:41:18 PM PDT 24
Finished May 09 02:56:38 PM PDT 24
Peak memory 200416 kb
Host smart-bcd3bbc1-1e3f-452d-be92-7982cfb0fe9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927200933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2927200933
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.530095179
Short name T636
Test name
Test status
Simulation time 2555749228 ps
CPU time 5.85 seconds
Started May 09 02:41:04 PM PDT 24
Finished May 09 02:41:12 PM PDT 24
Peak memory 199576 kb
Host smart-4df01ac6-604c-454a-8d4c-c19c4be838fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530095179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.530095179
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1152264176
Short name T584
Test name
Test status
Simulation time 39041034824 ps
CPU time 59.83 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 199568 kb
Host smart-dfc9e294-a330-4e0d-bb4d-9613c7156b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152264176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1152264176
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3173743857
Short name T946
Test name
Test status
Simulation time 24393203650 ps
CPU time 518.05 seconds
Started May 09 02:41:01 PM PDT 24
Finished May 09 02:49:40 PM PDT 24
Peak memory 200408 kb
Host smart-c1d8aaa1-db91-4977-a78c-128404425092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173743857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3173743857
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1501526134
Short name T1085
Test name
Test status
Simulation time 6546446893 ps
CPU time 58.55 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 199100 kb
Host smart-1f583186-22f4-4ee9-8b9d-bfec0321b551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501526134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1501526134
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1729123911
Short name T959
Test name
Test status
Simulation time 166502180028 ps
CPU time 63.22 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:42:08 PM PDT 24
Peak memory 200352 kb
Host smart-f2790ada-33ea-47ec-b0e9-4f3515a416b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729123911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1729123911
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.69570875
Short name T509
Test name
Test status
Simulation time 4691446764 ps
CPU time 4.5 seconds
Started May 09 02:41:11 PM PDT 24
Finished May 09 02:41:17 PM PDT 24
Peak memory 196492 kb
Host smart-bf9ef4ab-60e2-4909-a55f-0c2a2d1af753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69570875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.69570875
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1959491460
Short name T539
Test name
Test status
Simulation time 6235594278 ps
CPU time 9.92 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:41:16 PM PDT 24
Peak memory 200104 kb
Host smart-92f58647-42f7-49ea-9834-7c376ea061e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959491460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1959491460
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1370816599
Short name T177
Test name
Test status
Simulation time 483980390357 ps
CPU time 465.26 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:49:01 PM PDT 24
Peak memory 216252 kb
Host smart-2732188d-d6a5-48be-87da-aa4fb684a93f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370816599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1370816599
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2675924671
Short name T1049
Test name
Test status
Simulation time 346276923551 ps
CPU time 846.61 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:55:21 PM PDT 24
Peak memory 225292 kb
Host smart-901a8196-93ef-469c-9a13-d204e60e3fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675924671 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2675924671
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2577922830
Short name T313
Test name
Test status
Simulation time 6022335375 ps
CPU time 19.12 seconds
Started May 09 02:41:02 PM PDT 24
Finished May 09 02:41:23 PM PDT 24
Peak memory 200316 kb
Host smart-ebb50f47-38dd-4264-aa72-8ea72568d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577922830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2577922830
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2756525953
Short name T750
Test name
Test status
Simulation time 171845852839 ps
CPU time 60.86 seconds
Started May 09 02:41:03 PM PDT 24
Finished May 09 02:42:05 PM PDT 24
Peak memory 200476 kb
Host smart-78458c76-fa43-4cba-a3eb-a1e37d223e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756525953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2756525953
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2813554778
Short name T758
Test name
Test status
Simulation time 32311463 ps
CPU time 0.55 seconds
Started May 09 02:38:24 PM PDT 24
Finished May 09 02:38:26 PM PDT 24
Peak memory 195300 kb
Host smart-4ccb2731-d5e4-4607-8369-503c7668ad4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813554778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2813554778
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3717709643
Short name T564
Test name
Test status
Simulation time 69884109033 ps
CPU time 74.45 seconds
Started May 09 02:38:18 PM PDT 24
Finished May 09 02:39:34 PM PDT 24
Peak memory 200440 kb
Host smart-93f890b1-ba80-4ea8-84e4-615eb5a8b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717709643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3717709643
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3233130824
Short name T512
Test name
Test status
Simulation time 71420721619 ps
CPU time 114.63 seconds
Started May 09 02:38:21 PM PDT 24
Finished May 09 02:40:16 PM PDT 24
Peak memory 200396 kb
Host smart-ae26e6b3-884c-4f9b-97e0-a5cf6c0d280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233130824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3233130824
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.172075649
Short name T576
Test name
Test status
Simulation time 371521747471 ps
CPU time 113.8 seconds
Started May 09 02:38:28 PM PDT 24
Finished May 09 02:40:23 PM PDT 24
Peak memory 200324 kb
Host smart-77da59c1-5d8e-4e87-a7db-6aac9b997369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172075649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.172075649
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3495996987
Short name T444
Test name
Test status
Simulation time 21210658303 ps
CPU time 11.06 seconds
Started May 09 02:38:23 PM PDT 24
Finished May 09 02:38:35 PM PDT 24
Peak memory 200144 kb
Host smart-429999fd-1f78-4e82-b681-87faaf09b7b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495996987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3495996987
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3517317800
Short name T81
Test name
Test status
Simulation time 175684184637 ps
CPU time 277.19 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:43:04 PM PDT 24
Peak memory 200428 kb
Host smart-a741c46f-e0e4-4bd3-97a5-5f375f3c64db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517317800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3517317800
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2388590827
Short name T499
Test name
Test status
Simulation time 7160844355 ps
CPU time 4.7 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:38:30 PM PDT 24
Peak memory 199720 kb
Host smart-fcd55627-df51-4edc-a18a-e0a9230a5839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388590827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2388590827
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3491383896
Short name T1014
Test name
Test status
Simulation time 25305820764 ps
CPU time 48.86 seconds
Started May 09 02:38:31 PM PDT 24
Finished May 09 02:39:21 PM PDT 24
Peak memory 198808 kb
Host smart-459a2c2f-c529-41e4-ad2c-bab4b872810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491383896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3491383896
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2032495527
Short name T513
Test name
Test status
Simulation time 14459422158 ps
CPU time 593.21 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 200644 kb
Host smart-c5e3a470-6254-4cce-9414-fbe494119099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032495527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2032495527
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1042165160
Short name T552
Test name
Test status
Simulation time 2227536643 ps
CPU time 5.64 seconds
Started May 09 02:38:27 PM PDT 24
Finished May 09 02:38:34 PM PDT 24
Peak memory 199004 kb
Host smart-64745b4f-7757-4b83-a82e-c9fc65b5e585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042165160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1042165160
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1252293261
Short name T281
Test name
Test status
Simulation time 25770589504 ps
CPU time 60 seconds
Started May 09 02:38:20 PM PDT 24
Finished May 09 02:39:21 PM PDT 24
Peak memory 200448 kb
Host smart-3c6675a5-2316-43c0-858f-79f2a5a5bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252293261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1252293261
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1990584495
Short name T388
Test name
Test status
Simulation time 3292705673 ps
CPU time 2.03 seconds
Started May 09 02:38:33 PM PDT 24
Finished May 09 02:38:37 PM PDT 24
Peak memory 196468 kb
Host smart-1dedeb1f-7cc8-421b-a290-86c9553cbb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990584495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1990584495
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1425354649
Short name T789
Test name
Test status
Simulation time 657474841 ps
CPU time 3.14 seconds
Started May 09 02:38:27 PM PDT 24
Finished May 09 02:38:32 PM PDT 24
Peak memory 199208 kb
Host smart-4728903e-d8cc-4df3-b40d-12745dbe19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425354649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1425354649
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1627496817
Short name T1047
Test name
Test status
Simulation time 307428337895 ps
CPU time 183.34 seconds
Started May 09 02:38:28 PM PDT 24
Finished May 09 02:41:33 PM PDT 24
Peak memory 216952 kb
Host smart-7dc74dd9-8b41-44eb-9926-ab9c382d8880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627496817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1627496817
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3611994583
Short name T52
Test name
Test status
Simulation time 46669221369 ps
CPU time 526.19 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 216868 kb
Host smart-16e4b4f2-11f0-4f77-b7ca-9088a00f72a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611994583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3611994583
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3576656016
Short name T657
Test name
Test status
Simulation time 586982118 ps
CPU time 1.69 seconds
Started May 09 02:38:35 PM PDT 24
Finished May 09 02:38:37 PM PDT 24
Peak memory 200348 kb
Host smart-030a2fe5-7747-45ab-bf71-a6666b6ce716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576656016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3576656016
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2094329221
Short name T790
Test name
Test status
Simulation time 32038639822 ps
CPU time 18.68 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:39:09 PM PDT 24
Peak memory 200480 kb
Host smart-d6853208-f532-4c59-bc92-2facd0887ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094329221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2094329221
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1725564637
Short name T1071
Test name
Test status
Simulation time 219947429345 ps
CPU time 48.28 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:42:03 PM PDT 24
Peak memory 200456 kb
Host smart-d9175f57-77f0-47b4-a5cf-a3856d1dfda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725564637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1725564637
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4216362821
Short name T1062
Test name
Test status
Simulation time 194510503071 ps
CPU time 605.65 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:51:22 PM PDT 24
Peak memory 216848 kb
Host smart-109e5a90-91da-487e-adae-20f60841884f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216362821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4216362821
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4222227214
Short name T201
Test name
Test status
Simulation time 136263747563 ps
CPU time 73.93 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:42:30 PM PDT 24
Peak memory 200392 kb
Host smart-ccf520ab-67d9-4a96-821e-dfb0e60ba2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222227214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4222227214
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2775278712
Short name T1155
Test name
Test status
Simulation time 515742368813 ps
CPU time 849.6 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:55:25 PM PDT 24
Peak memory 217040 kb
Host smart-b5273604-4dc8-480c-95ed-c674eade93e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775278712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2775278712
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3401807124
Short name T261
Test name
Test status
Simulation time 30997705621 ps
CPU time 26.56 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:41:43 PM PDT 24
Peak memory 200444 kb
Host smart-74521f1f-57eb-4d5e-987c-3d0e6e1bb001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401807124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3401807124
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3684659747
Short name T31
Test name
Test status
Simulation time 72436029096 ps
CPU time 882.26 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:55:58 PM PDT 24
Peak memory 216256 kb
Host smart-cb4c37cd-40d3-4b8b-ba97-93c9c91d3700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684659747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3684659747
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3401928698
Short name T214
Test name
Test status
Simulation time 12981432444 ps
CPU time 11.39 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:41:27 PM PDT 24
Peak memory 200088 kb
Host smart-c8d0c635-cf66-4966-a71b-39a579bc3f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401928698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3401928698
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2667094097
Short name T652
Test name
Test status
Simulation time 56174029554 ps
CPU time 351.91 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 215892 kb
Host smart-e208cdb0-2843-4c84-8acd-4e1888101805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667094097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2667094097
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3764147288
Short name T415
Test name
Test status
Simulation time 205262074139 ps
CPU time 432.15 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 200428 kb
Host smart-33d291c8-3508-4a21-b1b7-36e0b811b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764147288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3764147288
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1188653222
Short name T1135
Test name
Test status
Simulation time 8488145446 ps
CPU time 91.63 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:42:49 PM PDT 24
Peak memory 208756 kb
Host smart-3c9a98ce-2351-463e-92b8-310c3fb1afa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188653222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1188653222
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1344947935
Short name T900
Test name
Test status
Simulation time 53953265443 ps
CPU time 85.95 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:42:42 PM PDT 24
Peak memory 200448 kb
Host smart-5d62b12a-3c0f-4200-a5df-564683d3a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344947935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1344947935
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.207964083
Short name T656
Test name
Test status
Simulation time 56437180653 ps
CPU time 49.44 seconds
Started May 09 02:41:12 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 200352 kb
Host smart-b9ebcf12-6a5e-42f0-a546-bf5683b7814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207964083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.207964083
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2984159262
Short name T353
Test name
Test status
Simulation time 22133944000 ps
CPU time 447.45 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:48:42 PM PDT 24
Peak memory 217052 kb
Host smart-3b2d6f33-723e-4c6f-a565-e6ea175fe9d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984159262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2984159262
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1060749541
Short name T1016
Test name
Test status
Simulation time 78023825248 ps
CPU time 46.97 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 200476 kb
Host smart-65db98db-6e11-47b6-85c3-344cbbf0221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060749541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1060749541
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1871097329
Short name T1032
Test name
Test status
Simulation time 682245633201 ps
CPU time 504.85 seconds
Started May 09 02:41:15 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 217064 kb
Host smart-ae1649be-7f5c-4931-94b8-9a3f58ccf1ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871097329 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1871097329
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.442465569
Short name T962
Test name
Test status
Simulation time 116509046194 ps
CPU time 370.03 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:47:27 PM PDT 24
Peak memory 200336 kb
Host smart-b57bc112-f784-4c1b-ad50-73e8e61eb4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442465569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.442465569
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2101329944
Short name T125
Test name
Test status
Simulation time 249222891562 ps
CPU time 500.74 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:49:37 PM PDT 24
Peak memory 216904 kb
Host smart-a2e0d633-020a-44b7-95f6-ffbb5b281c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101329944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2101329944
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3814758023
Short name T609
Test name
Test status
Simulation time 21508526364 ps
CPU time 42.11 seconds
Started May 09 02:41:15 PM PDT 24
Finished May 09 02:42:00 PM PDT 24
Peak memory 200448 kb
Host smart-2ab2732c-cd80-4b95-8cc6-30c519f0feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814758023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3814758023
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3156784811
Short name T737
Test name
Test status
Simulation time 155256697787 ps
CPU time 445.69 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:48:42 PM PDT 24
Peak memory 225236 kb
Host smart-3e2a58dc-082b-4942-80b8-0230ea8f49d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156784811 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3156784811
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2718650616
Short name T701
Test name
Test status
Simulation time 35957394 ps
CPU time 0.54 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:38:27 PM PDT 24
Peak memory 194764 kb
Host smart-d856b75f-0a84-40b6-b0f2-171512ee2ddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718650616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2718650616
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2931845309
Short name T874
Test name
Test status
Simulation time 21992568901 ps
CPU time 14.36 seconds
Started May 09 02:38:36 PM PDT 24
Finished May 09 02:38:51 PM PDT 24
Peak memory 200492 kb
Host smart-9697600b-ea67-4680-959a-5a1145ffc230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931845309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2931845309
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2593491412
Short name T677
Test name
Test status
Simulation time 27341700791 ps
CPU time 43.3 seconds
Started May 09 02:38:24 PM PDT 24
Finished May 09 02:39:08 PM PDT 24
Peak memory 200420 kb
Host smart-a42351cf-5f6f-4c12-b79f-0120732efe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593491412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2593491412
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2134558931
Short name T222
Test name
Test status
Simulation time 87887837172 ps
CPU time 37.93 seconds
Started May 09 02:38:24 PM PDT 24
Finished May 09 02:39:02 PM PDT 24
Peak memory 200444 kb
Host smart-e835941d-184a-495b-b3b0-c29a213991df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134558931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2134558931
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1773328245
Short name T560
Test name
Test status
Simulation time 3311710367 ps
CPU time 6.32 seconds
Started May 09 02:38:26 PM PDT 24
Finished May 09 02:38:34 PM PDT 24
Peak memory 197124 kb
Host smart-a634b955-2b04-4a8e-ad35-1dde8e2049b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773328245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1773328245
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2887631923
Short name T1020
Test name
Test status
Simulation time 136664328773 ps
CPU time 653.62 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 200356 kb
Host smart-ecd32ff8-075c-43e5-9b9d-cb90d2827921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887631923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2887631923
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2858572874
Short name T631
Test name
Test status
Simulation time 8624239623 ps
CPU time 6.08 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:38:38 PM PDT 24
Peak memory 199152 kb
Host smart-d69369a7-de69-4795-82f9-4906d6dad843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858572874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2858572874
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2200859398
Short name T309
Test name
Test status
Simulation time 50510371410 ps
CPU time 91.08 seconds
Started May 09 02:38:26 PM PDT 24
Finished May 09 02:39:59 PM PDT 24
Peak memory 200012 kb
Host smart-a08e9925-7cf6-477f-afce-08c520604c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200859398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2200859398
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2622937065
Short name T545
Test name
Test status
Simulation time 23475194471 ps
CPU time 345.38 seconds
Started May 09 02:38:22 PM PDT 24
Finished May 09 02:44:08 PM PDT 24
Peak memory 200432 kb
Host smart-312e72fa-5092-4599-bd7e-20116a470dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622937065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2622937065
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2988046304
Short name T1093
Test name
Test status
Simulation time 4368557281 ps
CPU time 15.74 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:38:46 PM PDT 24
Peak memory 198536 kb
Host smart-c1e35c38-b37b-4c0a-b3d6-1d47b5eee27c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988046304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2988046304
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3271439338
Short name T832
Test name
Test status
Simulation time 18981545305 ps
CPU time 36 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:39:07 PM PDT 24
Peak memory 200456 kb
Host smart-bbdf96a5-8757-4c0d-b84a-b6063161c8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271439338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3271439338
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3662380069
Short name T546
Test name
Test status
Simulation time 5822385088 ps
CPU time 6.38 seconds
Started May 09 02:38:33 PM PDT 24
Finished May 09 02:38:41 PM PDT 24
Peak memory 196440 kb
Host smart-7dbd5fac-8462-40ed-bd28-f540a57521a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662380069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3662380069
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.361994845
Short name T407
Test name
Test status
Simulation time 11099250331 ps
CPU time 33.83 seconds
Started May 09 02:38:25 PM PDT 24
Finished May 09 02:39:00 PM PDT 24
Peak memory 200304 kb
Host smart-98e058d9-8bd3-4fec-aaeb-f9d58d5d6fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361994845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.361994845
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.297228217
Short name T89
Test name
Test status
Simulation time 666947953912 ps
CPU time 745.74 seconds
Started May 09 02:38:26 PM PDT 24
Finished May 09 02:50:53 PM PDT 24
Peak memory 217064 kb
Host smart-323b5861-7a57-4500-92ea-8bf68bc750e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297228217 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.297228217
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.633495608
Short name T1076
Test name
Test status
Simulation time 14398229504 ps
CPU time 20.38 seconds
Started May 09 02:38:31 PM PDT 24
Finished May 09 02:38:54 PM PDT 24
Peak memory 200364 kb
Host smart-20fb25e9-bd9c-466a-a25e-582f42f849db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633495608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.633495608
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2621219012
Short name T114
Test name
Test status
Simulation time 54925072323 ps
CPU time 97.85 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:40:16 PM PDT 24
Peak memory 200456 kb
Host smart-83b849a5-4663-478a-8111-ad9ee12955d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621219012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2621219012
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4212048393
Short name T510
Test name
Test status
Simulation time 130546553639 ps
CPU time 107.72 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:43:05 PM PDT 24
Peak memory 200396 kb
Host smart-f86cbee5-0943-46f6-837d-f4b190c534d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212048393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4212048393
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3519951684
Short name T817
Test name
Test status
Simulation time 97651889484 ps
CPU time 605.92 seconds
Started May 09 02:41:16 PM PDT 24
Finished May 09 02:51:24 PM PDT 24
Peak memory 225448 kb
Host smart-3a3331c3-794b-4208-8106-3121460bf285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519951684 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3519951684
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.529812984
Short name T124
Test name
Test status
Simulation time 297751805058 ps
CPU time 806.18 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:54:42 PM PDT 24
Peak memory 225312 kb
Host smart-2fbe2192-037e-4822-9990-c3356c64d634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529812984 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.529812984
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2657639227
Short name T244
Test name
Test status
Simulation time 18174624898 ps
CPU time 12.21 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:41:29 PM PDT 24
Peak memory 199884 kb
Host smart-899e7503-adfa-4f6e-a188-1294b64a5b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657639227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2657639227
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2958460798
Short name T355
Test name
Test status
Simulation time 32514606424 ps
CPU time 557.28 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:50:34 PM PDT 24
Peak memory 216884 kb
Host smart-e623aea6-9d38-45f2-aaef-63bb89a01fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958460798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2958460798
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.470416951
Short name T919
Test name
Test status
Simulation time 7034989313 ps
CPU time 6.36 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:41:24 PM PDT 24
Peak memory 199556 kb
Host smart-fa23ab68-d2d9-424b-ac1b-666893af0b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470416951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.470416951
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.620769580
Short name T725
Test name
Test status
Simulation time 19197358170 ps
CPU time 279.89 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:45:56 PM PDT 24
Peak memory 208744 kb
Host smart-3e28d244-73a6-4585-a901-d0cccd8d0d8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620769580 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.620769580
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2054658822
Short name T718
Test name
Test status
Simulation time 39323991406 ps
CPU time 24.67 seconds
Started May 09 02:41:14 PM PDT 24
Finished May 09 02:41:41 PM PDT 24
Peak memory 200468 kb
Host smart-2018a792-5f2d-4b63-a59d-85dfe23887b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054658822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2054658822
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2588483637
Short name T1043
Test name
Test status
Simulation time 210672073829 ps
CPU time 748.1 seconds
Started May 09 02:41:13 PM PDT 24
Finished May 09 02:53:44 PM PDT 24
Peak memory 225248 kb
Host smart-e40cbe04-cd31-4ad7-9490-006a15996dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588483637 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2588483637
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2857521907
Short name T870
Test name
Test status
Simulation time 68230532925 ps
CPU time 101.84 seconds
Started May 09 02:41:25 PM PDT 24
Finished May 09 02:43:10 PM PDT 24
Peak memory 200396 kb
Host smart-556695dc-2645-4cd7-b07d-4422004c87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857521907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2857521907
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1101919275
Short name T146
Test name
Test status
Simulation time 93100041961 ps
CPU time 639.34 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:52:09 PM PDT 24
Peak memory 217116 kb
Host smart-b09b607a-0311-4bd6-a305-53a7980fc593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101919275 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1101919275
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.997099787
Short name T996
Test name
Test status
Simulation time 49546657274 ps
CPU time 46.22 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:42:16 PM PDT 24
Peak memory 200484 kb
Host smart-85a0b74c-4d9d-4070-9dde-7ca7055dc246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997099787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.997099787
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1953344244
Short name T774
Test name
Test status
Simulation time 29293876356 ps
CPU time 818.48 seconds
Started May 09 02:41:25 PM PDT 24
Finished May 09 02:55:06 PM PDT 24
Peak memory 208724 kb
Host smart-3c15fefa-2311-477e-99a7-a7c6383bf352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953344244 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1953344244
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2919771512
Short name T607
Test name
Test status
Simulation time 9618852338 ps
CPU time 14.56 seconds
Started May 09 02:41:24 PM PDT 24
Finished May 09 02:41:40 PM PDT 24
Peak memory 198868 kb
Host smart-e38b4c61-eb8b-418a-8e10-f27857d2ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919771512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2919771512
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1384515255
Short name T1131
Test name
Test status
Simulation time 351551531459 ps
CPU time 799.06 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:54:49 PM PDT 24
Peak memory 216880 kb
Host smart-df6294ff-10cb-4a91-8677-765be672a273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384515255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1384515255
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.776035230
Short name T648
Test name
Test status
Simulation time 128579430764 ps
CPU time 14.75 seconds
Started May 09 02:41:25 PM PDT 24
Finished May 09 02:41:41 PM PDT 24
Peak memory 199840 kb
Host smart-50132e8c-e9e0-4d3a-86ba-74adb0fd51a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776035230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.776035230
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3999461475
Short name T1116
Test name
Test status
Simulation time 1430459884201 ps
CPU time 937.58 seconds
Started May 09 02:41:25 PM PDT 24
Finished May 09 02:57:05 PM PDT 24
Peak memory 233436 kb
Host smart-6dc20047-d567-48d2-b83b-5ffec45ac652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999461475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3999461475
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.571602799
Short name T180
Test name
Test status
Simulation time 47149203119 ps
CPU time 33 seconds
Started May 09 02:41:24 PM PDT 24
Finished May 09 02:41:58 PM PDT 24
Peak memory 200440 kb
Host smart-6af0ef40-aa6c-4700-a94d-ffab4465e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571602799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.571602799
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.549361550
Short name T593
Test name
Test status
Simulation time 60867609963 ps
CPU time 914.88 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:56:44 PM PDT 24
Peak memory 215320 kb
Host smart-d202a980-dda1-4a09-935b-72d383853fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549361550 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.549361550
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2955905091
Short name T398
Test name
Test status
Simulation time 67465274 ps
CPU time 0.56 seconds
Started May 09 02:38:27 PM PDT 24
Finished May 09 02:38:29 PM PDT 24
Peak memory 195836 kb
Host smart-81b26cc6-5bf9-4a78-a69e-78920aeec6bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955905091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2955905091
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3697041203
Short name T1133
Test name
Test status
Simulation time 122126116100 ps
CPU time 103.26 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:40:15 PM PDT 24
Peak memory 200228 kb
Host smart-7d6be316-4ef8-4141-b862-feddd1068172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697041203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3697041203
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2246099527
Short name T901
Test name
Test status
Simulation time 188200738309 ps
CPU time 154.34 seconds
Started May 09 02:38:45 PM PDT 24
Finished May 09 02:41:20 PM PDT 24
Peak memory 200468 kb
Host smart-0e12ed89-991c-4cb1-9be1-d014bd487c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246099527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2246099527
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2744806223
Short name T364
Test name
Test status
Simulation time 31010369777 ps
CPU time 50.43 seconds
Started May 09 02:38:24 PM PDT 24
Finished May 09 02:39:16 PM PDT 24
Peak memory 199732 kb
Host smart-f8da4db3-b4ae-43cb-be66-7ea8c516fca4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744806223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2744806223
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_loopback.743852455
Short name T487
Test name
Test status
Simulation time 3564239813 ps
CPU time 2.57 seconds
Started May 09 02:38:40 PM PDT 24
Finished May 09 02:38:44 PM PDT 24
Peak memory 198808 kb
Host smart-01dbfa6f-4b77-40a0-8a3a-b1a2857b7140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743852455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.743852455
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1018075610
Short name T839
Test name
Test status
Simulation time 185324729078 ps
CPU time 79.63 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:39:51 PM PDT 24
Peak memory 200252 kb
Host smart-22e2e50b-3679-46ad-9e06-64d471f43888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018075610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1018075610
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3230574833
Short name T807
Test name
Test status
Simulation time 17078904269 ps
CPU time 240.52 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 200412 kb
Host smart-84d9cf40-5b68-410e-8c29-374f0c2a05a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230574833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3230574833
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.4006716362
Short name T787
Test name
Test status
Simulation time 5641195055 ps
CPU time 19.04 seconds
Started May 09 02:38:39 PM PDT 24
Finished May 09 02:38:59 PM PDT 24
Peak memory 198420 kb
Host smart-a7a41132-0cda-4220-9d1a-7e997619143c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006716362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4006716362
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1003886780
Short name T558
Test name
Test status
Simulation time 9022123429 ps
CPU time 16.56 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:39:01 PM PDT 24
Peak memory 200408 kb
Host smart-e8f87592-54d0-449c-a93f-0221a4cc763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003886780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1003886780
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3003165047
Short name T543
Test name
Test status
Simulation time 2045950871 ps
CPU time 1.91 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:38:49 PM PDT 24
Peak memory 195808 kb
Host smart-b83c7e0b-f830-4bcd-8c59-503e19ffb8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003165047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3003165047
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.466607148
Short name T331
Test name
Test status
Simulation time 800146746 ps
CPU time 4 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:38:52 PM PDT 24
Peak memory 199212 kb
Host smart-5fad5290-7385-4985-8fd8-df9cb6edcc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466607148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.466607148
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2474426452
Short name T102
Test name
Test status
Simulation time 199191895279 ps
CPU time 390.77 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:45:19 PM PDT 24
Peak memory 200448 kb
Host smart-a7f40bcf-5b5c-479f-ad2f-2393a57b8ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474426452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2474426452
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.4058096577
Short name T79
Test name
Test status
Simulation time 129909029217 ps
CPU time 1704.7 seconds
Started May 09 02:38:27 PM PDT 24
Finished May 09 03:06:53 PM PDT 24
Peak memory 230388 kb
Host smart-f8b039b0-2e36-49bb-b4ab-80c62ac65c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058096577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.4058096577
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3169198192
Short name T956
Test name
Test status
Simulation time 816819380 ps
CPU time 2.92 seconds
Started May 09 02:38:35 PM PDT 24
Finished May 09 02:38:39 PM PDT 24
Peak memory 198928 kb
Host smart-1538e191-7ced-4b0d-8bcd-33dc4140f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169198192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3169198192
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1105134490
Short name T538
Test name
Test status
Simulation time 50802397125 ps
CPU time 77.67 seconds
Started May 09 02:38:28 PM PDT 24
Finished May 09 02:39:47 PM PDT 24
Peak memory 200472 kb
Host smart-8c29a48d-02ad-4c77-8004-9510251b4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105134490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1105134490
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2236583157
Short name T126
Test name
Test status
Simulation time 6175572480 ps
CPU time 56.15 seconds
Started May 09 02:41:28 PM PDT 24
Finished May 09 02:42:27 PM PDT 24
Peak memory 216928 kb
Host smart-5d7d6d8b-a388-4d27-bd20-759b5ed1238e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236583157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2236583157
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1434632430
Short name T897
Test name
Test status
Simulation time 15274627809 ps
CPU time 9.07 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:41:38 PM PDT 24
Peak memory 200476 kb
Host smart-2d4000de-a110-4207-807c-55c6f484b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434632430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1434632430
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.228773564
Short name T964
Test name
Test status
Simulation time 10185270353 ps
CPU time 99.47 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:43:08 PM PDT 24
Peak memory 216036 kb
Host smart-1f2d4125-0d1b-4972-91d0-8bbd5b84e97f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228773564 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.228773564
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1195194103
Short name T592
Test name
Test status
Simulation time 19927831062 ps
CPU time 33.96 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:42:04 PM PDT 24
Peak memory 200496 kb
Host smart-f234284b-2705-4db1-9121-84d9739782cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195194103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1195194103
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4034531609
Short name T57
Test name
Test status
Simulation time 80653731850 ps
CPU time 284.95 seconds
Started May 09 02:41:29 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 216816 kb
Host smart-1dcb82c8-5f9f-4deb-80e1-2b0cdfd9e666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034531609 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4034531609
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.997181172
Short name T542
Test name
Test status
Simulation time 14170912159 ps
CPU time 17.79 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:41:47 PM PDT 24
Peak memory 200472 kb
Host smart-2a0d9d82-f064-47d8-b53c-28867981a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997181172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.997181172
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1062955453
Short name T1099
Test name
Test status
Simulation time 278602657437 ps
CPU time 933.32 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:57:02 PM PDT 24
Peak memory 226128 kb
Host smart-775aa435-c546-43d7-9b3d-bc0bf51c0893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062955453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1062955453
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1132644355
Short name T1120
Test name
Test status
Simulation time 25503363288 ps
CPU time 25.24 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:41:56 PM PDT 24
Peak memory 200488 kb
Host smart-a2f8895a-bcb3-472b-aeba-5114b93f3d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132644355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1132644355
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1656549294
Short name T30
Test name
Test status
Simulation time 23736280907 ps
CPU time 138.42 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:43:47 PM PDT 24
Peak memory 216476 kb
Host smart-e9bfbdbd-0d80-4b01-b471-805a09c2fa91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656549294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1656549294
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1739157624
Short name T865
Test name
Test status
Simulation time 45080102829 ps
CPU time 20.05 seconds
Started May 09 02:41:28 PM PDT 24
Finished May 09 02:41:51 PM PDT 24
Peak memory 200280 kb
Host smart-1282550b-bddf-4ef7-a214-2f2aa68fc115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739157624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1739157624
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.449830783
Short name T1127
Test name
Test status
Simulation time 48416317875 ps
CPU time 300.38 seconds
Started May 09 02:41:28 PM PDT 24
Finished May 09 02:46:31 PM PDT 24
Peak memory 216288 kb
Host smart-f92e02fe-0e0c-4917-882f-74fb120eb9d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449830783 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.449830783
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4135129582
Short name T247
Test name
Test status
Simulation time 114037718550 ps
CPU time 97.67 seconds
Started May 09 02:41:24 PM PDT 24
Finished May 09 02:43:02 PM PDT 24
Peak memory 200388 kb
Host smart-dc11b0f1-a4dd-4f64-ae92-8c2f931c5ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135129582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4135129582
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.797235167
Short name T981
Test name
Test status
Simulation time 45717565900 ps
CPU time 212.37 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:45:02 PM PDT 24
Peak memory 216868 kb
Host smart-7e652b35-e8e6-4938-9a4d-0bfa1e9adccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797235167 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.797235167
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.918577262
Short name T767
Test name
Test status
Simulation time 59762107511 ps
CPU time 41.55 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:42:12 PM PDT 24
Peak memory 200480 kb
Host smart-433b87e4-e65d-429a-a2f7-bac785ad3452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918577262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.918577262
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4179440474
Short name T666
Test name
Test status
Simulation time 29385736453 ps
CPU time 131.72 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:43:40 PM PDT 24
Peak memory 216840 kb
Host smart-ffc87e8a-3c5e-4b72-aa79-2eb5f8ad321e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179440474 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4179440474
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1852371558
Short name T892
Test name
Test status
Simulation time 25336433660 ps
CPU time 21.02 seconds
Started May 09 02:41:28 PM PDT 24
Finished May 09 02:41:52 PM PDT 24
Peak memory 200452 kb
Host smart-825c0d85-c70b-4919-aa0f-ebb49673a097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852371558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1852371558
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2988059479
Short name T948
Test name
Test status
Simulation time 19861039980 ps
CPU time 119.16 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:43:29 PM PDT 24
Peak memory 217096 kb
Host smart-03569ef8-8d61-48b0-a2cd-2f54af4eccd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988059479 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2988059479
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3530092044
Short name T1013
Test name
Test status
Simulation time 23482912 ps
CPU time 0.55 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:38:39 PM PDT 24
Peak memory 194708 kb
Host smart-0c293695-071f-46b5-9bc1-8def72f3a214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530092044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3530092044
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3095995294
Short name T598
Test name
Test status
Simulation time 75825361604 ps
CPU time 33.58 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:39:24 PM PDT 24
Peak memory 200396 kb
Host smart-073c2d75-5f05-4deb-80ca-79800110cb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095995294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3095995294
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2481157539
Short name T1111
Test name
Test status
Simulation time 16853289262 ps
CPU time 32.81 seconds
Started May 09 02:38:23 PM PDT 24
Finished May 09 02:38:57 PM PDT 24
Peak memory 200372 kb
Host smart-68cd2c0c-f1c5-4f19-8a9a-ade8a52a1983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481157539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2481157539
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.222232834
Short name T942
Test name
Test status
Simulation time 78608484639 ps
CPU time 131.08 seconds
Started May 09 02:38:27 PM PDT 24
Finished May 09 02:40:40 PM PDT 24
Peak memory 200400 kb
Host smart-38199530-908c-40a1-ba0d-e8111dc39363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222232834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.222232834
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3488697099
Short name T715
Test name
Test status
Simulation time 4579801763 ps
CPU time 5.76 seconds
Started May 09 02:38:33 PM PDT 24
Finished May 09 02:38:40 PM PDT 24
Peak memory 200464 kb
Host smart-2e6b5470-6c78-4fb3-9b57-1d31049d0dad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488697099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3488697099
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2327640298
Short name T41
Test name
Test status
Simulation time 250933469038 ps
CPU time 143.9 seconds
Started May 09 02:38:26 PM PDT 24
Finished May 09 02:40:51 PM PDT 24
Peak memory 200384 kb
Host smart-4dd63003-419d-453c-9b73-4bb12894438c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327640298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2327640298
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1208530609
Short name T362
Test name
Test status
Simulation time 892845889 ps
CPU time 1.44 seconds
Started May 09 02:38:42 PM PDT 24
Finished May 09 02:38:44 PM PDT 24
Peak memory 196384 kb
Host smart-c9af35f9-491b-4d72-8cc7-e60a6017e2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208530609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1208530609
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2394087503
Short name T621
Test name
Test status
Simulation time 17151146202 ps
CPU time 31.65 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:39:03 PM PDT 24
Peak memory 199428 kb
Host smart-c14f0176-18b1-4142-903c-87813f29f905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394087503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2394087503
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1666137484
Short name T816
Test name
Test status
Simulation time 27708429680 ps
CPU time 356.19 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:44:27 PM PDT 24
Peak memory 200476 kb
Host smart-379a5def-21e6-49a4-8981-d8054c6b14e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666137484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1666137484
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1137950048
Short name T1011
Test name
Test status
Simulation time 5493415045 ps
CPU time 12.26 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:38:43 PM PDT 24
Peak memory 199732 kb
Host smart-4431f5b1-6ae5-4e8e-b9a7-35a0862dc4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137950048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1137950048
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.993391803
Short name T340
Test name
Test status
Simulation time 62992367676 ps
CPU time 103.7 seconds
Started May 09 02:38:33 PM PDT 24
Finished May 09 02:40:18 PM PDT 24
Peak memory 200428 kb
Host smart-b8b4fb77-dd37-47b9-ae3e-42dbf4988b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993391803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.993391803
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.647947112
Short name T426
Test name
Test status
Simulation time 1985908507 ps
CPU time 1.09 seconds
Started May 09 02:38:40 PM PDT 24
Finished May 09 02:38:42 PM PDT 24
Peak memory 195800 kb
Host smart-7b78bc0a-0124-4b62-aca4-0bc8706a7270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647947112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.647947112
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4117041806
Short name T728
Test name
Test status
Simulation time 5715388518 ps
CPU time 18.92 seconds
Started May 09 02:38:42 PM PDT 24
Finished May 09 02:39:02 PM PDT 24
Peak memory 199776 kb
Host smart-16a22148-7d3b-4e5b-89f1-cf7c9dd22b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117041806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4117041806
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1549466006
Short name T720
Test name
Test status
Simulation time 61950787636 ps
CPU time 757.51 seconds
Started May 09 02:38:30 PM PDT 24
Finished May 09 02:51:09 PM PDT 24
Peak memory 226448 kb
Host smart-7c0b066f-b3a2-49d0-bc0d-9c79e56f8693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549466006 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1549466006
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2870588543
Short name T1053
Test name
Test status
Simulation time 2455316300 ps
CPU time 3.05 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:38:48 PM PDT 24
Peak memory 200404 kb
Host smart-f5ec2d39-68f1-43ed-9da2-9d28daf6e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870588543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2870588543
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2756167455
Short name T633
Test name
Test status
Simulation time 70284112878 ps
CPU time 141.82 seconds
Started May 09 02:38:29 PM PDT 24
Finished May 09 02:40:52 PM PDT 24
Peak memory 200472 kb
Host smart-24c81905-0724-40ed-a065-fb0e145eea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756167455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2756167455
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.199930943
Short name T274
Test name
Test status
Simulation time 24977476245 ps
CPU time 9.75 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:41:39 PM PDT 24
Peak memory 200432 kb
Host smart-9c648a64-be2b-43a3-9fa7-237e51de0339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199930943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.199930943
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3115045062
Short name T203
Test name
Test status
Simulation time 63293482747 ps
CPU time 723.49 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:53:33 PM PDT 24
Peak memory 216884 kb
Host smart-6fb780f5-265d-42d1-834c-107b2dda6a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115045062 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3115045062
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2180404461
Short name T682
Test name
Test status
Simulation time 9433350144 ps
CPU time 15.46 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:41:44 PM PDT 24
Peak memory 200360 kb
Host smart-8b079f6a-1c18-4ffd-ae0b-0c96f552d2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180404461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2180404461
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1970771678
Short name T971
Test name
Test status
Simulation time 78226788688 ps
CPU time 829.16 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:55:19 PM PDT 24
Peak memory 231188 kb
Host smart-084206bd-107c-4384-9818-1bde7fbc83b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970771678 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1970771678
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2358566909
Short name T1044
Test name
Test status
Simulation time 122931982172 ps
CPU time 209.65 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:44:58 PM PDT 24
Peak memory 200216 kb
Host smart-5a446464-8600-429b-8f30-821cf1312875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358566909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2358566909
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2712669377
Short name T504
Test name
Test status
Simulation time 106478426362 ps
CPU time 1709.68 seconds
Started May 09 02:41:28 PM PDT 24
Finished May 09 03:10:00 PM PDT 24
Peak memory 225280 kb
Host smart-9ad5ad14-5390-4e20-af41-193835c3c289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712669377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2712669377
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3556814117
Short name T522
Test name
Test status
Simulation time 28583276689 ps
CPU time 12.79 seconds
Started May 09 02:41:26 PM PDT 24
Finished May 09 02:41:42 PM PDT 24
Peak memory 200356 kb
Host smart-8f1f3873-695e-4b5d-a61e-dddf2b6d44c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556814117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3556814117
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2752397240
Short name T1138
Test name
Test status
Simulation time 32482008919 ps
CPU time 330.34 seconds
Started May 09 02:41:28 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 216104 kb
Host smart-7335496f-ef10-4593-807d-31493892bef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752397240 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2752397240
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3896464811
Short name T1162
Test name
Test status
Simulation time 25399995990 ps
CPU time 9.41 seconds
Started May 09 02:41:29 PM PDT 24
Finished May 09 02:41:40 PM PDT 24
Peak memory 200396 kb
Host smart-8db91f77-cf76-4628-8a7f-fd4836ec0546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896464811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3896464811
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.861982053
Short name T1080
Test name
Test status
Simulation time 74145123492 ps
CPU time 208.34 seconds
Started May 09 02:41:27 PM PDT 24
Finished May 09 02:44:58 PM PDT 24
Peak memory 217088 kb
Host smart-a94cfcea-12fe-4aba-a871-b134af2ab422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861982053 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.861982053
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2294900679
Short name T753
Test name
Test status
Simulation time 30358968466 ps
CPU time 48.79 seconds
Started May 09 02:41:25 PM PDT 24
Finished May 09 02:42:17 PM PDT 24
Peak memory 200248 kb
Host smart-28b3bc00-824d-4eec-855f-948001898e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294900679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2294900679
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1045292972
Short name T20
Test name
Test status
Simulation time 90858159020 ps
CPU time 266.49 seconds
Started May 09 02:41:35 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 215888 kb
Host smart-bfe19173-bff9-4267-8c37-a316433f054d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045292972 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1045292972
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1859978909
Short name T1145
Test name
Test status
Simulation time 26442802850 ps
CPU time 54.42 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:42:35 PM PDT 24
Peak memory 200432 kb
Host smart-d4352f33-dc82-45c1-8293-f6d060833d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859978909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1859978909
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.461589734
Short name T945
Test name
Test status
Simulation time 127865893372 ps
CPU time 406.93 seconds
Started May 09 02:41:42 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 211768 kb
Host smart-448c38a0-2beb-4c10-a6d4-4d7ca55822d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461589734 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.461589734
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2629429071
Short name T502
Test name
Test status
Simulation time 136074102891 ps
CPU time 16.8 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:41:58 PM PDT 24
Peak memory 200400 kb
Host smart-76e88ff6-54ee-41a7-aefb-45464ff4cdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629429071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2629429071
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.554376434
Short name T145
Test name
Test status
Simulation time 34362523350 ps
CPU time 413.51 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 217044 kb
Host smart-0da85a97-f680-496e-b978-45b3223627c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554376434 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.554376434
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1530844725
Short name T476
Test name
Test status
Simulation time 11591940271 ps
CPU time 18.55 seconds
Started May 09 02:41:35 PM PDT 24
Finished May 09 02:41:56 PM PDT 24
Peak memory 200408 kb
Host smart-bfcba5f6-2184-4e1a-bd8e-d25df55626ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530844725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1530844725
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.950063733
Short name T612
Test name
Test status
Simulation time 327674295940 ps
CPU time 1033.14 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:58:52 PM PDT 24
Peak memory 216840 kb
Host smart-f507c327-4197-4109-8b0b-a4329d1a9c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950063733 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.950063733
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.4153006392
Short name T860
Test name
Test status
Simulation time 102238523661 ps
CPU time 153.64 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:44:11 PM PDT 24
Peak memory 200416 kb
Host smart-a80e4c51-013b-48ed-b1a5-44170440f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153006392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4153006392
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1008369691
Short name T24
Test name
Test status
Simulation time 92867062348 ps
CPU time 911.76 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:56:53 PM PDT 24
Peak memory 227888 kb
Host smart-eb003324-598f-449f-9528-c6344e072a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008369691 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1008369691
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.248312205
Short name T441
Test name
Test status
Simulation time 32860952 ps
CPU time 0.54 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:38:48 PM PDT 24
Peak memory 195808 kb
Host smart-b7025b7f-f87c-45c8-9388-62fd9879ea81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248312205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.248312205
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.308615991
Short name T830
Test name
Test status
Simulation time 118845911958 ps
CPU time 60.91 seconds
Started May 09 02:38:31 PM PDT 24
Finished May 09 02:39:34 PM PDT 24
Peak memory 200456 kb
Host smart-30fb6173-87d8-49e1-ac52-4dbcd74aa4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308615991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.308615991
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1120589565
Short name T337
Test name
Test status
Simulation time 103258766813 ps
CPU time 172.24 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:41:31 PM PDT 24
Peak memory 200396 kb
Host smart-ce377530-924a-4ef0-8699-7d53db81e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120589565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1120589565
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1296375324
Short name T1164
Test name
Test status
Simulation time 209065858056 ps
CPU time 385.67 seconds
Started May 09 02:38:43 PM PDT 24
Finished May 09 02:45:10 PM PDT 24
Peak memory 200488 kb
Host smart-56f01265-c2a0-4c60-818f-7bb4eadf4d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296375324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1296375324
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3752484108
Short name T78
Test name
Test status
Simulation time 24759298552 ps
CPU time 37.27 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:39:22 PM PDT 24
Peak memory 198976 kb
Host smart-768f6b85-547f-4e1b-97dc-e4449445d0d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752484108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3752484108
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.394331404
Short name T516
Test name
Test status
Simulation time 81872124943 ps
CPU time 586.56 seconds
Started May 09 02:38:36 PM PDT 24
Finished May 09 02:48:24 PM PDT 24
Peak memory 200472 kb
Host smart-51501650-9b90-49e5-8c78-6e5c26096496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394331404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.394331404
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.843050057
Short name T359
Test name
Test status
Simulation time 3822486193 ps
CPU time 6.73 seconds
Started May 09 02:38:41 PM PDT 24
Finished May 09 02:38:48 PM PDT 24
Peak memory 200224 kb
Host smart-4f60a23c-ca90-43d2-8c8b-acb6f878feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843050057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.843050057
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1407688976
Short name T301
Test name
Test status
Simulation time 93933942916 ps
CPU time 40.77 seconds
Started May 09 02:38:49 PM PDT 24
Finished May 09 02:39:31 PM PDT 24
Peak memory 200544 kb
Host smart-42e8f94b-b171-4182-a2f3-3056eb0c639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407688976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1407688976
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.486530253
Short name T1171
Test name
Test status
Simulation time 13334712988 ps
CPU time 494.81 seconds
Started May 09 02:38:36 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 200452 kb
Host smart-a44323ba-01c7-4164-bf04-e5f8f0c88720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486530253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.486530253
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1998294254
Short name T706
Test name
Test status
Simulation time 5908129025 ps
CPU time 25.39 seconds
Started May 09 02:38:44 PM PDT 24
Finished May 09 02:39:10 PM PDT 24
Peak memory 200468 kb
Host smart-dcb9cb18-7b44-463d-aefd-fe821065fbb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998294254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1998294254
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.412687664
Short name T1068
Test name
Test status
Simulation time 94027784764 ps
CPU time 175.28 seconds
Started May 09 02:38:47 PM PDT 24
Finished May 09 02:41:43 PM PDT 24
Peak memory 200432 kb
Host smart-e04d9f66-988b-4471-b07b-cf5a39e27b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412687664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.412687664
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3861025364
Short name T457
Test name
Test status
Simulation time 4980996628 ps
CPU time 4.44 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:38:43 PM PDT 24
Peak memory 196472 kb
Host smart-6aa8be87-5ef4-48c8-8b02-f6ce120569d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861025364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3861025364
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3986746888
Short name T931
Test name
Test status
Simulation time 6032158683 ps
CPU time 16.67 seconds
Started May 09 02:38:41 PM PDT 24
Finished May 09 02:38:58 PM PDT 24
Peak memory 199576 kb
Host smart-27c25336-37f1-4e2b-8753-d00e3f929477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986746888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3986746888
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3064695413
Short name T1054
Test name
Test status
Simulation time 80905042623 ps
CPU time 41.9 seconds
Started May 09 02:38:43 PM PDT 24
Finished May 09 02:39:26 PM PDT 24
Peak memory 200448 kb
Host smart-79dee902-5c18-4622-b64d-7e1d1f82b8d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064695413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3064695413
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.693898102
Short name T202
Test name
Test status
Simulation time 268787633952 ps
CPU time 1111.44 seconds
Started May 09 02:38:37 PM PDT 24
Finished May 09 02:57:10 PM PDT 24
Peak memory 225260 kb
Host smart-005ae38a-c604-4970-a6e0-e9646d60b13b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693898102 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.693898102
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.431989873
Short name T995
Test name
Test status
Simulation time 2684608537 ps
CPU time 2.35 seconds
Started May 09 02:38:46 PM PDT 24
Finished May 09 02:38:49 PM PDT 24
Peak memory 199104 kb
Host smart-e3afdb3b-03d2-45f8-abb8-82b32abe9421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431989873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.431989873
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3449845489
Short name T896
Test name
Test status
Simulation time 90483080050 ps
CPU time 131.26 seconds
Started May 09 02:38:33 PM PDT 24
Finished May 09 02:40:45 PM PDT 24
Peak memory 200448 kb
Host smart-93c0f7a6-763d-46cd-818a-397b3de2bd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449845489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3449845489
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2403710620
Short name T966
Test name
Test status
Simulation time 11002548458 ps
CPU time 20.67 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:42:01 PM PDT 24
Peak memory 200600 kb
Host smart-3edc21f5-bc8e-4f1f-be51-7bfdbf0572dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403710620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2403710620
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3504812880
Short name T872
Test name
Test status
Simulation time 103746296873 ps
CPU time 556.87 seconds
Started May 09 02:41:37 PM PDT 24
Finished May 09 02:50:56 PM PDT 24
Peak memory 216880 kb
Host smart-4b4dd2d7-34ca-4542-8261-0eb61705c1a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504812880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3504812880
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1386039617
Short name T465
Test name
Test status
Simulation time 10211348551 ps
CPU time 18.77 seconds
Started May 09 02:41:37 PM PDT 24
Finished May 09 02:41:58 PM PDT 24
Peak memory 200436 kb
Host smart-df4aff5d-9805-4096-b0d6-4508c2254a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386039617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1386039617
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3808019450
Short name T819
Test name
Test status
Simulation time 77727745791 ps
CPU time 168.11 seconds
Started May 09 02:41:43 PM PDT 24
Finished May 09 02:44:33 PM PDT 24
Peak memory 208744 kb
Host smart-b4f05ded-bc89-4b80-a6ce-7bd18d8c7845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808019450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3808019450
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3310118019
Short name T1070
Test name
Test status
Simulation time 107944526611 ps
CPU time 635.44 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:52:14 PM PDT 24
Peak memory 229120 kb
Host smart-7cc33a24-49f8-49a2-b094-2e2fe7b4a770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310118019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3310118019
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1988377804
Short name T1148
Test name
Test status
Simulation time 249151806357 ps
CPU time 1354.1 seconds
Started May 09 02:41:34 PM PDT 24
Finished May 09 03:04:11 PM PDT 24
Peak memory 225332 kb
Host smart-f6b6b140-0d57-4376-8a4f-418513a71fe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988377804 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1988377804
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3317969031
Short name T418
Test name
Test status
Simulation time 389719666249 ps
CPU time 34.13 seconds
Started May 09 02:41:43 PM PDT 24
Finished May 09 02:42:19 PM PDT 24
Peak memory 200216 kb
Host smart-63ef4cc0-49f1-4256-a125-74d8b1a58545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317969031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3317969031
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2972820411
Short name T626
Test name
Test status
Simulation time 157043168100 ps
CPU time 385.52 seconds
Started May 09 02:41:40 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 210968 kb
Host smart-214161fe-7747-4a85-a326-32a3ca46e86e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972820411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2972820411
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1650916654
Short name T314
Test name
Test status
Simulation time 26844771709 ps
CPU time 10.9 seconds
Started May 09 02:41:37 PM PDT 24
Finished May 09 02:41:50 PM PDT 24
Peak memory 200428 kb
Host smart-43427769-98d0-4c8e-8b31-2e1f93896280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650916654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1650916654
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1202539911
Short name T785
Test name
Test status
Simulation time 129776874486 ps
CPU time 275.39 seconds
Started May 09 02:41:35 PM PDT 24
Finished May 09 02:46:12 PM PDT 24
Peak memory 217084 kb
Host smart-e8c62cb6-d490-4ebf-adf4-965d6385221a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202539911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1202539911
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3188866495
Short name T727
Test name
Test status
Simulation time 224710151726 ps
CPU time 353.43 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:47:35 PM PDT 24
Peak memory 200356 kb
Host smart-5579cf6c-a6a2-4abf-9c8b-f9bd2e87d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188866495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3188866495
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2702952062
Short name T357
Test name
Test status
Simulation time 43955575786 ps
CPU time 162.07 seconds
Started May 09 02:41:42 PM PDT 24
Finished May 09 02:44:26 PM PDT 24
Peak memory 208740 kb
Host smart-e6ac318b-6a8d-4879-af84-1487f481e9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702952062 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2702952062
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.902470744
Short name T242
Test name
Test status
Simulation time 30116335083 ps
CPU time 65.05 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:42:46 PM PDT 24
Peak memory 200448 kb
Host smart-3a22f853-9052-498e-af14-ba3308bedeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902470744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.902470744
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4189983656
Short name T577
Test name
Test status
Simulation time 192249788213 ps
CPU time 341.32 seconds
Started May 09 02:41:36 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 215676 kb
Host smart-dacb4412-3b62-4b13-8d3f-8264e1c6fe00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189983656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4189983656
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2901252609
Short name T627
Test name
Test status
Simulation time 11952695615 ps
CPU time 26.74 seconds
Started May 09 02:41:38 PM PDT 24
Finished May 09 02:42:06 PM PDT 24
Peak memory 200492 kb
Host smart-3cc94e13-57ab-4088-bcf2-70b9af758573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901252609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2901252609
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2226714874
Short name T176
Test name
Test status
Simulation time 213725281847 ps
CPU time 611.33 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:51:52 PM PDT 24
Peak memory 217132 kb
Host smart-1108e814-3df4-4727-9cc8-61a764e0f013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226714874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2226714874
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3792012175
Short name T250
Test name
Test status
Simulation time 31713964051 ps
CPU time 53.25 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:42:35 PM PDT 24
Peak memory 200636 kb
Host smart-a3bda89e-a21a-4e13-8e3d-a1007e890538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792012175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3792012175
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1712166045
Short name T976
Test name
Test status
Simulation time 28567204884 ps
CPU time 269.9 seconds
Started May 09 02:41:39 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 212740 kb
Host smart-2ab10283-94f1-4bfc-9b4e-90b5b7d022ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712166045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1712166045
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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