Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101727	1			T1	18		T2	1		T3	1
all_values[1]	101727	1			T1	18		T2	1		T3	1
all_values[2]	101727	1			T1	18		T2	1		T3	1
all_values[3]	101727	1			T1	18		T2	1		T3	1
all_values[4]	101727	1			T1	18		T2	1		T3	1
all_values[5]	101727	1			T1	18		T2	1		T3	1
all_values[6]	101727	1			T1	18		T2	1		T3	1
all_values[7]	101727	1			T1	18		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406324

1

T1

101

T2

5

T3

5

auto[1]

407492

1

T1

43

T2

3

T3

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

761332

1

T1

119

T2

7

T3

7

auto[1]

52484

1

T1

25

T2

1

T3

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29590	1			T5	5		T6	713		T7	2
all_values[0]	auto[0]	auto[1]	20827	1			T1	16		T4	6		T5	19
all_values[0]	auto[1]	auto[0]	31179	1			T6	309		T28	17		T30	11
all_values[0]	auto[1]	auto[1]	20131	1			T1	2		T2	1		T3	1
all_values[1]	auto[0]	auto[0]	49961	1			T1	16		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	1615	1			T4	2		T6	11		T9	2
all_values[1]	auto[1]	auto[0]	48567	1			T1	2		T4	2		T5	24
all_values[1]	auto[1]	auto[1]	1584	1			T9	1		T24	10		T30	11
all_values[2]	auto[0]	auto[0]	49441	1			T1	12		T3	1		T4	9
all_values[2]	auto[0]	auto[1]	2771	1			T4	2		T6	16		T8	1
all_values[2]	auto[1]	auto[0]	46939	1			T2	1		T6	1160		T7	4
all_values[2]	auto[1]	auto[1]	2576	1			T1	6		T6	22		T7	5
all_values[3]	auto[0]	auto[0]	52804	1			T1	17		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	333	1			T1	1		T14	1		T16	3
all_values[3]	auto[1]	auto[0]	48293	1			T4	5		T5	24		T6	768
all_values[3]	auto[1]	auto[1]	297	1			T14	2		T13	2		T50	1
all_values[4]	auto[0]	auto[0]	49403	1			T1	7		T2	1		T6	791
all_values[4]	auto[0]	auto[1]	491	1			T13	2		T16	1		T17	1
all_values[4]	auto[1]	auto[0]	51377	1			T1	11		T3	1		T4	11
all_values[4]	auto[1]	auto[1]	456	1			T14	6		T15	2		T16	2
all_values[5]	auto[0]	auto[0]	47658	1			T1	10		T3	1		T4	11
all_values[5]	auto[0]	auto[1]	198	1			T14	2		T16	5		T38	2
all_values[5]	auto[1]	auto[0]	53691	1			T1	8		T2	1		T5	24
all_values[5]	auto[1]	auto[1]	180	1			T16	1		T40	7		T145	5
all_values[6]	auto[0]	auto[0]	50535	1			T1	12		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	202	1			T14	1		T16	2		T38	1
all_values[6]	auto[1]	auto[0]	50790	1			T1	6		T4	11		T5	24
all_values[6]	auto[1]	auto[1]	200	1			T14	4		T16	1		T38	2
all_values[7]	auto[0]	auto[0]	50174	1			T1	10		T2	1		T4	8
all_values[7]	auto[0]	auto[1]	321	1			T14	2		T18	1		T27	1
all_values[7]	auto[1]	auto[0]	50930	1			T1	8		T3	1		T4	3
all_values[7]	auto[1]	auto[1]	302	1			T14	7		T15	2		T18	17