Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2586

1

T1

1

T2

1

T3

1

auto[UartRx]

2586

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4601	1			T1	2		T2	2		T3	2
values[1]	33	1			T20	1		T22	1		T298	1
values[2]	54	1			T20	1		T38	2		T298	1
values[3]	50	1			T39	2		T289	1		T110	1
values[4]	45	1			T20	2		T40	1		T194	1
values[5]	44	1			T20	2		T39	2		T40	1
values[6]	69	1			T6	1		T20	2		T40	2
values[7]	61	1			T6	1		T14	1		T20	1
values[8]	54	1			T6	3		T38	2		T40	1
values[9]	73	1			T6	2		T40	2		T194	2
values[10]	61	1			T14	1		T20	1		T22	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2378	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	9	1			T22	1		T321	1		T111	1
auto[UartTx]	values[2]	22	1			T20	1		T38	1		T110	1
auto[UartTx]	values[3]	20	1			T289	1		T110	1		T113	1
auto[UartTx]	values[4]	15	1			T40	1		T194	1		T112	1
auto[UartTx]	values[5]	19	1			T20	2		T39	2		T289	1
auto[UartTx]	values[6]	23	1			T20	1		T40	1		T111	1
auto[UartTx]	values[7]	19	1			T289	1		T111	1		T113	1
auto[UartTx]	values[8]	19	1			T6	1		T38	1		T60	1
auto[UartTx]	values[9]	27	1			T6	1		T40	2		T194	2
auto[UartTx]	values[10]	26	1			T20	1		T112	1		T322	1
auto[UartRx]	values[0]	2223	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	24	1			T20	1		T298	1		T110	1
auto[UartRx]	values[2]	32	1			T38	1		T298	1		T110	1
auto[UartRx]	values[3]	30	1			T39	2		T111	1		T112	1
auto[UartRx]	values[4]	30	1			T20	2		T110	2		T112	1
auto[UartRx]	values[5]	25	1			T40	1		T322	1		T323	1
auto[UartRx]	values[6]	46	1			T6	1		T20	1		T40	1
auto[UartRx]	values[7]	42	1			T6	1		T14	1		T20	1
auto[UartRx]	values[8]	35	1			T6	2		T38	1		T40	1
auto[UartRx]	values[9]	46	1			T6	1		T110	2		T321	1
auto[UartRx]	values[10]	35	1			T14	1		T22	1		T111	1