Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2393	1			T2	2		T3	3		T4	1
auto[BaudRate115200]	2126	1			T1	1		T4	1		T5	1
auto[BaudRate230400]	2212	1			T4	1		T6	6		T7	1
auto[BaudRate128Kbps]	1995	1			T1	2		T4	2		T6	12
auto[BaudRate256Kbps]	2292	1			T4	1		T6	6		T9	2
auto[BaudRate1Mbps]	1968	1			T1	1		T6	5		T7	1
auto[BaudRate1p5Mbps]	1328	1			T1	1		T4	1		T6	11

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1095	1			T7	6		T44	10		T163	5
freqs[25]	1719	1			T11	8		T30	10		T133	8
freqs[48]	534	1			T2	2		T299	10		T282	10
freqs[50]	316	1			T13	4		T284	12		T190	9
freqs[100]	1230	1			T5	1		T151	5		T149	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	228	1			T7	2		T44	2		T26	12
auto[BaudRate9600]	freqs[25]	252	1			T30	1		T133	1		T50	3
auto[BaudRate9600]	freqs[48]	74	1			T2	2		T299	1		T204	1
auto[BaudRate9600]	freqs[50]	59	1			T284	2		T190	1		T108	1
auto[BaudRate9600]	freqs[100]	172	1			T151	1		T149	2		T152	3
auto[BaudRate115200]	freqs[24]	144	1			T155	1		T55	1		T154	2
auto[BaudRate115200]	freqs[25]	278	1			T11	2		T30	1		T133	1
auto[BaudRate115200]	freqs[48]	75	1			T299	1		T204	2		T324	1
auto[BaudRate115200]	freqs[50]	42	1			T284	1		T108	1		T171	2
auto[BaudRate115200]	freqs[100]	161	1			T5	1		T135	3		T130	1
auto[BaudRate230400]	freqs[24]	158	1			T7	1		T163	2		T26	9
auto[BaudRate230400]	freqs[25]	278	1			T11	2		T30	2		T133	2
auto[BaudRate230400]	freqs[48]	79	1			T325	1		T324	1		T326	3
auto[BaudRate230400]	freqs[50]	50	1			T13	2		T284	2		T190	2
auto[BaudRate230400]	freqs[100]	172	1			T151	1		T149	2		T135	1
auto[BaudRate128Kbps]	freqs[24]	144	1			T7	1		T44	1		T163	1
auto[BaudRate128Kbps]	freqs[25]	264	1			T11	2		T133	1		T117	3
auto[BaudRate128Kbps]	freqs[48]	63	1			T299	4		T204	1		T327	2
auto[BaudRate128Kbps]	freqs[50]	35	1			T13	2		T284	3		T190	3
auto[BaudRate128Kbps]	freqs[100]	143	1			T151	1		T149	1		T311	1
auto[BaudRate256Kbps]	freqs[24]	174	1			T44	2		T163	2		T26	6
auto[BaudRate256Kbps]	freqs[25]	269	1			T30	1		T133	1		T50	1
auto[BaudRate256Kbps]	freqs[48]	80	1			T299	1		T282	3		T204	4
auto[BaudRate256Kbps]	freqs[50]	34	1			T284	1		T108	2		T171	2
auto[BaudRate256Kbps]	freqs[100]	186	1			T135	1		T130	1		T120	3
auto[BaudRate1Mbps]	freqs[24]	148	1			T7	1		T44	2		T26	3
auto[BaudRate1Mbps]	freqs[25]	261	1			T11	1		T30	4		T133	1
auto[BaudRate1Mbps]	freqs[48]	82	1			T299	2		T282	5		T327	1
auto[BaudRate1Mbps]	freqs[50]	51	1			T284	2		T190	1		T108	2
auto[BaudRate1Mbps]	freqs[100]	218	1			T135	1		T120	1		T51	6
auto[BaudRate1p5Mbps]	freqs[25]	117	1			T11	1		T30	1		T133	1
auto[BaudRate1p5Mbps]	freqs[48]	81	1			T299	1		T282	2		T204	1
auto[BaudRate1p5Mbps]	freqs[50]	45	1			T284	1		T190	2		T108	1
auto[BaudRate1p5Mbps]	freqs[100]	178	1			T151	2		T149	1		T135	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded