Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28235581	1			T1	18		T2	1		T3	1
all_levels[1]	205674	1			T4	1		T6	432		T11	1
all_levels[2]	2593	1			T6	18		T12	6		T28	7
all_levels[3]	1169	1			T4	3		T6	5		T29	2
all_levels[4]	812	1			T1	1		T4	3		T6	2
all_levels[5]	602	1			T6	1		T9	3		T12	3
all_levels[6]	455	1			T4	3		T30	2		T47	1
all_levels[7]	371	1			T4	1		T6	2		T12	2
all_levels[8]	342	1			T6	1		T12	2		T24	2
all_levels[9]	249	1			T1	2		T4	5		T6	1
all_levels[10]	214	1			T4	2		T6	2		T29	1
all_levels[11]	161	1			T30	1		T43	2		T44	1
all_levels[12]	153	1			T4	1		T6	1		T7	1
all_levels[13]	164	1			T1	1		T147	1		T148	2
all_levels[14]	131	1			T4	1		T30	1		T148	1
all_levels[15]	120	1			T4	1		T148	2		T135	2
all_levels[16]	118	1			T4	2		T148	1		T149	1
all_levels[17]	91	1			T18	1		T150	1		T128	1
all_levels[18]	92	1			T6	1		T24	1		T30	1
all_levels[19]	66	1			T4	1		T135	1		T27	1
all_levels[20]	84	1			T1	1		T151	1		T134	1
all_levels[21]	57	1			T128	1		T152	1		T153	1
all_levels[22]	75	1			T6	1		T43	2		T149	1
all_levels[23]	62	1			T4	1		T135	3		T154	1
all_levels[24]	69	1			T14	1		T155	1		T134	1
all_levels[25]	43	1			T6	1		T156	1		T157	1
all_levels[26]	51	1			T6	1		T14	1		T148	1
all_levels[27]	56	1			T124	1		T158	1		T157	1
all_levels[28]	41	1			T30	1		T148	1		T159	1
all_levels[29]	47	1			T6	1		T30	2		T43	1
all_levels[30]	39	1			T30	1		T148	2		T158	1
all_levels[31]	52	1			T134	1		T160	1		T39	1
all_levels[32]	39	1			T151	1		T161	1		T154	1
all_levels[33]	46	1			T14	2		T133	1		T149	1
all_levels[34]	35	1			T1	2		T162	1		T160	2
all_levels[35]	28	1			T44	1		T128	1		T158	1
all_levels[36]	24	1			T30	1		T44	1		T163	1
all_levels[37]	19	1			T155	1		T134	1		T53	1
all_levels[38]	31	1			T163	1		T158	2		T164	2
all_levels[39]	23	1			T154	1		T41	1		T165	1
all_levels[40]	16	1			T166	2		T167	1		T146	1
all_levels[41]	15	1			T168	1		T41	1		T169	1
all_levels[42]	24	1			T148	1		T168	1		T169	1
all_levels[43]	22	1			T44	1		T134	1		T170	1
all_levels[44]	22	1			T147	1		T134	3		T124	1
all_levels[45]	18	1			T134	2		T171	1		T172	4
all_levels[46]	4	1			T173	1		T174	1		T175	1
all_levels[47]	26	1			T148	1		T176	1		T124	1
all_levels[48]	13	1			T39	1		T106	1		T177	4
all_levels[49]	12	1			T176	1		T122	1		T178	1
all_levels[50]	5	1			T179	1		T180	1		T181	1
all_levels[51]	14	1			T132	1		T110	1		T171	1
all_levels[52]	12	1			T127	1		T119	1		T107	2
all_levels[53]	11	1			T124	1		T110	1		T182	1
all_levels[54]	14	1			T30	1		T183	1		T167	1
all_levels[55]	13	1			T160	1		T127	3		T154	1
all_levels[56]	13	1			T122	1		T105	1		T184	2
all_levels[57]	4	1			T185	1		T186	1		T64	1
all_levels[58]	12	1			T166	1		T187	1		T188	1
all_levels[59]	7	1			T127	1		T179	1		T189	2
all_levels[60]	6	1			T132	1		T158	1		T188	1
all_levels[61]	12	1			T30	1		T150	1		T190	1
all_levels[62]	15	1			T191	2		T192	1		T193	1
all_levels[63]	12	1			T105	1		T194	1		T192	1
all_levels[64]	89	1			T128	1		T119	4		T124	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28445839

1

T1

20

T4

60

T5

1148

auto[1]

4651

1

T1

5

T2

1

T3

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35] , all_levels[36]]	[auto[1]]	--	--	2
[all_levels[41] , all_levels[42]]	[auto[1]]	--	--	2
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28231370	1			T1	15		T4	38		T5	1148
all_levels[0]	auto[1]	4211	1			T1	3		T2	1		T3	1
all_levels[1]	auto[0]	205610	1			T4	1		T6	432		T11	1
all_levels[1]	auto[1]	64	1			T135	1		T195	3		T152	2
all_levels[2]	auto[0]	2568	1			T6	18		T12	6		T28	7
all_levels[2]	auto[1]	25	1			T156	1		T196	1		T191	1
all_levels[3]	auto[0]	1143	1			T4	3		T6	5		T29	2
all_levels[3]	auto[1]	26	1			T162	2		T127	2		T152	1
all_levels[4]	auto[0]	795	1			T1	1		T4	3		T6	2
all_levels[4]	auto[1]	17	1			T164	1		T197	2		T198	2
all_levels[5]	auto[0]	581	1			T6	1		T9	1		T12	3
all_levels[5]	auto[1]	21	1			T9	2		T190	1		T199	1
all_levels[6]	auto[0]	422	1			T4	3		T30	2		T47	1
all_levels[6]	auto[1]	33	1			T127	1		T196	2		T166	1
all_levels[7]	auto[0]	363	1			T4	1		T6	2		T12	2
all_levels[7]	auto[1]	8	1			T153	1		T200	1		T201	1
all_levels[8]	auto[0]	319	1			T6	1		T12	2		T24	2
all_levels[8]	auto[1]	23	1			T135	3		T202	1		T153	1
all_levels[9]	auto[0]	239	1			T1	1		T4	3		T6	1
all_levels[9]	auto[1]	10	1			T1	1		T4	2		T203	1
all_levels[10]	auto[0]	203	1			T4	2		T6	2		T29	1
all_levels[10]	auto[1]	11	1			T153	1		T204	1		T205	2
all_levels[11]	auto[0]	153	1			T30	1		T43	1		T44	1
all_levels[11]	auto[1]	8	1			T43	1		T206	2		T187	1
all_levels[12]	auto[0]	147	1			T4	1		T6	1		T7	1
all_levels[12]	auto[1]	6	1			T207	1		T208	1		T209	2
all_levels[13]	auto[0]	156	1			T1	1		T147	1		T148	2
all_levels[13]	auto[1]	8	1			T210	3		T211	1		T212	1
all_levels[14]	auto[0]	121	1			T4	1		T30	1		T148	1
all_levels[14]	auto[1]	10	1			T213	3		T214	1		T215	1
all_levels[15]	auto[0]	108	1			T4	1		T148	1		T135	2
all_levels[15]	auto[1]	12	1			T148	1		T102	2		T216	1
all_levels[16]	auto[0]	110	1			T4	1		T148	1		T149	1
all_levels[16]	auto[1]	8	1			T4	1		T161	1		T165	3
all_levels[17]	auto[0]	87	1			T18	1		T150	1		T128	1
all_levels[17]	auto[1]	4	1			T217	1		T201	1		T218	1
all_levels[18]	auto[0]	85	1			T6	1		T24	1		T30	1
all_levels[18]	auto[1]	7	1			T217	1		T219	1		T220	1
all_levels[19]	auto[0]	62	1			T4	1		T135	1		T27	1
all_levels[19]	auto[1]	4	1			T221	1		T222	2		T223	1
all_levels[20]	auto[0]	79	1			T1	1		T151	1		T134	1
all_levels[20]	auto[1]	5	1			T196	1		T224	1		T225	1
all_levels[21]	auto[0]	54	1			T128	1		T152	1		T153	1
all_levels[21]	auto[1]	3	1			T226	1		T227	2		-	-
all_levels[22]	auto[0]	70	1			T6	1		T43	1		T149	1
all_levels[22]	auto[1]	5	1			T43	1		T228	4		-	-
all_levels[23]	auto[0]	56	1			T4	1		T135	1		T154	1
all_levels[23]	auto[1]	6	1			T135	2		T101	1		T110	1
all_levels[24]	auto[0]	64	1			T14	1		T155	1		T134	1
all_levels[24]	auto[1]	5	1			T229	1		T230	2		T231	2
all_levels[25]	auto[0]	40	1			T6	1		T156	1		T157	1
all_levels[25]	auto[1]	3	1			T232	2		T233	1		-	-
all_levels[26]	auto[0]	49	1			T6	1		T14	1		T148	1
all_levels[26]	auto[1]	2	1			T234	1		T235	1		-	-
all_levels[27]	auto[0]	47	1			T124	1		T158	1		T157	1
all_levels[27]	auto[1]	9	1			T236	1		T237	4		T238	3
all_levels[28]	auto[0]	36	1			T30	1		T148	1		T159	1
all_levels[28]	auto[1]	5	1			T136	1		T239	1		T240	3
all_levels[29]	auto[0]	43	1			T6	1		T30	2		T43	1
all_levels[29]	auto[1]	4	1			T241	1		T226	2		T242	1
all_levels[30]	auto[0]	37	1			T30	1		T148	1		T158	1
all_levels[30]	auto[1]	2	1			T148	1		T243	1		-	-
all_levels[31]	auto[0]	45	1			T134	1		T160	1		T39	1
all_levels[31]	auto[1]	7	1			T174	1		T244	1		T245	2
all_levels[32]	auto[0]	35	1			T151	1		T161	1		T154	1
all_levels[32]	auto[1]	4	1			T246	1		T233	2		T247	1
all_levels[33]	auto[0]	40	1			T14	2		T133	1		T149	1
all_levels[33]	auto[1]	6	1			T129	1		T136	1		T248	1
all_levels[34]	auto[0]	30	1			T1	1		T162	1		T160	1
all_levels[34]	auto[1]	5	1			T1	1		T160	1		T249	2
all_levels[35]	auto[0]	28	1			T44	1		T128	1		T158	1
all_levels[36]	auto[0]	24	1			T30	1		T44	1		T163	1
all_levels[37]	auto[0]	18	1			T155	1		T134	1		T53	1
all_levels[37]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[38]	auto[0]	28	1			T163	1		T158	2		T164	1
all_levels[38]	auto[1]	3	1			T164	1		T251	1		T252	1
all_levels[39]	auto[0]	20	1			T154	1		T41	1		T165	1
all_levels[39]	auto[1]	3	1			T253	1		T238	2		-	-
all_levels[40]	auto[0]	12	1			T166	1		T167	1		T146	1
all_levels[40]	auto[1]	4	1			T166	1		T254	1		T255	1
all_levels[41]	auto[0]	15	1			T168	1		T41	1		T169	1
all_levels[42]	auto[0]	24	1			T148	1		T168	1		T169	1
all_levels[43]	auto[0]	16	1			T44	1		T134	1		T170	1
all_levels[43]	auto[1]	6	1			T256	1		T257	2		T258	2
all_levels[44]	auto[0]	21	1			T147	1		T134	3		T124	1
all_levels[44]	auto[1]	1	1			T259	1		-	-		-	-
all_levels[45]	auto[0]	13	1			T134	2		T171	1		T172	1
all_levels[45]	auto[1]	5	1			T172	3		T260	2		-	-
all_levels[46]	auto[0]	4	1			T173	1		T174	1		T175	1
all_levels[47]	auto[0]	22	1			T148	1		T176	1		T124	1
all_levels[47]	auto[1]	4	1			T110	3		T261	1		-	-
all_levels[48]	auto[0]	9	1			T39	1		T106	1		T177	1
all_levels[48]	auto[1]	4	1			T177	3		T262	1		-	-
all_levels[49]	auto[0]	10	1			T176	1		T122	1		T178	1
all_levels[49]	auto[1]	2	1			T230	1		T263	1		-	-
all_levels[50]	auto[0]	5	1			T179	1		T180	1		T181	1
all_levels[51]	auto[0]	13	1			T132	1		T110	1		T171	1
all_levels[51]	auto[1]	1	1			T174	1		-	-		-	-
all_levels[52]	auto[0]	10	1			T127	1		T119	1		T107	1
all_levels[52]	auto[1]	2	1			T107	1		T264	1		-	-
all_levels[53]	auto[0]	9	1			T124	1		T110	1		T182	1
all_levels[53]	auto[1]	2	1			T265	2		-	-		-	-
all_levels[54]	auto[0]	12	1			T30	1		T183	1		T167	1
all_levels[54]	auto[1]	2	1			T266	1		T267	1		-	-
all_levels[55]	auto[0]	11	1			T160	1		T127	1		T154	1
all_levels[55]	auto[1]	2	1			T127	2		-	-		-	-
all_levels[56]	auto[0]	12	1			T122	1		T105	1		T184	1
all_levels[56]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[57]	auto[0]	4	1			T185	1		T186	1		T64	1
all_levels[58]	auto[0]	10	1			T166	1		T187	1		T188	1
all_levels[58]	auto[1]	2	1			T173	2		-	-		-	-
all_levels[59]	auto[0]	6	1			T127	1		T179	1		T189	1
all_levels[59]	auto[1]	1	1			T189	1		-	-		-	-
all_levels[60]	auto[0]	6	1			T132	1		T158	1		T188	1
all_levels[61]	auto[0]	10	1			T30	1		T150	1		T190	1
all_levels[61]	auto[1]	2	1			T268	1		T269	1		-	-
all_levels[62]	auto[0]	12	1			T191	1		T192	1		T193	1
all_levels[62]	auto[1]	3	1			T191	1		T270	2		-	-
all_levels[63]	auto[0]	10	1			T105	1		T194	1		T192	1
all_levels[63]	auto[1]	2	1			T271	1		T218	1		-	-
all_levels[64]	auto[0]	78	1			T128	1		T119	3		T124	1
all_levels[64]	auto[1]	11	1			T119	1		T197	1		T262	3