Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101727	1			T1	18		T2	1		T3	1
all_pins[1]	101727	1			T1	18		T2	1		T3	1
all_pins[2]	101727	1			T1	18		T2	1		T3	1
all_pins[3]	101727	1			T1	18		T2	1		T3	1
all_pins[4]	101727	1			T1	18		T2	1		T3	1
all_pins[5]	101727	1			T1	18		T2	1		T3	1
all_pins[6]	101727	1			T1	18		T2	1		T3	1
all_pins[7]	101727	1			T1	18		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	787205	1			T1	136		T2	7		T3	7
values[0x1]	26611	1			T1	8		T2	1		T3	1
transitions[0x0=>0x1]	25605	1			T1	8		T2	1		T3	1
transitions[0x1=>0x0]	25174	1			T1	7		T4	4		T6	431

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81534	1			T1	16		T4	6		T5	24
all_pins[0]	values[0x1]	20193	1			T1	2		T2	1		T3	1
all_pins[0]	transitions[0x0=>0x1]	19709	1			T1	2		T2	1		T3	1
all_pins[0]	transitions[0x1=>0x0]	1097	1			T9	1		T24	9		T30	11
all_pins[1]	values[0x0]	100146	1			T1	18		T2	1		T3	1
all_pins[1]	values[0x1]	1581	1			T9	1		T24	10		T30	11
all_pins[1]	transitions[0x0=>0x1]	1454	1			T9	1		T24	10		T30	11
all_pins[1]	transitions[0x1=>0x0]	2507	1			T1	6		T6	22		T7	5
all_pins[2]	values[0x0]	99093	1			T1	12		T2	1		T3	1
all_pins[2]	values[0x1]	2634	1			T1	6		T6	22		T7	5
all_pins[2]	transitions[0x0=>0x1]	2571	1			T1	6		T6	22		T7	5
all_pins[2]	transitions[0x1=>0x0]	234	1			T14	2		T13	2		T50	1
all_pins[3]	values[0x0]	101430	1			T1	18		T2	1		T3	1
all_pins[3]	values[0x1]	297	1			T14	2		T13	2		T50	1
all_pins[3]	transitions[0x0=>0x1]	253	1			T14	1		T13	2		T50	1
all_pins[3]	transitions[0x1=>0x0]	412	1			T14	5		T15	2		T16	2
all_pins[4]	values[0x0]	101271	1			T1	18		T2	1		T3	1
all_pins[4]	values[0x1]	456	1			T14	6		T15	2		T16	2
all_pins[4]	transitions[0x0=>0x1]	389	1			T14	6		T15	2		T16	2
all_pins[4]	transitions[0x1=>0x0]	156	1			T16	1		T39	1		T40	6
all_pins[5]	values[0x0]	101504	1			T1	18		T2	1		T3	1
all_pins[5]	values[0x1]	223	1			T16	1		T39	3		T40	7
all_pins[5]	transitions[0x0=>0x1]	170	1			T16	1		T39	3		T40	6
all_pins[5]	transitions[0x1=>0x0]	872	1			T9	1		T24	6		T44	2
all_pins[6]	values[0x0]	100802	1			T1	18		T2	1		T3	1
all_pins[6]	values[0x1]	925	1			T9	1		T24	6		T44	2
all_pins[6]	transitions[0x0=>0x1]	885	1			T9	1		T24	6		T44	2
all_pins[6]	transitions[0x1=>0x0]	262	1			T14	3		T15	2		T18	17
all_pins[7]	values[0x0]	101425	1			T1	18		T2	1		T3	1
all_pins[7]	values[0x1]	302	1			T14	7		T15	2		T18	17
all_pins[7]	transitions[0x0=>0x1]	174	1			T14	2		T15	1		T18	17
all_pins[7]	transitions[0x1=>0x0]	19634	1			T1	1		T4	4		T6	409