Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6360416	1			T1	7		T2	1		T4	37
all_levels[1]	1418565	1			T1	4		T4	4		T5	1147
all_levels[2]	375129	1			T4	1		T6	5907		T7	4
all_levels[3]	278865	1			T4	3		T6	6284		T7	2
all_levels[4]	273911	1			T4	4		T6	13501		T7	4
all_levels[5]	510271	1			T4	5		T6	6210		T7	8
all_levels[6]	202488	1			T1	2		T4	2		T6	5295
all_levels[7]	234789	1			T6	44141		T7	2		T12	46
all_levels[8]	252413	1			T4	1		T6	5315		T12	3
all_levels[9]	278509	1			T4	1		T6	5427		T28	25
all_levels[10]	198406	1			T1	1		T6	15675		T7	1
all_levels[11]	380407	1			T6	4690		T7	2		T11	1
all_levels[12]	221072	1			T4	2		T6	3525		T7	9
all_levels[13]	219418	1			T6	3684		T28	12		T29	18
all_levels[14]	266242	1			T1	4		T6	4801		T7	2
all_levels[15]	240667	1			T1	1		T6	3817		T7	1
all_levels[16]	277190	1			T1	2		T6	3800		T29	5
all_levels[17]	319204	1			T6	6283		T29	1		T24	20
all_levels[18]	187633	1			T4	1		T6	3305		T28	3
all_levels[19]	434581	1			T6	2518		T43	1		T14	2089
all_levels[20]	665616	1			T6	2437		T28	7		T14	1925
all_levels[21]	317106	1			T1	1		T6	2436		T28	4
all_levels[22]	208870	1			T6	2458		T14	2065		T275	41
all_levels[23]	290614	1			T6	2537		T28	5		T14	117879
all_levels[24]	177551	1			T4	2		T6	1809		T7	2
all_levels[25]	323151	1			T6	2123		T28	12		T44	1
all_levels[26]	179004	1			T6	2427		T28	1		T43	3
all_levels[27]	246724	1			T6	2601		T29	3		T14	3639
all_levels[28]	151070	1			T4	1		T6	1958		T30	6
all_levels[29]	259899	1			T6	2401		T28	1		T43	12
all_levels[30]	310979	1			T6	2405		T9	5		T28	2
all_levels[31]	1060824	1			T6	2698		T28	3		T30	1
all_levels[32]	11328474	1			T1	4		T6	7365		T7	6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28445839

1

T1

20

T4

60

T5

1148

auto[1]

4219

1

T1

6

T2

1

T4

4

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6358205	1			T1	5		T4	33		T5	1
all_levels[0]	auto[1]	2211	1			T1	2		T2	1		T4	4
all_levels[1]	auto[0]	1418241	1			T1	3		T4	4		T5	1147
all_levels[1]	auto[1]	324	1			T1	1		T29	1		T280	1
all_levels[2]	auto[0]	375095	1			T4	1		T6	5907		T7	4
all_levels[2]	auto[1]	34	1			T156	1		T101	1		T281	1
all_levels[3]	auto[0]	278708	1			T4	3		T6	6284		T7	2
all_levels[3]	auto[1]	157	1			T151	1		T13	12		T176	1
all_levels[4]	auto[0]	273849	1			T4	4		T6	13501		T7	4
all_levels[4]	auto[1]	62	1			T152	1		T196	1		T200	2
all_levels[5]	auto[0]	510230	1			T4	5		T6	6210		T7	8
all_levels[5]	auto[1]	41	1			T162	1		T53	2		T197	2
all_levels[6]	auto[0]	202455	1			T1	2		T4	2		T6	5295
all_levels[6]	auto[1]	33	1			T9	1		T280	1		T55	1
all_levels[7]	auto[0]	234654	1			T6	44141		T7	2		T12	46
all_levels[7]	auto[1]	135	1			T13	7		T152	1		T299	1
all_levels[8]	auto[0]	252384	1			T4	1		T6	5315		T12	3
all_levels[8]	auto[1]	29	1			T17	9		T152	1		T183	1
all_levels[9]	auto[0]	278484	1			T4	1		T6	5427		T28	25
all_levels[9]	auto[1]	25	1			T161	1		T55	1		T320	2
all_levels[10]	auto[0]	198371	1			T1	1		T6	15675		T7	1
all_levels[10]	auto[1]	35	1			T147	1		T160	3		T328	1
all_levels[11]	auto[0]	380391	1			T6	4690		T7	2		T11	1
all_levels[11]	auto[1]	16	1			T280	1		T298	1		T198	1
all_levels[12]	auto[0]	221054	1			T4	2		T6	3525		T7	9
all_levels[12]	auto[1]	18	1			T133	1		T152	1		T329	3
all_levels[13]	auto[0]	219392	1			T6	3684		T28	12		T29	18
all_levels[13]	auto[1]	26	1			T316	1		T157	1		T217	1
all_levels[14]	auto[0]	266218	1			T1	3		T6	4801		T7	2
all_levels[14]	auto[1]	24	1			T1	1		T153	1		T273	1
all_levels[15]	auto[0]	240525	1			T1	1		T6	3817		T7	1
all_levels[15]	auto[1]	142	1			T44	1		T151	2		T15	14
all_levels[16]	auto[0]	277122	1			T1	2		T6	3800		T29	5
all_levels[16]	auto[1]	68	1			T147	2		T104	2		T330	1
all_levels[17]	auto[0]	319179	1			T6	6283		T29	1		T24	20
all_levels[17]	auto[1]	25	1			T148	2		T135	1		T104	1
all_levels[18]	auto[0]	187614	1			T4	1		T6	3305		T28	3
all_levels[18]	auto[1]	19	1			T48	1		T103	1		T331	3
all_levels[19]	auto[0]	434556	1			T6	2518		T43	1		T14	2089
all_levels[19]	auto[1]	25	1			T49	1		T156	1		T299	2
all_levels[20]	auto[0]	665605	1			T6	2437		T28	7		T14	1925
all_levels[20]	auto[1]	11	1			T54	1		T332	3		T333	1
all_levels[21]	auto[0]	317082	1			T1	1		T6	2436		T28	4
all_levels[21]	auto[1]	24	1			T202	2		T17	1		T334	3
all_levels[22]	auto[0]	208855	1			T6	2458		T14	2065		T275	41
all_levels[22]	auto[1]	15	1			T152	2		T190	1		T335	1
all_levels[23]	auto[0]	290580	1			T6	2537		T28	5		T14	117879
all_levels[23]	auto[1]	34	1			T123	1		T273	1		T336	2
all_levels[24]	auto[0]	177532	1			T4	2		T6	1809		T7	2
all_levels[24]	auto[1]	19	1			T139	1		T327	2		T337	1
all_levels[25]	auto[0]	323130	1			T6	2123		T28	12		T44	1
all_levels[25]	auto[1]	21	1			T161	2		T153	2		T302	5
all_levels[26]	auto[0]	178979	1			T6	2427		T28	1		T43	2
all_levels[26]	auto[1]	25	1			T43	1		T162	2		T107	2
all_levels[27]	auto[0]	246708	1			T6	2601		T29	3		T14	3639
all_levels[27]	auto[1]	16	1			T104	1		T108	1		T164	1
all_levels[28]	auto[0]	151047	1			T4	1		T6	1958		T30	6
all_levels[28]	auto[1]	23	1			T122	2		T248	1		T262	1
all_levels[29]	auto[0]	259878	1			T6	2401		T28	1		T43	11
all_levels[29]	auto[1]	21	1			T43	1		T202	1		T166	1
all_levels[30]	auto[0]	310947	1			T6	2405		T9	3		T28	2
all_levels[30]	auto[1]	32	1			T9	2		T50	5		T110	3
all_levels[31]	auto[0]	1060798	1			T6	2698		T28	3		T30	1
all_levels[31]	auto[1]	26	1			T147	1		T132	2		T136	2
all_levels[32]	auto[0]	11327971	1			T1	2		T6	7364		T7	6
all_levels[32]	auto[1]	503	1			T1	2		T6	1		T43	1