Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	841	1			T14	11		T16	7		T38	7
all_values[1]	841	1			T14	11		T16	7		T38	7
all_values[2]	841	1			T14	11		T16	7		T38	7
all_values[3]	841	1			T14	11		T16	7		T38	7
all_values[4]	841	1			T14	11		T16	7		T38	7
all_values[5]	841	1			T14	11		T16	7		T38	7
all_values[6]	841	1			T14	11		T16	7		T38	7
all_values[7]	841	1			T14	11		T16	7		T38	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3600

1

T14

46

T16

28

T38

27

auto[1]

3128

1

T14

42

T16

28

T38

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2449

1

T14

26

T16

20

T38

19

auto[1]

4279

1

T14

62

T16

36

T38

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3935

1

T14

40

T16

29

T38

31

auto[1]

2793

1

T14

48

T16

27

T38

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	285	1			T14	2		T16	1		T40	6
all_values[0]	auto[0]	auto[1]	auto[1]	231	1			T14	4		T16	1		T38	4
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T14	2		T16	2		T40	6
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T14	3		T16	3		T38	3
all_values[1]	auto[0]	auto[0]	auto[0]	251	1			T14	3		T16	1		T38	3
all_values[1]	auto[0]	auto[1]	auto[0]	247	1			T14	2		T16	4		T38	2
all_values[1]	auto[1]	auto[0]	auto[1]	179	1			T14	3		T40	6		T145	1
all_values[1]	auto[1]	auto[1]	auto[1]	164	1			T14	3		T16	2		T38	2
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T14	3		T16	3		T40	1
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T16	1		T38	1		T40	1
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T14	1		T16	2		T38	2
all_values[2]	auto[0]	auto[1]	auto[1]	93	1			T14	1		T38	2		T40	3
all_values[2]	auto[1]	auto[0]	auto[1]	179	1			T14	3		T16	1		T38	1
all_values[2]	auto[1]	auto[1]	auto[1]	151	1			T14	3		T38	1		T40	7
all_values[3]	auto[0]	auto[0]	auto[0]	192	1			T14	3		T16	1		T40	6
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T16	1		T38	1
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T14	1		T16	1		T38	1
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T40	3		T111	3		T146	1
all_values[3]	auto[1]	auto[0]	auto[1]	194	1			T14	3		T16	2		T38	4
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T14	3		T16	2		T38	1
all_values[4]	auto[0]	auto[0]	auto[0]	162	1			T14	2		T38	1		T40	6
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T38	1		T40	1		T112	2
all_values[4]	auto[0]	auto[1]	auto[0]	123	1			T16	2		T40	8		T145	2
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T14	1		T16	1		T38	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T14	3		T16	1		T38	3
all_values[4]	auto[1]	auto[1]	auto[1]	186	1			T14	5		T16	3		T38	1
all_values[5]	auto[0]	auto[0]	auto[0]	163	1			T14	5		T38	2		T40	5
all_values[5]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T16	2		T38	1
all_values[5]	auto[0]	auto[1]	auto[0]	169	1			T14	1		T38	1		T40	5
all_values[5]	auto[0]	auto[1]	auto[1]	74	1			T16	1		T40	3		T145	3
all_values[5]	auto[1]	auto[0]	auto[1]	194	1			T14	3		T16	4		T38	2
all_values[5]	auto[1]	auto[1]	auto[1]	158	1			T14	1		T38	1		T40	5
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T14	4		T16	1		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T16	1		T40	2		T111	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T14	1		T16	1		T38	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T14	2		T38	1		T40	1
all_values[6]	auto[1]	auto[0]	auto[1]	198	1			T14	2		T16	3		T38	2
all_values[6]	auto[1]	auto[1]	auto[1]	164	1			T14	2		T16	1		T38	2
all_values[7]	auto[0]	auto[0]	auto[0]	192	1			T16	1		T38	2		T40	10
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T40	3		T111	1		T146	2
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T16	3		T38	3		T40	3
all_values[7]	auto[0]	auto[1]	auto[1]	67	1			T14	2		T40	1		T111	2
all_values[7]	auto[1]	auto[0]	auto[1]	202	1			T14	3		T16	2		T38	2
all_values[7]	auto[1]	auto[1]	auto[1]	147	1			T14	6		T16	1		T40	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal