Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.64


Total test records in report: 1319
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T1257 /workspace/coverage/cover_reg_top/40.uart_intr_test.1176644532 May 12 12:26:48 PM PDT 24 May 12 12:26:49 PM PDT 24 56387368 ps
T1258 /workspace/coverage/cover_reg_top/24.uart_intr_test.2193668629 May 12 12:27:58 PM PDT 24 May 12 12:28:01 PM PDT 24 13957398 ps
T141 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3769021666 May 12 12:26:24 PM PDT 24 May 12 12:26:26 PM PDT 24 278827327 ps
T1259 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1259402819 May 12 12:30:20 PM PDT 24 May 12 12:30:23 PM PDT 24 64412112 ps
T1260 /workspace/coverage/cover_reg_top/12.uart_tl_errors.573324698 May 12 12:25:59 PM PDT 24 May 12 12:26:03 PM PDT 24 471707372 ps
T1261 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2473129847 May 12 12:22:47 PM PDT 24 May 12 12:22:48 PM PDT 24 152149095 ps
T1262 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3833046893 May 12 12:27:03 PM PDT 24 May 12 12:27:06 PM PDT 24 472372616 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1803478931 May 12 12:23:42 PM PDT 24 May 12 12:23:45 PM PDT 24 42727874 ps
T1264 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2496701462 May 12 12:22:09 PM PDT 24 May 12 12:22:10 PM PDT 24 46106531 ps
T1265 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3438068934 May 12 12:26:16 PM PDT 24 May 12 12:26:17 PM PDT 24 16437710 ps
T1266 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2029084169 May 12 12:23:34 PM PDT 24 May 12 12:23:36 PM PDT 24 53263078 ps
T76 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1381379210 May 12 12:26:37 PM PDT 24 May 12 12:26:39 PM PDT 24 14487998 ps
T1267 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3578480250 May 12 12:23:45 PM PDT 24 May 12 12:23:47 PM PDT 24 28821548 ps
T77 /workspace/coverage/cover_reg_top/13.uart_csr_rw.388422144 May 12 12:25:59 PM PDT 24 May 12 12:26:01 PM PDT 24 15882850 ps
T1268 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3138456214 May 12 12:25:50 PM PDT 24 May 12 12:25:51 PM PDT 24 72921133 ps
T1269 /workspace/coverage/cover_reg_top/16.uart_intr_test.1512941269 May 12 12:26:48 PM PDT 24 May 12 12:26:50 PM PDT 24 36450761 ps
T1270 /workspace/coverage/cover_reg_top/7.uart_intr_test.2050747441 May 12 12:26:51 PM PDT 24 May 12 12:26:52 PM PDT 24 14137463 ps
T1271 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1035448724 May 12 12:22:18 PM PDT 24 May 12 12:22:19 PM PDT 24 20807490 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2324502442 May 12 12:21:38 PM PDT 24 May 12 12:21:41 PM PDT 24 79778879 ps
T1273 /workspace/coverage/cover_reg_top/5.uart_intr_test.1560004981 May 12 12:26:59 PM PDT 24 May 12 12:27:01 PM PDT 24 21785185 ps
T1274 /workspace/coverage/cover_reg_top/41.uart_intr_test.3545128832 May 12 12:26:35 PM PDT 24 May 12 12:26:36 PM PDT 24 52709694 ps
T1275 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3993798058 May 12 12:22:23 PM PDT 24 May 12 12:22:24 PM PDT 24 74768458 ps
T1276 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2280013449 May 12 12:26:59 PM PDT 24 May 12 12:27:01 PM PDT 24 36943882 ps
T1277 /workspace/coverage/cover_reg_top/10.uart_intr_test.3904427552 May 12 12:27:12 PM PDT 24 May 12 12:27:14 PM PDT 24 40993774 ps
T1278 /workspace/coverage/cover_reg_top/16.uart_tl_errors.188087538 May 12 12:26:06 PM PDT 24 May 12 12:26:08 PM PDT 24 296756478 ps
T1279 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3804765079 May 12 12:25:11 PM PDT 24 May 12 12:25:12 PM PDT 24 88240973 ps
T1280 /workspace/coverage/cover_reg_top/31.uart_intr_test.835027505 May 12 12:26:48 PM PDT 24 May 12 12:26:50 PM PDT 24 164292407 ps
T1281 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2854113797 May 12 12:26:05 PM PDT 24 May 12 12:26:07 PM PDT 24 12935952 ps
T1282 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2953172843 May 12 12:22:09 PM PDT 24 May 12 12:22:10 PM PDT 24 16075210 ps
T1283 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.675363203 May 12 12:23:38 PM PDT 24 May 12 12:23:39 PM PDT 24 15162358 ps
T78 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.185580144 May 12 12:21:34 PM PDT 24 May 12 12:21:35 PM PDT 24 36683070 ps
T142 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.759355705 May 12 12:24:13 PM PDT 24 May 12 12:24:15 PM PDT 24 137027084 ps
T1284 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4130178533 May 12 12:26:18 PM PDT 24 May 12 12:26:19 PM PDT 24 24778816 ps
T1285 /workspace/coverage/cover_reg_top/10.uart_tl_errors.4133181418 May 12 12:27:12 PM PDT 24 May 12 12:27:15 PM PDT 24 143909718 ps
T1286 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3402277193 May 12 12:26:24 PM PDT 24 May 12 12:26:25 PM PDT 24 12618825 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3029497534 May 12 12:25:00 PM PDT 24 May 12 12:25:02 PM PDT 24 455127043 ps
T1288 /workspace/coverage/cover_reg_top/30.uart_intr_test.509138192 May 12 12:26:37 PM PDT 24 May 12 12:26:39 PM PDT 24 25697649 ps
T1289 /workspace/coverage/cover_reg_top/17.uart_intr_test.3955897356 May 12 12:23:28 PM PDT 24 May 12 12:23:29 PM PDT 24 11883839 ps
T1290 /workspace/coverage/cover_reg_top/20.uart_intr_test.498058354 May 12 12:26:44 PM PDT 24 May 12 12:26:45 PM PDT 24 14350162 ps
T1291 /workspace/coverage/cover_reg_top/38.uart_intr_test.2367965919 May 12 12:26:48 PM PDT 24 May 12 12:26:49 PM PDT 24 120441275 ps
T1292 /workspace/coverage/cover_reg_top/19.uart_intr_test.319655791 May 12 12:26:31 PM PDT 24 May 12 12:26:32 PM PDT 24 35102644 ps
T1293 /workspace/coverage/cover_reg_top/18.uart_tl_errors.695165364 May 12 12:26:18 PM PDT 24 May 12 12:26:21 PM PDT 24 462001258 ps
T1294 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3742625696 May 12 12:30:04 PM PDT 24 May 12 12:30:06 PM PDT 24 83437477 ps
T1295 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.163700468 May 12 12:27:58 PM PDT 24 May 12 12:28:01 PM PDT 24 34502217 ps
T1296 /workspace/coverage/cover_reg_top/36.uart_intr_test.865950014 May 12 12:26:48 PM PDT 24 May 12 12:26:50 PM PDT 24 46278229 ps
T1297 /workspace/coverage/cover_reg_top/33.uart_intr_test.1770837119 May 12 12:26:36 PM PDT 24 May 12 12:26:38 PM PDT 24 13707102 ps
T1298 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1263733227 May 12 12:26:44 PM PDT 24 May 12 12:26:46 PM PDT 24 36986358 ps
T1299 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2626979452 May 12 12:25:58 PM PDT 24 May 12 12:26:01 PM PDT 24 36340318 ps
T1300 /workspace/coverage/cover_reg_top/3.uart_csr_rw.4263501315 May 12 12:25:57 PM PDT 24 May 12 12:25:59 PM PDT 24 32472547 ps
T1301 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2617467299 May 12 12:26:44 PM PDT 24 May 12 12:26:47 PM PDT 24 335189044 ps
T1302 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1366533404 May 12 12:27:09 PM PDT 24 May 12 12:27:12 PM PDT 24 72317773 ps
T1303 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1346793419 May 12 12:25:32 PM PDT 24 May 12 12:25:33 PM PDT 24 64737413 ps
T1304 /workspace/coverage/cover_reg_top/44.uart_intr_test.752766594 May 12 12:27:57 PM PDT 24 May 12 12:28:00 PM PDT 24 15691479 ps
T1305 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2888959658 May 12 12:26:13 PM PDT 24 May 12 12:26:14 PM PDT 24 14360273 ps
T79 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1953734938 May 12 12:21:28 PM PDT 24 May 12 12:21:31 PM PDT 24 1079246681 ps
T1306 /workspace/coverage/cover_reg_top/17.uart_csr_rw.126209963 May 12 12:26:17 PM PDT 24 May 12 12:26:18 PM PDT 24 37795546 ps
T1307 /workspace/coverage/cover_reg_top/21.uart_intr_test.3034964316 May 12 12:26:35 PM PDT 24 May 12 12:26:37 PM PDT 24 35091081 ps
T1308 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2973811904 May 12 12:26:13 PM PDT 24 May 12 12:26:14 PM PDT 24 21665080 ps
T1309 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2819053014 May 12 12:21:02 PM PDT 24 May 12 12:21:03 PM PDT 24 71922134 ps
T1310 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.381070459 May 12 12:22:36 PM PDT 24 May 12 12:22:38 PM PDT 24 63741807 ps
T1311 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2139919960 May 12 12:26:51 PM PDT 24 May 12 12:26:53 PM PDT 24 32110121 ps
T1312 /workspace/coverage/cover_reg_top/43.uart_intr_test.2436173720 May 12 12:26:36 PM PDT 24 May 12 12:26:38 PM PDT 24 43095928 ps
T1313 /workspace/coverage/cover_reg_top/15.uart_csr_rw.633091161 May 12 12:27:03 PM PDT 24 May 12 12:27:04 PM PDT 24 15999402 ps
T1314 /workspace/coverage/cover_reg_top/8.uart_intr_test.89451372 May 12 12:23:20 PM PDT 24 May 12 12:23:21 PM PDT 24 53092054 ps
T1315 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3864324457 May 12 12:32:51 PM PDT 24 May 12 12:32:52 PM PDT 24 24222562 ps
T1316 /workspace/coverage/cover_reg_top/29.uart_intr_test.662966128 May 12 12:26:36 PM PDT 24 May 12 12:26:38 PM PDT 24 181368388 ps
T1317 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2043279393 May 12 12:25:57 PM PDT 24 May 12 12:26:01 PM PDT 24 136414341 ps
T1318 /workspace/coverage/cover_reg_top/47.uart_intr_test.3379191581 May 12 12:26:35 PM PDT 24 May 12 12:26:37 PM PDT 24 11519813 ps
T1319 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2289689845 May 12 12:23:01 PM PDT 24 May 12 12:23:02 PM PDT 24 21703119 ps

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2924375333
Short name T6
Test name
Test status
Simulation time 165480717893 ps
CPU time 1587.82 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:54:25 PM PDT 24
Peak memory 217592 kb
Host smart-015fe636-a3d4-42d7-b9e1-2512130a3ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924375333 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2924375333
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2353617206
Short name T39
Test name
Test status
Simulation time 250735515668 ps
CPU time 614.05 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:34:54 PM PDT 24
Peak memory 216776 kb
Host smart-f7a86902-d0eb-4591-9a4a-30acaf67f71a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353617206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2353617206
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1236884670
Short name T14
Test name
Test status
Simulation time 94999281748 ps
CPU time 998.45 seconds
Started May 12 01:26:12 PM PDT 24
Finished May 12 01:42:51 PM PDT 24
Peak memory 216988 kb
Host smart-4183bad6-93d0-4dc3-843f-04a029252f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236884670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1236884670
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.1289371882
Short name T157
Test name
Test status
Simulation time 254200992912 ps
CPU time 1170.68 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 200592 kb
Host smart-3810e812-3774-4c47-a77b-5bb344c4c5f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289371882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1289371882
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.4079083323
Short name T137
Test name
Test status
Simulation time 315123198423 ps
CPU time 1492.1 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:49:36 PM PDT 24
Peak memory 200368 kb
Host smart-e5879827-24d1-48f8-ba60-feb480d2bb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079083323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4079083323
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all.1790977142
Short name T17
Test name
Test status
Simulation time 705326289541 ps
CPU time 1298.35 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:46:23 PM PDT 24
Peak memory 208692 kb
Host smart-efbd1ffe-6586-4b25-920c-551757f3168b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790977142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1790977142
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2659258358
Short name T38
Test name
Test status
Simulation time 108765661527 ps
CPU time 729.31 seconds
Started May 12 01:28:07 PM PDT 24
Finished May 12 01:40:16 PM PDT 24
Peak memory 216872 kb
Host smart-88d68ecc-291f-417e-8eb5-37a8cbf8f58c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659258358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2659258358
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3113025377
Short name T36
Test name
Test status
Simulation time 33338800 ps
CPU time 0.78 seconds
Started May 12 01:24:25 PM PDT 24
Finished May 12 01:24:26 PM PDT 24
Peak memory 218592 kb
Host smart-d3731898-bd10-40de-9507-ae7d9aaeb8b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113025377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3113025377
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2960984013
Short name T41
Test name
Test status
Simulation time 94159116047 ps
CPU time 399.38 seconds
Started May 12 01:28:11 PM PDT 24
Finished May 12 01:34:51 PM PDT 24
Peak memory 217060 kb
Host smart-14a61ff1-c2ca-47c9-928c-1a5ffbecd1ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960984013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2960984013
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.4129631017
Short name T50
Test name
Test status
Simulation time 121134412565 ps
CPU time 56.6 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:29:37 PM PDT 24
Peak memory 200432 kb
Host smart-6db2d477-2bbc-4255-b4d3-29d247d58709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129631017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4129631017
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.413326717
Short name T273
Test name
Test status
Simulation time 724059186144 ps
CPU time 297.25 seconds
Started May 12 01:25:15 PM PDT 24
Finished May 12 01:30:12 PM PDT 24
Peak memory 200432 kb
Host smart-abefff58-6e38-4129-8234-906aed611a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413326717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.413326717
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2917273538
Short name T1
Test name
Test status
Simulation time 12735753842 ps
CPU time 21.12 seconds
Started May 12 01:28:25 PM PDT 24
Finished May 12 01:28:46 PM PDT 24
Peak memory 200288 kb
Host smart-4709e6f1-9e23-4db5-9b52-3cea190ba9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917273538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2917273538
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2601701928
Short name T147
Test name
Test status
Simulation time 20789646434 ps
CPU time 29.96 seconds
Started May 12 01:29:22 PM PDT 24
Finished May 12 01:29:52 PM PDT 24
Peak memory 200340 kb
Host smart-e0630209-017d-408d-a901-7f6156a81136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601701928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2601701928
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1219630968
Short name T110
Test name
Test status
Simulation time 560781508525 ps
CPU time 1166.51 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:47:37 PM PDT 24
Peak memory 227432 kb
Host smart-544ea49e-b59c-4241-8b1f-2734782e799a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219630968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1219630968
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1147653546
Short name T158
Test name
Test status
Simulation time 157810389222 ps
CPU time 158.94 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:27:16 PM PDT 24
Peak memory 200356 kb
Host smart-133966f2-909f-4775-a553-a1e559b45390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147653546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1147653546
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3214899196
Short name T40
Test name
Test status
Simulation time 62203368567 ps
CPU time 362.87 seconds
Started May 12 01:28:15 PM PDT 24
Finished May 12 01:34:18 PM PDT 24
Peak memory 217020 kb
Host smart-5da6f20b-bbef-417b-9a29-8c1941775595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214899196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3214899196
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2704117146
Short name T95
Test name
Test status
Simulation time 343208607 ps
CPU time 1.35 seconds
Started May 12 12:25:49 PM PDT 24
Finished May 12 12:25:51 PM PDT 24
Peak memory 199372 kb
Host smart-2554e059-0ecb-4741-a5dc-eaa8ce2ae7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704117146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2704117146
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2136330319
Short name T150
Test name
Test status
Simulation time 108808001651 ps
CPU time 39.92 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:25:30 PM PDT 24
Peak memory 200276 kb
Host smart-130f295f-10ce-4001-a8cd-5c3c6d8fffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136330319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2136330319
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_alert_test.2334115449
Short name T352
Test name
Test status
Simulation time 22025989 ps
CPU time 0.56 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:22 PM PDT 24
Peak memory 195756 kb
Host smart-4caafede-1c10-4c39-a043-10fbd179e172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334115449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2334115449
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2842560186
Short name T135
Test name
Test status
Simulation time 21781294945 ps
CPU time 39.81 seconds
Started May 12 01:28:59 PM PDT 24
Finished May 12 01:29:40 PM PDT 24
Peak memory 200408 kb
Host smart-746eea46-b636-4d6a-91e8-c66edd20c91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842560186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2842560186
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1775274660
Short name T282
Test name
Test status
Simulation time 148866216632 ps
CPU time 600.56 seconds
Started May 12 01:25:26 PM PDT 24
Finished May 12 01:35:27 PM PDT 24
Peak memory 200396 kb
Host smart-2593756c-62b2-4e5b-9a34-2cc2dd50ab9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775274660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1775274660
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3729278243
Short name T42
Test name
Test status
Simulation time 506463271760 ps
CPU time 433.87 seconds
Started May 12 01:27:21 PM PDT 24
Finished May 12 01:34:36 PM PDT 24
Peak memory 216976 kb
Host smart-0eb4141e-9dac-44e8-9278-f8482c3bf84e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729278243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3729278243
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3790820473
Short name T279
Test name
Test status
Simulation time 79393267555 ps
CPU time 42.41 seconds
Started May 12 01:26:39 PM PDT 24
Finished May 12 01:27:22 PM PDT 24
Peak memory 200324 kb
Host smart-e3b33bf2-29d1-4441-9899-61d355410c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790820473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3790820473
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_stress_all.3322380430
Short name T145
Test name
Test status
Simulation time 256698463194 ps
CPU time 777.75 seconds
Started May 12 01:25:27 PM PDT 24
Finished May 12 01:38:25 PM PDT 24
Peak memory 200588 kb
Host smart-9d680037-823c-4610-8498-29bd2735fb79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322380430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3322380430
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.573496494
Short name T85
Test name
Test status
Simulation time 54249368 ps
CPU time 0.76 seconds
Started May 12 12:22:33 PM PDT 24
Finished May 12 12:22:34 PM PDT 24
Peak memory 197484 kb
Host smart-a881f028-db1c-4633-9d84-34a2468a1d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573496494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.573496494
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.185580144
Short name T78
Test name
Test status
Simulation time 36683070 ps
CPU time 0.54 seconds
Started May 12 12:21:34 PM PDT 24
Finished May 12 12:21:35 PM PDT 24
Peak memory 195536 kb
Host smart-b41313df-e97d-4085-bda6-cd52978a5a50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185580144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.185580144
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2456872169
Short name T170
Test name
Test status
Simulation time 487657354317 ps
CPU time 1734.45 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:56:52 PM PDT 24
Peak memory 228204 kb
Host smart-75ca16cd-cfc5-4bad-a204-0ee56fd5907c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456872169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2456872169
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3450125905
Short name T438
Test name
Test status
Simulation time 46836321302 ps
CPU time 39.54 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:25:23 PM PDT 24
Peak memory 200412 kb
Host smart-385b8814-1947-4d68-a751-ddd053863e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450125905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3450125905
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.823121879
Short name T44
Test name
Test status
Simulation time 115064704624 ps
CPU time 46.53 seconds
Started May 12 01:28:46 PM PDT 24
Finished May 12 01:29:33 PM PDT 24
Peak memory 200352 kb
Host smart-c90a3c0a-adfb-4a37-9b6a-4cecfb7bd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823121879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.823121879
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.362622686
Short name T308
Test name
Test status
Simulation time 86502606749 ps
CPU time 165.89 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:31:26 PM PDT 24
Peak memory 200440 kb
Host smart-b83cc7f0-146c-410c-8cc5-cfdcdb49d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362622686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.362622686
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2589902806
Short name T127
Test name
Test status
Simulation time 155530191682 ps
CPU time 66.01 seconds
Started May 12 01:29:18 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 200268 kb
Host smart-92b1b166-b128-4628-b685-8e9086324827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589902806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2589902806
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1970586240
Short name T173
Test name
Test status
Simulation time 18746279545 ps
CPU time 24.57 seconds
Started May 12 01:28:38 PM PDT 24
Finished May 12 01:29:03 PM PDT 24
Peak memory 200144 kb
Host smart-462a27ed-9396-4d93-9ebb-58eca5bee41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970586240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1970586240
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3600262125
Short name T200
Test name
Test status
Simulation time 143705515449 ps
CPU time 194.9 seconds
Started May 12 01:28:57 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 200352 kb
Host smart-f39d3654-e43d-4c1f-b753-411cd24e626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600262125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3600262125
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2806168116
Short name T194
Test name
Test status
Simulation time 117361706910 ps
CPU time 286.98 seconds
Started May 12 01:25:44 PM PDT 24
Finished May 12 01:30:31 PM PDT 24
Peak memory 217084 kb
Host smart-632d49f4-c59a-48a3-9b37-32a6abac239f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806168116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2806168116
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3265397629
Short name T608
Test name
Test status
Simulation time 60498234122 ps
CPU time 651.87 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:38:49 PM PDT 24
Peak memory 216360 kb
Host smart-c3f8de54-0c92-4ce0-bc1f-53b722c2f199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265397629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3265397629
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3672916929
Short name T93
Test name
Test status
Simulation time 46237025 ps
CPU time 0.92 seconds
Started May 12 12:27:07 PM PDT 24
Finished May 12 12:27:09 PM PDT 24
Peak memory 198940 kb
Host smart-f19f744c-5fb9-4c9f-93ef-6c4650695ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672916929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3672916929
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2590544887
Short name T122
Test name
Test status
Simulation time 41941400871 ps
CPU time 19.79 seconds
Started May 12 01:28:22 PM PDT 24
Finished May 12 01:28:42 PM PDT 24
Peak memory 200320 kb
Host smart-fb833ad3-df72-4cbf-bbfc-a44951177953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590544887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2590544887
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2441520854
Short name T272
Test name
Test status
Simulation time 170281853563 ps
CPU time 264.31 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:29:17 PM PDT 24
Peak memory 200340 kb
Host smart-343018d2-3ffa-40f6-acb0-f1db6255ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441520854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2441520854
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.411202190
Short name T302
Test name
Test status
Simulation time 59862988868 ps
CPU time 358.71 seconds
Started May 12 01:25:23 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 215696 kb
Host smart-42f14321-f2fc-4757-8673-b3fb6953a3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411202190 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.411202190
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3077092507
Short name T136
Test name
Test status
Simulation time 58174936648 ps
CPU time 26.88 seconds
Started May 12 01:25:25 PM PDT 24
Finished May 12 01:25:52 PM PDT 24
Peak memory 200408 kb
Host smart-83655d33-3253-4cc8-a733-9b5960d72aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077092507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3077092507
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2251479477
Short name T43
Test name
Test status
Simulation time 10929041700 ps
CPU time 19.51 seconds
Started May 12 01:27:24 PM PDT 24
Finished May 12 01:27:44 PM PDT 24
Peak memory 200324 kb
Host smart-dd675044-a5e8-413f-a654-0419f7b94cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251479477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2251479477
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3295753700
Short name T191
Test name
Test status
Simulation time 28243418908 ps
CPU time 68.83 seconds
Started May 12 01:25:59 PM PDT 24
Finished May 12 01:27:09 PM PDT 24
Peak memory 200380 kb
Host smart-7d21d75f-4a98-4a37-b78f-ebaa9b9f34e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295753700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3295753700
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_noise_filter.910543320
Short name T108
Test name
Test status
Simulation time 25438692016 ps
CPU time 21.12 seconds
Started May 12 01:27:11 PM PDT 24
Finished May 12 01:27:32 PM PDT 24
Peak memory 198812 kb
Host smart-cf9a5eee-75f9-4ee9-9b63-2fc871a66495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910543320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.910543320
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.99320150
Short name T333
Test name
Test status
Simulation time 30926565734 ps
CPU time 56.2 seconds
Started May 12 01:28:39 PM PDT 24
Finished May 12 01:29:35 PM PDT 24
Peak memory 200384 kb
Host smart-cf95b401-3f90-4f58-a40d-9089b8e9b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99320150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.99320150
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3280977001
Short name T233
Test name
Test status
Simulation time 83838327287 ps
CPU time 16.33 seconds
Started May 12 01:28:51 PM PDT 24
Finished May 12 01:29:07 PM PDT 24
Peak memory 200296 kb
Host smart-a2be2d04-ca6d-4637-9143-759c357d3615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280977001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3280977001
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1343727309
Short name T286
Test name
Test status
Simulation time 67042732194 ps
CPU time 105.91 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 200376 kb
Host smart-dd672d5f-63e9-4050-8703-03a8fbe53f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343727309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1343727309
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.611957617
Short name T1027
Test name
Test status
Simulation time 25949037641 ps
CPU time 36.04 seconds
Started May 12 01:29:14 PM PDT 24
Finished May 12 01:29:50 PM PDT 24
Peak memory 200412 kb
Host smart-8912da0a-1f68-4540-890c-55a8a6fdddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611957617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.611957617
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_tx_rx.268515557
Short name T281
Test name
Test status
Simulation time 55975484227 ps
CPU time 76.43 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:25:54 PM PDT 24
Peak memory 200372 kb
Host smart-5d147f78-df46-48ac-a23c-9f4682b546b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268515557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.268515557
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4066188528
Short name T212
Test name
Test status
Simulation time 33250196619 ps
CPU time 56.08 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:28:53 PM PDT 24
Peak memory 200360 kb
Host smart-7cb6167c-e0a6-4885-ba15-fe715178c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066188528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4066188528
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2007882642
Short name T231
Test name
Test status
Simulation time 157892590751 ps
CPU time 71.08 seconds
Started May 12 01:27:58 PM PDT 24
Finished May 12 01:29:09 PM PDT 24
Peak memory 200388 kb
Host smart-48b20317-8f0d-4923-9db9-f60216bc3ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007882642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2007882642
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4165678546
Short name T494
Test name
Test status
Simulation time 22005760605 ps
CPU time 22.53 seconds
Started May 12 01:24:47 PM PDT 24
Finished May 12 01:25:11 PM PDT 24
Peak memory 200360 kb
Host smart-da0f27fe-d196-4925-9e5a-26947b17f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165678546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4165678546
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1099374978
Short name T262
Test name
Test status
Simulation time 10953621110 ps
CPU time 17.68 seconds
Started May 12 01:28:43 PM PDT 24
Finished May 12 01:29:00 PM PDT 24
Peak memory 200312 kb
Host smart-49fc8cb6-bfa6-4aaf-93bd-e8e7a964557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099374978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1099374978
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1305328433
Short name T161
Test name
Test status
Simulation time 307986884213 ps
CPU time 51.77 seconds
Started May 12 01:28:48 PM PDT 24
Finished May 12 01:29:40 PM PDT 24
Peak memory 200356 kb
Host smart-0ba63410-245a-4eb4-980b-60666fa9994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305328433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1305328433
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.596734534
Short name T632
Test name
Test status
Simulation time 134536820948 ps
CPU time 233.69 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:29:03 PM PDT 24
Peak memory 200320 kb
Host smart-03b212c0-98c0-431c-bb23-a19c10543491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596734534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.596734534
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.175234286
Short name T1164
Test name
Test status
Simulation time 108424092733 ps
CPU time 182.28 seconds
Started May 12 01:29:00 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 200332 kb
Host smart-c259499a-209b-4845-aa87-5213ca8dbf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175234286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.175234286
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3332305144
Short name T238
Test name
Test status
Simulation time 118755722495 ps
CPU time 73.84 seconds
Started May 12 01:29:12 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 200336 kb
Host smart-86ac5ae4-a8db-4386-9307-6e56521055bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332305144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3332305144
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.208179599
Short name T111
Test name
Test status
Simulation time 80331582031 ps
CPU time 875.14 seconds
Started May 12 01:25:41 PM PDT 24
Finished May 12 01:40:16 PM PDT 24
Peak memory 216832 kb
Host smart-9f5fda2b-35df-459d-bba0-45c17bde9986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208179599 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.208179599
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2857369946
Short name T185
Test name
Test status
Simulation time 378549770851 ps
CPU time 1523.47 seconds
Started May 12 01:26:55 PM PDT 24
Finished May 12 01:52:19 PM PDT 24
Peak memory 227144 kb
Host smart-1fa16527-ab84-4252-b9ed-61224ca0c6e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857369946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2857369946
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3202862004
Short name T181
Test name
Test status
Simulation time 46410181351 ps
CPU time 43.89 seconds
Started May 12 01:27:17 PM PDT 24
Finished May 12 01:28:01 PM PDT 24
Peak memory 200352 kb
Host smart-6dba965c-e886-45fa-9d78-318fb70a3b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202862004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3202862004
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.13991305
Short name T226
Test name
Test status
Simulation time 120002687601 ps
CPU time 353.09 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:34:04 PM PDT 24
Peak memory 200336 kb
Host smart-b2208222-51cc-4210-9385-4340bfe6fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13991305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.13991305
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2844781639
Short name T98
Test name
Test status
Simulation time 363741722 ps
CPU time 1.39 seconds
Started May 12 12:21:02 PM PDT 24
Finished May 12 12:21:05 PM PDT 24
Peak memory 199316 kb
Host smart-239f7797-e37d-4ebc-9cb5-571c60bec3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844781639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2844781639
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.759355705
Short name T142
Test name
Test status
Simulation time 137027084 ps
CPU time 0.97 seconds
Started May 12 12:24:13 PM PDT 24
Finished May 12 12:24:15 PM PDT 24
Peak memory 199108 kb
Host smart-7c610ca9-166f-44c2-ac8c-1b6a9b395e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759355705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.759355705
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1469727151
Short name T332
Test name
Test status
Simulation time 117216772472 ps
CPU time 25.66 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:45 PM PDT 24
Peak memory 200352 kb
Host smart-84574bcd-4ef7-4bb5-bf66-af8b703b3a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469727151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1469727151
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.22763186
Short name T250
Test name
Test status
Simulation time 23888422697 ps
CPU time 40.76 seconds
Started May 12 01:28:21 PM PDT 24
Finished May 12 01:29:02 PM PDT 24
Peak memory 200436 kb
Host smart-b9486100-5609-4f21-a487-ce46b4d36420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22763186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.22763186
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2756413246
Short name T271
Test name
Test status
Simulation time 64278028326 ps
CPU time 116.87 seconds
Started May 12 01:24:46 PM PDT 24
Finished May 12 01:26:44 PM PDT 24
Peak memory 200272 kb
Host smart-7c683a63-fd67-46a6-b3d0-ebdbc48a159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756413246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2756413246
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1796786719
Short name T252
Test name
Test status
Simulation time 82029622450 ps
CPU time 19.35 seconds
Started May 12 01:28:29 PM PDT 24
Finished May 12 01:28:49 PM PDT 24
Peak memory 200540 kb
Host smart-e201c7e5-8835-496f-82b5-211c832e9b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796786719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1796786719
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3579256459
Short name T260
Test name
Test status
Simulation time 92834068765 ps
CPU time 79.22 seconds
Started May 12 01:28:32 PM PDT 24
Finished May 12 01:29:51 PM PDT 24
Peak memory 200424 kb
Host smart-5a0c8286-acd4-4787-bcfb-7d483f7db920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579256459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3579256459
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4282465252
Short name T549
Test name
Test status
Simulation time 6279743236 ps
CPU time 3.07 seconds
Started May 12 01:24:50 PM PDT 24
Finished May 12 01:24:54 PM PDT 24
Peak memory 196344 kb
Host smart-fe5fc0ad-214c-4bcf-8b2f-487c00831ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282465252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4282465252
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2845743097
Short name T217
Test name
Test status
Simulation time 60137333918 ps
CPU time 25.1 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:29:06 PM PDT 24
Peak memory 200420 kb
Host smart-4a505cd2-a728-440b-881e-8a6d1e2f2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845743097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2845743097
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.354223416
Short name T222
Test name
Test status
Simulation time 37919488123 ps
CPU time 58.66 seconds
Started May 12 01:28:49 PM PDT 24
Finished May 12 01:29:48 PM PDT 24
Peak memory 200444 kb
Host smart-fdc998c8-a307-4ebb-a811-c9a4b12fe6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354223416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.354223416
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2444175929
Short name T107
Test name
Test status
Simulation time 58350408241 ps
CPU time 103.74 seconds
Started May 12 01:28:48 PM PDT 24
Finished May 12 01:30:32 PM PDT 24
Peak memory 200352 kb
Host smart-bc2eacf0-ebfe-4997-aeb2-d87f47c8cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444175929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2444175929
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2704138502
Short name T258
Test name
Test status
Simulation time 106883998555 ps
CPU time 19.06 seconds
Started May 12 01:28:49 PM PDT 24
Finished May 12 01:29:08 PM PDT 24
Peak memory 200428 kb
Host smart-0c09df95-1e2d-430c-9059-5e1f068f542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704138502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2704138502
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2055921278
Short name T209
Test name
Test status
Simulation time 99086997283 ps
CPU time 26.81 seconds
Started May 12 01:28:45 PM PDT 24
Finished May 12 01:29:12 PM PDT 24
Peak memory 200336 kb
Host smart-ef9eb600-5b32-4697-94ec-5f7184db6dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055921278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2055921278
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3956030921
Short name T230
Test name
Test status
Simulation time 26992197179 ps
CPU time 40.6 seconds
Started May 12 01:28:55 PM PDT 24
Finished May 12 01:29:36 PM PDT 24
Peak memory 200300 kb
Host smart-2a154bab-a10e-44f8-9fbb-f7007a72f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956030921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3956030921
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2810074353
Short name T266
Test name
Test status
Simulation time 110447699551 ps
CPU time 86.05 seconds
Started May 12 01:28:54 PM PDT 24
Finished May 12 01:30:20 PM PDT 24
Peak memory 200416 kb
Host smart-0b89bc2f-e464-42f1-80ef-d7c0f367a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810074353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2810074353
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.62460568
Short name T268
Test name
Test status
Simulation time 31202063246 ps
CPU time 22.63 seconds
Started May 12 01:28:59 PM PDT 24
Finished May 12 01:29:23 PM PDT 24
Peak memory 200412 kb
Host smart-bb7ab4bc-5f3e-45a7-a407-363499d0c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62460568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.62460568
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1303010286
Short name T148
Test name
Test status
Simulation time 40908481399 ps
CPU time 73.32 seconds
Started May 12 01:29:03 PM PDT 24
Finished May 12 01:30:16 PM PDT 24
Peak memory 200364 kb
Host smart-ccbfeeaf-921d-4195-9169-9caf51dd0fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303010286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1303010286
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3878664247
Short name T184
Test name
Test status
Simulation time 43141717516 ps
CPU time 104.25 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:30:47 PM PDT 24
Peak memory 200348 kb
Host smart-5bc9988e-44b5-4e24-8b88-7f2811cf7600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878664247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3878664247
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3197942533
Short name T259
Test name
Test status
Simulation time 35144675128 ps
CPU time 56.69 seconds
Started May 12 01:29:21 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 200112 kb
Host smart-311704c9-de7a-463d-889d-e9c289df76f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197942533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3197942533
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2719697936
Short name T265
Test name
Test status
Simulation time 28122536138 ps
CPU time 22.73 seconds
Started May 12 01:29:37 PM PDT 24
Finished May 12 01:30:01 PM PDT 24
Peak memory 200268 kb
Host smart-63cdfbd8-b234-4f5c-af9f-b8002104cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719697936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2719697936
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2690641053
Short name T234
Test name
Test status
Simulation time 31569750152 ps
CPU time 14.01 seconds
Started May 12 01:27:47 PM PDT 24
Finished May 12 01:28:01 PM PDT 24
Peak memory 200340 kb
Host smart-38c51cc0-de9c-4421-8437-d581f5d6137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690641053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2690641053
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1340675214
Short name T189
Test name
Test status
Simulation time 263633137662 ps
CPU time 43.35 seconds
Started May 12 01:27:53 PM PDT 24
Finished May 12 01:28:37 PM PDT 24
Peak memory 200320 kb
Host smart-4830d716-28fb-481f-bd18-971bde2b3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340675214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1340675214
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2471341739
Short name T174
Test name
Test status
Simulation time 45866800753 ps
CPU time 22.37 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:28:33 PM PDT 24
Peak memory 200376 kb
Host smart-b5fe3670-cc92-46a3-aa34-3d13080b0e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471341739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2471341739
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2953172843
Short name T1282
Test name
Test status
Simulation time 16075210 ps
CPU time 0.79 seconds
Started May 12 12:22:09 PM PDT 24
Finished May 12 12:22:10 PM PDT 24
Peak memory 195568 kb
Host smart-7b0256c4-dff8-414b-9be0-5c3e2fb64aca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953172843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2953172843
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3940725844
Short name T1242
Test name
Test status
Simulation time 59574877 ps
CPU time 2.31 seconds
Started May 12 12:23:48 PM PDT 24
Finished May 12 12:23:50 PM PDT 24
Peak memory 198144 kb
Host smart-32fed0af-e8c4-46a0-9d32-ca790fc0f274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940725844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3940725844
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4218826236
Short name T1231
Test name
Test status
Simulation time 14869687 ps
CPU time 0.6 seconds
Started May 12 12:23:10 PM PDT 24
Finished May 12 12:23:12 PM PDT 24
Peak memory 195404 kb
Host smart-b5108626-1c7f-4ac3-a60a-ca9c214fa4fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218826236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4218826236
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4084069273
Short name T1188
Test name
Test status
Simulation time 15858030 ps
CPU time 0.71 seconds
Started May 12 12:22:10 PM PDT 24
Finished May 12 12:22:11 PM PDT 24
Peak memory 197020 kb
Host smart-6e76642b-9899-43da-8cfe-dde8bcbfc1f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084069273 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.4084069273
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2496701462
Short name T1264
Test name
Test status
Simulation time 46106531 ps
CPU time 0.61 seconds
Started May 12 12:22:09 PM PDT 24
Finished May 12 12:22:10 PM PDT 24
Peak memory 194656 kb
Host smart-6d58276d-4727-41dd-880d-13f734c9f6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496701462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2496701462
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1385943444
Short name T1253
Test name
Test status
Simulation time 17585162 ps
CPU time 0.54 seconds
Started May 12 12:30:20 PM PDT 24
Finished May 12 12:30:21 PM PDT 24
Peak memory 194444 kb
Host smart-c1823e05-e83e-4316-b432-baa6dceddf60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385943444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1385943444
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1803478931
Short name T1263
Test name
Test status
Simulation time 42727874 ps
CPU time 2.09 seconds
Started May 12 12:23:42 PM PDT 24
Finished May 12 12:23:45 PM PDT 24
Peak memory 200508 kb
Host smart-15701018-0a22-4ef3-af3e-1212b19da9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803478931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1803478931
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.205969602
Short name T1229
Test name
Test status
Simulation time 31335900 ps
CPU time 0.83 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:26:56 PM PDT 24
Peak memory 195532 kb
Host smart-534302d8-d39f-4bd4-ae6b-541a0c66f721
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205969602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.205969602
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2292748673
Short name T1250
Test name
Test status
Simulation time 111063167 ps
CPU time 2.25 seconds
Started May 12 12:21:41 PM PDT 24
Finished May 12 12:21:44 PM PDT 24
Peak memory 197940 kb
Host smart-edef141b-299d-4947-96ca-02f3c9a4cbf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292748673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2292748673
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3168469978
Short name T1200
Test name
Test status
Simulation time 17429847 ps
CPU time 0.75 seconds
Started May 12 12:26:11 PM PDT 24
Finished May 12 12:26:12 PM PDT 24
Peak memory 197864 kb
Host smart-10798116-3e0e-4d0c-8b76-6f78d198efad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168469978 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3168469978
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3742625696
Short name T1294
Test name
Test status
Simulation time 83437477 ps
CPU time 0.61 seconds
Started May 12 12:30:04 PM PDT 24
Finished May 12 12:30:06 PM PDT 24
Peak memory 194640 kb
Host smart-80160cce-218c-4572-84f9-28746813789b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742625696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3742625696
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2808376873
Short name T1237
Test name
Test status
Simulation time 14285861 ps
CPU time 0.57 seconds
Started May 12 12:30:20 PM PDT 24
Finished May 12 12:30:22 PM PDT 24
Peak memory 193860 kb
Host smart-3739b98c-2017-44b7-ab17-a397b3e85ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808376873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2808376873
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4237483683
Short name T1227
Test name
Test status
Simulation time 30154897 ps
CPU time 0.76 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:27:20 PM PDT 24
Peak memory 196996 kb
Host smart-c80a40d2-a693-40af-b2af-f5197d87015f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237483683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.4237483683
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1259402819
Short name T1259
Test name
Test status
Simulation time 64412112 ps
CPU time 1.61 seconds
Started May 12 12:30:20 PM PDT 24
Finished May 12 12:30:23 PM PDT 24
Peak memory 199572 kb
Host smart-9af2c84c-6948-45d8-befc-069424e5173a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259402819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1259402819
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3626452215
Short name T92
Test name
Test status
Simulation time 143339150 ps
CPU time 0.96 seconds
Started May 12 12:21:01 PM PDT 24
Finished May 12 12:21:04 PM PDT 24
Peak memory 197300 kb
Host smart-ad852b90-74c9-45df-884e-e28078e70a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626452215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3626452215
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2888959658
Short name T1305
Test name
Test status
Simulation time 14360273 ps
CPU time 0.69 seconds
Started May 12 12:26:13 PM PDT 24
Finished May 12 12:26:14 PM PDT 24
Peak memory 198024 kb
Host smart-fa050958-d85e-44fd-b181-d182019a5e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888959658 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2888959658
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.330105579
Short name T88
Test name
Test status
Simulation time 44503450 ps
CPU time 0.59 seconds
Started May 12 12:27:27 PM PDT 24
Finished May 12 12:27:29 PM PDT 24
Peak memory 195604 kb
Host smart-1ac2f4c4-7ee3-4b5b-93d8-3a9d9ad2528f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330105579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.330105579
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3904427552
Short name T1277
Test name
Test status
Simulation time 40993774 ps
CPU time 0.63 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:27:14 PM PDT 24
Peak memory 193788 kb
Host smart-1c98bacb-5195-4993-a000-da0fce8e27ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904427552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3904427552
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2973811904
Short name T1308
Test name
Test status
Simulation time 21665080 ps
CPU time 0.62 seconds
Started May 12 12:26:13 PM PDT 24
Finished May 12 12:26:14 PM PDT 24
Peak memory 194336 kb
Host smart-4da1409d-050d-4173-9fad-174496de1c44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973811904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2973811904
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4133181418
Short name T1285
Test name
Test status
Simulation time 143909718 ps
CPU time 1.38 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:27:15 PM PDT 24
Peak memory 199796 kb
Host smart-1f80b619-426b-4595-acc5-3a4b605f87a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133181418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4133181418
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3864324457
Short name T1315
Test name
Test status
Simulation time 24222562 ps
CPU time 0.98 seconds
Started May 12 12:32:51 PM PDT 24
Finished May 12 12:32:52 PM PDT 24
Peak memory 199528 kb
Host smart-680d1215-ad16-49b1-a99a-ed4baf821abb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864324457 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3864324457
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.605680955
Short name T86
Test name
Test status
Simulation time 17659395 ps
CPU time 0.61 seconds
Started May 12 12:24:37 PM PDT 24
Finished May 12 12:24:38 PM PDT 24
Peak memory 195464 kb
Host smart-8219638d-6b71-4043-90b0-3d2386219183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605680955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.605680955
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2379810619
Short name T1249
Test name
Test status
Simulation time 43142191 ps
CPU time 0.59 seconds
Started May 12 12:26:13 PM PDT 24
Finished May 12 12:26:14 PM PDT 24
Peak memory 194048 kb
Host smart-e028c998-031b-49ec-bed0-60fd709af2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379810619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2379810619
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2029084169
Short name T1266
Test name
Test status
Simulation time 53263078 ps
CPU time 0.7 seconds
Started May 12 12:23:34 PM PDT 24
Finished May 12 12:23:36 PM PDT 24
Peak memory 197416 kb
Host smart-489d10da-6b2c-408b-a6a6-c535e100b1e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029084169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2029084169
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1210798362
Short name T1212
Test name
Test status
Simulation time 400518171 ps
CPU time 1.8 seconds
Started May 12 12:23:22 PM PDT 24
Finished May 12 12:23:24 PM PDT 24
Peak memory 200152 kb
Host smart-c0feb1af-373a-4c58-a180-adbfd34a1f58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210798362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1210798362
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2084012531
Short name T94
Test name
Test status
Simulation time 172114579 ps
CPU time 1.29 seconds
Started May 12 12:26:12 PM PDT 24
Finished May 12 12:26:14 PM PDT 24
Peak memory 198132 kb
Host smart-cd72bb63-4387-48e2-9d87-7af270a1849a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084012531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2084012531
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1807698536
Short name T1243
Test name
Test status
Simulation time 85515148 ps
CPU time 0.79 seconds
Started May 12 12:26:14 PM PDT 24
Finished May 12 12:26:16 PM PDT 24
Peak memory 197796 kb
Host smart-21e2116e-31dd-4561-ae08-c6f62622a740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807698536 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1807698536
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.227927318
Short name T1230
Test name
Test status
Simulation time 22179304 ps
CPU time 0.59 seconds
Started May 12 12:26:14 PM PDT 24
Finished May 12 12:26:15 PM PDT 24
Peak memory 195420 kb
Host smart-f04b9313-3ab4-4cdf-a2cd-c110405f9425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227927318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.227927318
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3756537396
Short name T1194
Test name
Test status
Simulation time 43558025 ps
CPU time 0.6 seconds
Started May 12 12:32:50 PM PDT 24
Finished May 12 12:32:52 PM PDT 24
Peak memory 193512 kb
Host smart-8c3221f6-95c4-402a-8bb8-df7a04c99114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756537396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3756537396
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2090709195
Short name T80
Test name
Test status
Simulation time 180548806 ps
CPU time 0.79 seconds
Started May 12 12:32:50 PM PDT 24
Finished May 12 12:32:52 PM PDT 24
Peak memory 196296 kb
Host smart-15e52c74-a193-4449-bbc2-724828fca3de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090709195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2090709195
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.573324698
Short name T1260
Test name
Test status
Simulation time 471707372 ps
CPU time 2.25 seconds
Started May 12 12:25:59 PM PDT 24
Finished May 12 12:26:03 PM PDT 24
Peak memory 199372 kb
Host smart-b79ea0a6-f08b-4910-b568-e270ba73bb90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573324698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.573324698
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.448045652
Short name T1228
Test name
Test status
Simulation time 54072594 ps
CPU time 0.83 seconds
Started May 12 12:26:53 PM PDT 24
Finished May 12 12:26:56 PM PDT 24
Peak memory 199148 kb
Host smart-7f7e7e38-4491-4f4f-b5c6-72b4028690d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448045652 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.448045652
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.388422144
Short name T77
Test name
Test status
Simulation time 15882850 ps
CPU time 0.59 seconds
Started May 12 12:25:59 PM PDT 24
Finished May 12 12:26:01 PM PDT 24
Peak memory 194432 kb
Host smart-a2ee576a-d3e6-4779-a40c-9dafab585833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388422144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.388422144
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1751235163
Short name T1225
Test name
Test status
Simulation time 36888830 ps
CPU time 0.61 seconds
Started May 12 12:25:01 PM PDT 24
Finished May 12 12:25:02 PM PDT 24
Peak memory 194904 kb
Host smart-cecdc330-cb69-4784-9f21-b0b086025d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751235163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1751235163
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1784198573
Short name T1220
Test name
Test status
Simulation time 110529067 ps
CPU time 0.75 seconds
Started May 12 12:26:15 PM PDT 24
Finished May 12 12:26:16 PM PDT 24
Peak memory 197080 kb
Host smart-5cc0be56-dda0-4820-8464-ba8c882223bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784198573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1784198573
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1239624312
Short name T1204
Test name
Test status
Simulation time 94455534 ps
CPU time 1.38 seconds
Started May 12 12:25:01 PM PDT 24
Finished May 12 12:25:03 PM PDT 24
Peak memory 200084 kb
Host smart-75df8195-e6bf-4918-a512-5358494eac52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239624312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1239624312
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3804765079
Short name T1279
Test name
Test status
Simulation time 88240973 ps
CPU time 0.86 seconds
Started May 12 12:25:11 PM PDT 24
Finished May 12 12:25:12 PM PDT 24
Peak memory 199932 kb
Host smart-65ef12af-3139-416a-8afe-2d02621c9b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804765079 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3804765079
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1381379210
Short name T76
Test name
Test status
Simulation time 14487998 ps
CPU time 0.62 seconds
Started May 12 12:26:37 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 195532 kb
Host smart-91fd8dc8-1b2a-45f5-bea0-18b7b7b3498f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381379210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1381379210
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2375313827
Short name T1206
Test name
Test status
Simulation time 157703568 ps
CPU time 0.56 seconds
Started May 12 12:23:18 PM PDT 24
Finished May 12 12:23:19 PM PDT 24
Peak memory 194428 kb
Host smart-814a982e-8a41-4b21-9a89-51802d7db356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375313827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2375313827
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1263404810
Short name T1219
Test name
Test status
Simulation time 78854872 ps
CPU time 0.71 seconds
Started May 12 12:26:36 PM PDT 24
Finished May 12 12:26:38 PM PDT 24
Peak memory 194932 kb
Host smart-3b090951-058f-496f-ba53-1aee126c7c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263404810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1263404810
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1000196326
Short name T1224
Test name
Test status
Simulation time 138610674 ps
CPU time 1.45 seconds
Started May 12 12:26:51 PM PDT 24
Finished May 12 12:26:54 PM PDT 24
Peak memory 198904 kb
Host smart-99d5c820-9973-4f26-baa1-fda759a89f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000196326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1000196326
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3132017577
Short name T1234
Test name
Test status
Simulation time 51619781 ps
CPU time 0.93 seconds
Started May 12 12:27:05 PM PDT 24
Finished May 12 12:27:07 PM PDT 24
Peak memory 199004 kb
Host smart-372b439f-bb03-4a0a-98fd-2c3af9858818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132017577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3132017577
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3489874746
Short name T1247
Test name
Test status
Simulation time 30165062 ps
CPU time 0.8 seconds
Started May 12 12:23:33 PM PDT 24
Finished May 12 12:23:34 PM PDT 24
Peak memory 199920 kb
Host smart-af73bea7-3c6a-4d3e-96b3-c2795be1d44f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489874746 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3489874746
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.633091161
Short name T1313
Test name
Test status
Simulation time 15999402 ps
CPU time 0.6 seconds
Started May 12 12:27:03 PM PDT 24
Finished May 12 12:27:04 PM PDT 24
Peak memory 195452 kb
Host smart-9e1cd45e-2a46-417e-9efd-79001fa9a210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633091161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.633091161
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3371741610
Short name T1222
Test name
Test status
Simulation time 13649570 ps
CPU time 0.56 seconds
Started May 12 12:26:55 PM PDT 24
Finished May 12 12:26:57 PM PDT 24
Peak memory 194224 kb
Host smart-3edd2fdf-acc1-40f1-bced-cbcee5096391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371741610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3371741610
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2473129847
Short name T1261
Test name
Test status
Simulation time 152149095 ps
CPU time 0.71 seconds
Started May 12 12:22:47 PM PDT 24
Finished May 12 12:22:48 PM PDT 24
Peak memory 197480 kb
Host smart-efba3ba1-107d-4c0a-9bdb-0f6601bc4ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473129847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2473129847
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.206391609
Short name T1199
Test name
Test status
Simulation time 36149984 ps
CPU time 1.08 seconds
Started May 12 12:24:16 PM PDT 24
Finished May 12 12:24:17 PM PDT 24
Peak memory 199996 kb
Host smart-22caeff8-5a2c-45ae-8b7b-cee5fddc10e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206391609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.206391609
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1693264882
Short name T144
Test name
Test status
Simulation time 40370586 ps
CPU time 0.93 seconds
Started May 12 12:24:06 PM PDT 24
Finished May 12 12:24:08 PM PDT 24
Peak memory 199148 kb
Host smart-aabf0240-7544-40bc-b690-c2eea1c2ea6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693264882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1693264882
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4046383768
Short name T1190
Test name
Test status
Simulation time 48378934 ps
CPU time 1.33 seconds
Started May 12 12:23:28 PM PDT 24
Finished May 12 12:23:29 PM PDT 24
Peak memory 200180 kb
Host smart-42cb6cd5-7447-4cd3-a807-9150e51d010d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046383768 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4046383768
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2854113797
Short name T1281
Test name
Test status
Simulation time 12935952 ps
CPU time 0.63 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:26:07 PM PDT 24
Peak memory 194244 kb
Host smart-5591f16c-e53f-4edf-b4b0-f5ede55f937e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854113797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2854113797
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1512941269
Short name T1269
Test name
Test status
Simulation time 36450761 ps
CPU time 0.6 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:26:50 PM PDT 24
Peak memory 193680 kb
Host smart-4c71eddf-b5c0-45a6-b705-afe9abc682f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512941269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1512941269
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.600054409
Short name T84
Test name
Test status
Simulation time 284821087 ps
CPU time 0.78 seconds
Started May 12 12:26:05 PM PDT 24
Finished May 12 12:26:07 PM PDT 24
Peak memory 195792 kb
Host smart-9876269a-2eee-4971-be39-94f99964c032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600054409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.600054409
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.188087538
Short name T1278
Test name
Test status
Simulation time 296756478 ps
CPU time 1.59 seconds
Started May 12 12:26:06 PM PDT 24
Finished May 12 12:26:08 PM PDT 24
Peak memory 199772 kb
Host smart-32238321-5136-4f5f-8ffe-202a792810f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188087538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.188087538
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2617467299
Short name T1301
Test name
Test status
Simulation time 335189044 ps
CPU time 1.24 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:26:47 PM PDT 24
Peak memory 198548 kb
Host smart-0125182c-be69-4e7e-aae9-3301c8d4514c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617467299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2617467299
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3438068934
Short name T1265
Test name
Test status
Simulation time 16437710 ps
CPU time 0.66 seconds
Started May 12 12:26:16 PM PDT 24
Finished May 12 12:26:17 PM PDT 24
Peak memory 197640 kb
Host smart-5809e76b-d915-49db-ae89-87d05245838c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438068934 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3438068934
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.126209963
Short name T1306
Test name
Test status
Simulation time 37795546 ps
CPU time 0.65 seconds
Started May 12 12:26:17 PM PDT 24
Finished May 12 12:26:18 PM PDT 24
Peak memory 195464 kb
Host smart-b1dedfb4-bfa0-4b24-97c7-b69b424d1764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126209963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.126209963
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3955897356
Short name T1289
Test name
Test status
Simulation time 11883839 ps
CPU time 0.59 seconds
Started May 12 12:23:28 PM PDT 24
Finished May 12 12:23:29 PM PDT 24
Peak memory 194536 kb
Host smart-74be1ef2-d8ec-455c-a53e-996b889ad989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955897356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3955897356
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4130178533
Short name T1284
Test name
Test status
Simulation time 24778816 ps
CPU time 0.76 seconds
Started May 12 12:26:18 PM PDT 24
Finished May 12 12:26:19 PM PDT 24
Peak memory 197616 kb
Host smart-a57b2b1a-e033-4060-a655-6c9baf9444ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130178533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4130178533
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3833046893
Short name T1262
Test name
Test status
Simulation time 472372616 ps
CPU time 2.09 seconds
Started May 12 12:27:03 PM PDT 24
Finished May 12 12:27:06 PM PDT 24
Peak memory 200056 kb
Host smart-1cc282ab-4a0e-483f-bf92-6744d40a3181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833046893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3833046893
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3581096750
Short name T1216
Test name
Test status
Simulation time 311766447 ps
CPU time 1.29 seconds
Started May 12 12:25:57 PM PDT 24
Finished May 12 12:26:00 PM PDT 24
Peak memory 198380 kb
Host smart-25761b2e-d5a6-416c-9eed-d66749e12057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581096750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3581096750
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.173034962
Short name T1245
Test name
Test status
Simulation time 26937543 ps
CPU time 1.13 seconds
Started May 12 12:27:56 PM PDT 24
Finished May 12 12:27:58 PM PDT 24
Peak memory 200124 kb
Host smart-1f477fb0-4add-43ae-b0d7-1347aad4d03f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173034962 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.173034962
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2321508953
Short name T1254
Test name
Test status
Simulation time 17616857 ps
CPU time 0.63 seconds
Started May 12 12:26:41 PM PDT 24
Finished May 12 12:26:42 PM PDT 24
Peak memory 195628 kb
Host smart-b4e40ddc-ccf7-41ce-80c1-41d96ed373d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321508953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2321508953
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1255213134
Short name T1197
Test name
Test status
Simulation time 31115538 ps
CPU time 0.53 seconds
Started May 12 12:27:56 PM PDT 24
Finished May 12 12:27:58 PM PDT 24
Peak memory 194432 kb
Host smart-832bfccd-8d19-4ab5-a33a-c013487f519f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255213134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1255213134
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.163700468
Short name T1295
Test name
Test status
Simulation time 34502217 ps
CPU time 0.63 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:28:01 PM PDT 24
Peak memory 194924 kb
Host smart-83a18e37-11e3-4c3f-84cd-f919f9088013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163700468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.163700468
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.695165364
Short name T1293
Test name
Test status
Simulation time 462001258 ps
CPU time 1.89 seconds
Started May 12 12:26:18 PM PDT 24
Finished May 12 12:26:21 PM PDT 24
Peak memory 200496 kb
Host smart-58f2d063-ac13-4d2d-8738-95e682c2c4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695165364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.695165364
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1447019945
Short name T143
Test name
Test status
Simulation time 82022702 ps
CPU time 1.35 seconds
Started May 12 12:26:27 PM PDT 24
Finished May 12 12:26:29 PM PDT 24
Peak memory 199508 kb
Host smart-cd184c58-31a5-4d57-9bf3-a86886feca52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447019945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1447019945
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1263733227
Short name T1298
Test name
Test status
Simulation time 36986358 ps
CPU time 0.66 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:26:46 PM PDT 24
Peak memory 197728 kb
Host smart-56c7dc64-c6d9-4150-970b-70b6a5a5a3f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263733227 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1263733227
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.4108666640
Short name T1221
Test name
Test status
Simulation time 15366748 ps
CPU time 0.64 seconds
Started May 12 12:26:36 PM PDT 24
Finished May 12 12:26:38 PM PDT 24
Peak memory 195452 kb
Host smart-54c7947c-c326-459b-a2da-0f530c9b8761
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108666640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4108666640
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.319655791
Short name T1292
Test name
Test status
Simulation time 35102644 ps
CPU time 0.59 seconds
Started May 12 12:26:31 PM PDT 24
Finished May 12 12:26:32 PM PDT 24
Peak memory 194392 kb
Host smart-aef57238-a7d0-46f6-9af3-00d723fc074d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319655791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.319655791
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1794581025
Short name T1248
Test name
Test status
Simulation time 27885761 ps
CPU time 0.77 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 195104 kb
Host smart-9f092cf2-7ddf-4220-9899-8eecc509f67a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794581025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1794581025
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1874590161
Short name T1198
Test name
Test status
Simulation time 102589939 ps
CPU time 1.49 seconds
Started May 12 12:27:54 PM PDT 24
Finished May 12 12:27:56 PM PDT 24
Peak memory 200108 kb
Host smart-ac7515a5-c0d3-4a2f-a44e-0c0cc111f3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874590161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1874590161
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1390054261
Short name T1235
Test name
Test status
Simulation time 76530624 ps
CPU time 0.93 seconds
Started May 12 12:27:40 PM PDT 24
Finished May 12 12:27:42 PM PDT 24
Peak memory 198696 kb
Host smart-e2e1d816-9ff0-4b6a-870b-acce9d1b0732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390054261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1390054261
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.405589352
Short name T1240
Test name
Test status
Simulation time 116311262 ps
CPU time 0.76 seconds
Started May 12 12:27:07 PM PDT 24
Finished May 12 12:27:08 PM PDT 24
Peak memory 196048 kb
Host smart-e722a26a-c92a-4992-818f-142ab6bd1efa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405589352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.405589352
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1953734938
Short name T79
Test name
Test status
Simulation time 1079246681 ps
CPU time 2.57 seconds
Started May 12 12:21:28 PM PDT 24
Finished May 12 12:21:31 PM PDT 24
Peak memory 198000 kb
Host smart-d87907d2-d466-4538-a837-230bdb8eb3b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953734938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1953734938
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2970482077
Short name T72
Test name
Test status
Simulation time 17039053 ps
CPU time 0.59 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:27:10 PM PDT 24
Peak memory 195396 kb
Host smart-a9de3d65-910c-4504-9860-f6c1f98f3e2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970482077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2970482077
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3578480250
Short name T1267
Test name
Test status
Simulation time 28821548 ps
CPU time 1.29 seconds
Started May 12 12:23:45 PM PDT 24
Finished May 12 12:23:47 PM PDT 24
Peak memory 200028 kb
Host smart-1c31425b-c0ec-41ad-ac1f-6cb9c333c05f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578480250 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3578480250
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2584324880
Short name T75
Test name
Test status
Simulation time 21914954 ps
CPU time 0.61 seconds
Started May 12 12:23:31 PM PDT 24
Finished May 12 12:23:32 PM PDT 24
Peak memory 195824 kb
Host smart-72be6cdb-a34c-4771-b698-b10199cd0e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584324880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2584324880
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3035333860
Short name T1214
Test name
Test status
Simulation time 44900836 ps
CPU time 0.55 seconds
Started May 12 12:25:55 PM PDT 24
Finished May 12 12:25:57 PM PDT 24
Peak memory 193952 kb
Host smart-54aa83d8-79d5-4aaa-b8bd-369e3ae045bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035333860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3035333860
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.675363203
Short name T1283
Test name
Test status
Simulation time 15162358 ps
CPU time 0.73 seconds
Started May 12 12:23:38 PM PDT 24
Finished May 12 12:23:39 PM PDT 24
Peak memory 197656 kb
Host smart-eda88b07-3450-473a-b025-a71c73c99d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675363203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.675363203
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2689169828
Short name T1256
Test name
Test status
Simulation time 230614974 ps
CPU time 1.37 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:27:11 PM PDT 24
Peak memory 200056 kb
Host smart-9c5e61a6-fc6b-4277-88bc-a568ea0a7d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689169828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2689169828
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2455817449
Short name T1217
Test name
Test status
Simulation time 85361931 ps
CPU time 0.91 seconds
Started May 12 12:26:28 PM PDT 24
Finished May 12 12:26:30 PM PDT 24
Peak memory 198788 kb
Host smart-5a570bd4-f3a8-41c9-bb9b-20da17781d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455817449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2455817449
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.498058354
Short name T1290
Test name
Test status
Simulation time 14350162 ps
CPU time 0.55 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:26:45 PM PDT 24
Peak memory 194412 kb
Host smart-a85a5db4-e45b-4aec-9fc6-07c8412d5e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498058354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.498058354
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3034964316
Short name T1307
Test name
Test status
Simulation time 35091081 ps
CPU time 0.57 seconds
Started May 12 12:26:35 PM PDT 24
Finished May 12 12:26:37 PM PDT 24
Peak memory 194424 kb
Host smart-0e7e5117-9103-44cb-847e-0fec10a92cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034964316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3034964316
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1461342495
Short name T1205
Test name
Test status
Simulation time 50168606 ps
CPU time 0.53 seconds
Started May 12 12:27:25 PM PDT 24
Finished May 12 12:27:26 PM PDT 24
Peak memory 194348 kb
Host smart-f5c72a96-c4a6-417b-9f77-d258dee772ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461342495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1461342495
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1405381940
Short name T1196
Test name
Test status
Simulation time 13365708 ps
CPU time 0.63 seconds
Started May 12 12:26:37 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 194848 kb
Host smart-dda0dc97-1dfc-444f-879e-27aa276b8ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405381940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1405381940
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2193668629
Short name T1258
Test name
Test status
Simulation time 13957398 ps
CPU time 0.55 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:28:01 PM PDT 24
Peak memory 194172 kb
Host smart-24260334-b480-4843-8e56-a269bfce742e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193668629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2193668629
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.344304141
Short name T1255
Test name
Test status
Simulation time 28774464 ps
CPU time 0.6 seconds
Started May 12 12:26:38 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 194504 kb
Host smart-eba36480-8066-4c11-a162-8fd0bb1475a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344304141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.344304141
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3165317809
Short name T1213
Test name
Test status
Simulation time 11970518 ps
CPU time 0.56 seconds
Started May 12 12:27:59 PM PDT 24
Finished May 12 12:28:02 PM PDT 24
Peak memory 194184 kb
Host smart-c313f0ec-2fb4-44b9-a13a-9a2c6e08a7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165317809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3165317809
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2753392536
Short name T1203
Test name
Test status
Simulation time 23652533 ps
CPU time 0.58 seconds
Started May 12 12:26:34 PM PDT 24
Finished May 12 12:26:35 PM PDT 24
Peak memory 194436 kb
Host smart-5754f7bc-967c-4b27-a500-7ab2810c858e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753392536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2753392536
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.269763805
Short name T1207
Test name
Test status
Simulation time 36686820 ps
CPU time 0.55 seconds
Started May 12 12:27:44 PM PDT 24
Finished May 12 12:27:45 PM PDT 24
Peak memory 194356 kb
Host smart-dc8cb63a-d162-4ceb-8d22-90b786cf22af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269763805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.269763805
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.662966128
Short name T1316
Test name
Test status
Simulation time 181368388 ps
CPU time 0.58 seconds
Started May 12 12:26:36 PM PDT 24
Finished May 12 12:26:38 PM PDT 24
Peak memory 194832 kb
Host smart-162f7f28-0016-414b-b904-7008e7b2b884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662966128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.662966128
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2666126702
Short name T71
Test name
Test status
Simulation time 106540206 ps
CPU time 0.8 seconds
Started May 12 12:26:54 PM PDT 24
Finished May 12 12:26:57 PM PDT 24
Peak memory 195556 kb
Host smart-cdf2615f-ff64-40b5-acd2-23ed4e17a41a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666126702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2666126702
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3336865824
Short name T73
Test name
Test status
Simulation time 1077875177 ps
CPU time 2.59 seconds
Started May 12 12:23:33 PM PDT 24
Finished May 12 12:23:37 PM PDT 24
Peak memory 197776 kb
Host smart-3e7d7a79-ab49-46f1-9f73-0b9245a7af89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336865824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3336865824
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3104400451
Short name T1191
Test name
Test status
Simulation time 15671021 ps
CPU time 0.59 seconds
Started May 12 12:25:09 PM PDT 24
Finished May 12 12:25:10 PM PDT 24
Peak memory 195464 kb
Host smart-94a8fafd-0d31-416c-9a9d-352f37547dc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104400451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3104400451
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1366509595
Short name T1246
Test name
Test status
Simulation time 39842698 ps
CPU time 0.95 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:27:15 PM PDT 24
Peak memory 199584 kb
Host smart-c8f17168-e19f-416e-b4c8-2de4f215f83b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366509595 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1366509595
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4263501315
Short name T1300
Test name
Test status
Simulation time 32472547 ps
CPU time 0.6 seconds
Started May 12 12:25:57 PM PDT 24
Finished May 12 12:25:59 PM PDT 24
Peak memory 193632 kb
Host smart-db0ddfab-da9b-4b87-89df-5dbdc063722d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263501315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4263501315
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1571110522
Short name T1232
Test name
Test status
Simulation time 29240283 ps
CPU time 0.59 seconds
Started May 12 12:24:18 PM PDT 24
Finished May 12 12:24:19 PM PDT 24
Peak memory 194396 kb
Host smart-1e591f38-2535-4dba-811f-9a9f46fea3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571110522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1571110522
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1350158605
Short name T82
Test name
Test status
Simulation time 93349042 ps
CPU time 0.7 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:27:14 PM PDT 24
Peak memory 194164 kb
Host smart-dc3a041f-64c4-4a5b-9649-1504c4b6e11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350158605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1350158605
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1659788352
Short name T1226
Test name
Test status
Simulation time 70668369 ps
CPU time 1.45 seconds
Started May 12 12:27:03 PM PDT 24
Finished May 12 12:27:06 PM PDT 24
Peak memory 199660 kb
Host smart-5422a56b-5b63-4ab5-9fe1-afd1e450fae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659788352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1659788352
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1815611307
Short name T91
Test name
Test status
Simulation time 170197511 ps
CPU time 1.4 seconds
Started May 12 12:27:12 PM PDT 24
Finished May 12 12:27:15 PM PDT 24
Peak memory 198908 kb
Host smart-f4dff723-ce77-4821-abb8-27ef9a80bc51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815611307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1815611307
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.509138192
Short name T1288
Test name
Test status
Simulation time 25697649 ps
CPU time 0.58 seconds
Started May 12 12:26:37 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 194488 kb
Host smart-6fbc7273-6641-425d-b940-aa03c634dd56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509138192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.509138192
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.835027505
Short name T1280
Test name
Test status
Simulation time 164292407 ps
CPU time 0.56 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:26:50 PM PDT 24
Peak memory 194368 kb
Host smart-160df420-f813-4c88-b7b3-4562151cbe85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835027505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.835027505
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.155831959
Short name T1218
Test name
Test status
Simulation time 11694345 ps
CPU time 0.56 seconds
Started May 12 12:26:37 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 194336 kb
Host smart-01e4ace0-7f74-4fb9-8dc2-df7672453579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155831959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.155831959
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1770837119
Short name T1297
Test name
Test status
Simulation time 13707102 ps
CPU time 0.57 seconds
Started May 12 12:26:36 PM PDT 24
Finished May 12 12:26:38 PM PDT 24
Peak memory 194408 kb
Host smart-b748a483-4054-4521-8e94-40e87e42df35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770837119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1770837119
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3959213275
Short name T1233
Test name
Test status
Simulation time 36238202 ps
CPU time 0.61 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 192508 kb
Host smart-4ef5a29d-4c01-45a5-9b6f-be8fbc100dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959213275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3959213275
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1168028156
Short name T1223
Test name
Test status
Simulation time 13999007 ps
CPU time 0.57 seconds
Started May 12 12:26:38 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 194908 kb
Host smart-5ab062c0-7583-4070-a828-598d7c2b87a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168028156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1168028156
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.865950014
Short name T1296
Test name
Test status
Simulation time 46278229 ps
CPU time 0.6 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:26:50 PM PDT 24
Peak memory 194372 kb
Host smart-17661b82-7d98-4f4c-9098-a439d310ec6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865950014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.865950014
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1626510452
Short name T1193
Test name
Test status
Simulation time 24190788 ps
CPU time 0.59 seconds
Started May 12 12:26:45 PM PDT 24
Finished May 12 12:26:47 PM PDT 24
Peak memory 194460 kb
Host smart-9fc74ac0-d963-4d28-a9ae-2a0ace00314b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626510452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1626510452
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2367965919
Short name T1291
Test name
Test status
Simulation time 120441275 ps
CPU time 0.63 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:26:49 PM PDT 24
Peak memory 194408 kb
Host smart-0326e45e-59fc-426b-8e31-2c5ae447e750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367965919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2367965919
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1620602165
Short name T1239
Test name
Test status
Simulation time 14969322 ps
CPU time 0.57 seconds
Started May 12 12:27:58 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 194092 kb
Host smart-0d27e4d7-4d4f-4498-95a4-77d1a8c3bddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620602165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1620602165
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2289689845
Short name T1319
Test name
Test status
Simulation time 21703119 ps
CPU time 0.68 seconds
Started May 12 12:23:01 PM PDT 24
Finished May 12 12:23:02 PM PDT 24
Peak memory 195512 kb
Host smart-49f05908-ea11-43cd-bbe2-86ea8ed5cbf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289689845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2289689845
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1366533404
Short name T1302
Test name
Test status
Simulation time 72317773 ps
CPU time 1.37 seconds
Started May 12 12:27:09 PM PDT 24
Finished May 12 12:27:12 PM PDT 24
Peak memory 197692 kb
Host smart-9503c9ff-e8f1-4b20-ad76-a2b6f890e00a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366533404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1366533404
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2819053014
Short name T1309
Test name
Test status
Simulation time 71922134 ps
CPU time 0.59 seconds
Started May 12 12:21:02 PM PDT 24
Finished May 12 12:21:03 PM PDT 24
Peak memory 195452 kb
Host smart-4407929e-2e22-4c28-9550-1c749bf1b716
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819053014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2819053014
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3138456214
Short name T1268
Test name
Test status
Simulation time 72921133 ps
CPU time 0.67 seconds
Started May 12 12:25:50 PM PDT 24
Finished May 12 12:25:51 PM PDT 24
Peak memory 198284 kb
Host smart-98cf708a-ab9e-4e9e-a624-627de3a5a75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138456214 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3138456214
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2280013449
Short name T1276
Test name
Test status
Simulation time 36943882 ps
CPU time 0.59 seconds
Started May 12 12:26:59 PM PDT 24
Finished May 12 12:27:01 PM PDT 24
Peak memory 195176 kb
Host smart-1d4802b1-1110-4d44-9961-0571ad110227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280013449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2280013449
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4148769416
Short name T1202
Test name
Test status
Simulation time 15638989 ps
CPU time 0.58 seconds
Started May 12 12:24:55 PM PDT 24
Finished May 12 12:24:56 PM PDT 24
Peak memory 194560 kb
Host smart-b2dc13a9-ab3f-4cd2-beca-76af89b1174a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148769416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4148769416
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.75030632
Short name T1244
Test name
Test status
Simulation time 73902731 ps
CPU time 0.7 seconds
Started May 12 12:23:06 PM PDT 24
Finished May 12 12:23:07 PM PDT 24
Peak memory 197332 kb
Host smart-544b1bbe-05a5-4e94-9e3e-206639c64008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75030632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o
utstanding.75030632
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3029497534
Short name T1287
Test name
Test status
Simulation time 455127043 ps
CPU time 1.63 seconds
Started May 12 12:25:00 PM PDT 24
Finished May 12 12:25:02 PM PDT 24
Peak memory 200060 kb
Host smart-877b15bb-f444-471d-bdad-d4438bacd48e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029497534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3029497534
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.11986370
Short name T96
Test name
Test status
Simulation time 159862016 ps
CPU time 1.24 seconds
Started May 12 12:26:12 PM PDT 24
Finished May 12 12:26:14 PM PDT 24
Peak memory 197776 kb
Host smart-621cbebb-a6c8-46d2-ac3c-281bf8932cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.11986370
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1176644532
Short name T1257
Test name
Test status
Simulation time 56387368 ps
CPU time 0.63 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:26:49 PM PDT 24
Peak memory 194404 kb
Host smart-35b8b9e3-5657-4413-83ad-37bfb8c69ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176644532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1176644532
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3545128832
Short name T1274
Test name
Test status
Simulation time 52709694 ps
CPU time 0.56 seconds
Started May 12 12:26:35 PM PDT 24
Finished May 12 12:26:36 PM PDT 24
Peak memory 194348 kb
Host smart-4e9be932-9631-4935-bfbb-2f950982d573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545128832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3545128832
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1444180647
Short name T1238
Test name
Test status
Simulation time 13973005 ps
CPU time 0.57 seconds
Started May 12 12:27:20 PM PDT 24
Finished May 12 12:27:21 PM PDT 24
Peak memory 194344 kb
Host smart-d5a1b733-e731-43bc-81c9-c9c22fa16d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444180647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1444180647
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2436173720
Short name T1312
Test name
Test status
Simulation time 43095928 ps
CPU time 0.56 seconds
Started May 12 12:26:36 PM PDT 24
Finished May 12 12:26:38 PM PDT 24
Peak memory 194832 kb
Host smart-eaa20f3f-d765-4ad6-8cd5-c183a996e800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436173720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2436173720
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.752766594
Short name T1304
Test name
Test status
Simulation time 15691479 ps
CPU time 0.65 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 192564 kb
Host smart-34127420-7fb6-48ef-899d-6b548c3333c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752766594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.752766594
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1123814563
Short name T1192
Test name
Test status
Simulation time 42583919 ps
CPU time 0.56 seconds
Started May 12 12:26:44 PM PDT 24
Finished May 12 12:26:46 PM PDT 24
Peak memory 194372 kb
Host smart-93be8a7b-dc9d-4a9d-a25e-e77e9711bd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123814563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1123814563
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.4003171511
Short name T1189
Test name
Test status
Simulation time 65190482 ps
CPU time 0.62 seconds
Started May 12 12:26:48 PM PDT 24
Finished May 12 12:26:49 PM PDT 24
Peak memory 194356 kb
Host smart-1425345e-1daf-41e7-a107-68938117d00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003171511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4003171511
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3379191581
Short name T1318
Test name
Test status
Simulation time 11519813 ps
CPU time 0.58 seconds
Started May 12 12:26:35 PM PDT 24
Finished May 12 12:26:37 PM PDT 24
Peak memory 194364 kb
Host smart-c4657219-ef5a-4c42-8e68-f5074771cba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379191581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3379191581
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.113437633
Short name T1215
Test name
Test status
Simulation time 44370091 ps
CPU time 0.58 seconds
Started May 12 12:27:57 PM PDT 24
Finished May 12 12:28:00 PM PDT 24
Peak memory 192668 kb
Host smart-2c0b2b50-9640-4eb9-a4ec-0a9e60cdcfad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113437633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.113437633
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1013991594
Short name T1195
Test name
Test status
Simulation time 72998920 ps
CPU time 0.64 seconds
Started May 12 12:26:37 PM PDT 24
Finished May 12 12:26:39 PM PDT 24
Peak memory 194416 kb
Host smart-ade8cda1-541c-4396-a23f-b78ab6481809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013991594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1013991594
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2922282204
Short name T1241
Test name
Test status
Simulation time 20185806 ps
CPU time 0.72 seconds
Started May 12 12:26:52 PM PDT 24
Finished May 12 12:26:54 PM PDT 24
Peak memory 196796 kb
Host smart-9e6c78c9-071e-491d-bbd8-94a8b6d008e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922282204 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2922282204
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.35377786
Short name T74
Test name
Test status
Simulation time 19652227 ps
CPU time 0.61 seconds
Started May 12 12:27:08 PM PDT 24
Finished May 12 12:27:09 PM PDT 24
Peak memory 195552 kb
Host smart-e2731f5c-c565-412e-8c08-329e81948743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.35377786
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1560004981
Short name T1273
Test name
Test status
Simulation time 21785185 ps
CPU time 0.58 seconds
Started May 12 12:26:59 PM PDT 24
Finished May 12 12:27:01 PM PDT 24
Peak memory 194136 kb
Host smart-bae0dbf2-4b91-4598-8a71-b67e479298d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560004981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1560004981
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2007607572
Short name T89
Test name
Test status
Simulation time 29540914 ps
CPU time 0.82 seconds
Started May 12 12:26:52 PM PDT 24
Finished May 12 12:26:54 PM PDT 24
Peak memory 196064 kb
Host smart-d28f0861-c31f-4ecd-85c8-c68422d08be8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007607572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2007607572
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2324502442
Short name T1272
Test name
Test status
Simulation time 79778879 ps
CPU time 1.63 seconds
Started May 12 12:21:38 PM PDT 24
Finished May 12 12:21:41 PM PDT 24
Peak memory 200116 kb
Host smart-c1d3f004-41aa-4c04-8d0e-17429ae9e657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324502442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2324502442
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3374392533
Short name T140
Test name
Test status
Simulation time 246476310 ps
CPU time 1.23 seconds
Started May 12 12:30:20 PM PDT 24
Finished May 12 12:30:22 PM PDT 24
Peak memory 199300 kb
Host smart-7ce0a16c-e8c3-4264-89d9-d71888e33c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374392533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3374392533
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3993798058
Short name T1275
Test name
Test status
Simulation time 74768458 ps
CPU time 0.72 seconds
Started May 12 12:22:23 PM PDT 24
Finished May 12 12:22:24 PM PDT 24
Peak memory 198812 kb
Host smart-31fb2804-e6d4-42d0-82ba-45ff414ba472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993798058 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3993798058
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3209250499
Short name T83
Test name
Test status
Simulation time 48507841 ps
CPU time 0.61 seconds
Started May 12 12:22:36 PM PDT 24
Finished May 12 12:22:37 PM PDT 24
Peak memory 195440 kb
Host smart-205e026a-3393-4542-b381-173cd7e87b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209250499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3209250499
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.639362060
Short name T1209
Test name
Test status
Simulation time 19347862 ps
CPU time 0.59 seconds
Started May 12 12:25:56 PM PDT 24
Finished May 12 12:25:58 PM PDT 24
Peak memory 193404 kb
Host smart-3d54d40d-b177-4842-a4ff-6700ec23ddf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639362060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.639362060
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.381070459
Short name T1310
Test name
Test status
Simulation time 63741807 ps
CPU time 0.74 seconds
Started May 12 12:22:36 PM PDT 24
Finished May 12 12:22:38 PM PDT 24
Peak memory 195948 kb
Host smart-ffe6b31a-cacf-4ce3-a5d6-b9e1bc5906fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381070459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.381070459
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2043279393
Short name T1317
Test name
Test status
Simulation time 136414341 ps
CPU time 2.47 seconds
Started May 12 12:25:57 PM PDT 24
Finished May 12 12:26:01 PM PDT 24
Peak memory 199900 kb
Host smart-56e5ab53-f278-49e1-b0bf-6af7a888f92a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043279393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2043279393
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3929188100
Short name T1236
Test name
Test status
Simulation time 184256693 ps
CPU time 0.93 seconds
Started May 12 12:25:58 PM PDT 24
Finished May 12 12:26:01 PM PDT 24
Peak memory 198176 kb
Host smart-a8e81ac2-2a02-439b-8772-11c71dfdcc96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929188100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3929188100
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2194931618
Short name T1208
Test name
Test status
Simulation time 38846424 ps
CPU time 0.89 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:27:21 PM PDT 24
Peak memory 199756 kb
Host smart-d7b36a37-6401-4b48-bce2-27e8283c47e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194931618 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2194931618
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3784416143
Short name T87
Test name
Test status
Simulation time 12437062 ps
CPU time 0.64 seconds
Started May 12 12:27:01 PM PDT 24
Finished May 12 12:27:02 PM PDT 24
Peak memory 194660 kb
Host smart-841237c5-3214-40f8-94eb-f3f123d29d98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784416143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3784416143
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2050747441
Short name T1270
Test name
Test status
Simulation time 14137463 ps
CPU time 0.62 seconds
Started May 12 12:26:51 PM PDT 24
Finished May 12 12:26:52 PM PDT 24
Peak memory 193208 kb
Host smart-28ab660f-bcca-40ae-9fe8-c42c732f7aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050747441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2050747441
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1406566424
Short name T1211
Test name
Test status
Simulation time 16618614 ps
CPU time 0.63 seconds
Started May 12 12:27:19 PM PDT 24
Finished May 12 12:27:20 PM PDT 24
Peak memory 195324 kb
Host smart-e24bd683-3032-47d7-86c7-ec6643b421c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406566424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1406566424
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2139919960
Short name T1311
Test name
Test status
Simulation time 32110121 ps
CPU time 1.5 seconds
Started May 12 12:26:51 PM PDT 24
Finished May 12 12:26:53 PM PDT 24
Peak memory 198840 kb
Host smart-2fc863d0-d35d-4305-8d7b-0ee88e6b2318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139919960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2139919960
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4116586670
Short name T97
Test name
Test status
Simulation time 46422350 ps
CPU time 0.92 seconds
Started May 12 12:26:52 PM PDT 24
Finished May 12 12:26:54 PM PDT 24
Peak memory 198900 kb
Host smart-8a995b6e-8d0e-4118-be60-af56ff8dbcd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116586670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4116586670
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.895736519
Short name T1251
Test name
Test status
Simulation time 76032876 ps
CPU time 0.75 seconds
Started May 12 12:21:28 PM PDT 24
Finished May 12 12:21:29 PM PDT 24
Peak memory 198492 kb
Host smart-18cc9f0d-9414-4b08-88da-671da51eb9a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895736519 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.895736519
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1346793419
Short name T1303
Test name
Test status
Simulation time 64737413 ps
CPU time 0.64 seconds
Started May 12 12:25:32 PM PDT 24
Finished May 12 12:25:33 PM PDT 24
Peak memory 195624 kb
Host smart-c1546f68-3753-40ca-a259-d5a29a38e4bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346793419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1346793419
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.89451372
Short name T1314
Test name
Test status
Simulation time 53092054 ps
CPU time 0.58 seconds
Started May 12 12:23:20 PM PDT 24
Finished May 12 12:23:21 PM PDT 24
Peak memory 194344 kb
Host smart-1d8fdebf-5c9d-4079-858a-6abac2ebeead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89451372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.89451372
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.29958414
Short name T81
Test name
Test status
Simulation time 43208147 ps
CPU time 0.63 seconds
Started May 12 12:27:15 PM PDT 24
Finished May 12 12:27:17 PM PDT 24
Peak memory 195588 kb
Host smart-30cf1a6c-5071-4851-ad69-2c2670585178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29958414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_o
utstanding.29958414
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2046744522
Short name T1210
Test name
Test status
Simulation time 89569078 ps
CPU time 1.31 seconds
Started May 12 12:21:54 PM PDT 24
Finished May 12 12:21:56 PM PDT 24
Peak memory 200012 kb
Host smart-861b3bc2-67ca-4ac9-9757-4e133d178b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046744522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2046744522
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.60586449
Short name T90
Test name
Test status
Simulation time 205225307 ps
CPU time 0.98 seconds
Started May 12 12:27:18 PM PDT 24
Finished May 12 12:27:20 PM PDT 24
Peak memory 198420 kb
Host smart-23ff4f35-eebf-4a3c-b33f-5bb3a9b74e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60586449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.60586449
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1035448724
Short name T1271
Test name
Test status
Simulation time 20807490 ps
CPU time 0.73 seconds
Started May 12 12:22:18 PM PDT 24
Finished May 12 12:22:19 PM PDT 24
Peak memory 199036 kb
Host smart-f52131cb-26c3-4a6a-b36e-b6ce8f2d39de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035448724 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1035448724
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3402277193
Short name T1286
Test name
Test status
Simulation time 12618825 ps
CPU time 0.56 seconds
Started May 12 12:26:24 PM PDT 24
Finished May 12 12:26:25 PM PDT 24
Peak memory 195144 kb
Host smart-ca18c9b9-dc43-4392-88f1-453f8ec70e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402277193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3402277193
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2114859085
Short name T1252
Test name
Test status
Simulation time 51998432 ps
CPU time 0.62 seconds
Started May 12 12:25:57 PM PDT 24
Finished May 12 12:25:59 PM PDT 24
Peak memory 192616 kb
Host smart-71e6411d-09cd-4263-a119-5612f3680fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114859085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2114859085
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2626979452
Short name T1299
Test name
Test status
Simulation time 36340318 ps
CPU time 0.7 seconds
Started May 12 12:25:58 PM PDT 24
Finished May 12 12:26:01 PM PDT 24
Peak memory 196884 kb
Host smart-466840d6-bed8-48a6-ae91-43c0e19b55e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626979452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2626979452
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1835085368
Short name T1201
Test name
Test status
Simulation time 48382731 ps
CPU time 2.41 seconds
Started May 12 12:21:56 PM PDT 24
Finished May 12 12:21:59 PM PDT 24
Peak memory 200532 kb
Host smart-a89df1d6-b1da-4435-8c42-6e842506544f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835085368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1835085368
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3769021666
Short name T141
Test name
Test status
Simulation time 278827327 ps
CPU time 1.2 seconds
Started May 12 12:26:24 PM PDT 24
Finished May 12 12:26:26 PM PDT 24
Peak memory 199176 kb
Host smart-14ec0884-c5aa-48bc-b51c-46a50e9eff88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769021666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3769021666
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2401932562
Short name T811
Test name
Test status
Simulation time 90589234672 ps
CPU time 91.41 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:25:47 PM PDT 24
Peak memory 200328 kb
Host smart-03ca68a8-ff8e-4b4c-a71e-72797535a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401932562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2401932562
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1537634083
Short name T741
Test name
Test status
Simulation time 31547621586 ps
CPU time 30.94 seconds
Started May 12 01:24:16 PM PDT 24
Finished May 12 01:24:47 PM PDT 24
Peak memory 200188 kb
Host smart-74d16a70-73bd-49d0-b329-f73a55721ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537634083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1537634083
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3004883204
Short name T190
Test name
Test status
Simulation time 58296280559 ps
CPU time 45.65 seconds
Started May 12 01:24:14 PM PDT 24
Finished May 12 01:25:00 PM PDT 24
Peak memory 200328 kb
Host smart-4ba32a2d-dfd9-4acf-8cf1-50be2e13da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004883204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3004883204
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3815653664
Short name T394
Test name
Test status
Simulation time 185172931310 ps
CPU time 83.82 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 198420 kb
Host smart-637b3a81-ff7f-428c-af7a-034baeecfd32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815653664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3815653664
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2550455969
Short name T313
Test name
Test status
Simulation time 89400201788 ps
CPU time 255.97 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:28:37 PM PDT 24
Peak memory 200280 kb
Host smart-95b08fef-337a-48e1-bf22-d22ff1e0ab2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550455969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2550455969
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2284223885
Short name T25
Test name
Test status
Simulation time 6017703003 ps
CPU time 10.98 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:24:33 PM PDT 24
Peak memory 198624 kb
Host smart-39688e2c-b80a-4a59-bd74-ee8a76813c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284223885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2284223885
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1462884962
Short name T728
Test name
Test status
Simulation time 41665478098 ps
CPU time 28.32 seconds
Started May 12 01:24:19 PM PDT 24
Finished May 12 01:24:48 PM PDT 24
Peak memory 199024 kb
Host smart-cbb77210-3f58-45df-ba83-bd7b14db8df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462884962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1462884962
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3259987309
Short name T663
Test name
Test status
Simulation time 5580775683 ps
CPU time 261.83 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:28:47 PM PDT 24
Peak memory 200412 kb
Host smart-966369ba-249b-42aa-b07c-09ae550a53a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259987309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3259987309
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4142736479
Short name T1099
Test name
Test status
Simulation time 2662101915 ps
CPU time 5.45 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:21 PM PDT 24
Peak memory 198884 kb
Host smart-c2bc0413-c0d5-4e17-a7b2-884595ba8839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142736479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4142736479
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3355903159
Short name T531
Test name
Test status
Simulation time 73297872294 ps
CPU time 31.24 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 200520 kb
Host smart-2872e8c2-3f75-4fee-af6f-9cc0f05e3b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355903159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3355903159
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2623938426
Short name T379
Test name
Test status
Simulation time 4800611649 ps
CPU time 8.56 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:30 PM PDT 24
Peak memory 196688 kb
Host smart-74506cb4-5ad9-4c8a-8a61-675170688fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623938426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2623938426
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.4275832938
Short name T99
Test name
Test status
Simulation time 254429271 ps
CPU time 0.9 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:24:25 PM PDT 24
Peak memory 218352 kb
Host smart-42fc159a-7bbe-4bb2-9f40-1c4851e824e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275832938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.4275832938
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1861286509
Short name T380
Test name
Test status
Simulation time 6012989222 ps
CPU time 13.69 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:30 PM PDT 24
Peak memory 200144 kb
Host smart-36bac350-6131-472c-835e-228883e354d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861286509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1861286509
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3829751289
Short name T970
Test name
Test status
Simulation time 13225975747 ps
CPU time 66.46 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:25:31 PM PDT 24
Peak memory 200400 kb
Host smart-900a6406-004b-4905-a0d8-4c8c325cbddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829751289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3829751289
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3552609286
Short name T735
Test name
Test status
Simulation time 11025403387 ps
CPU time 154.91 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:26:53 PM PDT 24
Peak memory 215932 kb
Host smart-cbe233a1-3eb2-4729-a14d-96e9e99da980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552609286 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3552609286
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2832461484
Short name T968
Test name
Test status
Simulation time 1096038821 ps
CPU time 2.28 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:24:24 PM PDT 24
Peak memory 198776 kb
Host smart-36ea20a7-2008-419e-a19f-0c28ef5dfc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832461484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2832461484
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1884273119
Short name T445
Test name
Test status
Simulation time 103721705757 ps
CPU time 108.27 seconds
Started May 12 01:24:14 PM PDT 24
Finished May 12 01:26:03 PM PDT 24
Peak memory 200412 kb
Host smart-b3033063-9951-4003-9c22-57bc7ca50224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884273119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1884273119
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2803517572
Short name T785
Test name
Test status
Simulation time 43564059 ps
CPU time 0.55 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:24:22 PM PDT 24
Peak memory 195736 kb
Host smart-6fbf5592-4f4e-4edc-a4f7-65854b472f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803517572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2803517572
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1516003656
Short name T353
Test name
Test status
Simulation time 148897439795 ps
CPU time 111.17 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:26:14 PM PDT 24
Peak memory 200304 kb
Host smart-0e831bf4-153b-4f8c-a042-77f10bb2cb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516003656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1516003656
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2303578393
Short name T155
Test name
Test status
Simulation time 121755558666 ps
CPU time 70.81 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:25:33 PM PDT 24
Peak memory 200292 kb
Host smart-82968ca7-3017-44d2-97d7-f0afa4d4c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303578393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2303578393
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.3085352176
Short name T390
Test name
Test status
Simulation time 19797375448 ps
CPU time 34.08 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:24:59 PM PDT 24
Peak memory 200388 kb
Host smart-8ef7e5ee-ad06-4371-a49e-a9625e77b07e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085352176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3085352176
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2979382791
Short name T276
Test name
Test status
Simulation time 86189583782 ps
CPU time 489.17 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 200304 kb
Host smart-3467c3c4-7570-488c-ac76-51898c6324a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979382791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2979382791
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.776392615
Short name T488
Test name
Test status
Simulation time 13739953975 ps
CPU time 9.98 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:24:32 PM PDT 24
Peak memory 200056 kb
Host smart-07233429-2cd0-40a4-82c9-2f62cd12cab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776392615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.776392615
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3724265852
Short name T49
Test name
Test status
Simulation time 4476326908 ps
CPU time 7.6 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:33 PM PDT 24
Peak memory 196212 kb
Host smart-5a82f977-04e1-4e04-85ea-6405da73f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724265852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3724265852
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3873737874
Short name T1016
Test name
Test status
Simulation time 15630113229 ps
CPU time 62.74 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:25:27 PM PDT 24
Peak memory 200392 kb
Host smart-a4d0ac93-4671-4f14-ac11-a27023a51cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873737874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3873737874
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3551432828
Short name T464
Test name
Test status
Simulation time 4822463143 ps
CPU time 4.99 seconds
Started May 12 01:24:17 PM PDT 24
Finished May 12 01:24:23 PM PDT 24
Peak memory 199568 kb
Host smart-8709c989-6f06-4f56-a4dc-c9d0cf1a7f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551432828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3551432828
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3216237152
Short name T11
Test name
Test status
Simulation time 74776004166 ps
CPU time 40.19 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 200352 kb
Host smart-2912f387-9381-4a53-a737-91d946b89fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216237152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3216237152
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1592151294
Short name T10
Test name
Test status
Simulation time 3885037518 ps
CPU time 1.83 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:24:25 PM PDT 24
Peak memory 196644 kb
Host smart-d2cda6b8-9756-4b2d-ac42-4371d18428b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592151294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1592151294
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1522208227
Short name T100
Test name
Test status
Simulation time 85754477 ps
CPU time 0.83 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:24:22 PM PDT 24
Peak memory 218540 kb
Host smart-b029172d-422a-427b-8e72-288460ba3a70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522208227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1522208227
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1281814074
Short name T746
Test name
Test status
Simulation time 5451520606 ps
CPU time 14.38 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:35 PM PDT 24
Peak memory 200160 kb
Host smart-2aa4c426-2782-42a2-8585-8351fe309ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281814074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1281814074
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3024282259
Short name T762
Test name
Test status
Simulation time 38783136677 ps
CPU time 32.74 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:58 PM PDT 24
Peak memory 200368 kb
Host smart-4f8c6802-cfb0-41d1-9e17-dc91564e0736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024282259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3024282259
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1064744266
Short name T598
Test name
Test status
Simulation time 97710547164 ps
CPU time 1052.78 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:41:58 PM PDT 24
Peak memory 219240 kb
Host smart-8c4a5a50-708a-42be-82f3-14c0f81fda29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064744266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1064744266
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.4142112545
Short name T1114
Test name
Test status
Simulation time 2767873520 ps
CPU time 2.2 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:23 PM PDT 24
Peak memory 199196 kb
Host smart-58ed7217-fb25-43c2-b037-b2a037f8d7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142112545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.4142112545
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.13842772
Short name T441
Test name
Test status
Simulation time 9634937168 ps
CPU time 14.83 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:36 PM PDT 24
Peak memory 200132 kb
Host smart-4d49c8d3-169f-429f-8702-bb150348f9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13842772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.13842772
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2927154898
Short name T1038
Test name
Test status
Simulation time 65466498 ps
CPU time 0.54 seconds
Started May 12 01:24:46 PM PDT 24
Finished May 12 01:24:47 PM PDT 24
Peak memory 194768 kb
Host smart-376cca53-483e-49d8-ad93-e7a25f0139de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927154898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2927154898
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.556900111
Short name T428
Test name
Test status
Simulation time 34187604906 ps
CPU time 50.56 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 200412 kb
Host smart-10447165-caa0-466d-8352-f5c6600e107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556900111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.556900111
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1882895181
Short name T753
Test name
Test status
Simulation time 158196689172 ps
CPU time 248.29 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200276 kb
Host smart-91eb1b13-1e48-4ae3-a67b-3a72cca32fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882895181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1882895181
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2632956500
Short name T742
Test name
Test status
Simulation time 27691935074 ps
CPU time 13.63 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:25:00 PM PDT 24
Peak memory 200300 kb
Host smart-cee10811-c9bd-4f56-9799-5c0ec8ccb37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632956500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2632956500
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3625769472
Short name T439
Test name
Test status
Simulation time 27626174003 ps
CPU time 46.46 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:25:30 PM PDT 24
Peak memory 197988 kb
Host smart-22103690-8369-4022-a05e-8b3e46d76e12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625769472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3625769472
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3216726862
Short name T1134
Test name
Test status
Simulation time 30797345738 ps
CPU time 269.32 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:29:12 PM PDT 24
Peak memory 200360 kb
Host smart-daec7ad9-8ef6-4df8-8a27-7c766baa8f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216726862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3216726862
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4220011628
Short name T496
Test name
Test status
Simulation time 319111082 ps
CPU time 1.2 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:47 PM PDT 24
Peak memory 199164 kb
Host smart-89c9ba89-4e90-4a9c-a55c-4b0e8a0b6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220011628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4220011628
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.4094915083
Short name T474
Test name
Test status
Simulation time 71529910428 ps
CPU time 101.52 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:26:23 PM PDT 24
Peak memory 200520 kb
Host smart-1c437ca1-f6ef-45a2-a860-78e05ff2ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094915083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.4094915083
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2376876038
Short name T1153
Test name
Test status
Simulation time 14029287064 ps
CPU time 355.49 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:30:37 PM PDT 24
Peak memory 200280 kb
Host smart-9cef229e-528b-45cd-8078-e90e6d0d2e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376876038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2376876038
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.433715165
Short name T909
Test name
Test status
Simulation time 1168217767 ps
CPU time 2.68 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:24:44 PM PDT 24
Peak memory 197304 kb
Host smart-20aec933-bf6e-4147-9c39-05027b82a561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433715165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.433715165
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3596229370
Short name T862
Test name
Test status
Simulation time 46809324810 ps
CPU time 19.64 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:25:02 PM PDT 24
Peak memory 200256 kb
Host smart-8f7f8324-ac81-473f-9e6b-f06ce0013a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596229370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3596229370
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3157800443
Short name T896
Test name
Test status
Simulation time 5574140643 ps
CPU time 8.98 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:54 PM PDT 24
Peak memory 196676 kb
Host smart-e88fd502-b597-4a6b-b4d7-109626cf5983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157800443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3157800443
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3263588540
Short name T1147
Test name
Test status
Simulation time 5753668921 ps
CPU time 13.05 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:24:57 PM PDT 24
Peak memory 200340 kb
Host smart-3aede504-1cc4-4897-bcdd-dcc04c46509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263588540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3263588540
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.421957536
Short name T772
Test name
Test status
Simulation time 18096127004 ps
CPU time 224.04 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:28:26 PM PDT 24
Peak memory 208788 kb
Host smart-d72eaaff-c1ca-488d-9d0d-899653730a15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421957536 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.421957536
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4259207329
Short name T1179
Test name
Test status
Simulation time 1918720725 ps
CPU time 1.88 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:24:46 PM PDT 24
Peak memory 198852 kb
Host smart-e342f9ed-f779-4a69-99e2-8dc0a79ebd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259207329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4259207329
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1897948654
Short name T609
Test name
Test status
Simulation time 124012268417 ps
CPU time 248.47 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:28:49 PM PDT 24
Peak memory 200416 kb
Host smart-c27bf8b0-88bb-4e18-9bdb-10216f9517a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897948654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1897948654
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3846455384
Short name T205
Test name
Test status
Simulation time 22937753348 ps
CPU time 38.94 seconds
Started May 12 01:28:24 PM PDT 24
Finished May 12 01:29:04 PM PDT 24
Peak memory 200308 kb
Host smart-f6d3a11d-cc80-4ca0-9719-9ca2856e487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846455384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3846455384
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3664925368
Short name T1048
Test name
Test status
Simulation time 102317906156 ps
CPU time 249.37 seconds
Started May 12 01:28:24 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 200324 kb
Host smart-8a7be958-9807-4cca-82cf-11b5a3ac6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664925368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3664925368
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.664511994
Short name T606
Test name
Test status
Simulation time 17032313774 ps
CPU time 28.21 seconds
Started May 12 01:28:22 PM PDT 24
Finished May 12 01:28:50 PM PDT 24
Peak memory 200404 kb
Host smart-678eff10-bf11-48b0-924e-fd59622ce03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664511994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.664511994
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1781982851
Short name T58
Test name
Test status
Simulation time 163882917296 ps
CPU time 49.48 seconds
Started May 12 01:28:22 PM PDT 24
Finished May 12 01:29:12 PM PDT 24
Peak memory 200404 kb
Host smart-1f20bd1c-246b-4b7a-a47e-76305f196170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781982851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1781982851
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1235817161
Short name T177
Test name
Test status
Simulation time 146142622249 ps
CPU time 97.42 seconds
Started May 12 01:28:22 PM PDT 24
Finished May 12 01:30:00 PM PDT 24
Peak memory 200340 kb
Host smart-e671e9ce-f7ad-4d55-8e57-d4265b7206e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235817161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1235817161
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.606366729
Short name T724
Test name
Test status
Simulation time 144273938913 ps
CPU time 229.07 seconds
Started May 12 01:28:24 PM PDT 24
Finished May 12 01:32:14 PM PDT 24
Peak memory 200280 kb
Host smart-c2bdf4dd-ffd1-4775-ac8c-d32f5a6f6776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606366729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.606366729
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3678230794
Short name T242
Test name
Test status
Simulation time 64076464897 ps
CPU time 109.36 seconds
Started May 12 01:28:24 PM PDT 24
Finished May 12 01:30:14 PM PDT 24
Peak memory 200288 kb
Host smart-d3a78f08-66b0-4f2b-a035-43fec4662bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678230794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3678230794
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4003672469
Short name T55
Test name
Test status
Simulation time 51189208112 ps
CPU time 25.47 seconds
Started May 12 01:28:22 PM PDT 24
Finished May 12 01:28:48 PM PDT 24
Peak memory 200300 kb
Host smart-16326d7f-cd1b-4ccf-a4b2-22ac3d52dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003672469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4003672469
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.807448507
Short name T727
Test name
Test status
Simulation time 43192625 ps
CPU time 0.58 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:46 PM PDT 24
Peak memory 195720 kb
Host smart-2a42ea72-a711-4cb2-bcac-349b8ab41235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807448507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.807448507
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4292160586
Short name T892
Test name
Test status
Simulation time 94436187995 ps
CPU time 43.81 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:25:30 PM PDT 24
Peak memory 200344 kb
Host smart-e0e71497-53a0-4efc-b904-2c6f0976a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292160586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4292160586
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.176044313
Short name T1174
Test name
Test status
Simulation time 37107697273 ps
CPU time 30.06 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:25:15 PM PDT 24
Peak memory 200276 kb
Host smart-28127351-9290-453a-8eb3-7e5588d58b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176044313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.176044313
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3551084243
Short name T204
Test name
Test status
Simulation time 72593587584 ps
CPU time 62.85 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:25:49 PM PDT 24
Peak memory 200380 kb
Host smart-a1229a55-481e-4500-b2ec-95c6f6b1b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551084243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3551084243
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2602837586
Short name T21
Test name
Test status
Simulation time 63939064821 ps
CPU time 10.62 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:24:59 PM PDT 24
Peak memory 198260 kb
Host smart-50002a36-c5ae-4fb1-94e5-a157dd10d194
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602837586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2602837586
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1379184911
Short name T868
Test name
Test status
Simulation time 68085258348 ps
CPU time 300.61 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:29:47 PM PDT 24
Peak memory 200304 kb
Host smart-20aa9d93-c519-4dbd-a880-24f625db408e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379184911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1379184911
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2423398263
Short name T916
Test name
Test status
Simulation time 9612614848 ps
CPU time 5.99 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 198692 kb
Host smart-dc5bf0a2-c102-4fe2-ab27-965bb897700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423398263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2423398263
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1701184883
Short name T672
Test name
Test status
Simulation time 32790749675 ps
CPU time 73.75 seconds
Started May 12 01:24:46 PM PDT 24
Finished May 12 01:26:01 PM PDT 24
Peak memory 200580 kb
Host smart-72fa5a4b-8a9e-4b13-bd4a-e8aed47c4db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701184883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1701184883
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1386029699
Short name T1148
Test name
Test status
Simulation time 10169156719 ps
CPU time 153.37 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:27:20 PM PDT 24
Peak memory 200396 kb
Host smart-0ac20812-7d3e-404c-bbf6-ab5df948a642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386029699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1386029699
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2640399078
Short name T846
Test name
Test status
Simulation time 5264462610 ps
CPU time 9.89 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:24:56 PM PDT 24
Peak memory 199304 kb
Host smart-1e721eb3-e294-4972-84aa-29923cbe209d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640399078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2640399078
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4145208420
Short name T456
Test name
Test status
Simulation time 64768320530 ps
CPU time 31.71 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:25:18 PM PDT 24
Peak memory 200372 kb
Host smart-f2607ac1-2b3e-44e8-ba1f-cc033f3c84a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145208420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4145208420
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1054390818
Short name T1151
Test name
Test status
Simulation time 36440191873 ps
CPU time 43.6 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:25:29 PM PDT 24
Peak memory 196680 kb
Host smart-3c492098-ca75-49d9-be8e-1c1a2d5b6001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054390818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1054390818
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2490271240
Short name T493
Test name
Test status
Simulation time 11062394180 ps
CPU time 16.37 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:25:02 PM PDT 24
Peak memory 200172 kb
Host smart-2a60821e-3802-4776-ae6c-93e7b4091136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490271240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2490271240
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3145002034
Short name T796
Test name
Test status
Simulation time 190169919134 ps
CPU time 56.56 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:25:41 PM PDT 24
Peak memory 208720 kb
Host smart-2a6f2546-aac3-44c4-9beb-3d15a18386c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145002034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3145002034
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2236209334
Short name T715
Test name
Test status
Simulation time 124758269180 ps
CPU time 2186.4 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 02:01:11 PM PDT 24
Peak memory 230284 kb
Host smart-6c0b2fbe-3729-4999-b121-ff5668d23e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236209334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2236209334
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.304525630
Short name T692
Test name
Test status
Simulation time 1940513850 ps
CPU time 2.49 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:48 PM PDT 24
Peak memory 199008 kb
Host smart-2f87c50d-96e1-42ad-b49e-eb5c674a45f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304525630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.304525630
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4165282629
Short name T1032
Test name
Test status
Simulation time 7444299467 ps
CPU time 7.73 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:24:56 PM PDT 24
Peak memory 200264 kb
Host smart-b2b5a71d-cf24-4182-804f-9f779a07e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165282629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4165282629
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1027569759
Short name T160
Test name
Test status
Simulation time 42189681391 ps
CPU time 58.13 seconds
Started May 12 01:28:22 PM PDT 24
Finished May 12 01:29:20 PM PDT 24
Peak memory 200340 kb
Host smart-672abfc9-d868-4b2f-b984-846c0740739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027569759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1027569759
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2493643399
Short name T930
Test name
Test status
Simulation time 26927329692 ps
CPU time 20.62 seconds
Started May 12 01:28:23 PM PDT 24
Finished May 12 01:28:44 PM PDT 24
Peak memory 200420 kb
Host smart-0d0a6c4d-ab8c-41c6-804b-82d7e553e9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493643399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2493643399
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3938380999
Short name T559
Test name
Test status
Simulation time 34786184102 ps
CPU time 47.61 seconds
Started May 12 01:28:27 PM PDT 24
Finished May 12 01:29:15 PM PDT 24
Peak memory 200324 kb
Host smart-52508c3a-b436-4a3b-bb91-0be359917fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938380999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3938380999
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.44463417
Short name T236
Test name
Test status
Simulation time 12407596300 ps
CPU time 20.77 seconds
Started May 12 01:28:27 PM PDT 24
Finished May 12 01:28:48 PM PDT 24
Peak memory 200372 kb
Host smart-08e01b1a-6fec-40fd-abc1-15cef2f42a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44463417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.44463417
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.396850977
Short name T480
Test name
Test status
Simulation time 126119925973 ps
CPU time 147.15 seconds
Started May 12 01:28:26 PM PDT 24
Finished May 12 01:30:53 PM PDT 24
Peak memory 200432 kb
Host smart-84fa1715-962f-4458-a89b-2801edf60f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396850977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.396850977
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1139181264
Short name T102
Test name
Test status
Simulation time 13946093109 ps
CPU time 28.32 seconds
Started May 12 01:28:27 PM PDT 24
Finished May 12 01:28:55 PM PDT 24
Peak memory 200348 kb
Host smart-9d8ebf7e-e623-4e0a-bba2-ee57627d7d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139181264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1139181264
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1302017172
Short name T538
Test name
Test status
Simulation time 155329583100 ps
CPU time 73.28 seconds
Started May 12 01:28:27 PM PDT 24
Finished May 12 01:29:40 PM PDT 24
Peak memory 200284 kb
Host smart-ec6c5a4b-66d8-4aa0-bdfe-4bcdd1f48b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302017172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1302017172
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.104346854
Short name T430
Test name
Test status
Simulation time 33206391989 ps
CPU time 15.6 seconds
Started May 12 01:28:27 PM PDT 24
Finished May 12 01:28:43 PM PDT 24
Peak memory 200364 kb
Host smart-62e37d94-60ae-4114-9a52-306ad907a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104346854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.104346854
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1830639573
Short name T757
Test name
Test status
Simulation time 201927476455 ps
CPU time 16.92 seconds
Started May 12 01:28:27 PM PDT 24
Finished May 12 01:28:44 PM PDT 24
Peak memory 200176 kb
Host smart-9aafc452-1fc2-4ea7-8e3f-6b38aa7894f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830639573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1830639573
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.149099361
Short name T455
Test name
Test status
Simulation time 46742221 ps
CPU time 0.58 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:24:54 PM PDT 24
Peak memory 195784 kb
Host smart-0575392c-adde-4f2a-bc4e-96c6312452a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149099361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.149099361
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2448094516
Short name T620
Test name
Test status
Simulation time 64990924687 ps
CPU time 51.88 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:25:38 PM PDT 24
Peak memory 200316 kb
Host smart-3217dbe1-23d2-4510-b501-f9eda22d2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448094516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2448094516
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_intr.1462129489
Short name T750
Test name
Test status
Simulation time 59491711381 ps
CPU time 51.97 seconds
Started May 12 01:24:46 PM PDT 24
Finished May 12 01:25:39 PM PDT 24
Peak memory 199532 kb
Host smart-a3ad0427-91bc-40da-9772-46368eda0d41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462129489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1462129489
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3562960434
Short name T610
Test name
Test status
Simulation time 72394346832 ps
CPU time 138.22 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:27:04 PM PDT 24
Peak memory 200432 kb
Host smart-16f0a0d0-68d0-4d91-a0ba-4322007aaedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562960434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3562960434
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3939059016
Short name T777
Test name
Test status
Simulation time 3788838301 ps
CPU time 4.63 seconds
Started May 12 01:24:46 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 199616 kb
Host smart-c3b780e0-84b2-4754-9b65-55c05c283fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939059016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3939059016
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.4099755400
Short name T884
Test name
Test status
Simulation time 95094126020 ps
CPU time 43.87 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:25:27 PM PDT 24
Peak memory 200536 kb
Host smart-8028e17b-5947-4786-85ab-d21e6cb325b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099755400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4099755400
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3912196889
Short name T710
Test name
Test status
Simulation time 10156500495 ps
CPU time 489.99 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 200260 kb
Host smart-e54c6040-7743-4432-9885-0d85e0755e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912196889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3912196889
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1466240928
Short name T690
Test name
Test status
Simulation time 5656136139 ps
CPU time 27.24 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:25:12 PM PDT 24
Peak memory 198532 kb
Host smart-dcf56e27-1e2e-4e43-b8dc-8b863e802b9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466240928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1466240928
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1456696144
Short name T922
Test name
Test status
Simulation time 13091128105 ps
CPU time 24.24 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:25:10 PM PDT 24
Peak memory 200324 kb
Host smart-b112d92e-b970-4192-993c-b797efb713f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456696144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1456696144
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1362426006
Short name T473
Test name
Test status
Simulation time 2492165408 ps
CPU time 4.24 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:24:50 PM PDT 24
Peak memory 196344 kb
Host smart-153ab9d4-cfdb-4891-b8e0-2eb567d360a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362426006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1362426006
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2922956508
Short name T290
Test name
Test status
Simulation time 288805141 ps
CPU time 0.96 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:24:47 PM PDT 24
Peak memory 198136 kb
Host smart-a1d0ddea-2b05-4c4e-b93b-6b02972ee21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922956508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2922956508
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.523696294
Short name T708
Test name
Test status
Simulation time 228851884903 ps
CPU time 356.94 seconds
Started May 12 01:24:50 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 200376 kb
Host smart-c9c820d0-4aa8-48dc-a4db-4886789521c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523696294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.523696294
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2674777182
Short name T1083
Test name
Test status
Simulation time 234443338919 ps
CPU time 469.31 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 208852 kb
Host smart-d02e705d-9c3b-48c6-ba8d-057f536467bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674777182 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2674777182
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2943245049
Short name T504
Test name
Test status
Simulation time 747608981 ps
CPU time 1.59 seconds
Started May 12 01:24:47 PM PDT 24
Finished May 12 01:24:50 PM PDT 24
Peak memory 199444 kb
Host smart-14d09ed5-e9b9-4bc0-b759-0b41781e0c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943245049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2943245049
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2608940771
Short name T498
Test name
Test status
Simulation time 166464576318 ps
CPU time 83.99 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:26:09 PM PDT 24
Peak memory 200360 kb
Host smart-ecfa0a96-468a-4c26-a321-c433f845d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608940771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2608940771
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.212428162
Short name T1006
Test name
Test status
Simulation time 19085937409 ps
CPU time 6.71 seconds
Started May 12 01:28:26 PM PDT 24
Finished May 12 01:28:33 PM PDT 24
Peak memory 200432 kb
Host smart-645bbb8a-10bc-4c74-b1da-13446b375969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212428162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.212428162
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2639743537
Short name T836
Test name
Test status
Simulation time 96437774526 ps
CPU time 158.52 seconds
Started May 12 01:28:28 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 200352 kb
Host smart-5a68096e-3453-488c-b498-51558fcfd745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639743537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2639743537
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3297234379
Short name T201
Test name
Test status
Simulation time 44601374333 ps
CPU time 40.68 seconds
Started May 12 01:28:26 PM PDT 24
Finished May 12 01:29:07 PM PDT 24
Peak memory 200340 kb
Host smart-d9f28a5f-cf49-4682-9a1d-a4d204ec72b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297234379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3297234379
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2568148950
Short name T101
Test name
Test status
Simulation time 7096886112 ps
CPU time 12.7 seconds
Started May 12 01:28:26 PM PDT 24
Finished May 12 01:28:38 PM PDT 24
Peak memory 200384 kb
Host smart-e05742b8-5b9a-42d8-b523-24d368559deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568148950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2568148950
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3817896215
Short name T336
Test name
Test status
Simulation time 139392999228 ps
CPU time 76.97 seconds
Started May 12 01:28:29 PM PDT 24
Finished May 12 01:29:46 PM PDT 24
Peak memory 200384 kb
Host smart-9ca35f62-2017-4d92-80f9-0fa1882bb34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817896215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3817896215
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1093377969
Short name T1078
Test name
Test status
Simulation time 72605646744 ps
CPU time 58.63 seconds
Started May 12 01:28:30 PM PDT 24
Finished May 12 01:29:29 PM PDT 24
Peak memory 199744 kb
Host smart-c46db43f-3d6c-46fa-90f0-9d8474a35e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093377969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1093377969
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2381166754
Short name T793
Test name
Test status
Simulation time 125785807753 ps
CPU time 242.5 seconds
Started May 12 01:28:30 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 200352 kb
Host smart-70052a58-7f29-4497-9ab0-796da7127057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381166754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2381166754
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1495660209
Short name T784
Test name
Test status
Simulation time 223302421910 ps
CPU time 44.07 seconds
Started May 12 01:28:29 PM PDT 24
Finished May 12 01:29:14 PM PDT 24
Peak memory 200404 kb
Host smart-91e09924-548d-49ef-94f8-d510761e5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495660209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1495660209
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1709162988
Short name T340
Test name
Test status
Simulation time 40996404 ps
CPU time 0.53 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:24:49 PM PDT 24
Peak memory 195140 kb
Host smart-709d3e80-ba99-41de-85e8-47a792a19f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709162988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1709162988
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.387700214
Short name T664
Test name
Test status
Simulation time 22237577008 ps
CPU time 23.37 seconds
Started May 12 01:24:50 PM PDT 24
Finished May 12 01:25:14 PM PDT 24
Peak memory 200420 kb
Host smart-76307553-36dd-47d1-a1ca-f050426d164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387700214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.387700214
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4219916022
Short name T1056
Test name
Test status
Simulation time 40795413624 ps
CPU time 17.66 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:25:07 PM PDT 24
Peak memory 200284 kb
Host smart-917b5b8c-4577-4d7d-b22b-07c422bb1110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219916022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4219916022
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.4061116508
Short name T5
Test name
Test status
Simulation time 12399167791 ps
CPU time 27.75 seconds
Started May 12 01:24:50 PM PDT 24
Finished May 12 01:25:19 PM PDT 24
Peak memory 200000 kb
Host smart-d0a09086-d40c-49f4-9ac9-4f1faaa3e679
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061116508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4061116508
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1996911008
Short name T471
Test name
Test status
Simulation time 139826017514 ps
CPU time 1068.59 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:42:38 PM PDT 24
Peak memory 200364 kb
Host smart-0085c890-20ae-40c0-a5f2-8cc170c2fa56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996911008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1996911008
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.647338867
Short name T338
Test name
Test status
Simulation time 1523520721 ps
CPU time 1.4 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:24:51 PM PDT 24
Peak memory 198348 kb
Host smart-91b4e96a-490e-43df-a8eb-60886ad46ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647338867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.647338867
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2295899323
Short name T383
Test name
Test status
Simulation time 42636841812 ps
CPU time 6.86 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:24:57 PM PDT 24
Peak memory 195032 kb
Host smart-1f38c905-6904-45fe-9f61-ef0f29ab5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295899323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2295899323
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1293519743
Short name T351
Test name
Test status
Simulation time 24072336429 ps
CPU time 363.39 seconds
Started May 12 01:24:53 PM PDT 24
Finished May 12 01:30:57 PM PDT 24
Peak memory 200356 kb
Host smart-fd646ed2-f9fc-4537-9e3f-67bc211cbc99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293519743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1293519743
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.716262985
Short name T1074
Test name
Test status
Simulation time 2609794409 ps
CPU time 15.5 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:25:06 PM PDT 24
Peak memory 198692 kb
Host smart-82f97790-1f19-4cbd-af0c-227fd5015d2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716262985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.716262985
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2557937601
Short name T416
Test name
Test status
Simulation time 119489272493 ps
CPU time 182.42 seconds
Started May 12 01:24:50 PM PDT 24
Finished May 12 01:27:53 PM PDT 24
Peak memory 200344 kb
Host smart-d5bc0b7d-635d-47b1-895b-a55507fffa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557937601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2557937601
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_smoke.575751385
Short name T508
Test name
Test status
Simulation time 653416536 ps
CPU time 1.58 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:24:50 PM PDT 24
Peak memory 199076 kb
Host smart-b7c35f0a-9fdd-4b5f-95f4-0808a9481ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575751385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.575751385
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4269385784
Short name T974
Test name
Test status
Simulation time 10841695969 ps
CPU time 170.58 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:27:41 PM PDT 24
Peak memory 216080 kb
Host smart-2b14d26a-7f40-4b9c-956b-1de3a1d3c84e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269385784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4269385784
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.276065044
Short name T1168
Test name
Test status
Simulation time 7355182429 ps
CPU time 8.69 seconds
Started May 12 01:24:48 PM PDT 24
Finished May 12 01:24:58 PM PDT 24
Peak memory 200384 kb
Host smart-05331f7f-6be7-4e1b-855b-07b7b2c46496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276065044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.276065044
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2107759040
Short name T301
Test name
Test status
Simulation time 41195714811 ps
CPU time 15.83 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:25:05 PM PDT 24
Peak memory 200400 kb
Host smart-f2cbbe60-c9d5-44c2-a36a-9f13449bb3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107759040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2107759040
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.492001036
Short name T593
Test name
Test status
Simulation time 77948606490 ps
CPU time 11.78 seconds
Started May 12 01:28:34 PM PDT 24
Finished May 12 01:28:47 PM PDT 24
Peak memory 199936 kb
Host smart-6c027e20-0b10-49f9-a75c-ce0d88b28312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492001036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.492001036
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3401959719
Short name T653
Test name
Test status
Simulation time 189562280423 ps
CPU time 86.82 seconds
Started May 12 01:28:32 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 200420 kb
Host smart-d9741f2a-6b5e-4d1d-bfb7-ca98e2c13e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401959719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3401959719
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3129103439
Short name T524
Test name
Test status
Simulation time 151827149735 ps
CPU time 264.87 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:33:05 PM PDT 24
Peak memory 200220 kb
Host smart-bad94961-9209-48ed-90ec-38b7f5a7f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129103439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3129103439
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1460003690
Short name T543
Test name
Test status
Simulation time 222355460278 ps
CPU time 418.8 seconds
Started May 12 01:28:33 PM PDT 24
Finished May 12 01:35:32 PM PDT 24
Peak memory 200424 kb
Host smart-4ac0727b-abc2-4870-a393-b31c9a2986dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460003690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1460003690
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.929423765
Short name T1181
Test name
Test status
Simulation time 57202995158 ps
CPU time 74.86 seconds
Started May 12 01:28:34 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 200124 kb
Host smart-8d8a4759-0f31-4a83-820d-55c13ec6c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929423765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.929423765
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1397485446
Short name T652
Test name
Test status
Simulation time 23993226723 ps
CPU time 10.87 seconds
Started May 12 01:28:33 PM PDT 24
Finished May 12 01:28:44 PM PDT 24
Peak memory 200384 kb
Host smart-ec020e8d-6f51-422f-b943-026407967b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397485446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1397485446
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3942115285
Short name T677
Test name
Test status
Simulation time 57818388153 ps
CPU time 90.21 seconds
Started May 12 01:28:35 PM PDT 24
Finished May 12 01:30:06 PM PDT 24
Peak memory 200380 kb
Host smart-dee19304-4fac-43b2-b978-bb8eb039c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942115285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3942115285
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.214600997
Short name T280
Test name
Test status
Simulation time 40031648886 ps
CPU time 90.13 seconds
Started May 12 01:28:31 PM PDT 24
Finished May 12 01:30:02 PM PDT 24
Peak memory 200372 kb
Host smart-f0dd9420-0468-4d81-b39d-53444f2670cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214600997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.214600997
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2271156349
Short name T1060
Test name
Test status
Simulation time 26394293963 ps
CPU time 36.91 seconds
Started May 12 01:28:32 PM PDT 24
Finished May 12 01:29:09 PM PDT 24
Peak memory 200368 kb
Host smart-7a5f9b38-eb0f-4aec-ab30-f4016be446b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271156349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2271156349
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3016021991
Short name T866
Test name
Test status
Simulation time 77438470995 ps
CPU time 122.13 seconds
Started May 12 01:28:35 PM PDT 24
Finished May 12 01:30:38 PM PDT 24
Peak memory 200408 kb
Host smart-7687e574-2843-4216-aff5-4d8b9eb37d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016021991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3016021991
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2486830647
Short name T484
Test name
Test status
Simulation time 15117579 ps
CPU time 0.58 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:24:53 PM PDT 24
Peak memory 195688 kb
Host smart-52c02081-756b-4095-9504-e8b95040d21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486830647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2486830647
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.366600806
Short name T895
Test name
Test status
Simulation time 36367661392 ps
CPU time 61.52 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:25:57 PM PDT 24
Peak memory 200328 kb
Host smart-12b15a5d-f26c-4643-96c8-5da7e1373a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366600806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.366600806
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1344303449
Short name T1004
Test name
Test status
Simulation time 47592318450 ps
CPU time 102.02 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:26:35 PM PDT 24
Peak memory 200368 kb
Host smart-9d6ad3c1-5d61-42e3-afa3-c39cb2280472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344303449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1344303449
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3311787239
Short name T1129
Test name
Test status
Simulation time 49268346494 ps
CPU time 36.67 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:25:31 PM PDT 24
Peak memory 200260 kb
Host smart-3c153cf3-f747-4453-8c0c-045a522218d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311787239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3311787239
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1896970304
Short name T983
Test name
Test status
Simulation time 26132640147 ps
CPU time 10.24 seconds
Started May 12 01:24:53 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 198292 kb
Host smart-d62c4c14-c780-4931-901f-945d01cc8197
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896970304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1896970304
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3883486480
Short name T120
Test name
Test status
Simulation time 113397452584 ps
CPU time 1083.85 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:42:58 PM PDT 24
Peak memory 200240 kb
Host smart-c78a0e89-705b-4569-80b3-fb2585a4f45e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883486480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3883486480
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.693820218
Short name T1118
Test name
Test status
Simulation time 9389710554 ps
CPU time 16.86 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:25:10 PM PDT 24
Peak memory 200400 kb
Host smart-092fc744-4480-40fb-b945-e80c127dcfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693820218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.693820218
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1349231119
Short name T574
Test name
Test status
Simulation time 109687485400 ps
CPU time 72.64 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:26:09 PM PDT 24
Peak memory 200512 kb
Host smart-24d838aa-c688-4292-99af-856c22ece16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349231119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1349231119
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1489240649
Short name T1030
Test name
Test status
Simulation time 15325646802 ps
CPU time 57.16 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:25:52 PM PDT 24
Peak memory 200296 kb
Host smart-eee50293-27c7-4bf2-b6fb-30960f2797f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489240649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1489240649
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2500658650
Short name T397
Test name
Test status
Simulation time 2832463648 ps
CPU time 9.71 seconds
Started May 12 01:24:51 PM PDT 24
Finished May 12 01:25:01 PM PDT 24
Peak memory 198588 kb
Host smart-cbdb7375-f213-4729-92ea-5c11f302a0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500658650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2500658650
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1952635423
Short name T888
Test name
Test status
Simulation time 86835785415 ps
CPU time 94.9 seconds
Started May 12 01:24:55 PM PDT 24
Finished May 12 01:26:30 PM PDT 24
Peak memory 200272 kb
Host smart-3f15f51f-3784-4fea-8cce-242cec4849f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952635423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1952635423
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.812102899
Short name T130
Test name
Test status
Simulation time 4247973303 ps
CPU time 8.05 seconds
Started May 12 01:24:53 PM PDT 24
Finished May 12 01:25:01 PM PDT 24
Peak memory 196652 kb
Host smart-ddc550b7-f85b-492b-beda-d71b0f74e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812102899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.812102899
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3055550133
Short name T437
Test name
Test status
Simulation time 552087773 ps
CPU time 2.28 seconds
Started May 12 01:24:49 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 200280 kb
Host smart-b3ad8e65-df59-424c-81fb-2deefd936203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055550133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3055550133
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1607875244
Short name T977
Test name
Test status
Simulation time 36624996433 ps
CPU time 94.39 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:26:28 PM PDT 24
Peak memory 200320 kb
Host smart-437f8922-8090-462e-b61c-68d7f908e1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607875244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1607875244
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2836010988
Short name T69
Test name
Test status
Simulation time 112234331816 ps
CPU time 902.61 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:39:57 PM PDT 24
Peak memory 225276 kb
Host smart-bf6d29d9-1bc3-4cf8-a574-a2c601717f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836010988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2836010988
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1841986388
Short name T673
Test name
Test status
Simulation time 1145988891 ps
CPU time 3.76 seconds
Started May 12 01:24:55 PM PDT 24
Finished May 12 01:24:59 PM PDT 24
Peak memory 199416 kb
Host smart-369143e6-3587-4eec-875a-ba7cf0395c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841986388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1841986388
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3205653006
Short name T618
Test name
Test status
Simulation time 66946730881 ps
CPU time 39.33 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 200372 kb
Host smart-bafadd09-f56b-4e0b-8f53-15b649c65fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205653006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3205653006
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1476361511
Short name T821
Test name
Test status
Simulation time 161506567125 ps
CPU time 287.02 seconds
Started May 12 01:28:37 PM PDT 24
Finished May 12 01:33:24 PM PDT 24
Peak memory 200384 kb
Host smart-685cdb82-bf82-4882-ba34-a9fc8b2c4253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476361511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1476361511
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.4175977954
Short name T254
Test name
Test status
Simulation time 126446158843 ps
CPU time 153.63 seconds
Started May 12 01:28:37 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 200384 kb
Host smart-3e626c51-cb7a-4ed8-a0ca-21f9c48d4dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175977954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4175977954
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.218966717
Short name T955
Test name
Test status
Simulation time 9056613506 ps
CPU time 17.05 seconds
Started May 12 01:28:35 PM PDT 24
Finished May 12 01:28:52 PM PDT 24
Peak memory 200396 kb
Host smart-9d731264-27b4-471b-bfb5-9dbeac0cf8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218966717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.218966717
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2969566955
Short name T1169
Test name
Test status
Simulation time 42871057692 ps
CPU time 24.42 seconds
Started May 12 01:28:36 PM PDT 24
Finished May 12 01:29:01 PM PDT 24
Peak memory 200376 kb
Host smart-e0dbb8e7-ced7-4505-872c-360318619cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969566955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2969566955
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1454486530
Short name T198
Test name
Test status
Simulation time 124119873363 ps
CPU time 93.09 seconds
Started May 12 01:28:37 PM PDT 24
Finished May 12 01:30:10 PM PDT 24
Peak memory 200328 kb
Host smart-7e457140-a657-4249-90b9-3666bbf2bedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454486530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1454486530
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.937886660
Short name T215
Test name
Test status
Simulation time 18659418708 ps
CPU time 58.08 seconds
Started May 12 01:28:35 PM PDT 24
Finished May 12 01:29:34 PM PDT 24
Peak memory 200348 kb
Host smart-ea01f174-9839-4ece-b909-f3c3b97f7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937886660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.937886660
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.315672623
Short name T436
Test name
Test status
Simulation time 41754814150 ps
CPU time 15.83 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200380 kb
Host smart-459ac293-928f-4263-b904-5b58a8c65cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315672623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.315672623
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4253891174
Short name T729
Test name
Test status
Simulation time 91998918681 ps
CPU time 130.24 seconds
Started May 12 01:28:37 PM PDT 24
Finished May 12 01:30:47 PM PDT 24
Peak memory 200360 kb
Host smart-1b614b91-cdbc-4a33-9422-95df2b74a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253891174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4253891174
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2857410254
Short name T389
Test name
Test status
Simulation time 20929634 ps
CPU time 0.54 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:24:57 PM PDT 24
Peak memory 195760 kb
Host smart-98a604f7-b082-420c-857a-c97b303d5d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857410254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2857410254
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.615962467
Short name T645
Test name
Test status
Simulation time 46719187798 ps
CPU time 38.33 seconds
Started May 12 01:24:54 PM PDT 24
Finished May 12 01:25:33 PM PDT 24
Peak memory 200316 kb
Host smart-89256b7f-9afa-488c-adbd-5923e18d1eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615962467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.615962467
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.171119928
Short name T210
Test name
Test status
Simulation time 32347523930 ps
CPU time 52.29 seconds
Started May 12 01:24:55 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 200348 kb
Host smart-946a0032-c3ca-4266-9c8a-54411ae84c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171119928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.171119928
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1627938112
Short name T1130
Test name
Test status
Simulation time 313238415167 ps
CPU time 553.02 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:34:06 PM PDT 24
Peak memory 200200 kb
Host smart-4b70e57f-02b1-41cb-856e-92bd85dbe46b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627938112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1627938112
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2391296741
Short name T960
Test name
Test status
Simulation time 87062637401 ps
CPU time 669.74 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:36:12 PM PDT 24
Peak memory 200436 kb
Host smart-52252e30-e39b-4f38-bd0c-adef40f8c621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391296741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2391296741
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3724360768
Short name T339
Test name
Test status
Simulation time 2739401492 ps
CPU time 5.14 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:25:07 PM PDT 24
Peak memory 200312 kb
Host smart-075e20df-977d-4603-b415-fe00cfba1593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724360768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3724360768
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1843919209
Short name T630
Test name
Test status
Simulation time 168050523653 ps
CPU time 77.43 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:26:20 PM PDT 24
Peak memory 208324 kb
Host smart-5fbb972f-f67e-4309-9582-d09d72558a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843919209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1843919209
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3713502621
Short name T1120
Test name
Test status
Simulation time 41258591288 ps
CPU time 136.06 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:27:13 PM PDT 24
Peak memory 200376 kb
Host smart-c61d5fb4-34c6-4634-b850-4eb7fac48c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713502621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3713502621
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3633673548
Short name T367
Test name
Test status
Simulation time 5808163561 ps
CPU time 12.94 seconds
Started May 12 01:24:52 PM PDT 24
Finished May 12 01:25:05 PM PDT 24
Peak memory 199156 kb
Host smart-d4cfb868-ccad-4df0-915a-bb9d3337a1c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633673548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3633673548
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4199444707
Short name T704
Test name
Test status
Simulation time 67986941690 ps
CPU time 107.73 seconds
Started May 12 01:24:55 PM PDT 24
Finished May 12 01:26:43 PM PDT 24
Peak memory 200132 kb
Host smart-1cd32966-231a-4aec-a1ee-607e5b64348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199444707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4199444707
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3056015399
Short name T646
Test name
Test status
Simulation time 35240793517 ps
CPU time 55.15 seconds
Started May 12 01:24:57 PM PDT 24
Finished May 12 01:25:53 PM PDT 24
Peak memory 196344 kb
Host smart-cd16068c-502e-41ff-b4bf-e0abbe215590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056015399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3056015399
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1213949595
Short name T8
Test name
Test status
Simulation time 6305443187 ps
CPU time 8.85 seconds
Started May 12 01:24:55 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 200292 kb
Host smart-38842c0c-8552-4dcd-ba10-f9a383021a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213949595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1213949595
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1473347078
Short name T853
Test name
Test status
Simulation time 817194366802 ps
CPU time 109.4 seconds
Started May 12 01:25:07 PM PDT 24
Finished May 12 01:26:57 PM PDT 24
Peak memory 208800 kb
Host smart-bcbcf9c9-4827-4ae6-9360-ae8408f916bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473347078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1473347078
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1787656873
Short name T322
Test name
Test status
Simulation time 5542854787 ps
CPU time 62.91 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:26:00 PM PDT 24
Peak memory 216984 kb
Host smart-e9c7ac47-2158-4c84-88d6-0b831df35a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787656873 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1787656873
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3858522010
Short name T476
Test name
Test status
Simulation time 676652556 ps
CPU time 2.63 seconds
Started May 12 01:24:57 PM PDT 24
Finished May 12 01:25:00 PM PDT 24
Peak memory 198592 kb
Host smart-645ee3be-57e4-4dc0-802c-54864e5ef297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858522010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3858522010
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.315542873
Short name T450
Test name
Test status
Simulation time 85689933121 ps
CPU time 43.71 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 200376 kb
Host smart-0ba4e27b-fde6-4d26-ad9b-dab7fb525061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315542873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.315542873
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4254113519
Short name T245
Test name
Test status
Simulation time 98101764467 ps
CPU time 297.84 seconds
Started May 12 01:28:37 PM PDT 24
Finished May 12 01:33:35 PM PDT 24
Peak memory 200448 kb
Host smart-3ee928db-7e52-4bde-95d2-740e609facea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254113519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4254113519
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2928197166
Short name T774
Test name
Test status
Simulation time 19961415936 ps
CPU time 29.84 seconds
Started May 12 01:28:39 PM PDT 24
Finished May 12 01:29:10 PM PDT 24
Peak memory 200500 kb
Host smart-4fa99d80-a62f-41c5-b703-9d42d4b09f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928197166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2928197166
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.463859925
Short name T193
Test name
Test status
Simulation time 55068601766 ps
CPU time 21.87 seconds
Started May 12 01:28:39 PM PDT 24
Finished May 12 01:29:02 PM PDT 24
Peak memory 200328 kb
Host smart-fa6a5fe2-e209-4143-8d3a-ea9ec51bd601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463859925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.463859925
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.56831110
Short name T707
Test name
Test status
Simulation time 42236121236 ps
CPU time 65.61 seconds
Started May 12 01:28:43 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 200340 kb
Host smart-c6a05d51-fd83-4f91-b8bc-4ea8bb3a8b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56831110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.56831110
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.4105746179
Short name T963
Test name
Test status
Simulation time 81862830674 ps
CPU time 126.74 seconds
Started May 12 01:28:38 PM PDT 24
Finished May 12 01:30:45 PM PDT 24
Peak memory 200328 kb
Host smart-2d2590bb-007e-4419-a477-479585496044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105746179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4105746179
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.79051362
Short name T832
Test name
Test status
Simulation time 149131698580 ps
CPU time 108.71 seconds
Started May 12 01:28:39 PM PDT 24
Finished May 12 01:30:28 PM PDT 24
Peak memory 200304 kb
Host smart-aa55e63d-4d59-4e2d-86d8-d1b3927c6232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79051362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.79051362
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.243359444
Short name T479
Test name
Test status
Simulation time 4012884628 ps
CPU time 6.9 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:28:48 PM PDT 24
Peak memory 200388 kb
Host smart-d2e83309-ce89-4e83-a478-aa8ea0848b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243359444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.243359444
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2366275370
Short name T33
Test name
Test status
Simulation time 58154598 ps
CPU time 0.58 seconds
Started May 12 01:25:00 PM PDT 24
Finished May 12 01:25:01 PM PDT 24
Peak memory 195740 kb
Host smart-de298cac-2e93-4c24-83b7-0b0cac19f6aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366275370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2366275370
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2300708926
Short name T1175
Test name
Test status
Simulation time 168095889422 ps
CPU time 35.69 seconds
Started May 12 01:24:57 PM PDT 24
Finished May 12 01:25:33 PM PDT 24
Peak memory 200404 kb
Host smart-873afafb-41ea-4048-801d-e93bb29f470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300708926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2300708926
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3268039959
Short name T446
Test name
Test status
Simulation time 14466726257 ps
CPU time 22.51 seconds
Started May 12 01:25:06 PM PDT 24
Finished May 12 01:25:29 PM PDT 24
Peak memory 200400 kb
Host smart-ded34e93-986c-4558-ac84-3f423bd9862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268039959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3268039959
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1823022456
Short name T53
Test name
Test status
Simulation time 34101714591 ps
CPU time 17.45 seconds
Started May 12 01:25:06 PM PDT 24
Finished May 12 01:25:24 PM PDT 24
Peak memory 200424 kb
Host smart-4e7e7d7b-9da0-4d2e-91f1-b9cd749f5f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823022456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1823022456
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.194627003
Short name T463
Test name
Test status
Simulation time 7797426306 ps
CPU time 1.69 seconds
Started May 12 01:24:58 PM PDT 24
Finished May 12 01:25:00 PM PDT 24
Peak memory 197180 kb
Host smart-e43d8d5b-aacb-45a7-9b80-e3d74e01aef0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194627003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.194627003
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2291907422
Short name T443
Test name
Test status
Simulation time 116343289707 ps
CPU time 691.86 seconds
Started May 12 01:25:06 PM PDT 24
Finished May 12 01:36:38 PM PDT 24
Peak memory 200408 kb
Host smart-19d19411-9be1-441b-a432-53a966894e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291907422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2291907422
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1298395221
Short name T872
Test name
Test status
Simulation time 1613881004 ps
CPU time 2.29 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 199244 kb
Host smart-1d53114f-626b-41dd-b741-5a8f3706af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298395221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1298395221
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.249486752
Short name T906
Test name
Test status
Simulation time 70047277570 ps
CPU time 31.81 seconds
Started May 12 01:25:07 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 200596 kb
Host smart-003c5b24-2004-45f9-ab1b-3b251e3357fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249486752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.249486752
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3770892931
Short name T923
Test name
Test status
Simulation time 14499557415 ps
CPU time 41.29 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:25:44 PM PDT 24
Peak memory 200348 kb
Host smart-6ecbc25d-20ad-4d68-af38-edde14214c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770892931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3770892931
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1134355002
Short name T384
Test name
Test status
Simulation time 6124461662 ps
CPU time 6.53 seconds
Started May 12 01:24:57 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 200308 kb
Host smart-c7fe4b22-013a-43e4-a073-b30a6171668c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134355002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1134355002
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.575609702
Short name T1145
Test name
Test status
Simulation time 148002637642 ps
CPU time 76.31 seconds
Started May 12 01:25:07 PM PDT 24
Finished May 12 01:26:24 PM PDT 24
Peak memory 200384 kb
Host smart-79341fda-de55-4737-aec6-a2689315424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575609702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.575609702
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.444812068
Short name T627
Test name
Test status
Simulation time 1919470334 ps
CPU time 1.5 seconds
Started May 12 01:25:02 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 195720 kb
Host smart-a8d31849-98f3-42cc-afb0-b730377614d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444812068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.444812068
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.757242728
Short name T360
Test name
Test status
Simulation time 618455941 ps
CPU time 0.84 seconds
Started May 12 01:24:56 PM PDT 24
Finished May 12 01:24:58 PM PDT 24
Peak memory 198720 kb
Host smart-90ba5aaf-12ff-40ae-a2f5-506dc3eae020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757242728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.757242728
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.282914119
Short name T560
Test name
Test status
Simulation time 305679682841 ps
CPU time 739.06 seconds
Started May 12 01:25:02 PM PDT 24
Finished May 12 01:37:22 PM PDT 24
Peak memory 216064 kb
Host smart-d382dede-fd9f-4c29-8db7-0bf998d5ac76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282914119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.282914119
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3154386921
Short name T20
Test name
Test status
Simulation time 33803981765 ps
CPU time 401.47 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:31:44 PM PDT 24
Peak memory 216472 kb
Host smart-78f4bcc4-5113-4622-8724-181ff5565fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154386921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3154386921
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.494989947
Short name T304
Test name
Test status
Simulation time 5809912613 ps
CPU time 3.05 seconds
Started May 12 01:25:00 PM PDT 24
Finished May 12 01:25:04 PM PDT 24
Peak memory 200064 kb
Host smart-862d4844-ec31-4e28-8853-3d8cfb691584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494989947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.494989947
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1032099654
Short name T1176
Test name
Test status
Simulation time 70523886264 ps
CPU time 119.95 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:27:02 PM PDT 24
Peak memory 200404 kb
Host smart-a978795a-ec58-4ba3-a517-7f4b3cb4fa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032099654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1032099654
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.844039117
Short name T237
Test name
Test status
Simulation time 49060711720 ps
CPU time 20.46 seconds
Started May 12 01:28:40 PM PDT 24
Finished May 12 01:29:01 PM PDT 24
Peak memory 200372 kb
Host smart-a6f3433e-3ca6-4732-aa9b-9036549c18c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844039117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.844039117
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2276558851
Short name T951
Test name
Test status
Simulation time 75299847558 ps
CPU time 44.16 seconds
Started May 12 01:28:38 PM PDT 24
Finished May 12 01:29:23 PM PDT 24
Peak memory 200244 kb
Host smart-32be3c76-2a72-404c-82d2-7b4c4f36e1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276558851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2276558851
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1122802013
Short name T214
Test name
Test status
Simulation time 18890654245 ps
CPU time 31.74 seconds
Started May 12 01:28:39 PM PDT 24
Finished May 12 01:29:11 PM PDT 24
Peak memory 200340 kb
Host smart-4255fa3c-6128-4089-b4e7-9172826d5d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122802013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1122802013
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3760897839
Short name T253
Test name
Test status
Simulation time 129188825672 ps
CPU time 235.62 seconds
Started May 12 01:28:42 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 200340 kb
Host smart-ba72e3e1-c911-4bbe-a70e-af68734da74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760897839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3760897839
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1524440882
Short name T1135
Test name
Test status
Simulation time 49941673638 ps
CPU time 76.92 seconds
Started May 12 01:28:46 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 200388 kb
Host smart-47a1e521-4835-4d7f-8a47-dc5f29eb5496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524440882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1524440882
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3040501984
Short name T966
Test name
Test status
Simulation time 62623193477 ps
CPU time 30.11 seconds
Started May 12 01:28:43 PM PDT 24
Finished May 12 01:29:14 PM PDT 24
Peak memory 200328 kb
Host smart-cc16bf47-71a2-4424-bf7e-5343f27c7d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040501984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3040501984
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2306952030
Short name T1023
Test name
Test status
Simulation time 10581934434 ps
CPU time 14.73 seconds
Started May 12 01:28:41 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200404 kb
Host smart-928af3c1-db95-4710-ba48-923b62efaa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306952030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2306952030
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2713577128
Short name T1161
Test name
Test status
Simulation time 20240540 ps
CPU time 0.57 seconds
Started May 12 01:25:07 PM PDT 24
Finished May 12 01:25:08 PM PDT 24
Peak memory 195692 kb
Host smart-cc57e6c6-5bbb-484d-9e1b-ffa4a0f4190e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713577128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2713577128
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3792885186
Short name T518
Test name
Test status
Simulation time 200135823041 ps
CPU time 99.04 seconds
Started May 12 01:25:00 PM PDT 24
Finished May 12 01:26:41 PM PDT 24
Peak memory 200276 kb
Host smart-f410d84e-f379-47d9-b93e-5dd97dbf748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792885186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3792885186
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1723612407
Short name T171
Test name
Test status
Simulation time 42272508881 ps
CPU time 37.48 seconds
Started May 12 01:25:00 PM PDT 24
Finished May 12 01:25:38 PM PDT 24
Peak memory 200300 kb
Host smart-44bf014b-87e2-4236-9a5c-7e032a3dfe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723612407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1723612407
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2770483256
Short name T221
Test name
Test status
Simulation time 36532806507 ps
CPU time 36.8 seconds
Started May 12 01:25:02 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 200388 kb
Host smart-d3365110-fc37-4a93-a20d-9b7efb45b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770483256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2770483256
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3269712179
Short name T763
Test name
Test status
Simulation time 8977789037 ps
CPU time 4.1 seconds
Started May 12 01:25:00 PM PDT 24
Finished May 12 01:25:06 PM PDT 24
Peak memory 198056 kb
Host smart-f5c20806-c548-42ed-9cab-224f25ad0165
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269712179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3269712179
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.488285564
Short name T641
Test name
Test status
Simulation time 136262035186 ps
CPU time 108.57 seconds
Started May 12 01:25:03 PM PDT 24
Finished May 12 01:26:52 PM PDT 24
Peak memory 200224 kb
Host smart-fbc49d5e-5a27-4030-ab02-643f41b192cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488285564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.488285564
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3787373055
Short name T812
Test name
Test status
Simulation time 5130672767 ps
CPU time 9.67 seconds
Started May 12 01:25:04 PM PDT 24
Finished May 12 01:25:15 PM PDT 24
Peak memory 199156 kb
Host smart-0b6db713-8a93-4fe0-8ec4-4f2cb28b8b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787373055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3787373055
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.845486533
Short name T978
Test name
Test status
Simulation time 39775760912 ps
CPU time 64.37 seconds
Started May 12 01:25:05 PM PDT 24
Finished May 12 01:26:10 PM PDT 24
Peak memory 200260 kb
Host smart-f0ac05f8-51cb-4929-921f-297b0a4246aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845486533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.845486533
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2936957035
Short name T948
Test name
Test status
Simulation time 22236512872 ps
CPU time 1193.33 seconds
Started May 12 01:25:04 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 200408 kb
Host smart-679990cd-6d28-452e-9e88-c9e9b7d3e9ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936957035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2936957035
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.129280678
Short name T981
Test name
Test status
Simulation time 2854098387 ps
CPU time 21.84 seconds
Started May 12 01:25:03 PM PDT 24
Finished May 12 01:25:25 PM PDT 24
Peak memory 198808 kb
Host smart-10dbcf26-abcb-4b44-815d-d757c970d4a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129280678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.129280678
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.762138050
Short name T894
Test name
Test status
Simulation time 156945563002 ps
CPU time 62.93 seconds
Started May 12 01:25:07 PM PDT 24
Finished May 12 01:26:10 PM PDT 24
Peak memory 200316 kb
Host smart-cc1c9e7c-2c86-4550-9ec4-5870f726417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762138050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.762138050
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2857185926
Short name T426
Test name
Test status
Simulation time 4616602384 ps
CPU time 4.75 seconds
Started May 12 01:25:04 PM PDT 24
Finished May 12 01:25:10 PM PDT 24
Peak memory 196376 kb
Host smart-92e92870-a4eb-4aa4-b78d-4e941fbca6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857185926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2857185926
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2282906970
Short name T545
Test name
Test status
Simulation time 6277368699 ps
CPU time 8.15 seconds
Started May 12 01:25:01 PM PDT 24
Finished May 12 01:25:11 PM PDT 24
Peak memory 200160 kb
Host smart-4a338366-65cb-40e0-b17d-a5289cc4e34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282906970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2282906970
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3430180755
Short name T771
Test name
Test status
Simulation time 234534681313 ps
CPU time 343.64 seconds
Started May 12 01:25:05 PM PDT 24
Finished May 12 01:30:50 PM PDT 24
Peak memory 208852 kb
Host smart-2d2c21bf-4862-4900-b84e-1f34e10278ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430180755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3430180755
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3842909894
Short name T60
Test name
Test status
Simulation time 293689444399 ps
CPU time 660.47 seconds
Started May 12 01:25:05 PM PDT 24
Finished May 12 01:36:06 PM PDT 24
Peak memory 225260 kb
Host smart-9816a5ea-df4e-40e8-96e5-9377cc6d8186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842909894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3842909894
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1556576212
Short name T885
Test name
Test status
Simulation time 12247239149 ps
CPU time 49.27 seconds
Started May 12 01:25:05 PM PDT 24
Finished May 12 01:25:55 PM PDT 24
Peak memory 200312 kb
Host smart-0059a816-7172-4268-a8b6-3d6764db9639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556576212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1556576212
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2536496280
Short name T787
Test name
Test status
Simulation time 15777156214 ps
CPU time 6.95 seconds
Started May 12 01:25:02 PM PDT 24
Finished May 12 01:25:10 PM PDT 24
Peak memory 199796 kb
Host smart-107d85a1-9ff7-4149-b6a5-b70f33b8b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536496280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2536496280
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3513454606
Short name T1122
Test name
Test status
Simulation time 140910312127 ps
CPU time 216.89 seconds
Started May 12 01:28:48 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 200344 kb
Host smart-12f8f763-fdd0-4fa3-b71a-d393505c35e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513454606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3513454606
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2171515536
Short name T1166
Test name
Test status
Simulation time 39071944691 ps
CPU time 19.25 seconds
Started May 12 01:28:47 PM PDT 24
Finished May 12 01:29:07 PM PDT 24
Peak memory 200368 kb
Host smart-ecb513fb-7b3f-42f0-8b35-3b1322220100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171515536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2171515536
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.988067170
Short name T329
Test name
Test status
Simulation time 22693207848 ps
CPU time 35.47 seconds
Started May 12 01:28:51 PM PDT 24
Finished May 12 01:29:26 PM PDT 24
Peak memory 200340 kb
Host smart-80a2551d-a89e-4868-abb6-468a3e81163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988067170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.988067170
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1558198523
Short name T695
Test name
Test status
Simulation time 38704767260 ps
CPU time 28.85 seconds
Started May 12 01:28:48 PM PDT 24
Finished May 12 01:29:17 PM PDT 24
Peak memory 200388 kb
Host smart-3412f098-3161-4682-87f2-ec5e0fc2b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558198523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1558198523
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2430651741
Short name T931
Test name
Test status
Simulation time 170642467731 ps
CPU time 76.73 seconds
Started May 12 01:28:48 PM PDT 24
Finished May 12 01:30:05 PM PDT 24
Peak memory 200376 kb
Host smart-d7e0dd5d-1e89-401e-b845-ad55c3bd1213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430651741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2430651741
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3273867065
Short name T451
Test name
Test status
Simulation time 37321607406 ps
CPU time 37.01 seconds
Started May 12 01:28:51 PM PDT 24
Finished May 12 01:29:28 PM PDT 24
Peak memory 200356 kb
Host smart-97956d4d-ecf5-4295-bc70-424d63a49ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273867065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3273867065
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.757461400
Short name T335
Test name
Test status
Simulation time 4738216733 ps
CPU time 13.15 seconds
Started May 12 01:28:47 PM PDT 24
Finished May 12 01:29:01 PM PDT 24
Peak memory 200272 kb
Host smart-24836de2-86af-4e57-ad67-7867889542eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757461400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.757461400
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.596912155
Short name T582
Test name
Test status
Simulation time 52018313 ps
CPU time 0.55 seconds
Started May 12 01:25:10 PM PDT 24
Finished May 12 01:25:11 PM PDT 24
Peak memory 195792 kb
Host smart-0d57b797-2823-4db1-bee2-03e8c1bd8dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596912155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.596912155
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3485752311
Short name T789
Test name
Test status
Simulation time 56116030943 ps
CPU time 24.66 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 200420 kb
Host smart-73f3701c-1b79-4deb-ae57-45ae71d9d2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485752311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3485752311
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3492509403
Short name T409
Test name
Test status
Simulation time 75657363704 ps
CPU time 147 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:27:37 PM PDT 24
Peak memory 200376 kb
Host smart-7dacb5a0-7377-4381-9670-0da9b8a33485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492509403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3492509403
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.3652389329
Short name T381
Test name
Test status
Simulation time 21253521503 ps
CPU time 20.43 seconds
Started May 12 01:25:10 PM PDT 24
Finished May 12 01:25:31 PM PDT 24
Peak memory 200352 kb
Host smart-e46692d8-3ee4-4414-a1a8-fd8c9442883f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652389329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3652389329
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2902962015
Short name T852
Test name
Test status
Simulation time 145983399409 ps
CPU time 176.67 seconds
Started May 12 01:25:11 PM PDT 24
Finished May 12 01:28:09 PM PDT 24
Peak memory 200368 kb
Host smart-ac324e43-1daf-4037-a29c-3ea7c9e51a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902962015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2902962015
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.172192248
Short name T349
Test name
Test status
Simulation time 1183257107 ps
CPU time 1.17 seconds
Started May 12 01:25:08 PM PDT 24
Finished May 12 01:25:09 PM PDT 24
Peak memory 197600 kb
Host smart-db987ad1-c37b-436d-843e-0df9e3c267e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172192248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.172192248
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1826334678
Short name T45
Test name
Test status
Simulation time 48013097025 ps
CPU time 18.24 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:28 PM PDT 24
Peak memory 199684 kb
Host smart-3bd308b6-4cd0-476d-91f8-24e87a90faa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826334678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1826334678
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2282619739
Short name T570
Test name
Test status
Simulation time 27835866730 ps
CPU time 152.66 seconds
Started May 12 01:25:11 PM PDT 24
Finished May 12 01:27:44 PM PDT 24
Peak memory 200336 kb
Host smart-29a6266e-2b5b-4efb-b254-0af1fd2abf14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282619739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2282619739
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3182085652
Short name T813
Test name
Test status
Simulation time 5598985514 ps
CPU time 12.91 seconds
Started May 12 01:25:08 PM PDT 24
Finished May 12 01:25:22 PM PDT 24
Peak memory 198460 kb
Host smart-681afc4a-083a-4fa7-864b-4abcc10812bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182085652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3182085652
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.413261957
Short name T1046
Test name
Test status
Simulation time 35564618210 ps
CPU time 16.27 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:26 PM PDT 24
Peak memory 200388 kb
Host smart-7e529eee-af05-4625-baf1-f4eee270a2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413261957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.413261957
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.662663119
Short name T1012
Test name
Test status
Simulation time 6223628979 ps
CPU time 6.39 seconds
Started May 12 01:25:07 PM PDT 24
Finished May 12 01:25:14 PM PDT 24
Peak memory 196404 kb
Host smart-29cc09ae-9d4e-4d39-bcaf-a46d3fbc49c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662663119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.662663119
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1962480612
Short name T995
Test name
Test status
Simulation time 413409218 ps
CPU time 1.48 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:12 PM PDT 24
Peak memory 200268 kb
Host smart-48b72e22-f79b-4a77-bfe2-249afc6adcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962480612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1962480612
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.812512810
Short name T240
Test name
Test status
Simulation time 336941745487 ps
CPU time 1220.31 seconds
Started May 12 01:25:08 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 200396 kb
Host smart-d98fa05f-380b-4fd1-a6f1-5bccf185253c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812512810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.812512810
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3868921659
Short name T62
Test name
Test status
Simulation time 314326384101 ps
CPU time 753.42 seconds
Started May 12 01:25:10 PM PDT 24
Finished May 12 01:37:44 PM PDT 24
Peak memory 230568 kb
Host smart-10dd406f-1f5a-46de-97ab-09e4079180b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868921659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3868921659
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1409650903
Short name T997
Test name
Test status
Simulation time 366777233 ps
CPU time 1.59 seconds
Started May 12 01:25:11 PM PDT 24
Finished May 12 01:25:13 PM PDT 24
Peak memory 199012 kb
Host smart-1241d516-7c58-4e9a-a63b-f740679cab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409650903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1409650903
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.128745880
Short name T1146
Test name
Test status
Simulation time 13276837445 ps
CPU time 21.05 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:31 PM PDT 24
Peak memory 200328 kb
Host smart-52818b51-7a35-4522-a855-529196d1de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128745880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.128745880
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3324098830
Short name T251
Test name
Test status
Simulation time 11412785653 ps
CPU time 11.44 seconds
Started May 12 01:28:46 PM PDT 24
Finished May 12 01:28:58 PM PDT 24
Peak memory 200396 kb
Host smart-eaa6c323-dabb-447e-878a-133b9e8f3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324098830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3324098830
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2435366863
Short name T949
Test name
Test status
Simulation time 105363877981 ps
CPU time 106.71 seconds
Started May 12 01:28:52 PM PDT 24
Finished May 12 01:30:39 PM PDT 24
Peak memory 200376 kb
Host smart-5ab97a32-dc9d-46fc-aac3-d945fbd63eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435366863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2435366863
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2239079605
Short name T121
Test name
Test status
Simulation time 137473208947 ps
CPU time 53.87 seconds
Started May 12 01:28:51 PM PDT 24
Finished May 12 01:29:45 PM PDT 24
Peak memory 200312 kb
Host smart-b0dd3779-1a76-43d8-81d2-b064ceb4ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239079605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2239079605
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2533884471
Short name T172
Test name
Test status
Simulation time 45627526318 ps
CPU time 23.06 seconds
Started May 12 01:28:51 PM PDT 24
Finished May 12 01:29:14 PM PDT 24
Peak memory 200336 kb
Host smart-68c29b96-7ff8-4429-b390-1f48383fcaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533884471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2533884471
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.49074789
Short name T491
Test name
Test status
Simulation time 64733487460 ps
CPU time 41.01 seconds
Started May 12 01:28:50 PM PDT 24
Finished May 12 01:29:31 PM PDT 24
Peak memory 200412 kb
Host smart-c6cb126f-5d4b-4fca-b5e7-373358535798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49074789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.49074789
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4290818490
Short name T256
Test name
Test status
Simulation time 218273002710 ps
CPU time 81.94 seconds
Started May 12 01:28:52 PM PDT 24
Finished May 12 01:30:14 PM PDT 24
Peak memory 200392 kb
Host smart-6fe79c1d-66d3-4377-a392-a1f3ce8b78e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290818490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4290818490
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.808619336
Short name T731
Test name
Test status
Simulation time 13851693784 ps
CPU time 21.39 seconds
Started May 12 01:28:50 PM PDT 24
Finished May 12 01:29:12 PM PDT 24
Peak memory 200360 kb
Host smart-7d8b04d4-c252-47e6-9cd0-0abc93e95ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808619336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.808619336
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3664402756
Short name T363
Test name
Test status
Simulation time 15610523774 ps
CPU time 25.34 seconds
Started May 12 01:28:52 PM PDT 24
Finished May 12 01:29:18 PM PDT 24
Peak memory 200432 kb
Host smart-22c2fa38-b9b5-4d95-b587-90ea165552bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664402756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3664402756
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2946961734
Short name T1106
Test name
Test status
Simulation time 48272905 ps
CPU time 0.57 seconds
Started May 12 01:25:15 PM PDT 24
Finished May 12 01:25:16 PM PDT 24
Peak memory 195748 kb
Host smart-b9424450-a77d-4c54-a6fc-c45255063b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946961734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2946961734
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.182418295
Short name T959
Test name
Test status
Simulation time 23586944032 ps
CPU time 39.96 seconds
Started May 12 01:25:08 PM PDT 24
Finished May 12 01:25:49 PM PDT 24
Peak memory 200404 kb
Host smart-90712e36-d3fd-4dbd-8800-d63a4887c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182418295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.182418295
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.536893142
Short name T734
Test name
Test status
Simulation time 66509006112 ps
CPU time 14.55 seconds
Started May 12 01:25:11 PM PDT 24
Finished May 12 01:25:26 PM PDT 24
Peak memory 200352 kb
Host smart-2c93ec6e-8693-4d86-b2dc-87149a0e8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536893142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.536893142
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2226686900
Short name T1065
Test name
Test status
Simulation time 163239239548 ps
CPU time 58.76 seconds
Started May 12 01:25:12 PM PDT 24
Finished May 12 01:26:12 PM PDT 24
Peak memory 200400 kb
Host smart-66584fe1-6e20-463d-9d15-8b01ea613510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226686900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2226686900
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1477601240
Short name T611
Test name
Test status
Simulation time 34089203460 ps
CPU time 33.05 seconds
Started May 12 01:25:12 PM PDT 24
Finished May 12 01:25:46 PM PDT 24
Peak memory 200044 kb
Host smart-4af708ad-bda2-4e2b-8c44-23920bdf13c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477601240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1477601240
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.155547449
Short name T744
Test name
Test status
Simulation time 63071250187 ps
CPU time 211 seconds
Started May 12 01:25:18 PM PDT 24
Finished May 12 01:28:49 PM PDT 24
Peak memory 200380 kb
Host smart-1400e036-9e81-4768-9a8b-d3e89d7b1973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155547449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.155547449
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3303005782
Short name T396
Test name
Test status
Simulation time 6232868803 ps
CPU time 4.94 seconds
Started May 12 01:25:12 PM PDT 24
Finished May 12 01:25:17 PM PDT 24
Peak memory 200524 kb
Host smart-2934f157-8fbe-46ee-8dde-b6ec48ce6e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303005782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3303005782
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3188009508
Short name T1002
Test name
Test status
Simulation time 29354833902 ps
CPU time 50.42 seconds
Started May 12 01:25:13 PM PDT 24
Finished May 12 01:26:03 PM PDT 24
Peak memory 208748 kb
Host smart-ab494e55-7e9f-4604-8e7c-41828076276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188009508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3188009508
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.4124739666
Short name T555
Test name
Test status
Simulation time 14208009147 ps
CPU time 712.38 seconds
Started May 12 01:25:21 PM PDT 24
Finished May 12 01:37:13 PM PDT 24
Peak memory 200356 kb
Host smart-2b97aec5-a1ff-4690-9671-38c0b53c59e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124739666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4124739666
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1220774659
Short name T469
Test name
Test status
Simulation time 6228764100 ps
CPU time 15.29 seconds
Started May 12 01:25:11 PM PDT 24
Finished May 12 01:25:27 PM PDT 24
Peak memory 198848 kb
Host smart-8d234d44-89e4-4b1f-a7ea-4e13b0c34a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220774659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1220774659
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.436667519
Short name T910
Test name
Test status
Simulation time 35779167266 ps
CPU time 20.34 seconds
Started May 12 01:25:14 PM PDT 24
Finished May 12 01:25:34 PM PDT 24
Peak memory 200400 kb
Host smart-8072e8b2-0d00-4e29-ad90-819d8829a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436667519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.436667519
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3568309965
Short name T580
Test name
Test status
Simulation time 4214495314 ps
CPU time 7.76 seconds
Started May 12 01:25:13 PM PDT 24
Finished May 12 01:25:21 PM PDT 24
Peak memory 196588 kb
Host smart-a147aa7d-d44c-44fb-a4a1-33dfadfd4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568309965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3568309965
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.320458150
Short name T740
Test name
Test status
Simulation time 6252459363 ps
CPU time 18.78 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:29 PM PDT 24
Peak memory 200044 kb
Host smart-f358b3ee-4654-4f20-a4a0-0287004a5e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320458150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.320458150
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3874060313
Short name T22
Test name
Test status
Simulation time 40913517683 ps
CPU time 472.74 seconds
Started May 12 01:25:16 PM PDT 24
Finished May 12 01:33:09 PM PDT 24
Peak memory 217056 kb
Host smart-c1fdbd7b-fdee-4b93-b328-3f04bd4944d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874060313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3874060313
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1390333060
Short name T429
Test name
Test status
Simulation time 1319036369 ps
CPU time 3.98 seconds
Started May 12 01:25:11 PM PDT 24
Finished May 12 01:25:16 PM PDT 24
Peak memory 199696 kb
Host smart-7694c34f-278f-497a-b350-c788feba9891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390333060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1390333060
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1290339520
Short name T1126
Test name
Test status
Simulation time 7008720864 ps
CPU time 4.04 seconds
Started May 12 01:25:09 PM PDT 24
Finished May 12 01:25:13 PM PDT 24
Peak memory 196880 kb
Host smart-51973d99-2336-41c8-9f94-857e5455a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290339520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1290339520
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1516488818
Short name T225
Test name
Test status
Simulation time 36650723211 ps
CPU time 15.72 seconds
Started May 12 01:28:56 PM PDT 24
Finished May 12 01:29:12 PM PDT 24
Peak memory 200356 kb
Host smart-e89aaadd-13a8-4d71-b0df-43dad130a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516488818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1516488818
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3843146999
Short name T654
Test name
Test status
Simulation time 7381570441 ps
CPU time 10.37 seconds
Started May 12 01:28:56 PM PDT 24
Finished May 12 01:29:07 PM PDT 24
Peak memory 200312 kb
Host smart-15f213f4-50ef-4b75-b177-b36fb24113c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843146999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3843146999
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1180588588
Short name T199
Test name
Test status
Simulation time 99968131708 ps
CPU time 28.67 seconds
Started May 12 01:28:57 PM PDT 24
Finished May 12 01:29:26 PM PDT 24
Peak memory 199600 kb
Host smart-4500ddd1-08f4-4bd7-b6e8-6143f2e06cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180588588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1180588588
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.21246487
Short name T565
Test name
Test status
Simulation time 88924347722 ps
CPU time 31.6 seconds
Started May 12 01:28:54 PM PDT 24
Finished May 12 01:29:26 PM PDT 24
Peak memory 200384 kb
Host smart-7ccf8d0e-3a2b-40ed-865d-5ecb96d1a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21246487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.21246487
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2483999297
Short name T320
Test name
Test status
Simulation time 38556254255 ps
CPU time 19.45 seconds
Started May 12 01:28:56 PM PDT 24
Finished May 12 01:29:16 PM PDT 24
Peak memory 200320 kb
Host smart-39b3a68b-853d-4bdd-a67d-7d504545d90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483999297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2483999297
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3228358030
Short name T203
Test name
Test status
Simulation time 62400877127 ps
CPU time 11.93 seconds
Started May 12 01:28:54 PM PDT 24
Finished May 12 01:29:06 PM PDT 24
Peak memory 200304 kb
Host smart-ee9e18f6-c495-4fa7-b7f7-9cfbf0b52f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228358030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3228358030
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3188989211
Short name T246
Test name
Test status
Simulation time 32257965967 ps
CPU time 9.67 seconds
Started May 12 01:28:57 PM PDT 24
Finished May 12 01:29:07 PM PDT 24
Peak memory 200332 kb
Host smart-d966cae7-7df8-475b-88fe-8dd33bc158a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188989211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3188989211
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.522762492
Short name T346
Test name
Test status
Simulation time 43472979 ps
CPU time 0.58 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:25 PM PDT 24
Peak memory 195720 kb
Host smart-1e243a96-de64-4815-b1ef-2138d36d1b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522762492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.522762492
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2020901829
Short name T709
Test name
Test status
Simulation time 38364864517 ps
CPU time 70.4 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 200388 kb
Host smart-1b8ed740-7212-491b-839e-e9138436a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020901829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2020901829
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3387123191
Short name T465
Test name
Test status
Simulation time 40948343546 ps
CPU time 79.35 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:25:41 PM PDT 24
Peak memory 200248 kb
Host smart-24dd916f-80de-4350-8322-15d04218a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387123191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3387123191
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.97847339
Short name T132
Test name
Test status
Simulation time 9875107805 ps
CPU time 9.09 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:30 PM PDT 24
Peak memory 200216 kb
Host smart-c2fd7348-0b6a-4c4d-8ec8-78d00bb569cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97847339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.97847339
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.947177603
Short name T492
Test name
Test status
Simulation time 33710858279 ps
CPU time 15.08 seconds
Started May 12 01:24:21 PM PDT 24
Finished May 12 01:24:37 PM PDT 24
Peak memory 200364 kb
Host smart-228ee908-8ffd-4f49-9f3d-e3d896b7e5d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947177603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.947177603
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4130356864
Short name T711
Test name
Test status
Simulation time 91371017662 ps
CPU time 197.14 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:27:45 PM PDT 24
Peak memory 200312 kb
Host smart-10634ea4-fbc9-4a1a-a738-9a1ee73f4431
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130356864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4130356864
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.118586235
Short name T117
Test name
Test status
Simulation time 8015715497 ps
CPU time 7.61 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:24:32 PM PDT 24
Peak memory 200400 kb
Host smart-d0ec86cf-2d31-4f2a-ab76-38f132a81a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118586235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.118586235
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.954743628
Short name T594
Test name
Test status
Simulation time 133636268432 ps
CPU time 123.79 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:26:25 PM PDT 24
Peak memory 199408 kb
Host smart-250c2018-b3bb-443a-a3f9-61c933ffb62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954743628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.954743628
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3134525878
Short name T761
Test name
Test status
Simulation time 15073650343 ps
CPU time 60.3 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:25:25 PM PDT 24
Peak memory 200416 kb
Host smart-3a640a86-cbdf-4324-8adb-58ff00b3c4bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134525878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3134525878
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2854177291
Short name T365
Test name
Test status
Simulation time 6637830458 ps
CPU time 7.34 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:29 PM PDT 24
Peak memory 200288 kb
Host smart-5fdf8395-6d49-4fb6-97c3-a75b13c32c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854177291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2854177291
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.766014295
Short name T631
Test name
Test status
Simulation time 87807742491 ps
CPU time 131.76 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:26:37 PM PDT 24
Peak memory 200296 kb
Host smart-3002040f-9521-472e-93c6-3c80987b2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766014295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.766014295
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1334343261
Short name T849
Test name
Test status
Simulation time 1997589071 ps
CPU time 1.56 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:23 PM PDT 24
Peak memory 196044 kb
Host smart-451a605d-5695-4943-9f93-375dbaf5f9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334343261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1334343261
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.66065126
Short name T37
Test name
Test status
Simulation time 256535949 ps
CPU time 0.92 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:26 PM PDT 24
Peak memory 218640 kb
Host smart-8f1b52a8-bb8e-4e38-a3e6-60d41ae37d1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66065126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.66065126
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4095833701
Short name T461
Test name
Test status
Simulation time 525744776 ps
CPU time 1.3 seconds
Started May 12 01:24:19 PM PDT 24
Finished May 12 01:24:21 PM PDT 24
Peak memory 198724 kb
Host smart-e760ab1d-b58a-4421-aa12-958554cff343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095833701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4095833701
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1280137572
Short name T277
Test name
Test status
Simulation time 255410214844 ps
CPU time 1094.14 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:42:39 PM PDT 24
Peak memory 200168 kb
Host smart-25498e73-3a14-4de8-9766-09b3e5b37a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280137572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1280137572
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1465031516
Short name T1075
Test name
Test status
Simulation time 119167573767 ps
CPU time 627.34 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:34:52 PM PDT 24
Peak memory 216820 kb
Host smart-796c6909-b529-45b2-9192-0eec6c8ca686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465031516 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1465031516
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.395501293
Short name T738
Test name
Test status
Simulation time 6771486009 ps
CPU time 20.22 seconds
Started May 12 01:24:20 PM PDT 24
Finished May 12 01:24:41 PM PDT 24
Peak memory 200176 kb
Host smart-34b405e1-8f71-4604-a68e-a1bdd66c9dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395501293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.395501293
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_alert_test.478843069
Short name T544
Test name
Test status
Simulation time 30556085 ps
CPU time 0.56 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:25:20 PM PDT 24
Peak memory 195768 kb
Host smart-325c3789-6a90-4fc2-b961-e2834164580c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478843069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.478843069
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3173002607
Short name T806
Test name
Test status
Simulation time 169442671860 ps
CPU time 77.14 seconds
Started May 12 01:25:18 PM PDT 24
Finished May 12 01:26:35 PM PDT 24
Peak memory 200300 kb
Host smart-ec6a895f-4860-452c-af3a-d1a452fba2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173002607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3173002607
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2028422876
Short name T914
Test name
Test status
Simulation time 69413658249 ps
CPU time 33.13 seconds
Started May 12 01:25:16 PM PDT 24
Finished May 12 01:25:49 PM PDT 24
Peak memory 200304 kb
Host smart-4e0ad920-6038-4b40-8862-7fa2a6d83d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028422876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2028422876
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2216875133
Short name T1140
Test name
Test status
Simulation time 50622024049 ps
CPU time 51.98 seconds
Started May 12 01:25:17 PM PDT 24
Finished May 12 01:26:10 PM PDT 24
Peak memory 200416 kb
Host smart-b1911eb7-9ddb-4d8d-bbaf-a2dde732dfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216875133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2216875133
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1758692604
Short name T661
Test name
Test status
Simulation time 30392318629 ps
CPU time 10.65 seconds
Started May 12 01:25:18 PM PDT 24
Finished May 12 01:25:29 PM PDT 24
Peak memory 199448 kb
Host smart-052c23cd-f7ad-4689-9414-a8240bf9d742
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758692604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1758692604
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.600828979
Short name T413
Test name
Test status
Simulation time 150043938418 ps
CPU time 358.08 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 200360 kb
Host smart-df7e184b-1bfe-4644-bdbd-fe704a1abcf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600828979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.600828979
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1795735160
Short name T680
Test name
Test status
Simulation time 5181036406 ps
CPU time 16.92 seconds
Started May 12 01:25:24 PM PDT 24
Finished May 12 01:25:42 PM PDT 24
Peak memory 200360 kb
Host smart-7ff2e204-057a-4d5a-a7dd-198e112c9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795735160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1795735160
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3452724438
Short name T1101
Test name
Test status
Simulation time 55630021382 ps
CPU time 26.88 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:25:47 PM PDT 24
Peak memory 198344 kb
Host smart-4b2e60d8-4c74-49b6-82b8-17cef87b72ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452724438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3452724438
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3864999579
Short name T1102
Test name
Test status
Simulation time 7498916535 ps
CPU time 60.07 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:26:19 PM PDT 24
Peak memory 200352 kb
Host smart-509b3a40-9583-4c19-85bd-479a61d4f25e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864999579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3864999579
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.641322777
Short name T449
Test name
Test status
Simulation time 3063779653 ps
CPU time 26.01 seconds
Started May 12 01:25:18 PM PDT 24
Finished May 12 01:25:44 PM PDT 24
Peak memory 198700 kb
Host smart-b2f56d89-a1a9-4d6c-83f4-9d0e2177d6b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641322777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.641322777
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.496886296
Short name T467
Test name
Test status
Simulation time 17739214784 ps
CPU time 23.6 seconds
Started May 12 01:25:16 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 200340 kb
Host smart-ca1eff4b-8dda-495e-bae6-0d1f5bebba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496886296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.496886296
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3555946841
Short name T510
Test name
Test status
Simulation time 3557737469 ps
CPU time 2.13 seconds
Started May 12 01:25:21 PM PDT 24
Finished May 12 01:25:24 PM PDT 24
Peak memory 196404 kb
Host smart-f61fe96b-c4b9-4b4c-947e-7d77e304af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555946841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3555946841
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1622701988
Short name T1018
Test name
Test status
Simulation time 135136268 ps
CPU time 0.74 seconds
Started May 12 01:25:15 PM PDT 24
Finished May 12 01:25:16 PM PDT 24
Peak memory 198120 kb
Host smart-a6ec708d-797e-4459-9eae-326bf4a314e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622701988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1622701988
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.667473866
Short name T16
Test name
Test status
Simulation time 50194364977 ps
CPU time 99.14 seconds
Started May 12 01:25:18 PM PDT 24
Finished May 12 01:26:58 PM PDT 24
Peak memory 200396 kb
Host smart-21d34029-363c-4e96-98f4-1055f8bb55ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667473866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.667473866
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.582418347
Short name T935
Test name
Test status
Simulation time 473579471865 ps
CPU time 362.04 seconds
Started May 12 01:25:21 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 217064 kb
Host smart-763ad778-6f8d-4b3b-bd39-b382290c3193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582418347 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.582418347
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3098618043
Short name T1070
Test name
Test status
Simulation time 824906516 ps
CPU time 2.15 seconds
Started May 12 01:25:16 PM PDT 24
Finished May 12 01:25:19 PM PDT 24
Peak memory 198636 kb
Host smart-f296824f-bc16-42a3-8cbc-14d1d9f420b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098618043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3098618043
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.121827106
Short name T48
Test name
Test status
Simulation time 156206337780 ps
CPU time 105.36 seconds
Started May 12 01:25:17 PM PDT 24
Finished May 12 01:27:03 PM PDT 24
Peak memory 200432 kb
Host smart-8d289c0e-69af-42ca-a982-30ac383f2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121827106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.121827106
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.872014890
Short name T1033
Test name
Test status
Simulation time 16157762194 ps
CPU time 8.55 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:29:10 PM PDT 24
Peak memory 200376 kb
Host smart-1f3b4ba3-1ac6-4a75-8ba0-08802bbb0b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872014890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.872014890
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4002113617
Short name T851
Test name
Test status
Simulation time 23629989360 ps
CPU time 38.33 seconds
Started May 12 01:28:59 PM PDT 24
Finished May 12 01:29:38 PM PDT 24
Peak memory 200372 kb
Host smart-16ece513-a97f-4da5-a942-b1998461d55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002113617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4002113617
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1153126284
Short name T490
Test name
Test status
Simulation time 46555261895 ps
CPU time 81.67 seconds
Started May 12 01:28:59 PM PDT 24
Finished May 12 01:30:21 PM PDT 24
Peak memory 200344 kb
Host smart-1bfc8b51-ad2b-4d9a-ae73-d263ab44896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153126284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1153126284
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4283395920
Short name T1155
Test name
Test status
Simulation time 79276386667 ps
CPU time 140.21 seconds
Started May 12 01:29:01 PM PDT 24
Finished May 12 01:31:21 PM PDT 24
Peak memory 200360 kb
Host smart-89de90fb-e866-48c8-bc62-7436958f5070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283395920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4283395920
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1774367272
Short name T139
Test name
Test status
Simulation time 116901172534 ps
CPU time 143.43 seconds
Started May 12 01:28:59 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 200408 kb
Host smart-fde96cba-2147-47f0-98fc-dfc4993d4ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774367272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1774367272
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2996069252
Short name T4
Test name
Test status
Simulation time 22241797541 ps
CPU time 35.67 seconds
Started May 12 01:28:58 PM PDT 24
Finished May 12 01:29:34 PM PDT 24
Peak memory 200388 kb
Host smart-3d277e45-e490-4840-8fcb-b0307588c8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996069252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2996069252
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1643590393
Short name T220
Test name
Test status
Simulation time 105928110865 ps
CPU time 92.58 seconds
Started May 12 01:28:59 PM PDT 24
Finished May 12 01:30:32 PM PDT 24
Peak memory 200384 kb
Host smart-139c47d3-ab14-48b2-941f-cabee870c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643590393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1643590393
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.909120578
Short name T1071
Test name
Test status
Simulation time 39324408336 ps
CPU time 37.71 seconds
Started May 12 01:29:00 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 200436 kb
Host smart-e51c7405-566c-47cb-bcd3-06e79b866c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909120578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.909120578
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3825464333
Short name T356
Test name
Test status
Simulation time 12508364 ps
CPU time 0.57 seconds
Started May 12 01:25:26 PM PDT 24
Finished May 12 01:25:27 PM PDT 24
Peak memory 195784 kb
Host smart-2e4cb177-5ded-4d63-a586-054f49875784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825464333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3825464333
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4017355687
Short name T670
Test name
Test status
Simulation time 263019193561 ps
CPU time 123 seconds
Started May 12 01:25:20 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 200364 kb
Host smart-9eb32f67-7ef5-4906-9d79-8b8a990e89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017355687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4017355687
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3699375786
Short name T834
Test name
Test status
Simulation time 55099807121 ps
CPU time 81.39 seconds
Started May 12 01:25:22 PM PDT 24
Finished May 12 01:26:43 PM PDT 24
Peak memory 199604 kb
Host smart-9e4083ba-db22-4918-994e-53365a17d2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699375786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3699375786
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4154207805
Short name T516
Test name
Test status
Simulation time 150889211149 ps
CPU time 70.65 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:26:31 PM PDT 24
Peak memory 200412 kb
Host smart-25576fe2-2acf-4c8c-9bd8-7edea9ad6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154207805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4154207805
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.424202243
Short name T783
Test name
Test status
Simulation time 25908440359 ps
CPU time 19.94 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:25:39 PM PDT 24
Peak memory 197848 kb
Host smart-ab899622-ae5e-4eee-bfd3-cb62b4509d2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424202243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.424202243
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3956362562
Short name T1086
Test name
Test status
Simulation time 47653596353 ps
CPU time 228.04 seconds
Started May 12 01:25:25 PM PDT 24
Finished May 12 01:29:13 PM PDT 24
Peak memory 200328 kb
Host smart-b02f6864-7736-4699-8ef2-e491d82ab3c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956362562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3956362562
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1413567048
Short name T1092
Test name
Test status
Simulation time 4430705180 ps
CPU time 2.58 seconds
Started May 12 01:25:24 PM PDT 24
Finished May 12 01:25:27 PM PDT 24
Peak memory 198176 kb
Host smart-005f2da2-94c1-485e-b00b-d94b116a307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413567048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1413567048
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2180596238
Short name T54
Test name
Test status
Simulation time 101504226409 ps
CPU time 374.15 seconds
Started May 12 01:25:20 PM PDT 24
Finished May 12 01:31:34 PM PDT 24
Peak memory 200372 kb
Host smart-a1c87a54-de9d-47f4-82d9-099a05dcbbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180596238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2180596238
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3215083651
Short name T874
Test name
Test status
Simulation time 25178053688 ps
CPU time 164.98 seconds
Started May 12 01:25:24 PM PDT 24
Finished May 12 01:28:09 PM PDT 24
Peak memory 200364 kb
Host smart-49326e6d-0827-45fb-9204-50fd34e33dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215083651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3215083651
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3375163692
Short name T557
Test name
Test status
Simulation time 4554196577 ps
CPU time 35.48 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:25:55 PM PDT 24
Peak memory 199020 kb
Host smart-824b2172-cc1d-403b-82d8-098f084e6f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375163692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3375163692
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4102349677
Short name T993
Test name
Test status
Simulation time 144466813820 ps
CPU time 184.75 seconds
Started May 12 01:25:24 PM PDT 24
Finished May 12 01:28:29 PM PDT 24
Peak memory 200300 kb
Host smart-12c2034a-d903-4e5d-9dcb-a46e011b043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102349677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4102349677
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.271908833
Short name T605
Test name
Test status
Simulation time 628238137 ps
CPU time 1.74 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:25:21 PM PDT 24
Peak memory 195784 kb
Host smart-e77a8cad-3073-43e0-90b1-e9f9bfefde1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271908833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.271908833
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.465086413
Short name T287
Test name
Test status
Simulation time 6221195074 ps
CPU time 24.93 seconds
Started May 12 01:25:22 PM PDT 24
Finished May 12 01:25:47 PM PDT 24
Peak memory 199688 kb
Host smart-5674fb9f-ca49-455b-a354-5e6cb05ee66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465086413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.465086413
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2968916065
Short name T927
Test name
Test status
Simulation time 406861694376 ps
CPU time 273.41 seconds
Started May 12 01:25:25 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 200792 kb
Host smart-8aab77ae-e722-427e-b569-7c5c345063e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968916065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2968916065
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3894448489
Short name T714
Test name
Test status
Simulation time 1017769656 ps
CPU time 2.04 seconds
Started May 12 01:25:22 PM PDT 24
Finished May 12 01:25:24 PM PDT 24
Peak memory 199968 kb
Host smart-0d654c1b-7b5b-4fe5-8511-a7778e262459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894448489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3894448489
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1291813828
Short name T809
Test name
Test status
Simulation time 34240394389 ps
CPU time 20.73 seconds
Started May 12 01:25:19 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 197728 kb
Host smart-39ef1163-48ef-4efb-9272-d856f35ce661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291813828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1291813828
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.955743989
Short name T576
Test name
Test status
Simulation time 30012181419 ps
CPU time 47.41 seconds
Started May 12 01:29:00 PM PDT 24
Finished May 12 01:29:48 PM PDT 24
Peak memory 200436 kb
Host smart-8a0f7c11-8df5-4155-984d-fa1cbd2ba6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955743989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.955743989
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.288982534
Short name T773
Test name
Test status
Simulation time 41133557498 ps
CPU time 29.71 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:29:32 PM PDT 24
Peak memory 200372 kb
Host smart-ae5db236-f97f-44a8-a6ae-e7482df6a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288982534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.288982534
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1414236452
Short name T502
Test name
Test status
Simulation time 61866739415 ps
CPU time 91.94 seconds
Started May 12 01:28:58 PM PDT 24
Finished May 12 01:30:31 PM PDT 24
Peak memory 200392 kb
Host smart-782fd8ee-195b-4a52-af13-f4dc667a13e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414236452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1414236452
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2117907472
Short name T1132
Test name
Test status
Simulation time 19077107637 ps
CPU time 29.45 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:29:32 PM PDT 24
Peak memory 200360 kb
Host smart-9c1ac101-834a-42df-b0b5-151f90f80291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117907472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2117907472
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1492964870
Short name T331
Test name
Test status
Simulation time 12352927169 ps
CPU time 16.54 seconds
Started May 12 01:29:00 PM PDT 24
Finished May 12 01:29:17 PM PDT 24
Peak memory 199024 kb
Host smart-952421d0-aebe-43e1-852f-59b723638a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492964870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1492964870
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3771895382
Short name T152
Test name
Test status
Simulation time 263699348262 ps
CPU time 522.53 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:37:45 PM PDT 24
Peak memory 200416 kb
Host smart-321cb983-1eef-47a5-acfa-55143f19342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771895382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3771895382
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3630753043
Short name T162
Test name
Test status
Simulation time 28072254803 ps
CPU time 43.43 seconds
Started May 12 01:29:04 PM PDT 24
Finished May 12 01:29:48 PM PDT 24
Peak memory 200416 kb
Host smart-7d1c7c44-2bff-42ba-974d-45b9169729f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630753043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3630753043
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1377731362
Short name T151
Test name
Test status
Simulation time 31752315365 ps
CPU time 76.52 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 200368 kb
Host smart-12b1842e-7b94-4e12-9cc1-e64fb0a3152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377731362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1377731362
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.722113340
Short name T628
Test name
Test status
Simulation time 136038917193 ps
CPU time 104.45 seconds
Started May 12 01:29:02 PM PDT 24
Finished May 12 01:30:47 PM PDT 24
Peak memory 200024 kb
Host smart-0fb4e3d7-62d2-4f26-ae34-d5436abff5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722113340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.722113340
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3554991340
Short name T414
Test name
Test status
Simulation time 18499470 ps
CPU time 0.54 seconds
Started May 12 01:25:27 PM PDT 24
Finished May 12 01:25:28 PM PDT 24
Peak memory 195784 kb
Host smart-95472632-3834-451c-bf30-57771b25749b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554991340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3554991340
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1983920671
Short name T497
Test name
Test status
Simulation time 31305703585 ps
CPU time 18.05 seconds
Started May 12 01:25:23 PM PDT 24
Finished May 12 01:25:42 PM PDT 24
Peak memory 200200 kb
Host smart-00b7ca28-a42b-43a1-a6e7-c1cc3809a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983920671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1983920671
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1952570511
Short name T590
Test name
Test status
Simulation time 118166856376 ps
CPU time 57.5 seconds
Started May 12 01:25:22 PM PDT 24
Finished May 12 01:26:20 PM PDT 24
Peak memory 200380 kb
Host smart-3c3a5344-79d4-4fe9-a12b-579fa54074ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952570511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1952570511
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.3133338465
Short name T1156
Test name
Test status
Simulation time 196387997878 ps
CPU time 91.28 seconds
Started May 12 01:25:22 PM PDT 24
Finished May 12 01:26:54 PM PDT 24
Peak memory 197424 kb
Host smart-a6246708-f41f-4c3e-9e87-02bfd5b34e81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133338465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3133338465
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_loopback.203075397
Short name T1098
Test name
Test status
Simulation time 3018383398 ps
CPU time 5.7 seconds
Started May 12 01:25:28 PM PDT 24
Finished May 12 01:25:34 PM PDT 24
Peak memory 199024 kb
Host smart-f0b935b0-172b-43aa-a4ff-eb3d336c3a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203075397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.203075397
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3361511492
Short name T644
Test name
Test status
Simulation time 63873432667 ps
CPU time 50.67 seconds
Started May 12 01:25:23 PM PDT 24
Finished May 12 01:26:14 PM PDT 24
Peak memory 198720 kb
Host smart-aeb55395-6141-407b-b84d-31f65a71591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361511492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3361511492
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3447808392
Short name T423
Test name
Test status
Simulation time 8758138037 ps
CPU time 241.81 seconds
Started May 12 01:25:28 PM PDT 24
Finished May 12 01:29:30 PM PDT 24
Peak memory 200348 kb
Host smart-92690d44-f9c8-40e5-a060-620db5bedad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447808392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3447808392
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.260495520
Short name T1015
Test name
Test status
Simulation time 3516107255 ps
CPU time 3.22 seconds
Started May 12 01:25:23 PM PDT 24
Finished May 12 01:25:27 PM PDT 24
Peak memory 199156 kb
Host smart-6d0733e7-80aa-4e75-9cab-e3b0c824cb11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260495520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.260495520
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1926505393
Short name T1139
Test name
Test status
Simulation time 10680950208 ps
CPU time 10.78 seconds
Started May 12 01:25:23 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 198744 kb
Host smart-2e513d42-1b10-4b91-8bf0-e4335e806f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926505393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1926505393
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.185942097
Short name T639
Test name
Test status
Simulation time 37316077697 ps
CPU time 63.57 seconds
Started May 12 01:25:23 PM PDT 24
Finished May 12 01:26:27 PM PDT 24
Peak memory 196388 kb
Host smart-9a9b1f54-8869-42f2-ab4d-ce769f9b3ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185942097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.185942097
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1169138518
Short name T934
Test name
Test status
Simulation time 758909569 ps
CPU time 1.51 seconds
Started May 12 01:25:22 PM PDT 24
Finished May 12 01:25:24 PM PDT 24
Peak memory 199148 kb
Host smart-0fa8c8c2-c4df-4a97-9e2b-3fcc44508d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169138518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1169138518
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3199785390
Short name T778
Test name
Test status
Simulation time 285979109661 ps
CPU time 974.78 seconds
Started May 12 01:25:28 PM PDT 24
Finished May 12 01:41:43 PM PDT 24
Peak memory 225232 kb
Host smart-54ca6780-77ff-4c6f-b149-3b3cd15c235f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199785390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3199785390
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.498902696
Short name T462
Test name
Test status
Simulation time 187077951 ps
CPU time 1.18 seconds
Started May 12 01:25:27 PM PDT 24
Finished May 12 01:25:29 PM PDT 24
Peak memory 199012 kb
Host smart-3e098bdc-fe0c-4949-b8ba-2c86dbe918e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498902696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.498902696
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1147043962
Short name T818
Test name
Test status
Simulation time 37607718930 ps
CPU time 23.72 seconds
Started May 12 01:25:26 PM PDT 24
Finished May 12 01:25:50 PM PDT 24
Peak memory 200312 kb
Host smart-3e43d86d-4a84-4b34-9993-fa5197625a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147043962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1147043962
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2381441318
Short name T261
Test name
Test status
Simulation time 69132255084 ps
CPU time 36.5 seconds
Started May 12 01:29:01 PM PDT 24
Finished May 12 01:29:38 PM PDT 24
Peak memory 200408 kb
Host smart-5d5fb11e-089a-4f39-9694-d3cd1de5db2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381441318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2381441318
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1775212493
Short name T1143
Test name
Test status
Simulation time 20336940974 ps
CPU time 11.88 seconds
Started May 12 01:29:03 PM PDT 24
Finished May 12 01:29:15 PM PDT 24
Peak memory 200060 kb
Host smart-3fb68dcb-df48-4c8b-be6c-1ae976a7dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775212493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1775212493
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.147417416
Short name T1182
Test name
Test status
Simulation time 91208041684 ps
CPU time 86.16 seconds
Started May 12 01:29:04 PM PDT 24
Finished May 12 01:30:30 PM PDT 24
Peak memory 200400 kb
Host smart-fdb8dbe0-1251-4379-af64-5fcdc7c607f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147417416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.147417416
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1720574082
Short name T133
Test name
Test status
Simulation time 34083937231 ps
CPU time 16.44 seconds
Started May 12 01:29:03 PM PDT 24
Finished May 12 01:29:20 PM PDT 24
Peak memory 200348 kb
Host smart-ec535410-6cce-43cc-8db4-4f1a4cd60a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720574082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1720574082
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3165036196
Short name T1090
Test name
Test status
Simulation time 15281607027 ps
CPU time 27.56 seconds
Started May 12 01:29:08 PM PDT 24
Finished May 12 01:29:36 PM PDT 24
Peak memory 200400 kb
Host smart-6fdd9d48-dcf4-4113-b331-cca244cf75e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165036196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3165036196
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1635549671
Short name T129
Test name
Test status
Simulation time 136345265838 ps
CPU time 106.72 seconds
Started May 12 01:29:07 PM PDT 24
Finished May 12 01:30:54 PM PDT 24
Peak memory 199868 kb
Host smart-a3e97344-d3d3-45f3-ba5e-8a42f3cb3129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635549671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1635549671
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1502105530
Short name T175
Test name
Test status
Simulation time 46348754822 ps
CPU time 79.64 seconds
Started May 12 01:29:06 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 200380 kb
Host smart-e24aa13f-058d-438a-9604-37b68f50761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502105530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1502105530
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1486516560
Short name T854
Test name
Test status
Simulation time 57195444628 ps
CPU time 50.01 seconds
Started May 12 01:29:06 PM PDT 24
Finished May 12 01:29:57 PM PDT 24
Peak memory 200332 kb
Host smart-00dc0d39-4bc5-4e93-965c-5e1558cdbffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486516560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1486516560
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.611176983
Short name T407
Test name
Test status
Simulation time 15726578 ps
CPU time 0.55 seconds
Started May 12 01:25:31 PM PDT 24
Finished May 12 01:25:32 PM PDT 24
Peak memory 195168 kb
Host smart-ddf2f6ea-5fde-426d-964d-e2e40e075caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611176983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.611176983
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.507766998
Short name T539
Test name
Test status
Simulation time 265572951113 ps
CPU time 138.81 seconds
Started May 12 01:25:27 PM PDT 24
Finished May 12 01:27:46 PM PDT 24
Peak memory 200352 kb
Host smart-d31ca03e-11f4-44b3-998f-0a2b44fc49cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507766998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.507766998
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1247750887
Short name T7
Test name
Test status
Simulation time 130189682586 ps
CPU time 114.73 seconds
Started May 12 01:25:25 PM PDT 24
Finished May 12 01:27:20 PM PDT 24
Peak memory 200264 kb
Host smart-bf4b4b8e-7e35-4a06-ab3a-fa7fca8ac2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247750887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1247750887
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1523760742
Short name T216
Test name
Test status
Simulation time 34644446368 ps
CPU time 26.27 seconds
Started May 12 01:25:29 PM PDT 24
Finished May 12 01:25:56 PM PDT 24
Peak memory 200372 kb
Host smart-ccdd48f5-3796-42cc-9b1b-89b7b09414e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523760742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1523760742
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4043892605
Short name T575
Test name
Test status
Simulation time 30163945922 ps
CPU time 62.57 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:26:35 PM PDT 24
Peak memory 200388 kb
Host smart-efb16572-4cbd-43f4-90a2-c55d73dd649e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043892605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4043892605
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3436560297
Short name T562
Test name
Test status
Simulation time 95465564814 ps
CPU time 485.93 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:33:38 PM PDT 24
Peak memory 200080 kb
Host smart-34ccd866-94c1-4050-b489-0cbadeb121da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436560297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3436560297
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3714729266
Short name T752
Test name
Test status
Simulation time 259476802 ps
CPU time 0.88 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:25:33 PM PDT 24
Peak memory 197076 kb
Host smart-142d4c73-9432-435d-9379-9a497154eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714729266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3714729266
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.543123008
Short name T529
Test name
Test status
Simulation time 26854160328 ps
CPU time 38.83 seconds
Started May 12 01:25:29 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 198320 kb
Host smart-8aa6e4c0-4816-45fd-a892-671b1ac24094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543123008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.543123008
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3607025979
Short name T59
Test name
Test status
Simulation time 8594846648 ps
CPU time 124.06 seconds
Started May 12 01:25:35 PM PDT 24
Finished May 12 01:27:40 PM PDT 24
Peak memory 200348 kb
Host smart-680dd73b-db20-40b7-8a64-81ef68681ab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607025979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3607025979
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1708215521
Short name T1035
Test name
Test status
Simulation time 6191550766 ps
CPU time 30.71 seconds
Started May 12 01:25:30 PM PDT 24
Finished May 12 01:26:01 PM PDT 24
Peak memory 198508 kb
Host smart-d0b98171-9c43-49ad-8549-b539bcc431ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708215521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1708215521
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3130315580
Short name T596
Test name
Test status
Simulation time 33409075163 ps
CPU time 13.42 seconds
Started May 12 01:25:29 PM PDT 24
Finished May 12 01:25:43 PM PDT 24
Peak memory 200316 kb
Host smart-0f1607f2-5df8-464b-86c9-9dd98d5e12f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130315580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3130315580
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3081320799
Short name T844
Test name
Test status
Simulation time 40961907706 ps
CPU time 56.53 seconds
Started May 12 01:25:30 PM PDT 24
Finished May 12 01:26:27 PM PDT 24
Peak memory 196364 kb
Host smart-88bb14d4-4d2e-4f1e-b26b-1cc5a49599a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081320799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3081320799
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1756663157
Short name T310
Test name
Test status
Simulation time 959342651 ps
CPU time 1.6 seconds
Started May 12 01:25:28 PM PDT 24
Finished May 12 01:25:30 PM PDT 24
Peak memory 198592 kb
Host smart-5d472f14-06a7-491a-9b08-95d1f4e5c944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756663157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1756663157
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1523757028
Short name T903
Test name
Test status
Simulation time 115190124209 ps
CPU time 211.41 seconds
Started May 12 01:25:31 PM PDT 24
Finished May 12 01:29:03 PM PDT 24
Peak memory 200412 kb
Host smart-08a3fec4-1c4b-48af-9175-25744797bb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523757028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1523757028
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4095472932
Short name T1144
Test name
Test status
Simulation time 70060752830 ps
CPU time 284.02 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:30:16 PM PDT 24
Peak memory 216864 kb
Host smart-bc3a64ed-e095-4667-a7d7-63228c1f1940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095472932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4095472932
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2751511724
Short name T1154
Test name
Test status
Simulation time 335562908 ps
CPU time 1.04 seconds
Started May 12 01:25:31 PM PDT 24
Finished May 12 01:25:33 PM PDT 24
Peak memory 197588 kb
Host smart-ad50825a-d5a6-4252-9df2-b1ed93229965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751511724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2751511724
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.496415948
Short name T656
Test name
Test status
Simulation time 21059752732 ps
CPU time 11.56 seconds
Started May 12 01:25:27 PM PDT 24
Finished May 12 01:25:39 PM PDT 24
Peak memory 200408 kb
Host smart-79c74108-411d-43c3-8402-c26f00e1eedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496415948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.496415948
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.366745954
Short name T223
Test name
Test status
Simulation time 11826071039 ps
CPU time 20.43 seconds
Started May 12 01:29:07 PM PDT 24
Finished May 12 01:29:28 PM PDT 24
Peak memory 200420 kb
Host smart-7ef37235-473e-4189-8123-28c2d4ec0946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366745954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.366745954
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2429740274
Short name T833
Test name
Test status
Simulation time 22552387324 ps
CPU time 10.52 seconds
Started May 12 01:29:07 PM PDT 24
Finished May 12 01:29:18 PM PDT 24
Peak memory 200428 kb
Host smart-55ea9166-6135-4c51-94e8-e5f7f085d089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429740274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2429740274
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2937125409
Short name T732
Test name
Test status
Simulation time 3229092772 ps
CPU time 6.18 seconds
Started May 12 01:29:11 PM PDT 24
Finished May 12 01:29:18 PM PDT 24
Peak memory 200312 kb
Host smart-be34078b-15f4-4907-9cb4-fc9d6f819d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937125409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2937125409
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1770385445
Short name T163
Test name
Test status
Simulation time 50496335802 ps
CPU time 24.91 seconds
Started May 12 01:29:12 PM PDT 24
Finished May 12 01:29:37 PM PDT 24
Peak memory 200424 kb
Host smart-3b3f1594-e584-41de-9661-8004be8d2cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770385445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1770385445
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.482937785
Short name T1031
Test name
Test status
Simulation time 115244455108 ps
CPU time 172.31 seconds
Started May 12 01:29:10 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 200372 kb
Host smart-3ed6cb3a-ebaa-48ca-9dea-e782cba6df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482937785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.482937785
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3839043811
Short name T208
Test name
Test status
Simulation time 34048957544 ps
CPU time 61.41 seconds
Started May 12 01:29:10 PM PDT 24
Finished May 12 01:30:11 PM PDT 24
Peak memory 200228 kb
Host smart-9765aed4-54ac-4b0d-ae82-4c52f3eb9513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839043811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3839043811
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.730613853
Short name T533
Test name
Test status
Simulation time 152996281181 ps
CPU time 28.34 seconds
Started May 12 01:29:10 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 200388 kb
Host smart-e4069fa3-790a-4d33-9623-6ee0cc3a6755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730613853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.730613853
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3410137637
Short name T149
Test name
Test status
Simulation time 151467102287 ps
CPU time 400.07 seconds
Started May 12 01:29:11 PM PDT 24
Finished May 12 01:35:52 PM PDT 24
Peak memory 200348 kb
Host smart-2a8000ff-fb37-45ea-a517-f900ed484aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410137637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3410137637
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1090671201
Short name T315
Test name
Test status
Simulation time 195517182141 ps
CPU time 289.09 seconds
Started May 12 01:29:11 PM PDT 24
Finished May 12 01:34:01 PM PDT 24
Peak memory 200340 kb
Host smart-3a785a80-ac5a-47f1-a777-eb96cb0bdb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090671201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1090671201
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1040401431
Short name T373
Test name
Test status
Simulation time 46089328 ps
CPU time 0.53 seconds
Started May 12 01:25:35 PM PDT 24
Finished May 12 01:25:36 PM PDT 24
Peak memory 195780 kb
Host smart-0a1bbaf4-1c7d-467e-b5d2-147ba3e2c35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040401431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1040401431
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.713055281
Short name T1021
Test name
Test status
Simulation time 92764414946 ps
CPU time 151.72 seconds
Started May 12 01:25:31 PM PDT 24
Finished May 12 01:28:03 PM PDT 24
Peak memory 200412 kb
Host smart-68df4e6d-dc21-422e-bf14-927c8660c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713055281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.713055281
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2385841149
Short name T527
Test name
Test status
Simulation time 171427085728 ps
CPU time 159.41 seconds
Started May 12 01:25:30 PM PDT 24
Finished May 12 01:28:10 PM PDT 24
Peak memory 200340 kb
Host smart-6d3cd29d-741f-4eee-9f4f-f2504b90c220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385841149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2385841149
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2304808318
Short name T248
Test name
Test status
Simulation time 27333557752 ps
CPU time 19.63 seconds
Started May 12 01:25:37 PM PDT 24
Finished May 12 01:25:57 PM PDT 24
Peak memory 200280 kb
Host smart-d6a3489d-19a8-4238-8501-4fa3957f6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304808318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2304808318
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3932267578
Short name T674
Test name
Test status
Simulation time 8363238342 ps
CPU time 2.32 seconds
Started May 12 01:25:33 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 200392 kb
Host smart-de90dae3-6972-4d1d-b26d-e2f98b3d13e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932267578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3932267578
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.412334006
Short name T600
Test name
Test status
Simulation time 78470436990 ps
CPU time 554.84 seconds
Started May 12 01:25:33 PM PDT 24
Finished May 12 01:34:48 PM PDT 24
Peak memory 200356 kb
Host smart-533e6299-2351-4865-8e71-d59d0139ebf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412334006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.412334006
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2685140523
Short name T747
Test name
Test status
Simulation time 11022803942 ps
CPU time 11.12 seconds
Started May 12 01:25:33 PM PDT 24
Finished May 12 01:25:44 PM PDT 24
Peak memory 199400 kb
Host smart-d44aab9a-e35f-4ebb-abb9-01f2194010cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685140523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2685140523
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4055853487
Short name T377
Test name
Test status
Simulation time 72715332153 ps
CPU time 103.15 seconds
Started May 12 01:25:34 PM PDT 24
Finished May 12 01:27:17 PM PDT 24
Peak memory 199664 kb
Host smart-5186a8c2-9c4f-4560-bcbd-16772e04e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055853487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4055853487
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2516618314
Short name T402
Test name
Test status
Simulation time 22080415514 ps
CPU time 1222.84 seconds
Started May 12 01:25:35 PM PDT 24
Finished May 12 01:45:59 PM PDT 24
Peak memory 200348 kb
Host smart-a172cec3-2de5-49ce-b7c6-2741ceb0f9f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516618314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2516618314
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1401808954
Short name T745
Test name
Test status
Simulation time 3927866413 ps
CPU time 5.78 seconds
Started May 12 01:25:36 PM PDT 24
Finished May 12 01:25:42 PM PDT 24
Peak memory 199532 kb
Host smart-f441ef62-1a9b-4624-89db-8c7c5962460f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401808954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1401808954
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1499078308
Short name T967
Test name
Test status
Simulation time 69813912474 ps
CPU time 28.67 seconds
Started May 12 01:25:36 PM PDT 24
Finished May 12 01:26:05 PM PDT 24
Peak memory 200096 kb
Host smart-9038d82f-38aa-49bd-9bd9-73cf526eaa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499078308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1499078308
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.759603610
Short name T924
Test name
Test status
Simulation time 3100779630 ps
CPU time 5.5 seconds
Started May 12 01:25:35 PM PDT 24
Finished May 12 01:25:41 PM PDT 24
Peak memory 196376 kb
Host smart-c1f45d7c-2e61-4d3c-a2df-a43344392f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759603610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.759603610
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2615530194
Short name T466
Test name
Test status
Simulation time 527425781 ps
CPU time 2.28 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:25:35 PM PDT 24
Peak memory 198968 kb
Host smart-a289bb75-0b00-488c-bc54-a18ee9f8e000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615530194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2615530194
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3916251696
Short name T227
Test name
Test status
Simulation time 455768808397 ps
CPU time 204.44 seconds
Started May 12 01:25:34 PM PDT 24
Finished May 12 01:28:59 PM PDT 24
Peak memory 200424 kb
Host smart-75ff39f7-d5ae-424b-81cb-dfa0e11b2c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916251696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3916251696
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2650190958
Short name T1037
Test name
Test status
Simulation time 83928862121 ps
CPU time 948.17 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:41:21 PM PDT 24
Peak memory 225076 kb
Host smart-c38c83fa-8812-426c-90ee-a9310d28b79e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650190958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2650190958
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2493463925
Short name T947
Test name
Test status
Simulation time 7231133425 ps
CPU time 2.01 seconds
Started May 12 01:25:33 PM PDT 24
Finished May 12 01:25:36 PM PDT 24
Peak memory 199784 kb
Host smart-1d2447de-faf9-4f01-9ed3-268e1e9d8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493463925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2493463925
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2157301016
Short name T905
Test name
Test status
Simulation time 5930717866 ps
CPU time 5.11 seconds
Started May 12 01:25:32 PM PDT 24
Finished May 12 01:25:38 PM PDT 24
Peak memory 198844 kb
Host smart-a0e6788f-6934-4ff4-8c6d-9e4a44702b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157301016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2157301016
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.318160685
Short name T243
Test name
Test status
Simulation time 36157362112 ps
CPU time 23.38 seconds
Started May 12 01:29:11 PM PDT 24
Finished May 12 01:29:35 PM PDT 24
Peak memory 200336 kb
Host smart-68754560-dee6-41fa-8ed2-f9a2a8185a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318160685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.318160685
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3810640444
Short name T964
Test name
Test status
Simulation time 46224648146 ps
CPU time 23.38 seconds
Started May 12 01:29:12 PM PDT 24
Finished May 12 01:29:36 PM PDT 24
Peak memory 200352 kb
Host smart-6700c5b5-1adc-4d33-b0e3-eef0f07782e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810640444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3810640444
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3090381776
Short name T513
Test name
Test status
Simulation time 205433986078 ps
CPU time 123.04 seconds
Started May 12 01:29:11 PM PDT 24
Finished May 12 01:31:15 PM PDT 24
Peak memory 200348 kb
Host smart-ee565e1b-947d-46ee-9f4c-5f4c3f692a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090381776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3090381776
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2496203275
Short name T915
Test name
Test status
Simulation time 31732158475 ps
CPU time 30.86 seconds
Started May 12 01:29:16 PM PDT 24
Finished May 12 01:29:47 PM PDT 24
Peak memory 200316 kb
Host smart-363f2db6-04a1-47a2-908c-2488e33c7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496203275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2496203275
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.891490699
Short name T218
Test name
Test status
Simulation time 45205080468 ps
CPU time 35.95 seconds
Started May 12 01:29:16 PM PDT 24
Finished May 12 01:29:53 PM PDT 24
Peak memory 200344 kb
Host smart-12ff0b97-4dbb-45d8-8825-d81fade4ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891490699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.891490699
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3326068679
Short name T928
Test name
Test status
Simulation time 74576376524 ps
CPU time 307.03 seconds
Started May 12 01:29:16 PM PDT 24
Finished May 12 01:34:24 PM PDT 24
Peak memory 200284 kb
Host smart-5006d9df-f7d7-4c4e-aa0c-99bcd131e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326068679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3326068679
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3197931847
Short name T838
Test name
Test status
Simulation time 21892800305 ps
CPU time 9.54 seconds
Started May 12 01:29:14 PM PDT 24
Finished May 12 01:29:24 PM PDT 24
Peak memory 200380 kb
Host smart-b8ac75bb-38e3-4d8a-ab52-171dd78f4a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197931847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3197931847
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4099207408
Short name T453
Test name
Test status
Simulation time 2654860455 ps
CPU time 5.02 seconds
Started May 12 01:29:15 PM PDT 24
Finished May 12 01:29:21 PM PDT 24
Peak memory 200332 kb
Host smart-937c868c-34c9-489f-9d21-11b5a896e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099207408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4099207408
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1166195860
Short name T164
Test name
Test status
Simulation time 102226440818 ps
CPU time 159.11 seconds
Started May 12 01:29:18 PM PDT 24
Finished May 12 01:31:58 PM PDT 24
Peak memory 200324 kb
Host smart-e4fa9039-6ca2-40b4-a6c6-eccdf8875ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166195860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1166195860
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3299266109
Short name T503
Test name
Test status
Simulation time 13362722 ps
CPU time 0.55 seconds
Started May 12 01:25:39 PM PDT 24
Finished May 12 01:25:40 PM PDT 24
Peak memory 195776 kb
Host smart-b6bdc5c9-a234-47a9-8121-860dbc370891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299266109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3299266109
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2921997944
Short name T795
Test name
Test status
Simulation time 88615348523 ps
CPU time 147.92 seconds
Started May 12 01:25:37 PM PDT 24
Finished May 12 01:28:05 PM PDT 24
Peak memory 200168 kb
Host smart-f3c04ecd-18fd-4047-9ec0-bd86514b75ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921997944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2921997944
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.907573109
Short name T283
Test name
Test status
Simulation time 27710379049 ps
CPU time 72.18 seconds
Started May 12 01:25:38 PM PDT 24
Finished May 12 01:26:50 PM PDT 24
Peak memory 200260 kb
Host smart-762e8f6b-9367-43b5-96d4-fa6b94ea07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907573109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.907573109
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.91496740
Short name T241
Test name
Test status
Simulation time 222410167549 ps
CPU time 22.98 seconds
Started May 12 01:25:38 PM PDT 24
Finished May 12 01:26:01 PM PDT 24
Peak memory 200316 kb
Host smart-68bd6033-e0dd-4cd6-841c-38a3cb729f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91496740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.91496740
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1936914975
Short name T760
Test name
Test status
Simulation time 23173593435 ps
CPU time 14.79 seconds
Started May 12 01:25:39 PM PDT 24
Finished May 12 01:25:54 PM PDT 24
Peak memory 200148 kb
Host smart-d368b773-e50d-4f69-a143-55afd8bb75c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936914975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1936914975
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.232829277
Short name T400
Test name
Test status
Simulation time 133028127043 ps
CPU time 1328.34 seconds
Started May 12 01:25:42 PM PDT 24
Finished May 12 01:47:51 PM PDT 24
Peak memory 200376 kb
Host smart-59573f61-93f8-4135-ac54-c0e3f61b374e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232829277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.232829277
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3725990956
Short name T131
Test name
Test status
Simulation time 9936003203 ps
CPU time 5.08 seconds
Started May 12 01:25:40 PM PDT 24
Finished May 12 01:25:45 PM PDT 24
Peak memory 200136 kb
Host smart-a5ef12e3-e658-467d-8cf4-0e8a64803061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725990956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3725990956
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2911445092
Short name T354
Test name
Test status
Simulation time 44999976955 ps
CPU time 18.39 seconds
Started May 12 01:25:36 PM PDT 24
Finished May 12 01:25:55 PM PDT 24
Peak memory 199068 kb
Host smart-50b53c8b-9a5a-4976-8acf-a9711e1ef79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911445092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2911445092
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.250662378
Short name T676
Test name
Test status
Simulation time 19588791505 ps
CPU time 153.19 seconds
Started May 12 01:25:42 PM PDT 24
Finished May 12 01:28:15 PM PDT 24
Peak memory 200336 kb
Host smart-145675bd-513b-47eb-aa43-5bf31f87eca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250662378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.250662378
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3097585275
Short name T2
Test name
Test status
Simulation time 1601649175 ps
CPU time 3.33 seconds
Started May 12 01:25:39 PM PDT 24
Finished May 12 01:25:42 PM PDT 24
Peak memory 198312 kb
Host smart-9c1e5374-9c3a-49d9-84da-0ed06a2d9944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097585275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3097585275
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1746597871
Short name T1088
Test name
Test status
Simulation time 70810675011 ps
CPU time 30.06 seconds
Started May 12 01:25:37 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 200260 kb
Host smart-e0cc3a16-5d06-43b2-86c8-e6a18c8fe9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746597871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1746597871
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3048875440
Short name T421
Test name
Test status
Simulation time 509291535 ps
CPU time 1.53 seconds
Started May 12 01:25:37 PM PDT 24
Finished May 12 01:25:39 PM PDT 24
Peak memory 195620 kb
Host smart-eb298ef4-b194-4fbd-9e0b-e7f6bdf059dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048875440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3048875440
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1655126426
Short name T285
Test name
Test status
Simulation time 5893971130 ps
CPU time 35.62 seconds
Started May 12 01:25:34 PM PDT 24
Finished May 12 01:26:10 PM PDT 24
Peak memory 199940 kb
Host smart-d1b75deb-0dfc-45ef-afa8-23b9183fe543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655126426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1655126426
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1489729190
Short name T918
Test name
Test status
Simulation time 18241803278 ps
CPU time 40.68 seconds
Started May 12 01:25:40 PM PDT 24
Finished May 12 01:26:21 PM PDT 24
Peak memory 200320 kb
Host smart-57782ce8-42d5-4786-83a0-a29c50526f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489729190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1489729190
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3715416037
Short name T828
Test name
Test status
Simulation time 6139604000 ps
CPU time 10.77 seconds
Started May 12 01:25:37 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 199660 kb
Host smart-46b6fd87-5b01-4ab0-a95d-16f117068c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715416037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3715416037
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2567945483
Short name T798
Test name
Test status
Simulation time 50132821132 ps
CPU time 52.41 seconds
Started May 12 01:25:37 PM PDT 24
Finished May 12 01:26:30 PM PDT 24
Peak memory 200416 kb
Host smart-d8b4c8fe-3efe-4f9f-af4f-6a13a6ac70b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567945483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2567945483
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3331412361
Short name T688
Test name
Test status
Simulation time 32466852386 ps
CPU time 35.64 seconds
Started May 12 01:29:16 PM PDT 24
Finished May 12 01:29:52 PM PDT 24
Peak memory 200344 kb
Host smart-103b9aba-d681-48d0-a8c5-771a6ba6e263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331412361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3331412361
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.425097674
Short name T327
Test name
Test status
Simulation time 16119209482 ps
CPU time 12.35 seconds
Started May 12 01:29:16 PM PDT 24
Finished May 12 01:29:29 PM PDT 24
Peak memory 200124 kb
Host smart-3f8b0bc8-76f2-461f-848a-ce0da6437a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425097674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.425097674
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2008045278
Short name T801
Test name
Test status
Simulation time 55680795914 ps
CPU time 55.83 seconds
Started May 12 01:29:16 PM PDT 24
Finished May 12 01:30:13 PM PDT 24
Peak memory 200360 kb
Host smart-4ac92394-5f75-44a5-bc05-c6aecc6b8cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008045278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2008045278
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.740877375
Short name T512
Test name
Test status
Simulation time 21868128786 ps
CPU time 20.71 seconds
Started May 12 01:29:18 PM PDT 24
Finished May 12 01:29:39 PM PDT 24
Peak memory 200360 kb
Host smart-27bd4ab3-4285-47f5-af58-72af38fc265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740877375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.740877375
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3063004240
Short name T211
Test name
Test status
Simulation time 219915531652 ps
CPU time 104.43 seconds
Started May 12 01:29:17 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 200264 kb
Host smart-86e797f8-fd65-45f2-8105-48aaddc379fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063004240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3063004240
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1173447696
Short name T521
Test name
Test status
Simulation time 12142592694 ps
CPU time 23.67 seconds
Started May 12 01:29:19 PM PDT 24
Finished May 12 01:29:43 PM PDT 24
Peak memory 200360 kb
Host smart-6a859485-af99-4a9d-833c-289725d29141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173447696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1173447696
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2486055265
Short name T165
Test name
Test status
Simulation time 23479056471 ps
CPU time 26.85 seconds
Started May 12 01:29:17 PM PDT 24
Finished May 12 01:29:45 PM PDT 24
Peak memory 200324 kb
Host smart-c8f5fef7-acd4-4656-aae8-bf28b1359ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486055265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2486055265
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2529962495
Short name T1007
Test name
Test status
Simulation time 136885187924 ps
CPU time 131.81 seconds
Started May 12 01:29:22 PM PDT 24
Finished May 12 01:31:35 PM PDT 24
Peak memory 200336 kb
Host smart-110734ef-0edf-4a76-8ac0-7226f1f2d40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529962495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2529962495
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2662210530
Short name T932
Test name
Test status
Simulation time 41578542 ps
CPU time 0.55 seconds
Started May 12 01:25:47 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 195152 kb
Host smart-952f7507-5162-4c4f-b5ec-cb132f82de1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662210530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2662210530
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.649669745
Short name T552
Test name
Test status
Simulation time 25938320793 ps
CPU time 11.14 seconds
Started May 12 01:25:41 PM PDT 24
Finished May 12 01:25:52 PM PDT 24
Peak memory 200356 kb
Host smart-c00bcc2d-6d32-4c52-aefa-fc3d6a7bbcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649669745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.649669745
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1358911955
Short name T824
Test name
Test status
Simulation time 15985853248 ps
CPU time 33.72 seconds
Started May 12 01:25:41 PM PDT 24
Finished May 12 01:26:15 PM PDT 24
Peak memory 200336 kb
Host smart-874dd952-4119-49fe-80c3-77bc35233d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358911955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1358911955
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.228305267
Short name T1117
Test name
Test status
Simulation time 8179834952 ps
CPU time 14.8 seconds
Started May 12 01:25:42 PM PDT 24
Finished May 12 01:25:57 PM PDT 24
Peak memory 200424 kb
Host smart-14c97e99-d836-49c0-b0d0-4b923b362b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228305267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.228305267
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.167416886
Short name T597
Test name
Test status
Simulation time 69240030972 ps
CPU time 113.26 seconds
Started May 12 01:25:41 PM PDT 24
Finished May 12 01:27:34 PM PDT 24
Peak memory 199916 kb
Host smart-a5131f7d-6306-41ea-af24-1431ebb39d47
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167416886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.167416886
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.839721946
Short name T401
Test name
Test status
Simulation time 191495519845 ps
CPU time 459.09 seconds
Started May 12 01:25:44 PM PDT 24
Finished May 12 01:33:24 PM PDT 24
Peak memory 200340 kb
Host smart-0a0039b0-11ac-48d5-b0f0-1951ceb9c7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839721946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.839721946
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2819908939
Short name T57
Test name
Test status
Simulation time 4079827776 ps
CPU time 3.19 seconds
Started May 12 01:25:45 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 198988 kb
Host smart-a081bb02-2e9e-4625-b296-066f83c5ea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819908939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2819908939
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1059659696
Short name T29
Test name
Test status
Simulation time 49677367748 ps
CPU time 77.69 seconds
Started May 12 01:25:41 PM PDT 24
Finished May 12 01:26:59 PM PDT 24
Peak memory 200516 kb
Host smart-ce4548c4-3fbe-4d85-bd39-4f924abc6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059659696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1059659696
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4204045902
Short name T326
Test name
Test status
Simulation time 20358052892 ps
CPU time 401.78 seconds
Started May 12 01:25:43 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 200388 kb
Host smart-9ed8dbc6-10bf-45e7-892d-ee10c976bc14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204045902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4204045902
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1544695786
Short name T619
Test name
Test status
Simulation time 5064878320 ps
CPU time 7.96 seconds
Started May 12 01:25:41 PM PDT 24
Finished May 12 01:25:49 PM PDT 24
Peak memory 199664 kb
Host smart-b4e6ffde-b0ae-4a12-a8f3-7ad74b3b492c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544695786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1544695786
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.239628584
Short name T1055
Test name
Test status
Simulation time 214712034709 ps
CPU time 79.8 seconds
Started May 12 01:25:44 PM PDT 24
Finished May 12 01:27:04 PM PDT 24
Peak memory 200324 kb
Host smart-465e3c90-8cde-4698-857b-4f05013b9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239628584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.239628584
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4210937176
Short name T567
Test name
Test status
Simulation time 4870888748 ps
CPU time 4.47 seconds
Started May 12 01:25:43 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 196560 kb
Host smart-69b27f4c-7015-4f8c-a5aa-87393211f840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210937176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4210937176
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3856121567
Short name T1013
Test name
Test status
Simulation time 626754136 ps
CPU time 2.26 seconds
Started May 12 01:25:42 PM PDT 24
Finished May 12 01:25:44 PM PDT 24
Peak memory 200132 kb
Host smart-3301cae2-1c2f-49c9-8990-2692c577e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856121567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3856121567
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3039713586
Short name T944
Test name
Test status
Simulation time 187300935311 ps
CPU time 279.14 seconds
Started May 12 01:25:43 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 200328 kb
Host smart-a154f0ba-c830-41f8-9fd3-48dbcedb37d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039713586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3039713586
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2147729044
Short name T880
Test name
Test status
Simulation time 1057944920 ps
CPU time 2.52 seconds
Started May 12 01:25:45 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 198640 kb
Host smart-1a3992b2-167c-4d4c-9dc6-1f5eafefa859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147729044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2147729044
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2511919917
Short name T990
Test name
Test status
Simulation time 92512914877 ps
CPU time 190.6 seconds
Started May 12 01:25:45 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200412 kb
Host smart-f467efe2-4f6a-4094-ac10-ba9986be11d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511919917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2511919917
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3620102666
Short name T660
Test name
Test status
Simulation time 122365518945 ps
CPU time 103.93 seconds
Started May 12 01:29:19 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 200316 kb
Host smart-dcddd47e-ab57-4bcc-b403-bb6c68170239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620102666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3620102666
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3785596870
Short name T819
Test name
Test status
Simulation time 36272032816 ps
CPU time 31.62 seconds
Started May 12 01:29:18 PM PDT 24
Finished May 12 01:29:50 PM PDT 24
Peak memory 200324 kb
Host smart-2c97a09a-12dd-44a2-9933-4e8390b1f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785596870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3785596870
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2580249608
Short name T460
Test name
Test status
Simulation time 140092892368 ps
CPU time 215.45 seconds
Started May 12 01:29:18 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 200264 kb
Host smart-96a57fc4-37a6-488f-b91e-db983973c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580249608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2580249608
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.564668471
Short name T827
Test name
Test status
Simulation time 136050068909 ps
CPU time 74.14 seconds
Started May 12 01:29:24 PM PDT 24
Finished May 12 01:30:38 PM PDT 24
Peak memory 200612 kb
Host smart-5d1f03c8-3cb2-46cf-ae69-0e3769bcd217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564668471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.564668471
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1741827867
Short name T506
Test name
Test status
Simulation time 13609686641 ps
CPU time 11.63 seconds
Started May 12 01:29:21 PM PDT 24
Finished May 12 01:29:33 PM PDT 24
Peak memory 200368 kb
Host smart-792053d7-9251-42dc-bd8f-0854af527228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741827867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1741827867
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2346966907
Short name T1045
Test name
Test status
Simulation time 23044125403 ps
CPU time 42.86 seconds
Started May 12 01:29:23 PM PDT 24
Finished May 12 01:30:06 PM PDT 24
Peak memory 200336 kb
Host smart-89441edd-067b-41cd-ad37-7a8f0e6cc017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346966907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2346966907
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3623173679
Short name T629
Test name
Test status
Simulation time 28953989057 ps
CPU time 46.97 seconds
Started May 12 01:29:23 PM PDT 24
Finished May 12 01:30:10 PM PDT 24
Peak memory 200432 kb
Host smart-61035dfe-c6ef-47ff-bf1d-746b0fe30d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623173679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3623173679
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3493779580
Short name T958
Test name
Test status
Simulation time 23777079260 ps
CPU time 11.33 seconds
Started May 12 01:29:23 PM PDT 24
Finished May 12 01:29:34 PM PDT 24
Peak memory 200336 kb
Host smart-5d705370-ec53-4d5a-997d-7a4a293112db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493779580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3493779580
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4088981301
Short name T1113
Test name
Test status
Simulation time 37484892037 ps
CPU time 16.69 seconds
Started May 12 01:29:23 PM PDT 24
Finished May 12 01:29:40 PM PDT 24
Peak memory 200368 kb
Host smart-2f9c688b-bd73-4bf0-bd20-5f695c7df100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088981301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4088981301
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4152887106
Short name T925
Test name
Test status
Simulation time 18422755 ps
CPU time 0.54 seconds
Started May 12 01:25:55 PM PDT 24
Finished May 12 01:25:56 PM PDT 24
Peak memory 195156 kb
Host smart-d4f6fd13-23de-499a-a2eb-a51c1d84b8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152887106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4152887106
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.887761072
Short name T30
Test name
Test status
Simulation time 164617753455 ps
CPU time 119.92 seconds
Started May 12 01:25:47 PM PDT 24
Finished May 12 01:27:48 PM PDT 24
Peak memory 200352 kb
Host smart-c9a98502-e99c-4941-a20f-d4441561c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887761072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.887761072
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1077113760
Short name T472
Test name
Test status
Simulation time 15052933727 ps
CPU time 29.3 seconds
Started May 12 01:25:49 PM PDT 24
Finished May 12 01:26:19 PM PDT 24
Peak memory 200340 kb
Host smart-e39021f9-ca6e-43f1-a0e9-d7e4e6dc3bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077113760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1077113760
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3947904132
Short name T1125
Test name
Test status
Simulation time 34690763829 ps
CPU time 51.27 seconds
Started May 12 01:25:47 PM PDT 24
Finished May 12 01:26:38 PM PDT 24
Peak memory 200420 kb
Host smart-0454d4ce-0c69-4695-bb95-48249c1a9f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947904132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3947904132
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3535377715
Short name T444
Test name
Test status
Simulation time 54282172159 ps
CPU time 28.95 seconds
Started May 12 01:25:49 PM PDT 24
Finished May 12 01:26:18 PM PDT 24
Peak memory 200356 kb
Host smart-d9d10d16-78ba-4ce7-a8bb-11705023d681
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535377715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3535377715
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3332591316
Short name T499
Test name
Test status
Simulation time 117231669105 ps
CPU time 389.32 seconds
Started May 12 01:25:52 PM PDT 24
Finished May 12 01:32:22 PM PDT 24
Peak memory 200360 kb
Host smart-dc667ed7-8884-484e-bc6f-1fb0d635979b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332591316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3332591316
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.904723760
Short name T415
Test name
Test status
Simulation time 3007306433 ps
CPU time 1.26 seconds
Started May 12 01:25:52 PM PDT 24
Finished May 12 01:25:53 PM PDT 24
Peak memory 197828 kb
Host smart-1d8f9a94-3db7-4236-862b-9320417ad19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904723760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.904723760
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2776164466
Short name T822
Test name
Test status
Simulation time 282500275523 ps
CPU time 25.12 seconds
Started May 12 01:25:51 PM PDT 24
Finished May 12 01:26:17 PM PDT 24
Peak memory 200556 kb
Host smart-ca0f754f-749e-45f1-b07c-2f8b6aa50aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776164466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2776164466
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1552488548
Short name T616
Test name
Test status
Simulation time 16533289546 ps
CPU time 233.53 seconds
Started May 12 01:25:50 PM PDT 24
Finished May 12 01:29:44 PM PDT 24
Peak memory 200416 kb
Host smart-2d5424f5-8656-4637-867b-a544dc53d116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552488548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1552488548
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3265539913
Short name T829
Test name
Test status
Simulation time 3815318967 ps
CPU time 5.15 seconds
Started May 12 01:25:51 PM PDT 24
Finished May 12 01:25:56 PM PDT 24
Peak memory 198920 kb
Host smart-a1957adb-e1e5-4dc4-8513-21d37e4cbb16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265539913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3265539913
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.666839802
Short name T893
Test name
Test status
Simulation time 38081651799 ps
CPU time 54.42 seconds
Started May 12 01:25:51 PM PDT 24
Finished May 12 01:26:45 PM PDT 24
Peak memory 200276 kb
Host smart-879b66cd-760e-4c7c-9b10-36d05ad010a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666839802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.666839802
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.337301259
Short name T808
Test name
Test status
Simulation time 4802081691 ps
CPU time 4.33 seconds
Started May 12 01:25:51 PM PDT 24
Finished May 12 01:25:56 PM PDT 24
Peak memory 196552 kb
Host smart-5afbb73e-dab5-4a94-91f6-aba565aee74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337301259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.337301259
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3416515026
Short name T634
Test name
Test status
Simulation time 5516878532 ps
CPU time 10.79 seconds
Started May 12 01:25:50 PM PDT 24
Finished May 12 01:26:01 PM PDT 24
Peak memory 200224 kb
Host smart-cd2409ae-bd09-432e-93c6-ba94ddf6c893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416515026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3416515026
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1915864850
Short name T730
Test name
Test status
Simulation time 98279746654 ps
CPU time 117.33 seconds
Started May 12 01:25:56 PM PDT 24
Finished May 12 01:27:53 PM PDT 24
Peak memory 200380 kb
Host smart-e3809115-982c-46ee-ac66-902fbf0bedbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915864850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1915864850
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1199035774
Short name T956
Test name
Test status
Simulation time 237642756529 ps
CPU time 1090.68 seconds
Started May 12 01:25:53 PM PDT 24
Finished May 12 01:44:04 PM PDT 24
Peak memory 216856 kb
Host smart-296e0797-9d1f-4961-82d8-21aba3e057af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199035774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1199035774
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.514005727
Short name T362
Test name
Test status
Simulation time 1049722157 ps
CPU time 1.54 seconds
Started May 12 01:25:53 PM PDT 24
Finished May 12 01:25:55 PM PDT 24
Peak memory 198688 kb
Host smart-901eca7c-eaa4-408d-8dd6-0c929c700b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514005727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.514005727
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1906363016
Short name T886
Test name
Test status
Simulation time 94009883738 ps
CPU time 81.21 seconds
Started May 12 01:25:47 PM PDT 24
Finished May 12 01:27:09 PM PDT 24
Peak memory 200208 kb
Host smart-4a6cee48-3208-43bc-adb9-d4a6429ba723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906363016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1906363016
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3159937205
Short name T994
Test name
Test status
Simulation time 155411686291 ps
CPU time 162.98 seconds
Started May 12 01:29:22 PM PDT 24
Finished May 12 01:32:06 PM PDT 24
Peak memory 200360 kb
Host smart-c008d92f-8c70-400b-9311-b52d762c1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159937205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3159937205
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1593522654
Short name T213
Test name
Test status
Simulation time 112397445178 ps
CPU time 92.02 seconds
Started May 12 01:29:22 PM PDT 24
Finished May 12 01:30:54 PM PDT 24
Peak memory 200316 kb
Host smart-5ca7bd43-2023-4d5b-bd27-f42f924d0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593522654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1593522654
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4159829869
Short name T694
Test name
Test status
Simulation time 133029066393 ps
CPU time 138.13 seconds
Started May 12 01:29:25 PM PDT 24
Finished May 12 01:31:43 PM PDT 24
Peak memory 200364 kb
Host smart-a1f74715-7fc2-464a-81bc-ec6b1143becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159829869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4159829869
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1216206117
Short name T119
Test name
Test status
Simulation time 53400415772 ps
CPU time 9.12 seconds
Started May 12 01:29:27 PM PDT 24
Finished May 12 01:29:37 PM PDT 24
Peak memory 200420 kb
Host smart-c72731c7-b90d-4ea1-9828-a7931ff8cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216206117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1216206117
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4086189490
Short name T1058
Test name
Test status
Simulation time 165176273245 ps
CPU time 20.95 seconds
Started May 12 01:29:27 PM PDT 24
Finished May 12 01:29:49 PM PDT 24
Peak memory 200360 kb
Host smart-90af787b-e398-4169-bbd9-3e7a10f70c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086189490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4086189490
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.53396341
Short name T228
Test name
Test status
Simulation time 7149951384 ps
CPU time 13.65 seconds
Started May 12 01:29:24 PM PDT 24
Finished May 12 01:29:38 PM PDT 24
Peak memory 200404 kb
Host smart-25b31f17-6634-4328-8e78-3122f3155c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53396341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.53396341
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.776954498
Short name T187
Test name
Test status
Simulation time 137832318029 ps
CPU time 55.08 seconds
Started May 12 01:29:29 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200252 kb
Host smart-7cd50689-79f6-481b-ba22-4359bd2e1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776954498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.776954498
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3665073725
Short name T898
Test name
Test status
Simulation time 36670609023 ps
CPU time 28 seconds
Started May 12 01:29:31 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 200352 kb
Host smart-57f7d384-f7a4-49df-9384-d74ff4a1e306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665073725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3665073725
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2017186607
Short name T1159
Test name
Test status
Simulation time 43190695085 ps
CPU time 70.12 seconds
Started May 12 01:29:32 PM PDT 24
Finished May 12 01:30:42 PM PDT 24
Peak memory 200432 kb
Host smart-9773efdb-62d5-4364-b233-50b62c8c3d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017186607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2017186607
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1942045000
Short name T202
Test name
Test status
Simulation time 16186338253 ps
CPU time 5.93 seconds
Started May 12 01:29:38 PM PDT 24
Finished May 12 01:29:44 PM PDT 24
Peak memory 200268 kb
Host smart-b8501b40-1a46-46a1-9081-9a251b4abe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942045000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1942045000
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1507594065
Short name T578
Test name
Test status
Simulation time 12890092 ps
CPU time 0.54 seconds
Started May 12 01:25:58 PM PDT 24
Finished May 12 01:25:59 PM PDT 24
Peak memory 195792 kb
Host smart-29652a05-3cd9-495d-9ba2-61d96186231a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507594065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1507594065
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2225463987
Short name T718
Test name
Test status
Simulation time 29999357863 ps
CPU time 35.16 seconds
Started May 12 01:25:55 PM PDT 24
Finished May 12 01:26:31 PM PDT 24
Peak memory 200328 kb
Host smart-858156ab-5676-456d-a51e-9daa892ba577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225463987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2225463987
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4273852730
Short name T312
Test name
Test status
Simulation time 182798283713 ps
CPU time 428.11 seconds
Started May 12 01:25:55 PM PDT 24
Finished May 12 01:33:04 PM PDT 24
Peak memory 200604 kb
Host smart-06ab68bb-6c86-4ec2-95f9-a4c67b477ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273852730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4273852730
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4227694630
Short name T435
Test name
Test status
Simulation time 119327599983 ps
CPU time 208.38 seconds
Started May 12 01:25:57 PM PDT 24
Finished May 12 01:29:26 PM PDT 24
Peak memory 200380 kb
Host smart-ae9cc4b9-b6f9-4a8d-8d90-ea7845c8bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227694630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4227694630
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2929410081
Short name T530
Test name
Test status
Simulation time 11221428297 ps
CPU time 5.25 seconds
Started May 12 01:25:56 PM PDT 24
Finished May 12 01:26:02 PM PDT 24
Peak memory 196848 kb
Host smart-fee255f2-aef2-44de-a725-802b809a0d0c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929410081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2929410081
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.826214266
Short name T275
Test name
Test status
Simulation time 64822513376 ps
CPU time 347.55 seconds
Started May 12 01:25:58 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 200432 kb
Host smart-4df033d7-8442-4efe-b33b-5c13175d52ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826214266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.826214266
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2385163905
Short name T348
Test name
Test status
Simulation time 11992442660 ps
CPU time 7.42 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:26:13 PM PDT 24
Peak memory 199328 kb
Host smart-e306a9eb-0749-4aec-8262-0be09e4f2d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385163905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2385163905
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3874041723
Short name T457
Test name
Test status
Simulation time 41296042224 ps
CPU time 71.77 seconds
Started May 12 01:25:55 PM PDT 24
Finished May 12 01:27:08 PM PDT 24
Peak memory 200224 kb
Host smart-2440627c-cee3-4dc4-8f61-0ffc29928812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874041723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3874041723
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1901819731
Short name T651
Test name
Test status
Simulation time 12830058539 ps
CPU time 47.81 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:26:53 PM PDT 24
Peak memory 200308 kb
Host smart-9cf752c0-3b0a-44c3-9522-a3d95d39b7ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901819731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1901819731
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2900444733
Short name T845
Test name
Test status
Simulation time 3983515765 ps
CPU time 11.97 seconds
Started May 12 01:25:57 PM PDT 24
Finished May 12 01:26:09 PM PDT 24
Peak memory 198752 kb
Host smart-25e1a399-0cc7-441b-956d-468ea56c8e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900444733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2900444733
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2405185496
Short name T617
Test name
Test status
Simulation time 269871343672 ps
CPU time 115.62 seconds
Started May 12 01:25:59 PM PDT 24
Finished May 12 01:27:54 PM PDT 24
Peak memory 200320 kb
Host smart-0a411b33-e49a-4f62-b087-9b2981c11cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405185496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2405185496
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3142388632
Short name T719
Test name
Test status
Simulation time 4482456890 ps
CPU time 2.72 seconds
Started May 12 01:25:59 PM PDT 24
Finished May 12 01:26:02 PM PDT 24
Peak memory 196680 kb
Host smart-e0e078a7-5b36-4420-b272-a4ff9fc5406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142388632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3142388632
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1148917189
Short name T1094
Test name
Test status
Simulation time 11062523216 ps
CPU time 19.62 seconds
Started May 12 01:25:57 PM PDT 24
Finished May 12 01:26:17 PM PDT 24
Peak memory 200400 kb
Host smart-7ee935e9-f617-4f1e-81ff-4ebe95b9cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148917189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1148917189
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1187892480
Short name T792
Test name
Test status
Simulation time 262592144094 ps
CPU time 132.71 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:28:18 PM PDT 24
Peak memory 200272 kb
Host smart-397d08f1-ba50-42a6-a805-9308107835a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187892480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1187892480
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.233417264
Short name T1001
Test name
Test status
Simulation time 145301823407 ps
CPU time 414.37 seconds
Started May 12 01:25:59 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 215512 kb
Host smart-458a0e2e-22a6-4b25-b862-29a7a0e9630e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233417264 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.233417264
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.997324733
Short name T314
Test name
Test status
Simulation time 6913406100 ps
CPU time 11.65 seconds
Started May 12 01:25:58 PM PDT 24
Finished May 12 01:26:10 PM PDT 24
Peak memory 200276 kb
Host smart-2726a130-97a3-49e8-83cc-be0ac4bb2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997324733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.997324733
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3407803783
Short name T1039
Test name
Test status
Simulation time 118653739470 ps
CPU time 53.37 seconds
Started May 12 01:25:57 PM PDT 24
Finished May 12 01:26:50 PM PDT 24
Peak memory 200288 kb
Host smart-7562a1f5-5d58-4e2b-8c34-b67ee7ddd674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407803783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3407803783
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2503781465
Short name T364
Test name
Test status
Simulation time 116972716281 ps
CPU time 51.28 seconds
Started May 12 01:29:32 PM PDT 24
Finished May 12 01:30:24 PM PDT 24
Peak memory 200548 kb
Host smart-0ae18136-c474-4b10-821a-bfa1166073dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503781465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2503781465
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3068121302
Short name T197
Test name
Test status
Simulation time 150788305922 ps
CPU time 70.85 seconds
Started May 12 01:29:29 PM PDT 24
Finished May 12 01:30:40 PM PDT 24
Peak memory 200400 kb
Host smart-90c816c2-ccea-49d7-a819-4301acfa2bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068121302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3068121302
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3351895570
Short name T224
Test name
Test status
Simulation time 158220600554 ps
CPU time 74.4 seconds
Started May 12 01:29:31 PM PDT 24
Finished May 12 01:30:45 PM PDT 24
Peak memory 200428 kb
Host smart-98fd2090-f24e-454c-a473-0639cd879722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351895570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3351895570
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1972345886
Short name T858
Test name
Test status
Simulation time 17509139053 ps
CPU time 26.56 seconds
Started May 12 01:29:39 PM PDT 24
Finished May 12 01:30:06 PM PDT 24
Peak memory 200264 kb
Host smart-48bf3451-1c30-44e3-bb84-a79e0b00cebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972345886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1972345886
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1631024593
Short name T257
Test name
Test status
Simulation time 94698747327 ps
CPU time 43.35 seconds
Started May 12 01:29:38 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 200328 kb
Host smart-2037e7bb-047c-4f07-bfcd-af24c3d6591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631024593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1631024593
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.17270164
Short name T1017
Test name
Test status
Simulation time 9953628093 ps
CPU time 16.14 seconds
Started May 12 01:29:38 PM PDT 24
Finished May 12 01:29:55 PM PDT 24
Peak memory 200280 kb
Host smart-9aee78cf-1612-4e93-82c1-90c30fbe1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17270164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.17270164
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3310664833
Short name T655
Test name
Test status
Simulation time 96766885405 ps
CPU time 209.73 seconds
Started May 12 01:29:38 PM PDT 24
Finished May 12 01:33:09 PM PDT 24
Peak memory 200244 kb
Host smart-3cd56795-7eae-411e-aca0-f81cd4c86f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310664833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3310664833
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.907079553
Short name T751
Test name
Test status
Simulation time 67821547759 ps
CPU time 30.85 seconds
Started May 12 01:29:38 PM PDT 24
Finished May 12 01:30:10 PM PDT 24
Peak memory 199844 kb
Host smart-e417d305-297a-4344-80fd-7fe4328c1c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907079553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.907079553
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4080728024
Short name T1052
Test name
Test status
Simulation time 95297409123 ps
CPU time 11.66 seconds
Started May 12 01:29:30 PM PDT 24
Finished May 12 01:29:42 PM PDT 24
Peak memory 200348 kb
Host smart-4f1d0890-b293-4a7e-a32a-b831ec7c8894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080728024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4080728024
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2927329604
Short name T478
Test name
Test status
Simulation time 11225661 ps
CPU time 0.57 seconds
Started May 12 01:26:03 PM PDT 24
Finished May 12 01:26:04 PM PDT 24
Peak memory 194744 kb
Host smart-2675b9a3-2de9-4bfb-b56d-6cd4be47f28b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927329604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2927329604
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2907013096
Short name T548
Test name
Test status
Simulation time 47549100421 ps
CPU time 89.87 seconds
Started May 12 01:26:00 PM PDT 24
Finished May 12 01:27:30 PM PDT 24
Peak memory 200372 kb
Host smart-eb8e986d-f21f-41f3-aa66-fea728e39d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907013096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2907013096
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.237049328
Short name T794
Test name
Test status
Simulation time 233302051034 ps
CPU time 54.26 seconds
Started May 12 01:26:04 PM PDT 24
Finished May 12 01:26:59 PM PDT 24
Peak memory 200252 kb
Host smart-0576767d-bda0-4685-880a-8c9c02e0a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237049328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.237049328
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.3698002414
Short name T992
Test name
Test status
Simulation time 2214581240 ps
CPU time 2.39 seconds
Started May 12 01:26:00 PM PDT 24
Finished May 12 01:26:03 PM PDT 24
Peak memory 197004 kb
Host smart-8949617b-cfc7-45ca-99ca-05d4da732098
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698002414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3698002414
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2402861478
Short name T635
Test name
Test status
Simulation time 67132968415 ps
CPU time 562.49 seconds
Started May 12 01:26:03 PM PDT 24
Finished May 12 01:35:26 PM PDT 24
Peak memory 200304 kb
Host smart-533086a4-5880-449f-a524-fd5f6887f37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402861478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2402861478
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1236846485
Short name T943
Test name
Test status
Simulation time 5126806204 ps
CPU time 2.74 seconds
Started May 12 01:26:02 PM PDT 24
Finished May 12 01:26:05 PM PDT 24
Peak memory 199152 kb
Host smart-4f326015-bc6a-4fb2-8687-32d99fe7f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236846485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1236846485
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.270825647
Short name T558
Test name
Test status
Simulation time 69619121290 ps
CPU time 31.77 seconds
Started May 12 01:26:01 PM PDT 24
Finished May 12 01:26:33 PM PDT 24
Peak memory 200160 kb
Host smart-8ef60757-5912-4cf7-b02f-2913e7e0760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270825647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.270825647
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3796762646
Short name T369
Test name
Test status
Simulation time 6948498519 ps
CPU time 92.06 seconds
Started May 12 01:26:03 PM PDT 24
Finished May 12 01:27:35 PM PDT 24
Peak memory 200384 kb
Host smart-7c27adc5-836e-4c98-84ae-2112d3adf0c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796762646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3796762646
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2693564438
Short name T528
Test name
Test status
Simulation time 7040689070 ps
CPU time 6.34 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:26:13 PM PDT 24
Peak memory 199456 kb
Host smart-79bb3e44-247e-41bc-b960-64fcedc14a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693564438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2693564438
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3696931709
Short name T128
Test name
Test status
Simulation time 124294254105 ps
CPU time 55.89 seconds
Started May 12 01:26:01 PM PDT 24
Finished May 12 01:26:57 PM PDT 24
Peak memory 200380 kb
Host smart-8d8414cb-9785-4d64-bbfc-3c2734dbff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696931709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3696931709
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1725588597
Short name T294
Test name
Test status
Simulation time 1319221099 ps
CPU time 1.82 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:26:07 PM PDT 24
Peak memory 195744 kb
Host smart-8dd9558b-b1ff-42b1-8a0e-0756e91a766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725588597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1725588597
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2576332990
Short name T805
Test name
Test status
Simulation time 685015937 ps
CPU time 1.78 seconds
Started May 12 01:25:59 PM PDT 24
Finished May 12 01:26:01 PM PDT 24
Peak memory 200080 kb
Host smart-757aa381-196f-4409-a818-b3ccda38042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576332990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2576332990
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2181676937
Short name T982
Test name
Test status
Simulation time 51857841860 ps
CPU time 127.23 seconds
Started May 12 01:26:01 PM PDT 24
Finished May 12 01:28:08 PM PDT 24
Peak memory 216940 kb
Host smart-dd5b9367-e7d7-4ddc-af3c-0a8aa92960c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181676937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2181676937
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1400154975
Short name T755
Test name
Test status
Simulation time 296685898458 ps
CPU time 832.19 seconds
Started May 12 01:26:01 PM PDT 24
Finished May 12 01:39:54 PM PDT 24
Peak memory 224988 kb
Host smart-18ffd397-1460-489a-8aa7-9fd629bab028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400154975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1400154975
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3717831285
Short name T442
Test name
Test status
Simulation time 1282163513 ps
CPU time 1.37 seconds
Started May 12 01:26:02 PM PDT 24
Finished May 12 01:26:04 PM PDT 24
Peak memory 198792 kb
Host smart-0273eb64-c93f-467c-b01e-1843d6f7cd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717831285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3717831285
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3639716233
Short name T985
Test name
Test status
Simulation time 42883155351 ps
CPU time 134.94 seconds
Started May 12 01:25:59 PM PDT 24
Finished May 12 01:28:14 PM PDT 24
Peak memory 200412 kb
Host smart-6f105e6a-80a3-4ca1-a56c-819f0fb83a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639716233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3639716233
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1882062999
Short name T561
Test name
Test status
Simulation time 149448431420 ps
CPU time 314.73 seconds
Started May 12 01:29:30 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 200300 kb
Host smart-16c3740d-cc44-4f83-8d66-085ce0360c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882062999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1882062999
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4204186272
Short name T790
Test name
Test status
Simulation time 62402691626 ps
CPU time 23.34 seconds
Started May 12 01:29:34 PM PDT 24
Finished May 12 01:29:57 PM PDT 24
Peak memory 200128 kb
Host smart-514b0ae8-f9a4-4253-acf9-388fe31acfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204186272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4204186272
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3443422704
Short name T551
Test name
Test status
Simulation time 97485715391 ps
CPU time 253.28 seconds
Started May 12 01:29:33 PM PDT 24
Finished May 12 01:33:47 PM PDT 24
Peak memory 200412 kb
Host smart-0f9a7521-af97-4b29-b1ee-c355c891bdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443422704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3443422704
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3194568396
Short name T219
Test name
Test status
Simulation time 62087659849 ps
CPU time 118.35 seconds
Started May 12 01:29:36 PM PDT 24
Finished May 12 01:31:35 PM PDT 24
Peak memory 200300 kb
Host smart-673c4142-3185-4130-aad8-35c5f4a3ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194568396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3194568396
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2020421374
Short name T299
Test name
Test status
Simulation time 80606437053 ps
CPU time 148.9 seconds
Started May 12 01:29:33 PM PDT 24
Finished May 12 01:32:02 PM PDT 24
Peak memory 200404 kb
Host smart-1587ff22-4246-472c-9d89-5395406dc5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020421374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2020421374
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2716614082
Short name T702
Test name
Test status
Simulation time 34775928445 ps
CPU time 45.4 seconds
Started May 12 01:29:32 PM PDT 24
Finished May 12 01:30:17 PM PDT 24
Peak memory 200336 kb
Host smart-65ca1ecf-6ec4-4e81-9ad5-70e319338047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716614082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2716614082
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3183281231
Short name T800
Test name
Test status
Simulation time 12548716228 ps
CPU time 21.64 seconds
Started May 12 01:29:34 PM PDT 24
Finished May 12 01:29:56 PM PDT 24
Peak memory 200336 kb
Host smart-6a987ae7-0780-41b9-b685-af4439f511d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183281231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3183281231
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1766525893
Short name T206
Test name
Test status
Simulation time 10917648102 ps
CPU time 12.91 seconds
Started May 12 01:29:35 PM PDT 24
Finished May 12 01:29:48 PM PDT 24
Peak memory 200216 kb
Host smart-1bbefa41-6522-4f62-a3f9-9e68273f2590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766525893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1766525893
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1408991924
Short name T182
Test name
Test status
Simulation time 68004373465 ps
CPU time 28.57 seconds
Started May 12 01:29:32 PM PDT 24
Finished May 12 01:30:01 PM PDT 24
Peak memory 200320 kb
Host smart-039f777f-a820-4465-88c9-692ba33e6ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408991924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1408991924
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1131476497
Short name T244
Test name
Test status
Simulation time 265030216285 ps
CPU time 263.49 seconds
Started May 12 01:29:34 PM PDT 24
Finished May 12 01:33:58 PM PDT 24
Peak memory 200336 kb
Host smart-0d324fac-0115-46df-80f3-252ba6020722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131476497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1131476497
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2087854977
Short name T1066
Test name
Test status
Simulation time 14366662 ps
CPU time 0.57 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:24:24 PM PDT 24
Peak memory 195712 kb
Host smart-1c9e6047-55fa-43d7-b9de-6ff6cb62bad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087854977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2087854977
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1386493215
Short name T571
Test name
Test status
Simulation time 35326075898 ps
CPU time 32.03 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:24:55 PM PDT 24
Peak memory 200212 kb
Host smart-97f0f544-9215-4f31-806e-f6ed786f83d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386493215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1386493215
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2655194093
Short name T954
Test name
Test status
Simulation time 20672564138 ps
CPU time 21.57 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:24:46 PM PDT 24
Peak memory 200280 kb
Host smart-6105863c-09dc-40bb-914c-c4a537f0294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655194093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2655194093
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.276855742
Short name T156
Test name
Test status
Simulation time 210733068861 ps
CPU time 374.36 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:30:38 PM PDT 24
Peak memory 200324 kb
Host smart-5028d75c-8340-4cc1-b9d9-512cdde37cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276855742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.276855742
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2113983814
Short name T942
Test name
Test status
Simulation time 10898793662 ps
CPU time 23.1 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:24:46 PM PDT 24
Peak memory 200244 kb
Host smart-cef1e818-5da2-4ed7-907d-877adc580e51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113983814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2113983814
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3447344612
Short name T432
Test name
Test status
Simulation time 123547785961 ps
CPU time 151.92 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:26:59 PM PDT 24
Peak memory 200312 kb
Host smart-5adbf82f-b151-4d5e-a538-0344a0dcfa7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447344612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3447344612
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.411975665
Short name T961
Test name
Test status
Simulation time 10718299707 ps
CPU time 13.08 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 200260 kb
Host smart-f00ade8a-17f3-464d-96de-236d2d89ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411975665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.411975665
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1927302805
Short name T737
Test name
Test status
Simulation time 76626313589 ps
CPU time 71.14 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:25:34 PM PDT 24
Peak memory 200568 kb
Host smart-ecd30f7f-dda8-45b5-9956-3fb4f745c160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927302805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1927302805
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1805754838
Short name T1163
Test name
Test status
Simulation time 21544817330 ps
CPU time 1079.86 seconds
Started May 12 01:24:22 PM PDT 24
Finished May 12 01:42:23 PM PDT 24
Peak memory 200392 kb
Host smart-8fc79f0d-022b-43ec-b8ab-87e608241b6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805754838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1805754838
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3152926912
Short name T1128
Test name
Test status
Simulation time 1168378928 ps
CPU time 2.6 seconds
Started May 12 01:24:23 PM PDT 24
Finished May 12 01:24:26 PM PDT 24
Peak memory 198196 kb
Host smart-b587376d-8821-45f3-905b-79bf8fa109d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3152926912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3152926912
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1499835878
Short name T969
Test name
Test status
Simulation time 84229342857 ps
CPU time 140.04 seconds
Started May 12 01:24:26 PM PDT 24
Finished May 12 01:26:46 PM PDT 24
Peak memory 200328 kb
Host smart-1df75c4b-bba0-45c4-b58c-5b7ec48d0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499835878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1499835878
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1566976549
Short name T679
Test name
Test status
Simulation time 3159621910 ps
CPU time 2.03 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:24:30 PM PDT 24
Peak memory 196304 kb
Host smart-75f3952b-5e1b-4725-9f78-1500654d478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566976549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1566976549
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.2550488212
Short name T1072
Test name
Test status
Simulation time 106839289 ps
CPU time 0.91 seconds
Started May 12 01:24:28 PM PDT 24
Finished May 12 01:24:30 PM PDT 24
Peak memory 198404 kb
Host smart-06ddcf3b-9437-4445-bcb5-c7cb7f93619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550488212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2550488212
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3327678139
Short name T869
Test name
Test status
Simulation time 70793730407 ps
CPU time 102.89 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 200572 kb
Host smart-08ea1470-9862-421b-9636-f6568c1787d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327678139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3327678139
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.870724444
Short name T889
Test name
Test status
Simulation time 141159523606 ps
CPU time 233.62 seconds
Started May 12 01:24:26 PM PDT 24
Finished May 12 01:28:20 PM PDT 24
Peak memory 209500 kb
Host smart-ba599dfb-1b56-481d-8453-5949e8fd44d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870724444 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.870724444
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2679101325
Short name T295
Test name
Test status
Simulation time 1786890093 ps
CPU time 4.01 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:29 PM PDT 24
Peak memory 200260 kb
Host smart-726f43cd-8eab-4d21-9750-e03bf3d64d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679101325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2679101325
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3317829884
Short name T395
Test name
Test status
Simulation time 65410838692 ps
CPU time 32.04 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:57 PM PDT 24
Peak memory 200416 kb
Host smart-2a82e9e6-cb89-46f6-adfe-f2eb378b49fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317829884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3317829884
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.477820301
Short name T749
Test name
Test status
Simulation time 16666956 ps
CPU time 0.56 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:26:06 PM PDT 24
Peak memory 195736 kb
Host smart-5cb2a1e4-e9f6-49e0-9262-8a14e6282d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477820301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.477820301
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1051446699
Short name T686
Test name
Test status
Simulation time 56520716804 ps
CPU time 91.02 seconds
Started May 12 01:26:07 PM PDT 24
Finished May 12 01:27:39 PM PDT 24
Peak memory 200396 kb
Host smart-bed8b7ce-f614-45e8-ab63-e957ceb65bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051446699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1051446699
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3715286666
Short name T649
Test name
Test status
Simulation time 72533965676 ps
CPU time 111.17 seconds
Started May 12 01:26:07 PM PDT 24
Finished May 12 01:27:58 PM PDT 24
Peak memory 200060 kb
Host smart-b862fe5c-abee-4df2-8c4f-7764cd52be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715286666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3715286666
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.310307829
Short name T495
Test name
Test status
Simulation time 76732343360 ps
CPU time 130.72 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:28:17 PM PDT 24
Peak memory 200372 kb
Host smart-c632702a-4d2c-41e2-898c-aed7574cd378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310307829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.310307829
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.404095697
Short name T807
Test name
Test status
Simulation time 2071701022 ps
CPU time 1.37 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:26:07 PM PDT 24
Peak memory 195916 kb
Host smart-7d25881f-6c70-4c5d-bbcb-647bf75d9e8d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404095697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.404095697
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.613733743
Short name T743
Test name
Test status
Simulation time 117271976700 ps
CPU time 1223.87 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:46:30 PM PDT 24
Peak memory 200364 kb
Host smart-50c5f1a4-cd19-411f-8c41-601724c4327a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613733743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.613733743
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.393889910
Short name T667
Test name
Test status
Simulation time 8562220031 ps
CPU time 9.96 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:26:16 PM PDT 24
Peak memory 200356 kb
Host smart-cf51d3a6-5665-4bee-bce4-d9ee32c454a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393889910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.393889910
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3453377979
Short name T900
Test name
Test status
Simulation time 33120247456 ps
CPU time 27.65 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:26:33 PM PDT 24
Peak memory 200480 kb
Host smart-15c9b526-9c28-45c2-86a1-7be4234e5f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453377979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3453377979
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1287646760
Short name T522
Test name
Test status
Simulation time 7888072704 ps
CPU time 380.72 seconds
Started May 12 01:26:08 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 200320 kb
Host smart-95812e08-f450-4428-b3b1-61526e5fc22a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287646760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1287646760
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1086976249
Short name T553
Test name
Test status
Simulation time 6947619431 ps
CPU time 15.46 seconds
Started May 12 01:26:07 PM PDT 24
Finished May 12 01:26:23 PM PDT 24
Peak memory 198532 kb
Host smart-10086acc-76a2-45dc-8730-922d3a4513d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086976249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1086976249
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3991733232
Short name T293
Test name
Test status
Simulation time 25855351326 ps
CPU time 40.81 seconds
Started May 12 01:26:05 PM PDT 24
Finished May 12 01:26:46 PM PDT 24
Peak memory 200300 kb
Host smart-a40c6870-44bc-4c0c-88c4-3e0cd666d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991733232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3991733232
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1236668862
Short name T825
Test name
Test status
Simulation time 6585322156 ps
CPU time 1.26 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 196708 kb
Host smart-a6b8876b-b43f-4999-8f1c-13230ce44f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236668862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1236668862
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1447625866
Short name T1183
Test name
Test status
Simulation time 713374674 ps
CPU time 1.84 seconds
Started May 12 01:26:08 PM PDT 24
Finished May 12 01:26:10 PM PDT 24
Peak memory 199320 kb
Host smart-bd74f14d-779b-4ded-8044-748a20f67e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447625866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1447625866
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1676099274
Short name T507
Test name
Test status
Simulation time 126472272024 ps
CPU time 159.31 seconds
Started May 12 01:26:10 PM PDT 24
Finished May 12 01:28:49 PM PDT 24
Peak memory 200396 kb
Host smart-af766af6-5e2e-4040-9ba2-84043c614a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676099274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1676099274
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1674390288
Short name T482
Test name
Test status
Simulation time 210916421885 ps
CPU time 742.5 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:38:29 PM PDT 24
Peak memory 216744 kb
Host smart-829fa7d7-2855-44fd-91d5-9e1bd835f967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674390288 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1674390288
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.658011857
Short name T1110
Test name
Test status
Simulation time 806364721 ps
CPU time 2.32 seconds
Started May 12 01:26:06 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 198780 kb
Host smart-ebe82156-61df-48e8-ae10-e7630c3f6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658011857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.658011857
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3389458330
Short name T991
Test name
Test status
Simulation time 57787998700 ps
CPU time 55.85 seconds
Started May 12 01:26:08 PM PDT 24
Finished May 12 01:27:05 PM PDT 24
Peak memory 200420 kb
Host smart-a83c39ac-c2c8-4ba3-983d-374f3d18d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389458330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3389458330
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2010870952
Short name T34
Test name
Test status
Simulation time 12953522 ps
CPU time 0.56 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:26:14 PM PDT 24
Peak memory 195736 kb
Host smart-badc616c-bd38-4d1f-8035-f61ef22a8035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010870952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2010870952
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.989445246
Short name T1036
Test name
Test status
Simulation time 100898067654 ps
CPU time 112.56 seconds
Started May 12 01:26:12 PM PDT 24
Finished May 12 01:28:05 PM PDT 24
Peak memory 200404 kb
Host smart-99b28329-4a46-4b28-b9e4-483ff48e20fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989445246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.989445246
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1350339750
Short name T134
Test name
Test status
Simulation time 71922417979 ps
CPU time 114.1 seconds
Started May 12 01:26:11 PM PDT 24
Finished May 12 01:28:06 PM PDT 24
Peak memory 200344 kb
Host smart-0fe4b5c7-a0b7-4db1-8ff1-ee38a8ae9afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350339750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1350339750
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3915781686
Short name T650
Test name
Test status
Simulation time 34522193637 ps
CPU time 14.16 seconds
Started May 12 01:26:11 PM PDT 24
Finished May 12 01:26:26 PM PDT 24
Peak memory 200296 kb
Host smart-a575edb5-f1c8-49fd-989e-5454233648c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915781686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3915781686
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1438086584
Short name T1167
Test name
Test status
Simulation time 9399564173 ps
CPU time 8.4 seconds
Started May 12 01:26:10 PM PDT 24
Finished May 12 01:26:19 PM PDT 24
Peak memory 199892 kb
Host smart-9e017473-d402-48d8-841e-ac488ef8afcb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438086584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1438086584
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.98107610
Short name T424
Test name
Test status
Simulation time 94913090618 ps
CPU time 240.04 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:30:14 PM PDT 24
Peak memory 200376 kb
Host smart-a35676fa-96a8-446a-a235-f2541dd45c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98107610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.98107610
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.6641743
Short name T754
Test name
Test status
Simulation time 10684879215 ps
CPU time 15.24 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:26:28 PM PDT 24
Peak memory 199076 kb
Host smart-738c38d4-4b61-4560-b719-2d904cd78e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6641743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.6641743
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2177493813
Short name T284
Test name
Test status
Simulation time 72258812022 ps
CPU time 68.12 seconds
Started May 12 01:26:11 PM PDT 24
Finished May 12 01:27:20 PM PDT 24
Peak memory 200468 kb
Host smart-9b968ac1-12d1-40f3-af8c-8ed7f00fd0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177493813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2177493813
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2376126215
Short name T1097
Test name
Test status
Simulation time 19431881216 ps
CPU time 289.49 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 200312 kb
Host smart-29210e17-3722-45c7-bf9d-fe84c0d71288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376126215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2376126215
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3518467430
Short name T638
Test name
Test status
Simulation time 4741295009 ps
CPU time 11 seconds
Started May 12 01:26:10 PM PDT 24
Finished May 12 01:26:21 PM PDT 24
Peak memory 198712 kb
Host smart-b8e98668-1793-4d3c-ba93-a35aeae06918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518467430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3518467430
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.20117111
Short name T875
Test name
Test status
Simulation time 119320957931 ps
CPU time 43.09 seconds
Started May 12 01:26:10 PM PDT 24
Finished May 12 01:26:54 PM PDT 24
Peak memory 200360 kb
Host smart-bf23bec6-8fbf-45fa-a800-d7f7a7ba2e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20117111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.20117111
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1543234273
Short name T31
Test name
Test status
Simulation time 4196046596 ps
CPU time 1.93 seconds
Started May 12 01:26:11 PM PDT 24
Finished May 12 01:26:14 PM PDT 24
Peak memory 196420 kb
Host smart-1a7ceaaf-4b8b-48cc-83a1-74e9280cab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543234273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1543234273
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.448475604
Short name T726
Test name
Test status
Simulation time 5529176599 ps
CPU time 13.43 seconds
Started May 12 01:26:08 PM PDT 24
Finished May 12 01:26:22 PM PDT 24
Peak memory 199736 kb
Host smart-a694be30-6f30-419f-9d68-600ef203a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448475604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.448475604
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3659957278
Short name T267
Test name
Test status
Simulation time 250593994633 ps
CPU time 147.62 seconds
Started May 12 01:26:14 PM PDT 24
Finished May 12 01:28:42 PM PDT 24
Peak memory 216116 kb
Host smart-692cb661-8ef0-4071-a928-6be0215b1ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659957278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3659957278
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.274521272
Short name T926
Test name
Test status
Simulation time 312739544 ps
CPU time 1.16 seconds
Started May 12 01:26:12 PM PDT 24
Finished May 12 01:26:14 PM PDT 24
Peak memory 199468 kb
Host smart-cae81a52-e1c8-4a87-b11b-4d9b03395f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274521272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.274521272
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.133986171
Short name T669
Test name
Test status
Simulation time 58902442019 ps
CPU time 45.17 seconds
Started May 12 01:26:10 PM PDT 24
Finished May 12 01:26:55 PM PDT 24
Peak memory 200264 kb
Host smart-5baa6838-1eba-4ecf-a208-63ac3440dff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133986171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.133986171
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4248335049
Short name T56
Test name
Test status
Simulation time 15299328 ps
CPU time 0.54 seconds
Started May 12 01:26:17 PM PDT 24
Finished May 12 01:26:18 PM PDT 24
Peak memory 194740 kb
Host smart-bfdd72fc-31dc-415a-9dc1-31648e0c7b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248335049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4248335049
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2920837282
Short name T324
Test name
Test status
Simulation time 97469163045 ps
CPU time 103.18 seconds
Started May 12 01:26:12 PM PDT 24
Finished May 12 01:27:56 PM PDT 24
Peak memory 200412 kb
Host smart-818b48bc-1faa-4c43-a5a6-7f9fe7770a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920837282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2920837282
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2361592651
Short name T541
Test name
Test status
Simulation time 23317139301 ps
CPU time 24.3 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:26:38 PM PDT 24
Peak memory 200344 kb
Host smart-8fa8c0af-a4b1-4612-8128-be00e816be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361592651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2361592651
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1494207878
Short name T684
Test name
Test status
Simulation time 311901526209 ps
CPU time 30.48 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:26:44 PM PDT 24
Peak memory 200360 kb
Host smart-e536672f-3bc3-40d1-adfb-9df349cf5f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494207878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1494207878
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1175257015
Short name T1084
Test name
Test status
Simulation time 8686424109 ps
CPU time 14.28 seconds
Started May 12 01:26:14 PM PDT 24
Finished May 12 01:26:29 PM PDT 24
Peak memory 198144 kb
Host smart-235c2dd2-0bc6-4964-83f0-e733b6ceb663
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175257015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1175257015
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1530284224
Short name T1142
Test name
Test status
Simulation time 103026236481 ps
CPU time 482.48 seconds
Started May 12 01:26:18 PM PDT 24
Finished May 12 01:34:21 PM PDT 24
Peak memory 200268 kb
Host smart-d0c8ee9c-09be-41ed-a9ce-a1d67d95a953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530284224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1530284224
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1219196503
Short name T1107
Test name
Test status
Simulation time 1943508156 ps
CPU time 2.39 seconds
Started May 12 01:26:16 PM PDT 24
Finished May 12 01:26:18 PM PDT 24
Peak memory 198860 kb
Host smart-e57c74cc-99b5-41a4-bef9-f306b2ff885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219196503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1219196503
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2499472637
Short name T52
Test name
Test status
Simulation time 63552542406 ps
CPU time 35.85 seconds
Started May 12 01:26:18 PM PDT 24
Finished May 12 01:26:54 PM PDT 24
Peak memory 198140 kb
Host smart-bbbe30dc-93ea-47dc-911b-e91f3b7f1770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499472637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2499472637
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2541680533
Short name T520
Test name
Test status
Simulation time 21657537449 ps
CPU time 77.73 seconds
Started May 12 01:26:18 PM PDT 24
Finished May 12 01:27:36 PM PDT 24
Peak memory 200384 kb
Host smart-212fd713-4c3e-4fb5-a7d7-1e2f966abe0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541680533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2541680533
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2525099176
Short name T945
Test name
Test status
Simulation time 1577119707 ps
CPU time 3.1 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:26:17 PM PDT 24
Peak memory 198752 kb
Host smart-60c7f276-e5a6-448a-a823-4cb5f37554ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525099176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2525099176
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2322934635
Short name T786
Test name
Test status
Simulation time 118339162571 ps
CPU time 28.73 seconds
Started May 12 01:26:17 PM PDT 24
Finished May 12 01:26:46 PM PDT 24
Peak memory 200276 kb
Host smart-1effc29b-f924-4f54-9bc7-266a2f3a4596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322934635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2322934635
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3249218556
Short name T568
Test name
Test status
Simulation time 3477603094 ps
CPU time 1.83 seconds
Started May 12 01:26:19 PM PDT 24
Finished May 12 01:26:21 PM PDT 24
Peak memory 196396 kb
Host smart-2f75d81b-28a0-4aba-9db8-f22f4fc42105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249218556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3249218556
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2259721193
Short name T1063
Test name
Test status
Simulation time 5685668729 ps
CPU time 27.43 seconds
Started May 12 01:26:14 PM PDT 24
Finished May 12 01:26:41 PM PDT 24
Peak memory 199624 kb
Host smart-a6dd65d7-99ae-4c57-a25e-04ca693d199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259721193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2259721193
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.4040003310
Short name T106
Test name
Test status
Simulation time 357330180081 ps
CPU time 709.72 seconds
Started May 12 01:26:18 PM PDT 24
Finished May 12 01:38:08 PM PDT 24
Peak memory 200224 kb
Host smart-fdbfae7c-22d2-49c3-bfd1-743cd497e2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040003310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4040003310
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1878468653
Short name T1165
Test name
Test status
Simulation time 340092503503 ps
CPU time 935.5 seconds
Started May 12 01:26:19 PM PDT 24
Finished May 12 01:41:55 PM PDT 24
Peak memory 217044 kb
Host smart-61b9ca88-2743-4c7e-8e99-f7e5d8ad1e95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878468653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1878468653
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3290561154
Short name T939
Test name
Test status
Simulation time 1604202235 ps
CPU time 1.76 seconds
Started May 12 01:26:16 PM PDT 24
Finished May 12 01:26:18 PM PDT 24
Peak memory 198508 kb
Host smart-4465cf6d-9977-40b5-aeb2-429b99920dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290561154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3290561154
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3147548647
Short name T12
Test name
Test status
Simulation time 77423322123 ps
CPU time 39.06 seconds
Started May 12 01:26:13 PM PDT 24
Finished May 12 01:26:53 PM PDT 24
Peak memory 200276 kb
Host smart-11373680-95c1-46d6-9ba8-1d7ad83ce58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147548647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3147548647
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.890084555
Short name T368
Test name
Test status
Simulation time 45427684 ps
CPU time 0.55 seconds
Started May 12 01:26:25 PM PDT 24
Finished May 12 01:26:26 PM PDT 24
Peak memory 195160 kb
Host smart-839371c1-ff42-4054-8e2f-89d1ef473b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890084555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.890084555
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1803152020
Short name T1064
Test name
Test status
Simulation time 163784903205 ps
CPU time 85.21 seconds
Started May 12 01:26:23 PM PDT 24
Finished May 12 01:27:48 PM PDT 24
Peak memory 200360 kb
Host smart-61278771-6303-41b8-9029-83bee616f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803152020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1803152020
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4111118835
Short name T105
Test name
Test status
Simulation time 129357077419 ps
CPU time 101.56 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:28:03 PM PDT 24
Peak memory 200392 kb
Host smart-56936fb4-106d-49f0-8756-62f9d72099ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111118835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4111118835
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3153020336
Short name T183
Test name
Test status
Simulation time 52129840802 ps
CPU time 9.2 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:26:31 PM PDT 24
Peak memory 200408 kb
Host smart-e2384e98-5f3f-4f4e-afae-e7b9c944eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153020336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3153020336
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3930329312
Short name T399
Test name
Test status
Simulation time 74060281794 ps
CPU time 43.2 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:27:04 PM PDT 24
Peak memory 200172 kb
Host smart-470a8ceb-0d4b-481f-bbf3-5766a48b8da1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930329312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3930329312
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3672046797
Short name T361
Test name
Test status
Simulation time 66184248947 ps
CPU time 289.61 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 200420 kb
Host smart-c8d12fbb-5f9c-41b2-a242-b8ef64ce1aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672046797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3672046797
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1778012910
Short name T1150
Test name
Test status
Simulation time 7900755851 ps
CPU time 13.61 seconds
Started May 12 01:26:22 PM PDT 24
Finished May 12 01:26:36 PM PDT 24
Peak memory 200120 kb
Host smart-0184e60d-9968-4d42-ad58-5b40f6a82b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778012910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1778012910
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1558101646
Short name T899
Test name
Test status
Simulation time 67575874632 ps
CPU time 37.65 seconds
Started May 12 01:26:23 PM PDT 24
Finished May 12 01:27:01 PM PDT 24
Peak memory 200544 kb
Host smart-aad81e57-69be-4181-96c8-4ba61645142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558101646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1558101646
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2772581238
Short name T46
Test name
Test status
Simulation time 10805120182 ps
CPU time 39.96 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:27:01 PM PDT 24
Peak memory 200368 kb
Host smart-e4265975-ba5d-46d5-bdb4-abf49060aafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772581238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2772581238
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.517428091
Short name T341
Test name
Test status
Simulation time 4306811496 ps
CPU time 34.57 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:26:56 PM PDT 24
Peak memory 199692 kb
Host smart-35fe7faf-9f45-4bb2-b674-f4e4e24d9b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517428091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.517428091
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1892904289
Short name T584
Test name
Test status
Simulation time 72785047015 ps
CPU time 44.89 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:27:07 PM PDT 24
Peak memory 200048 kb
Host smart-868ead79-9844-4b2f-b9d4-4840cd087350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892904289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1892904289
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1953108771
Short name T358
Test name
Test status
Simulation time 4816291607 ps
CPU time 3.76 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:26:25 PM PDT 24
Peak memory 196300 kb
Host smart-a3729b20-b1b0-4b7f-bfa5-48799c42d70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953108771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1953108771
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2799992314
Short name T500
Test name
Test status
Simulation time 450511977 ps
CPU time 2.15 seconds
Started May 12 01:26:20 PM PDT 24
Finished May 12 01:26:22 PM PDT 24
Peak memory 199732 kb
Host smart-c39af648-9a5f-4a46-87b4-385261951191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799992314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2799992314
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1525297579
Short name T603
Test name
Test status
Simulation time 119220069672 ps
CPU time 2323.81 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 02:05:06 PM PDT 24
Peak memory 200364 kb
Host smart-ed44b19b-c865-45bd-9c99-b551b12a0071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525297579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1525297579
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1382625056
Short name T1100
Test name
Test status
Simulation time 88606446446 ps
CPU time 836.84 seconds
Started May 12 01:26:22 PM PDT 24
Finished May 12 01:40:19 PM PDT 24
Peak memory 217068 kb
Host smart-4a0a3141-3c14-4ad4-b6bd-a76673240772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382625056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1382625056
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1071798669
Short name T920
Test name
Test status
Simulation time 610569018 ps
CPU time 1.78 seconds
Started May 12 01:26:21 PM PDT 24
Finished May 12 01:26:24 PM PDT 24
Peak memory 199136 kb
Host smart-a96fa144-180d-4443-be00-5bc6f63f1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071798669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1071798669
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1037108695
Short name T489
Test name
Test status
Simulation time 56013557431 ps
CPU time 25.74 seconds
Started May 12 01:26:16 PM PDT 24
Finished May 12 01:26:42 PM PDT 24
Peak memory 200408 kb
Host smart-dc28ce8d-9638-4d1a-aca0-a8456c4de166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037108695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1037108695
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1472873089
Short name T342
Test name
Test status
Simulation time 11072637 ps
CPU time 0.53 seconds
Started May 12 01:26:28 PM PDT 24
Finished May 12 01:26:29 PM PDT 24
Peak memory 194764 kb
Host smart-412b3979-a44a-46cd-aefd-3bdd5f515ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472873089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1472873089
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1805425511
Short name T929
Test name
Test status
Simulation time 25484755227 ps
CPU time 23.26 seconds
Started May 12 01:26:24 PM PDT 24
Finished May 12 01:26:48 PM PDT 24
Peak memory 200276 kb
Host smart-a4487a48-8719-4d02-8345-dbff08ef1e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805425511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1805425511
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.4138101659
Short name T350
Test name
Test status
Simulation time 38963077627 ps
CPU time 84.09 seconds
Started May 12 01:26:24 PM PDT 24
Finished May 12 01:27:49 PM PDT 24
Peak memory 200372 kb
Host smart-9aa18b81-eea4-408e-b8a5-da90cbd459aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138101659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4138101659
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.417691120
Short name T615
Test name
Test status
Simulation time 5995241001 ps
CPU time 10.52 seconds
Started May 12 01:26:24 PM PDT 24
Finished May 12 01:26:35 PM PDT 24
Peak memory 200416 kb
Host smart-f4d16d53-425c-4f8e-94be-25997914c247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417691120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.417691120
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3168637293
Short name T481
Test name
Test status
Simulation time 45728962446 ps
CPU time 21.06 seconds
Started May 12 01:26:26 PM PDT 24
Finished May 12 01:26:48 PM PDT 24
Peak memory 200344 kb
Host smart-75b28a4d-0458-4c4f-b409-7adb18042539
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168637293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3168637293
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3892869331
Short name T1008
Test name
Test status
Simulation time 151279109620 ps
CPU time 1092.48 seconds
Started May 12 01:26:28 PM PDT 24
Finished May 12 01:44:41 PM PDT 24
Peak memory 200380 kb
Host smart-fe81c03c-a15d-4837-a51e-bc3d984e2ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892869331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3892869331
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3344608713
Short name T999
Test name
Test status
Simulation time 9251435645 ps
CPU time 18.62 seconds
Started May 12 01:26:26 PM PDT 24
Finished May 12 01:26:44 PM PDT 24
Peak memory 199080 kb
Host smart-67c57b5c-2c70-436a-8e79-b8803e0ff8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344608713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3344608713
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.222542720
Short name T316
Test name
Test status
Simulation time 57065923470 ps
CPU time 31.65 seconds
Started May 12 01:26:27 PM PDT 24
Finished May 12 01:26:59 PM PDT 24
Peak memory 200572 kb
Host smart-2d5ab4d5-b269-4d1d-a081-b0baee0d2267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222542720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.222542720
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3255809930
Short name T300
Test name
Test status
Simulation time 9436687131 ps
CPU time 114.33 seconds
Started May 12 01:26:25 PM PDT 24
Finished May 12 01:28:19 PM PDT 24
Peak memory 200396 kb
Host smart-c314c3ba-8258-4c65-88f6-337485acb7c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255809930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3255809930
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1465457533
Short name T698
Test name
Test status
Simulation time 4643217048 ps
CPU time 15.25 seconds
Started May 12 01:26:25 PM PDT 24
Finished May 12 01:26:41 PM PDT 24
Peak memory 198164 kb
Host smart-4fef0947-dedd-4694-8fe1-c09123b15257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465457533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1465457533
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3043787310
Short name T1152
Test name
Test status
Simulation time 87477443467 ps
CPU time 154.58 seconds
Started May 12 01:26:25 PM PDT 24
Finished May 12 01:29:00 PM PDT 24
Peak memory 200388 kb
Host smart-62f12647-d684-495a-ba39-773ed0b6646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043787310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3043787310
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.587090266
Short name T706
Test name
Test status
Simulation time 3698673023 ps
CPU time 6.96 seconds
Started May 12 01:26:25 PM PDT 24
Finished May 12 01:26:32 PM PDT 24
Peak memory 196400 kb
Host smart-d4603cd9-81ba-481e-8eae-2beba5fd3940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587090266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.587090266
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.445880146
Short name T697
Test name
Test status
Simulation time 5766020624 ps
CPU time 10.15 seconds
Started May 12 01:26:24 PM PDT 24
Finished May 12 01:26:35 PM PDT 24
Peak memory 199788 kb
Host smart-3971dcbe-ee5f-4000-8c08-6a72d9e20b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445880146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.445880146
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2858705961
Short name T897
Test name
Test status
Simulation time 494174949177 ps
CPU time 93.27 seconds
Started May 12 01:26:31 PM PDT 24
Finished May 12 01:28:04 PM PDT 24
Peak memory 208796 kb
Host smart-9b60436c-cbc9-4911-9247-056e0ad55131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858705961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2858705961
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1627682745
Short name T867
Test name
Test status
Simulation time 57721951787 ps
CPU time 193.39 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:29:50 PM PDT 24
Peak memory 216256 kb
Host smart-de8a61d2-db29-4a4b-a59d-4fa701bdacf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627682745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1627682745
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1294891993
Short name T458
Test name
Test status
Simulation time 954597888 ps
CPU time 1.69 seconds
Started May 12 01:26:26 PM PDT 24
Finished May 12 01:26:28 PM PDT 24
Peak memory 197284 kb
Host smart-ba6e5c79-0648-47cb-871b-fdd2ab1930c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294891993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1294891993
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1220834191
Short name T1069
Test name
Test status
Simulation time 82771953186 ps
CPU time 342.93 seconds
Started May 12 01:26:27 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 200292 kb
Host smart-00bbc492-2a18-4609-aa54-2b73aff80a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220834191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1220834191
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.184639866
Short name T485
Test name
Test status
Simulation time 98778390 ps
CPU time 0.56 seconds
Started May 12 01:26:33 PM PDT 24
Finished May 12 01:26:34 PM PDT 24
Peak memory 195756 kb
Host smart-4bd55667-d1eb-4db6-843e-41aa7b64f215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184639866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.184639866
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.427796347
Short name T291
Test name
Test status
Simulation time 28677517590 ps
CPU time 46.02 seconds
Started May 12 01:26:29 PM PDT 24
Finished May 12 01:27:16 PM PDT 24
Peak memory 200360 kb
Host smart-8d724d1f-abef-4aa4-80c8-07d8b972ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427796347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.427796347
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1184757425
Short name T768
Test name
Test status
Simulation time 112834801456 ps
CPU time 30.95 seconds
Started May 12 01:26:31 PM PDT 24
Finished May 12 01:27:02 PM PDT 24
Peak memory 200296 kb
Host smart-7fd1adc3-9f80-4eab-8cba-78feb3eed42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184757425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1184757425
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4146798025
Short name T1124
Test name
Test status
Simulation time 99113273375 ps
CPU time 53.1 seconds
Started May 12 01:26:30 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 200420 kb
Host smart-b8d3ca20-7dcc-4254-b76a-a8bb823d112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146798025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4146798025
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3949840173
Short name T15
Test name
Test status
Simulation time 21125502817 ps
CPU time 33.77 seconds
Started May 12 01:26:28 PM PDT 24
Finished May 12 01:27:02 PM PDT 24
Peak memory 200116 kb
Host smart-5ba79851-d3bd-4a90-b11b-1725e5ec55e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949840173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3949840173
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2365326294
Short name T816
Test name
Test status
Simulation time 182228109162 ps
CPU time 486.76 seconds
Started May 12 01:26:33 PM PDT 24
Finished May 12 01:34:40 PM PDT 24
Peak memory 200360 kb
Host smart-6161c5dc-f8f9-49e0-9926-a33fbf4168cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365326294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2365326294
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.299841330
Short name T987
Test name
Test status
Simulation time 1647153743 ps
CPU time 2.37 seconds
Started May 12 01:26:33 PM PDT 24
Finished May 12 01:26:35 PM PDT 24
Peak memory 197464 kb
Host smart-f976e0f5-54dc-4865-b035-0b107a66e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299841330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.299841330
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2883853506
Short name T1109
Test name
Test status
Simulation time 217824543339 ps
CPU time 54.65 seconds
Started May 12 01:26:31 PM PDT 24
Finished May 12 01:27:26 PM PDT 24
Peak memory 208636 kb
Host smart-59af078c-ed7d-4554-bdd0-658cf9a57836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883853506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2883853506
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1097896398
Short name T523
Test name
Test status
Simulation time 20711948910 ps
CPU time 1144.97 seconds
Started May 12 01:26:33 PM PDT 24
Finished May 12 01:45:39 PM PDT 24
Peak memory 200340 kb
Host smart-bcfe4ebf-396d-4415-bb22-071df74143a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097896398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1097896398
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1126590441
Short name T405
Test name
Test status
Simulation time 1921717095 ps
CPU time 2.85 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:26:40 PM PDT 24
Peak memory 199292 kb
Host smart-a00071a5-82b4-4c44-8b31-a868130799fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126590441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1126590441
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3958025135
Short name T817
Test name
Test status
Simulation time 113428683476 ps
CPU time 216.27 seconds
Started May 12 01:26:34 PM PDT 24
Finished May 12 01:30:11 PM PDT 24
Peak memory 200216 kb
Host smart-c680558c-7f8a-476a-a37f-dcfcd114d058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958025135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3958025135
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.268936899
Short name T1061
Test name
Test status
Simulation time 5343742475 ps
CPU time 9.36 seconds
Started May 12 01:26:34 PM PDT 24
Finished May 12 01:26:43 PM PDT 24
Peak memory 196388 kb
Host smart-d7ebfff2-f081-4468-8f78-d0a788469131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268936899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.268936899
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1722732108
Short name T486
Test name
Test status
Simulation time 443948610 ps
CPU time 1.18 seconds
Started May 12 01:26:31 PM PDT 24
Finished May 12 01:26:33 PM PDT 24
Peak memory 198900 kb
Host smart-1d33a215-6e95-4191-984e-22870a8f8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722732108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1722732108
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3895229686
Short name T1162
Test name
Test status
Simulation time 134182049157 ps
CPU time 225.61 seconds
Started May 12 01:26:32 PM PDT 24
Finished May 12 01:30:18 PM PDT 24
Peak memory 200324 kb
Host smart-345d78d0-b01f-4296-816e-b8d2b4f77c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895229686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3895229686
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1617161140
Short name T1184
Test name
Test status
Simulation time 107598684581 ps
CPU time 439.21 seconds
Started May 12 01:26:33 PM PDT 24
Finished May 12 01:33:52 PM PDT 24
Peak memory 225220 kb
Host smart-0253a65e-2ff4-4812-9319-211053392422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617161140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1617161140
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4113177713
Short name T1186
Test name
Test status
Simulation time 1132733601 ps
CPU time 3.35 seconds
Started May 12 01:26:32 PM PDT 24
Finished May 12 01:26:36 PM PDT 24
Peak memory 199956 kb
Host smart-2cf74271-73c7-41b7-9e84-a2826bb77e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113177713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4113177713
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2273660240
Short name T454
Test name
Test status
Simulation time 112155913188 ps
CPU time 53.11 seconds
Started May 12 01:26:30 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 200324 kb
Host smart-d1478818-9b9e-4fab-98ee-74223115b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273660240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2273660240
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.951698497
Short name T701
Test name
Test status
Simulation time 53350962 ps
CPU time 0.54 seconds
Started May 12 01:26:41 PM PDT 24
Finished May 12 01:26:42 PM PDT 24
Peak memory 195768 kb
Host smart-e57e502e-8570-4e3a-8e1e-e9b4312addc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951698497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.951698497
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1402040712
Short name T159
Test name
Test status
Simulation time 140342674617 ps
CPU time 230.18 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:30:26 PM PDT 24
Peak memory 200252 kb
Host smart-10f17224-3637-4f33-b888-ffcb340bcffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402040712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1402040712
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1660413297
Short name T878
Test name
Test status
Simulation time 103362320459 ps
CPU time 142.37 seconds
Started May 12 01:26:33 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200332 kb
Host smart-8d0fc061-4851-4b1d-a3a4-6525ad6358df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660413297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1660413297
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.89203713
Short name T1138
Test name
Test status
Simulation time 95141125445 ps
CPU time 38.72 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:27:15 PM PDT 24
Peak memory 200008 kb
Host smart-0f66a5d9-5f58-44cf-874e-47f7a16a00ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89203713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.89203713
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1709075947
Short name T1082
Test name
Test status
Simulation time 51246049250 ps
CPU time 77.97 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:27:54 PM PDT 24
Peak memory 200376 kb
Host smart-0d2ad645-b52b-49aa-8b21-ec9cee119428
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709075947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1709075947
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1951073728
Short name T1081
Test name
Test status
Simulation time 60623931428 ps
CPU time 374.26 seconds
Started May 12 01:26:35 PM PDT 24
Finished May 12 01:32:50 PM PDT 24
Peak memory 200368 kb
Host smart-2740c8fe-74d2-467f-a34d-effdfaa173af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951073728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1951073728
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1175273087
Short name T374
Test name
Test status
Simulation time 6023403051 ps
CPU time 13.25 seconds
Started May 12 01:26:35 PM PDT 24
Finished May 12 01:26:49 PM PDT 24
Peak memory 199544 kb
Host smart-98b6e150-d38c-4c7a-b42d-e2a36c461331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175273087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1175273087
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3932823617
Short name T666
Test name
Test status
Simulation time 145282024887 ps
CPU time 148.98 seconds
Started May 12 01:26:40 PM PDT 24
Finished May 12 01:29:09 PM PDT 24
Peak memory 199908 kb
Host smart-0f35aa04-2937-4df7-adc3-ecdc714f6faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932823617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3932823617
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3182845383
Short name T797
Test name
Test status
Simulation time 25128294070 ps
CPU time 351.05 seconds
Started May 12 01:26:37 PM PDT 24
Finished May 12 01:32:28 PM PDT 24
Peak memory 200368 kb
Host smart-cacd7497-04b7-45d4-9169-adfe1d025be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182845383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3182845383
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.4113281694
Short name T404
Test name
Test status
Simulation time 5686459579 ps
CPU time 49.3 seconds
Started May 12 01:26:32 PM PDT 24
Finished May 12 01:27:22 PM PDT 24
Peak memory 199588 kb
Host smart-c70dd50e-07bf-411f-bb0e-6af5982b4ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113281694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4113281694
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3592071511
Short name T459
Test name
Test status
Simulation time 39866307893 ps
CPU time 42.29 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:27:18 PM PDT 24
Peak memory 200384 kb
Host smart-41182434-7136-4516-b03b-d4975a52af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592071511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3592071511
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2786764165
Short name T940
Test name
Test status
Simulation time 4580981695 ps
CPU time 3.72 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:26:40 PM PDT 24
Peak memory 196700 kb
Host smart-5487d422-ffce-4934-887f-5c30fe0077a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786764165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2786764165
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1885037579
Short name T317
Test name
Test status
Simulation time 293960406 ps
CPU time 1.59 seconds
Started May 12 01:26:34 PM PDT 24
Finished May 12 01:26:36 PM PDT 24
Peak memory 200008 kb
Host smart-eae69e51-27d1-44ee-ba35-1f652eadd229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885037579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1885037579
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1176760619
Short name T1019
Test name
Test status
Simulation time 232038390601 ps
CPU time 472.2 seconds
Started May 12 01:26:41 PM PDT 24
Finished May 12 01:34:34 PM PDT 24
Peak memory 208728 kb
Host smart-88ab4c4f-ffef-425f-a115-2af90c3fc365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176760619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1176760619
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4060914349
Short name T890
Test name
Test status
Simulation time 94430883344 ps
CPU time 1659.48 seconds
Started May 12 01:26:39 PM PDT 24
Finished May 12 01:54:19 PM PDT 24
Peak memory 216764 kb
Host smart-58083257-deeb-40a1-9f85-82b58af094eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060914349 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4060914349
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1774470827
Short name T802
Test name
Test status
Simulation time 1192634097 ps
CPU time 4.13 seconds
Started May 12 01:26:36 PM PDT 24
Finished May 12 01:26:41 PM PDT 24
Peak memory 198680 kb
Host smart-cdab09b1-9aaa-4751-83eb-3eeeade0ef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774470827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1774470827
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1289312015
Short name T881
Test name
Test status
Simulation time 88240853357 ps
CPU time 87.58 seconds
Started May 12 01:26:32 PM PDT 24
Finished May 12 01:28:00 PM PDT 24
Peak memory 200256 kb
Host smart-91484068-50bb-439e-8e5f-d741fa12c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289312015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1289312015
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3871810204
Short name T984
Test name
Test status
Simulation time 16874949 ps
CPU time 0.58 seconds
Started May 12 01:26:44 PM PDT 24
Finished May 12 01:26:45 PM PDT 24
Peak memory 195756 kb
Host smart-cab93297-6b0b-4a84-9a77-a1fab1c8ccf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871810204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3871810204
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1442629252
Short name T986
Test name
Test status
Simulation time 248081287633 ps
CPU time 354.74 seconds
Started May 12 01:26:42 PM PDT 24
Finished May 12 01:32:37 PM PDT 24
Peak memory 200416 kb
Host smart-96fca7a0-0083-4ded-ab2b-cae2373f6827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442629252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1442629252
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1416139551
Short name T585
Test name
Test status
Simulation time 22096351310 ps
CPU time 23.47 seconds
Started May 12 01:26:42 PM PDT 24
Finished May 12 01:27:06 PM PDT 24
Peak memory 200400 kb
Host smart-d0436dfc-c284-4a33-a717-34749e61c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416139551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1416139551
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4258123326
Short name T587
Test name
Test status
Simulation time 118558034039 ps
CPU time 102.85 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:28:27 PM PDT 24
Peak memory 200312 kb
Host smart-07eda484-08fd-41c8-b2f8-fcffbc36293c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258123326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4258123326
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.518930879
Short name T447
Test name
Test status
Simulation time 55662120529 ps
CPU time 433.78 seconds
Started May 12 01:26:41 PM PDT 24
Finished May 12 01:33:55 PM PDT 24
Peak memory 200372 kb
Host smart-f349c729-e900-478e-b423-fc4f3c75ed8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518930879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.518930879
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4206759833
Short name T573
Test name
Test status
Simulation time 6403609837 ps
CPU time 9.74 seconds
Started May 12 01:26:41 PM PDT 24
Finished May 12 01:26:51 PM PDT 24
Peak memory 200296 kb
Host smart-85f265ad-772c-4c1c-90fc-6e91e13af42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206759833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4206759833
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1045834490
Short name T681
Test name
Test status
Simulation time 18683368886 ps
CPU time 31.13 seconds
Started May 12 01:26:38 PM PDT 24
Finished May 12 01:27:10 PM PDT 24
Peak memory 197428 kb
Host smart-c63a96c0-b7f7-4035-b2b9-f252e930c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045834490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1045834490
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.106597115
Short name T857
Test name
Test status
Simulation time 6507919935 ps
CPU time 391.37 seconds
Started May 12 01:26:40 PM PDT 24
Finished May 12 01:33:11 PM PDT 24
Peak memory 200312 kb
Host smart-277dba95-4423-4f55-860b-72f4fc5e4d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106597115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.106597115
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3640660232
Short name T602
Test name
Test status
Simulation time 3335147497 ps
CPU time 23.11 seconds
Started May 12 01:26:40 PM PDT 24
Finished May 12 01:27:03 PM PDT 24
Peak memory 198624 kb
Host smart-6b32f64d-e261-46ac-a240-6b9e2ce60de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640660232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3640660232
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1418047158
Short name T769
Test name
Test status
Simulation time 19333858775 ps
CPU time 35.11 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:27:18 PM PDT 24
Peak memory 200296 kb
Host smart-fa0a5377-ca06-4fb9-98ce-419395375156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418047158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1418047158
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1437087577
Short name T873
Test name
Test status
Simulation time 1619256683 ps
CPU time 3.28 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:26:47 PM PDT 24
Peak memory 195948 kb
Host smart-04e5c9f8-8398-40a4-a483-b42c72c88e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437087577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1437087577
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3068798000
Short name T278
Test name
Test status
Simulation time 790183327 ps
CPU time 1.35 seconds
Started May 12 01:26:40 PM PDT 24
Finished May 12 01:26:42 PM PDT 24
Peak memory 198780 kb
Host smart-d2fe04be-2f27-4fd9-a9e4-4e3148a73ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068798000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3068798000
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2176600237
Short name T840
Test name
Test status
Simulation time 252536118899 ps
CPU time 835.7 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:40:39 PM PDT 24
Peak memory 208808 kb
Host smart-d12cc939-36e9-483c-85ba-6f117b56491e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176600237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2176600237
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.27217673
Short name T321
Test name
Test status
Simulation time 38057940988 ps
CPU time 528.23 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:35:32 PM PDT 24
Peak memory 215872 kb
Host smart-e6a1033d-6892-4714-ac27-977b826ea1a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27217673 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.27217673
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1713841402
Short name T325
Test name
Test status
Simulation time 1219886475 ps
CPU time 2.14 seconds
Started May 12 01:26:44 PM PDT 24
Finished May 12 01:26:46 PM PDT 24
Peak memory 198352 kb
Host smart-f4406c4b-2b01-4524-aa7d-20473e6de8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713841402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1713841402
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1899496940
Short name T642
Test name
Test status
Simulation time 70741817030 ps
CPU time 38.54 seconds
Started May 12 01:26:42 PM PDT 24
Finished May 12 01:27:22 PM PDT 24
Peak memory 200416 kb
Host smart-b90d5372-746f-4caf-9126-907c1e1c04ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899496940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1899496940
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.400158819
Short name T408
Test name
Test status
Simulation time 37775166 ps
CPU time 0.56 seconds
Started May 12 01:26:53 PM PDT 24
Finished May 12 01:26:54 PM PDT 24
Peak memory 195784 kb
Host smart-8f0eb465-b0ac-4f63-a068-b4af19639e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400158819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.400158819
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.775855760
Short name T169
Test name
Test status
Simulation time 71199322913 ps
CPU time 32.31 seconds
Started May 12 01:26:44 PM PDT 24
Finished May 12 01:27:17 PM PDT 24
Peak memory 200304 kb
Host smart-5f594fdd-30cd-4f0d-9326-855a327148ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775855760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.775855760
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3271463282
Short name T626
Test name
Test status
Simulation time 155788587449 ps
CPU time 41.86 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:27:26 PM PDT 24
Peak memory 200232 kb
Host smart-2e2cc429-323f-4953-b4b0-3d929e2aab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271463282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3271463282
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3760260723
Short name T1091
Test name
Test status
Simulation time 121778027510 ps
CPU time 95.06 seconds
Started May 12 01:26:44 PM PDT 24
Finished May 12 01:28:19 PM PDT 24
Peak memory 200328 kb
Host smart-97b69b9c-9879-4a63-9d3e-1a99d692c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760260723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3760260723
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2419678600
Short name T1062
Test name
Test status
Simulation time 20157621570 ps
CPU time 32.58 seconds
Started May 12 01:26:43 PM PDT 24
Finished May 12 01:27:16 PM PDT 24
Peak memory 200304 kb
Host smart-caf09c01-196d-4df5-af2b-328464b89921
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419678600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2419678600
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2250619039
Short name T1104
Test name
Test status
Simulation time 178023091079 ps
CPU time 355.18 seconds
Started May 12 01:26:48 PM PDT 24
Finished May 12 01:32:44 PM PDT 24
Peak memory 200392 kb
Host smart-a121aa2d-a5c9-4a90-91dd-fb9467ab13d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250619039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2250619039
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3561973965
Short name T417
Test name
Test status
Simulation time 2345819783 ps
CPU time 2.75 seconds
Started May 12 01:26:48 PM PDT 24
Finished May 12 01:26:52 PM PDT 24
Peak memory 198276 kb
Host smart-bd1c8da1-1ffb-4574-815a-6ea71cbe8e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561973965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3561973965
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.218315976
Short name T973
Test name
Test status
Simulation time 41735734665 ps
CPU time 20.34 seconds
Started May 12 01:26:46 PM PDT 24
Finished May 12 01:27:07 PM PDT 24
Peak memory 200420 kb
Host smart-c519463f-6ae0-4649-bc2e-b058461c7456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218315976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.218315976
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.910299220
Short name T517
Test name
Test status
Simulation time 17127929322 ps
CPU time 887.22 seconds
Started May 12 01:26:49 PM PDT 24
Finished May 12 01:41:37 PM PDT 24
Peak memory 200272 kb
Host smart-9d1371b4-dc22-4e95-aec3-a671a5278553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910299220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.910299220
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2838406355
Short name T823
Test name
Test status
Simulation time 5202798345 ps
CPU time 41.7 seconds
Started May 12 01:26:42 PM PDT 24
Finished May 12 01:27:25 PM PDT 24
Peak memory 200232 kb
Host smart-599e478d-b34d-4bdd-a445-db9279b52952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838406355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2838406355
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1469392096
Short name T178
Test name
Test status
Simulation time 45279284055 ps
CPU time 73.5 seconds
Started May 12 01:26:49 PM PDT 24
Finished May 12 01:28:03 PM PDT 24
Peak memory 200340 kb
Host smart-f49fe4a9-3015-403f-a17c-5ae3eb044e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469392096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1469392096
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1530331422
Short name T877
Test name
Test status
Simulation time 3158197960 ps
CPU time 3.12 seconds
Started May 12 01:26:48 PM PDT 24
Finished May 12 01:26:51 PM PDT 24
Peak memory 196716 kb
Host smart-7ab8bfb7-31d3-410e-945f-2ba2ac8eed9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530331422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1530331422
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3672770260
Short name T1047
Test name
Test status
Simulation time 905344719 ps
CPU time 1.93 seconds
Started May 12 01:26:45 PM PDT 24
Finished May 12 01:26:47 PM PDT 24
Peak memory 200020 kb
Host smart-3dc7a73a-85a1-467f-8fa7-615d69453570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672770260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3672770260
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3605441640
Short name T739
Test name
Test status
Simulation time 124134892989 ps
CPU time 92.3 seconds
Started May 12 01:26:52 PM PDT 24
Finished May 12 01:28:25 PM PDT 24
Peak memory 200400 kb
Host smart-47cd1d13-2536-4f0b-8f1f-f5ed054d4c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605441640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3605441640
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3178203198
Short name T109
Test name
Test status
Simulation time 44172258203 ps
CPU time 258.21 seconds
Started May 12 01:26:48 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 217008 kb
Host smart-9e664b5a-7522-43d4-88ae-7e9861bdbfac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178203198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3178203198
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2988221701
Short name T815
Test name
Test status
Simulation time 1180627620 ps
CPU time 3.9 seconds
Started May 12 01:26:47 PM PDT 24
Finished May 12 01:26:51 PM PDT 24
Peak memory 200168 kb
Host smart-ea02ed86-c695-4a1c-80b2-e2c0fb29bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988221701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2988221701
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.922614813
Short name T47
Test name
Test status
Simulation time 77498309144 ps
CPU time 123.31 seconds
Started May 12 01:26:45 PM PDT 24
Finished May 12 01:28:48 PM PDT 24
Peak memory 200416 kb
Host smart-817eec55-31d3-429a-bc7a-e920a654cf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922614813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.922614813
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.4136730732
Short name T759
Test name
Test status
Simulation time 64389784 ps
CPU time 0.58 seconds
Started May 12 01:26:55 PM PDT 24
Finished May 12 01:26:56 PM PDT 24
Peak memory 195792 kb
Host smart-d481ee4a-9226-4e3f-8f12-72b1226ea8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136730732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4136730732
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2584636206
Short name T168
Test name
Test status
Simulation time 15203927492 ps
CPU time 14.42 seconds
Started May 12 01:26:50 PM PDT 24
Finished May 12 01:27:05 PM PDT 24
Peak memory 200356 kb
Host smart-31a5cbe3-72d8-4e61-82a0-fca56c3938f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584636206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2584636206
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.4135007888
Short name T1157
Test name
Test status
Simulation time 90253516710 ps
CPU time 43.9 seconds
Started May 12 01:26:51 PM PDT 24
Finished May 12 01:27:36 PM PDT 24
Peak memory 200284 kb
Host smart-01367505-e1ee-4c79-a089-0490fa5687a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135007888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4135007888
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2428978140
Short name T196
Test name
Test status
Simulation time 35601711199 ps
CPU time 65.64 seconds
Started May 12 01:26:50 PM PDT 24
Finished May 12 01:27:56 PM PDT 24
Peak memory 200384 kb
Host smart-3ba8ead7-4b52-46ec-9388-dc1ed71ae296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428978140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2428978140
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1669051098
Short name T913
Test name
Test status
Simulation time 67613317357 ps
CPU time 51 seconds
Started May 12 01:26:57 PM PDT 24
Finished May 12 01:27:49 PM PDT 24
Peak memory 200256 kb
Host smart-03da8260-3447-43b6-9b4e-59eda0bb5657
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669051098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1669051098
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3154078820
Short name T1136
Test name
Test status
Simulation time 39799381574 ps
CPU time 138.74 seconds
Started May 12 01:26:54 PM PDT 24
Finished May 12 01:29:13 PM PDT 24
Peak memory 200404 kb
Host smart-378c50ff-45f7-4769-88a8-28b7b50a0055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3154078820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3154078820
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1409012946
Short name T1010
Test name
Test status
Simulation time 12835727600 ps
CPU time 24.68 seconds
Started May 12 01:26:54 PM PDT 24
Finished May 12 01:27:19 PM PDT 24
Peak memory 200264 kb
Host smart-91af94b6-0d1c-43b8-93e4-77dc2320aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409012946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1409012946
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1067082993
Short name T839
Test name
Test status
Simulation time 107195908192 ps
CPU time 195.49 seconds
Started May 12 01:26:57 PM PDT 24
Finished May 12 01:30:13 PM PDT 24
Peak memory 200680 kb
Host smart-04bfb806-2bf9-4011-a9ae-831ba411b20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067082993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1067082993
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2433553466
Short name T387
Test name
Test status
Simulation time 10384584456 ps
CPU time 618.06 seconds
Started May 12 01:26:54 PM PDT 24
Finished May 12 01:37:12 PM PDT 24
Peak memory 200384 kb
Host smart-98e2e974-bfbf-4b0d-bde6-039334011cd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433553466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2433553466
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1003850954
Short name T366
Test name
Test status
Simulation time 6680045010 ps
CPU time 15.49 seconds
Started May 12 01:26:53 PM PDT 24
Finished May 12 01:27:09 PM PDT 24
Peak memory 198480 kb
Host smart-f672eb5d-6a36-46e4-942f-be7b3e34c74c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003850954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1003850954
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.198551222
Short name T901
Test name
Test status
Simulation time 263888093507 ps
CPU time 81.25 seconds
Started May 12 01:26:52 PM PDT 24
Finished May 12 01:28:13 PM PDT 24
Peak memory 200380 kb
Host smart-30a057a9-2f6d-42b4-83d0-0fa9df6f26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198551222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.198551222
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3898431840
Short name T554
Test name
Test status
Simulation time 4151251838 ps
CPU time 4.15 seconds
Started May 12 01:26:50 PM PDT 24
Finished May 12 01:26:55 PM PDT 24
Peak memory 196636 kb
Host smart-32ba7704-5a33-4dc1-a5d1-addcc237cc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898431840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3898431840
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1828324706
Short name T318
Test name
Test status
Simulation time 456586773 ps
CPU time 1.91 seconds
Started May 12 01:26:54 PM PDT 24
Finished May 12 01:26:56 PM PDT 24
Peak memory 200088 kb
Host smart-a4c93579-0460-4e4a-afa5-d2de88c3b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828324706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1828324706
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2429684700
Short name T1115
Test name
Test status
Simulation time 141321394545 ps
CPU time 309.07 seconds
Started May 12 01:26:56 PM PDT 24
Finished May 12 01:32:06 PM PDT 24
Peak memory 200588 kb
Host smart-74ae5fb3-9da1-4bcb-81bf-6338c0113279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429684700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2429684700
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2634136696
Short name T534
Test name
Test status
Simulation time 13576134545 ps
CPU time 15.12 seconds
Started May 12 01:26:56 PM PDT 24
Finished May 12 01:27:11 PM PDT 24
Peak memory 200288 kb
Host smart-3b8ec337-c822-4b58-8764-866d52470f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634136696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2634136696
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4102883279
Short name T1068
Test name
Test status
Simulation time 30242816662 ps
CPU time 27.69 seconds
Started May 12 01:26:51 PM PDT 24
Finished May 12 01:27:19 PM PDT 24
Peak memory 200344 kb
Host smart-a352d07a-abdb-4ca2-b1c4-a2124aafde7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102883279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4102883279
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3678835944
Short name T756
Test name
Test status
Simulation time 36552664 ps
CPU time 0.56 seconds
Started May 12 01:24:26 PM PDT 24
Finished May 12 01:24:27 PM PDT 24
Peak memory 195768 kb
Host smart-edc2f7e5-9ef0-471f-ba84-915b27af006c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678835944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3678835944
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2418178110
Short name T371
Test name
Test status
Simulation time 12999886132 ps
CPU time 6.63 seconds
Started May 12 01:24:28 PM PDT 24
Finished May 12 01:24:35 PM PDT 24
Peak memory 200060 kb
Host smart-ee952343-1325-4236-91da-fd456c9d3218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418178110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2418178110
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3910459521
Short name T1103
Test name
Test status
Simulation time 123539293234 ps
CPU time 30.95 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:24:59 PM PDT 24
Peak memory 200068 kb
Host smart-b453b65f-ec42-4166-8d29-f19ed713921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910459521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3910459521
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3430128073
Short name T569
Test name
Test status
Simulation time 60969666703 ps
CPU time 88.42 seconds
Started May 12 01:24:30 PM PDT 24
Finished May 12 01:25:59 PM PDT 24
Peak memory 200412 kb
Host smart-624a9c2c-c2e1-4bda-91c4-6b485f0eb93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430128073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3430128073
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1282522271
Short name T1180
Test name
Test status
Simulation time 28855874835 ps
CPU time 12.2 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:24:42 PM PDT 24
Peak memory 200368 kb
Host smart-ba39eabd-7bb2-4d36-ad3f-984398b85f65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282522271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1282522271
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3919832126
Short name T370
Test name
Test status
Simulation time 138411085106 ps
CPU time 210.19 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:28:01 PM PDT 24
Peak memory 200400 kb
Host smart-e3fae252-4fad-416e-91b2-d6020062e324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919832126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3919832126
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3417844613
Short name T440
Test name
Test status
Simulation time 3596089488 ps
CPU time 1.37 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:24:29 PM PDT 24
Peak memory 198516 kb
Host smart-8be943ef-3214-4a5f-8e3c-c2c7a9ba9b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417844613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3417844613
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1602181241
Short name T859
Test name
Test status
Simulation time 169955164334 ps
CPU time 453.13 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 208852 kb
Host smart-807fa33a-893b-43ce-979c-128afafec5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602181241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1602181241
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2844652646
Short name T625
Test name
Test status
Simulation time 17649117868 ps
CPU time 254.87 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:28:45 PM PDT 24
Peak memory 200372 kb
Host smart-cf9d84a6-92b5-4c4c-a640-6c956178cddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844652646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2844652646
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.775324400
Short name T1057
Test name
Test status
Simulation time 7058941279 ps
CPU time 14.88 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:24:42 PM PDT 24
Peak memory 198448 kb
Host smart-2beea13b-0d4c-4cfa-8c30-31d048602bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775324400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.775324400
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3487774076
Short name T501
Test name
Test status
Simulation time 24750430643 ps
CPU time 27.87 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:25:05 PM PDT 24
Peak memory 200324 kb
Host smart-9c11b6d2-8d1b-4978-a9ed-4beae286a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487774076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3487774076
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1123762765
Short name T577
Test name
Test status
Simulation time 597337234 ps
CPU time 1.09 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:24:31 PM PDT 24
Peak memory 196056 kb
Host smart-3c1bca37-8e7e-4a28-ab63-d373a0a09d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123762765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1123762765
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3358687653
Short name T35
Test name
Test status
Simulation time 780939278 ps
CPU time 0.89 seconds
Started May 12 01:24:35 PM PDT 24
Finished May 12 01:24:37 PM PDT 24
Peak memory 218688 kb
Host smart-6d4aec68-7e7d-41f6-85a2-6a279b049015
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358687653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3358687653
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1826165622
Short name T586
Test name
Test status
Simulation time 889015071 ps
CPU time 3.86 seconds
Started May 12 01:24:24 PM PDT 24
Finished May 12 01:24:29 PM PDT 24
Peak memory 199640 kb
Host smart-118ab940-462b-4b3d-b7ad-63a24b84883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826165622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1826165622
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3093706527
Short name T255
Test name
Test status
Simulation time 306836832467 ps
CPU time 779.97 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:37:31 PM PDT 24
Peak memory 200252 kb
Host smart-971b791b-4122-4321-915c-b59d58cd349b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093706527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3093706527
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1579995833
Short name T848
Test name
Test status
Simulation time 104823696650 ps
CPU time 717.74 seconds
Started May 12 01:24:30 PM PDT 24
Finished May 12 01:36:29 PM PDT 24
Peak memory 216836 kb
Host smart-91e5e455-6650-4ef9-8e6c-7e22af5432e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579995833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1579995833
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.665974069
Short name T359
Test name
Test status
Simulation time 13870920423 ps
CPU time 15.56 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:24:46 PM PDT 24
Peak memory 200312 kb
Host smart-41e153b4-b761-48c7-adc5-aaf04e0ce70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665974069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.665974069
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_alert_test.1641918619
Short name T989
Test name
Test status
Simulation time 14037933 ps
CPU time 0.56 seconds
Started May 12 01:27:07 PM PDT 24
Finished May 12 01:27:08 PM PDT 24
Peak memory 195136 kb
Host smart-1c2d7470-6e22-4ec2-b0bf-b17bee518797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641918619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1641918619
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3758832210
Short name T509
Test name
Test status
Simulation time 35470977764 ps
CPU time 61.89 seconds
Started May 12 01:26:58 PM PDT 24
Finished May 12 01:28:00 PM PDT 24
Peak memory 200384 kb
Host smart-9ecc6a49-8401-4735-9539-8c76cb8b6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758832210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3758832210
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2347049363
Short name T420
Test name
Test status
Simulation time 103981927088 ps
CPU time 42.28 seconds
Started May 12 01:27:00 PM PDT 24
Finished May 12 01:27:43 PM PDT 24
Peak memory 199988 kb
Host smart-57a35b15-ee69-4642-be23-4ad88b7c768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347049363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2347049363
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.59201206
Short name T721
Test name
Test status
Simulation time 192668948231 ps
CPU time 89.54 seconds
Started May 12 01:26:58 PM PDT 24
Finished May 12 01:28:28 PM PDT 24
Peak memory 200380 kb
Host smart-699fa29f-3ec5-4c27-a362-87a80023b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59201206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.59201206
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3072723146
Short name T410
Test name
Test status
Simulation time 6989218005 ps
CPU time 3.08 seconds
Started May 12 01:26:59 PM PDT 24
Finished May 12 01:27:02 PM PDT 24
Peak memory 197368 kb
Host smart-e985816f-43cc-4ea4-9b1c-28e8518689c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072723146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3072723146
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1127816065
Short name T448
Test name
Test status
Simulation time 192108259956 ps
CPU time 274.48 seconds
Started May 12 01:27:04 PM PDT 24
Finished May 12 01:31:39 PM PDT 24
Peak memory 200400 kb
Host smart-b18902eb-76b6-4496-822a-f431cae630f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127816065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1127816065
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2313117599
Short name T1054
Test name
Test status
Simulation time 5860910082 ps
CPU time 19.89 seconds
Started May 12 01:27:05 PM PDT 24
Finished May 12 01:27:26 PM PDT 24
Peak memory 200356 kb
Host smart-a6fab731-c066-4639-9b1f-79e2810ef627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313117599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2313117599
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.913247746
Short name T418
Test name
Test status
Simulation time 155465633067 ps
CPU time 88.33 seconds
Started May 12 01:27:04 PM PDT 24
Finished May 12 01:28:33 PM PDT 24
Peak memory 200492 kb
Host smart-f847800e-8f79-4103-a76b-acd7b6d8dcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913247746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.913247746
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.767948699
Short name T612
Test name
Test status
Simulation time 11582735069 ps
CPU time 150.55 seconds
Started May 12 01:26:59 PM PDT 24
Finished May 12 01:29:30 PM PDT 24
Peak memory 200328 kb
Host smart-2f57af71-c2dc-4d2b-bfd8-0b79aca19c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767948699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.767948699
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2218397605
Short name T882
Test name
Test status
Simulation time 6899680608 ps
CPU time 9.97 seconds
Started May 12 01:26:58 PM PDT 24
Finished May 12 01:27:08 PM PDT 24
Peak memory 199544 kb
Host smart-ecd203b0-958a-48e9-b4e4-57ae63646891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218397605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2218397605
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2365097550
Short name T1026
Test name
Test status
Simulation time 147655051453 ps
CPU time 63.32 seconds
Started May 12 01:26:59 PM PDT 24
Finished May 12 01:28:03 PM PDT 24
Peak memory 200516 kb
Host smart-ad8ad47a-96b1-49da-b215-767b89e3f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365097550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2365097550
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1552083852
Short name T637
Test name
Test status
Simulation time 1712911360 ps
CPU time 1.99 seconds
Started May 12 01:26:58 PM PDT 24
Finished May 12 01:27:00 PM PDT 24
Peak memory 196068 kb
Host smart-db621453-ef84-47d0-bba1-48f8f22fd8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552083852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1552083852
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3408229441
Short name T1044
Test name
Test status
Simulation time 473704550 ps
CPU time 2.26 seconds
Started May 12 01:26:54 PM PDT 24
Finished May 12 01:26:56 PM PDT 24
Peak memory 198668 kb
Host smart-20c37ef9-fe3f-4a08-9fdf-2a7cdf38df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408229441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3408229441
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3986142101
Short name T776
Test name
Test status
Simulation time 166073008456 ps
CPU time 278.01 seconds
Started May 12 01:27:03 PM PDT 24
Finished May 12 01:31:41 PM PDT 24
Peak memory 200304 kb
Host smart-8cc62c91-3e59-4ee8-9321-070faf456d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986142101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3986142101
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3917565954
Short name T146
Test name
Test status
Simulation time 253680249846 ps
CPU time 853.6 seconds
Started May 12 01:27:03 PM PDT 24
Finished May 12 01:41:17 PM PDT 24
Peak memory 216968 kb
Host smart-160cc078-6dab-4054-827a-7c381b7db1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917565954 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3917565954
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2478882221
Short name T1009
Test name
Test status
Simulation time 903174183 ps
CPU time 1.13 seconds
Started May 12 01:26:58 PM PDT 24
Finished May 12 01:27:00 PM PDT 24
Peak memory 197388 kb
Host smart-ff4ea4e2-c72a-436f-a24f-d58029386a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478882221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2478882221
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1773108692
Short name T303
Test name
Test status
Simulation time 300686255836 ps
CPU time 93.41 seconds
Started May 12 01:26:56 PM PDT 24
Finished May 12 01:28:29 PM PDT 24
Peak memory 200324 kb
Host smart-d19416e9-b030-4f61-a15b-24b185fe5d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773108692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1773108692
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.102411847
Short name T623
Test name
Test status
Simulation time 25013960 ps
CPU time 0.56 seconds
Started May 12 01:27:06 PM PDT 24
Finished May 12 01:27:07 PM PDT 24
Peak memory 195740 kb
Host smart-e1ae4b94-3bd8-4e8c-a48f-de725eadd5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102411847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.102411847
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.379364376
Short name T192
Test name
Test status
Simulation time 70839607802 ps
CPU time 31.03 seconds
Started May 12 01:27:04 PM PDT 24
Finished May 12 01:27:36 PM PDT 24
Peak memory 200428 kb
Host smart-4136cced-0212-4d4c-b964-35be4ddd0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379364376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.379364376
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1269479400
Short name T937
Test name
Test status
Simulation time 39297145356 ps
CPU time 21.26 seconds
Started May 12 01:27:02 PM PDT 24
Finished May 12 01:27:24 PM PDT 24
Peak memory 200316 kb
Host smart-1904d947-1814-4369-861d-218d9e2c6299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269479400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1269479400
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3641677373
Short name T475
Test name
Test status
Simulation time 69646891611 ps
CPU time 98.22 seconds
Started May 12 01:27:04 PM PDT 24
Finished May 12 01:28:42 PM PDT 24
Peak memory 200380 kb
Host smart-4455c153-6026-4371-b069-b53f7397bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641677373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3641677373
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2779058789
Short name T13
Test name
Test status
Simulation time 45385299637 ps
CPU time 37.54 seconds
Started May 12 01:27:06 PM PDT 24
Finished May 12 01:27:44 PM PDT 24
Peak memory 200024 kb
Host smart-adf4e3d3-5680-4dfa-8d7e-4cdc0c4ffef6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779058789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2779058789
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.559634200
Short name T511
Test name
Test status
Simulation time 137487155321 ps
CPU time 171.63 seconds
Started May 12 01:27:06 PM PDT 24
Finished May 12 01:29:58 PM PDT 24
Peak memory 200332 kb
Host smart-11440035-9655-4a3e-8878-6e208674d488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559634200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.559634200
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.983594859
Short name T1137
Test name
Test status
Simulation time 2160199611 ps
CPU time 1.4 seconds
Started May 12 01:27:07 PM PDT 24
Finished May 12 01:27:08 PM PDT 24
Peak memory 198504 kb
Host smart-64a55b7c-d0cf-4aa0-a3ea-db67bb32590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983594859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.983594859
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.488111143
Short name T425
Test name
Test status
Simulation time 127887366249 ps
CPU time 285.81 seconds
Started May 12 01:27:08 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 208772 kb
Host smart-37f647ba-0960-4544-8af7-85112cb1340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488111143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.488111143
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.140397664
Short name T406
Test name
Test status
Simulation time 8158683131 ps
CPU time 71.18 seconds
Started May 12 01:27:04 PM PDT 24
Finished May 12 01:28:16 PM PDT 24
Peak memory 200400 kb
Host smart-943991f0-ba1e-4ce4-823a-76c8b4376112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140397664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.140397664
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.304480795
Short name T917
Test name
Test status
Simulation time 6440997169 ps
CPU time 17.57 seconds
Started May 12 01:27:05 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 198456 kb
Host smart-071c98b5-50fd-408c-a616-8df873ed0cfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304480795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.304480795
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2145432276
Short name T633
Test name
Test status
Simulation time 119720905718 ps
CPU time 50.31 seconds
Started May 12 01:27:05 PM PDT 24
Finished May 12 01:27:56 PM PDT 24
Peak memory 200332 kb
Host smart-9e3c7d3b-c5ab-4799-9a48-c2e6cf57f841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145432276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2145432276
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.459736758
Short name T305
Test name
Test status
Simulation time 1705201792 ps
CPU time 2.94 seconds
Started May 12 01:27:05 PM PDT 24
Finished May 12 01:27:09 PM PDT 24
Peak memory 196024 kb
Host smart-fa014153-248a-401f-a6f3-08185f8498b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459736758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.459736758
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.626258063
Short name T347
Test name
Test status
Simulation time 107505187 ps
CPU time 0.92 seconds
Started May 12 01:27:06 PM PDT 24
Finished May 12 01:27:08 PM PDT 24
Peak memory 197460 kb
Host smart-29234c6d-3689-4d69-a79b-56417542c3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626258063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.626258063
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.811206588
Short name T671
Test name
Test status
Simulation time 241252544185 ps
CPU time 730.11 seconds
Started May 12 01:27:08 PM PDT 24
Finished May 12 01:39:19 PM PDT 24
Peak memory 216240 kb
Host smart-15f04e4d-0ec2-48c8-9616-4f5193e0ecbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811206588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.811206588
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1708283849
Short name T843
Test name
Test status
Simulation time 323380764388 ps
CPU time 475.01 seconds
Started May 12 01:27:08 PM PDT 24
Finished May 12 01:35:04 PM PDT 24
Peak memory 216976 kb
Host smart-9c6b0bd0-f3e6-424a-9753-5b36004075d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708283849 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1708283849
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1869785421
Short name T841
Test name
Test status
Simulation time 1321589028 ps
CPU time 2.01 seconds
Started May 12 01:27:08 PM PDT 24
Finished May 12 01:27:10 PM PDT 24
Peak memory 198788 kb
Host smart-7d9cb47a-c61b-4f2e-a385-4e2ead2d1990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869785421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1869785421
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2856539611
Short name T1185
Test name
Test status
Simulation time 20586718456 ps
CPU time 8.39 seconds
Started May 12 01:27:04 PM PDT 24
Finished May 12 01:27:13 PM PDT 24
Peak memory 200360 kb
Host smart-fc06b00f-17ef-4623-82e4-e53f7358171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856539611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2856539611
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2043163582
Short name T648
Test name
Test status
Simulation time 87291095 ps
CPU time 0.56 seconds
Started May 12 01:27:14 PM PDT 24
Finished May 12 01:27:15 PM PDT 24
Peak memory 195776 kb
Host smart-0fbf8447-1bd1-44b4-8684-1af88311a8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043163582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2043163582
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3135689474
Short name T804
Test name
Test status
Simulation time 57382086556 ps
CPU time 24.92 seconds
Started May 12 01:27:08 PM PDT 24
Finished May 12 01:27:33 PM PDT 24
Peak memory 200412 kb
Host smart-3cf9c9bd-5748-4eec-9939-98fcb150dd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135689474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3135689474
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1290061526
Short name T487
Test name
Test status
Simulation time 121068972331 ps
CPU time 203.75 seconds
Started May 12 01:27:10 PM PDT 24
Finished May 12 01:30:34 PM PDT 24
Peak memory 200456 kb
Host smart-1634df65-6824-495f-b114-a45d59872619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290061526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1290061526
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1994988310
Short name T247
Test name
Test status
Simulation time 53201378352 ps
CPU time 65.46 seconds
Started May 12 01:27:09 PM PDT 24
Finished May 12 01:28:15 PM PDT 24
Peak memory 200324 kb
Host smart-9b00b892-bbce-4898-b88d-810f887b6006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994988310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1994988310
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1322618471
Short name T842
Test name
Test status
Simulation time 44484574441 ps
CPU time 56.59 seconds
Started May 12 01:27:09 PM PDT 24
Finished May 12 01:28:06 PM PDT 24
Peak memory 200204 kb
Host smart-477b9491-106b-40a1-9fa7-38c3497b1956
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322618471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1322618471
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1849921028
Short name T357
Test name
Test status
Simulation time 206663560244 ps
CPU time 409.85 seconds
Started May 12 01:27:14 PM PDT 24
Finished May 12 01:34:05 PM PDT 24
Peak memory 200388 kb
Host smart-d3f6870d-7ee5-45d8-8929-eed1c832ed00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849921028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1849921028
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3151399711
Short name T1158
Test name
Test status
Simulation time 8534631081 ps
CPU time 9.45 seconds
Started May 12 01:27:13 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 200420 kb
Host smart-055e9a03-b465-473a-92c5-52c05c4c2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151399711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3151399711
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.2901990111
Short name T1133
Test name
Test status
Simulation time 6309303720 ps
CPU time 91.74 seconds
Started May 12 01:27:13 PM PDT 24
Finished May 12 01:28:46 PM PDT 24
Peak memory 200508 kb
Host smart-eb3caa86-4723-4026-90e0-708d7f8368e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901990111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2901990111
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1951997016
Short name T403
Test name
Test status
Simulation time 4634076457 ps
CPU time 21.51 seconds
Started May 12 01:27:11 PM PDT 24
Finished May 12 01:27:33 PM PDT 24
Peak memory 199636 kb
Host smart-ee0f416e-c40a-4088-8485-79a83e2916c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951997016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1951997016
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4076929534
Short name T622
Test name
Test status
Simulation time 195006923890 ps
CPU time 287.42 seconds
Started May 12 01:27:09 PM PDT 24
Finished May 12 01:31:57 PM PDT 24
Peak memory 200352 kb
Host smart-fdb97a51-a8b6-49e4-bf79-ebd58ce369b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076929534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4076929534
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1659978177
Short name T1011
Test name
Test status
Simulation time 4666584482 ps
CPU time 8.07 seconds
Started May 12 01:27:10 PM PDT 24
Finished May 12 01:27:19 PM PDT 24
Peak memory 196708 kb
Host smart-16f6836f-2176-4ded-acbd-0c9ea4572644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659978177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1659978177
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2097348580
Short name T288
Test name
Test status
Simulation time 5880943760 ps
CPU time 7.78 seconds
Started May 12 01:27:05 PM PDT 24
Finished May 12 01:27:13 PM PDT 24
Peak memory 199572 kb
Host smart-7648be4a-597e-4a12-96ca-bf6f6d666b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097348580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2097348580
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.699300882
Short name T581
Test name
Test status
Simulation time 148822677333 ps
CPU time 918.01 seconds
Started May 12 01:27:13 PM PDT 24
Finished May 12 01:42:31 PM PDT 24
Peak memory 200336 kb
Host smart-bc4ef5df-5544-4aca-aece-a1a7ed17d2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699300882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.699300882
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.354684744
Short name T1059
Test name
Test status
Simulation time 76944303417 ps
CPU time 1102.21 seconds
Started May 12 01:27:12 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 225268 kb
Host smart-3c7e6471-6d4c-41a3-9784-8cd8ee8365b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354684744 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.354684744
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1550006892
Short name T1131
Test name
Test status
Simulation time 1012780745 ps
CPU time 1.99 seconds
Started May 12 01:27:14 PM PDT 24
Finished May 12 01:27:17 PM PDT 24
Peak memory 198984 kb
Host smart-16912218-fef5-4056-8db8-24060c79f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550006892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1550006892
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2379644342
Short name T636
Test name
Test status
Simulation time 38914175387 ps
CPU time 92.33 seconds
Started May 12 01:27:05 PM PDT 24
Finished May 12 01:28:38 PM PDT 24
Peak memory 200356 kb
Host smart-e81d3d2d-d7af-4d62-ad98-6b4c1b293a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379644342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2379644342
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.393853324
Short name T542
Test name
Test status
Simulation time 32404578 ps
CPU time 0.53 seconds
Started May 12 01:27:20 PM PDT 24
Finished May 12 01:27:21 PM PDT 24
Peak memory 195696 kb
Host smart-423ab92b-b32f-4fe3-81b0-b51fcb8d3852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393853324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.393853324
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1667567938
Short name T427
Test name
Test status
Simulation time 29110062302 ps
CPU time 48.86 seconds
Started May 12 01:27:22 PM PDT 24
Finished May 12 01:28:11 PM PDT 24
Peak memory 200336 kb
Host smart-0b1f7eb9-956b-47da-ae01-005e5b456cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667567938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1667567938
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2266307790
Short name T723
Test name
Test status
Simulation time 234157492575 ps
CPU time 31.79 seconds
Started May 12 01:27:14 PM PDT 24
Finished May 12 01:27:46 PM PDT 24
Peak memory 200368 kb
Host smart-cc96a2ab-8c72-4a01-99db-3b4f83ca5b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266307790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2266307790
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2793646531
Short name T195
Test name
Test status
Simulation time 118237954246 ps
CPU time 15.58 seconds
Started May 12 01:27:15 PM PDT 24
Finished May 12 01:27:32 PM PDT 24
Peak memory 200344 kb
Host smart-bffc7760-64e6-4a45-bfdf-7c5abe0e8c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793646531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2793646531
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3741583531
Short name T470
Test name
Test status
Simulation time 34322953539 ps
CPU time 20.15 seconds
Started May 12 01:27:15 PM PDT 24
Finished May 12 01:27:36 PM PDT 24
Peak memory 200352 kb
Host smart-c2d7e735-4c08-4350-83a1-bee0c42e217d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741583531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3741583531
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1326436925
Short name T902
Test name
Test status
Simulation time 53342234819 ps
CPU time 306.6 seconds
Started May 12 01:27:17 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 200364 kb
Host smart-a2d3afc2-01f9-4589-aeaa-26c63e10d3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326436925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1326436925
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3707450080
Short name T515
Test name
Test status
Simulation time 5448860990 ps
CPU time 10.33 seconds
Started May 12 01:27:18 PM PDT 24
Finished May 12 01:27:29 PM PDT 24
Peak memory 196992 kb
Host smart-bdc68bf1-4a0f-4499-b4a8-54ef2b1b40a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707450080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3707450080
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1706919124
Short name T411
Test name
Test status
Simulation time 31880058147 ps
CPU time 14.15 seconds
Started May 12 01:27:16 PM PDT 24
Finished May 12 01:27:31 PM PDT 24
Peak memory 196312 kb
Host smart-6c7230f0-895d-4d2b-b2c2-ed84c45bdc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706919124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1706919124
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.712682163
Short name T799
Test name
Test status
Simulation time 12316622259 ps
CPU time 704.59 seconds
Started May 12 01:27:20 PM PDT 24
Finished May 12 01:39:05 PM PDT 24
Peak memory 200312 kb
Host smart-5be8da47-ad75-40fc-9f6d-a588019d01d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712682163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.712682163
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1257657955
Short name T118
Test name
Test status
Simulation time 7222914508 ps
CPU time 15.24 seconds
Started May 12 01:27:19 PM PDT 24
Finished May 12 01:27:35 PM PDT 24
Peak memory 199084 kb
Host smart-56ce108c-1237-4400-a3f6-3415906c41ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257657955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1257657955
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2034745081
Short name T378
Test name
Test status
Simulation time 38678419337 ps
CPU time 19.1 seconds
Started May 12 01:27:16 PM PDT 24
Finished May 12 01:27:36 PM PDT 24
Peak memory 199748 kb
Host smart-eef93fed-4b95-4005-9666-345720d409f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034745081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2034745081
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.424360955
Short name T788
Test name
Test status
Simulation time 4059450741 ps
CPU time 1.81 seconds
Started May 12 01:27:15 PM PDT 24
Finished May 12 01:27:17 PM PDT 24
Peak memory 196384 kb
Host smart-a729f11e-71fa-4e07-aacf-9742b8941d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424360955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.424360955
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3586874170
Short name T297
Test name
Test status
Simulation time 430770929 ps
CPU time 1.97 seconds
Started May 12 01:27:14 PM PDT 24
Finished May 12 01:27:16 PM PDT 24
Peak memory 198636 kb
Host smart-b00b2f81-3831-4439-9854-eabe4a9ab91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586874170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3586874170
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1595241040
Short name T941
Test name
Test status
Simulation time 69542289449 ps
CPU time 118.51 seconds
Started May 12 01:27:18 PM PDT 24
Finished May 12 01:29:16 PM PDT 24
Peak memory 200284 kb
Host smart-7df7d805-da67-47c9-83be-8aea13eaefd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595241040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1595241040
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.171117927
Short name T871
Test name
Test status
Simulation time 561723513 ps
CPU time 1.74 seconds
Started May 12 01:27:12 PM PDT 24
Finished May 12 01:27:14 PM PDT 24
Peak memory 198584 kb
Host smart-988164b3-01f4-4443-baf8-d7cb08c83593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171117927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.171117927
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1215088918
Short name T712
Test name
Test status
Simulation time 16801280773 ps
CPU time 7.87 seconds
Started May 12 01:27:15 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 200336 kb
Host smart-7d249fad-c37c-4316-9ad3-f3d07b5f3ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215088918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1215088918
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2903441948
Short name T716
Test name
Test status
Simulation time 22138219 ps
CPU time 0.53 seconds
Started May 12 01:27:23 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 194740 kb
Host smart-067e5651-ac67-4bb5-be8e-56424c2a59fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903441948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2903441948
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.757949537
Short name T779
Test name
Test status
Simulation time 44446030940 ps
CPU time 84.84 seconds
Started May 12 01:27:19 PM PDT 24
Finished May 12 01:28:44 PM PDT 24
Peak memory 200404 kb
Host smart-253c0b51-0630-42b1-90b7-81f53395ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757949537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.757949537
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.53329172
Short name T104
Test name
Test status
Simulation time 22662094528 ps
CPU time 51.75 seconds
Started May 12 01:27:16 PM PDT 24
Finished May 12 01:28:09 PM PDT 24
Peak memory 200392 kb
Host smart-1fd09ec3-e3e9-4acf-9a7c-ca1456a8facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53329172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.53329172
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.947862415
Short name T1095
Test name
Test status
Simulation time 5768752133 ps
CPU time 2.07 seconds
Started May 12 01:27:21 PM PDT 24
Finished May 12 01:27:24 PM PDT 24
Peak memory 197000 kb
Host smart-a03cf9d7-f468-419d-8b8a-202080335249
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947862415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.947862415
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2422177996
Short name T883
Test name
Test status
Simulation time 58485648196 ps
CPU time 274.72 seconds
Started May 12 01:27:21 PM PDT 24
Finished May 12 01:31:56 PM PDT 24
Peak memory 200384 kb
Host smart-e7b5815f-c44b-4134-b793-ee0bda46ace1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422177996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2422177996
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3673413311
Short name T803
Test name
Test status
Simulation time 7725648495 ps
CPU time 12.42 seconds
Started May 12 01:27:22 PM PDT 24
Finished May 12 01:27:35 PM PDT 24
Peak memory 198932 kb
Host smart-9381b436-02a3-4b93-b79c-149027478f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673413311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3673413311
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1632234515
Short name T123
Test name
Test status
Simulation time 444764283594 ps
CPU time 67.65 seconds
Started May 12 01:27:16 PM PDT 24
Finished May 12 01:28:25 PM PDT 24
Peak memory 208744 kb
Host smart-ec071218-ee8e-4c88-a60b-61072acbd8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632234515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1632234515
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.612644655
Short name T855
Test name
Test status
Simulation time 21856272618 ps
CPU time 1205.75 seconds
Started May 12 01:27:20 PM PDT 24
Finished May 12 01:47:27 PM PDT 24
Peak memory 200240 kb
Host smart-40e5990f-7c7b-437e-b2d3-064d865807c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612644655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.612644655
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3330721550
Short name T419
Test name
Test status
Simulation time 1607583989 ps
CPU time 2.88 seconds
Started May 12 01:27:15 PM PDT 24
Finished May 12 01:27:19 PM PDT 24
Peak memory 198532 kb
Host smart-c4e870a6-faa3-4e6d-be3b-d489fb77e3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330721550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3330721550
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.899154964
Short name T18
Test name
Test status
Simulation time 111033363830 ps
CPU time 43.27 seconds
Started May 12 01:27:26 PM PDT 24
Finished May 12 01:28:09 PM PDT 24
Peak memory 200228 kb
Host smart-e7007346-5c63-4c75-89a3-c37cb66ecc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899154964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.899154964
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2393197939
Short name T422
Test name
Test status
Simulation time 2086020606 ps
CPU time 1.45 seconds
Started May 12 01:27:21 PM PDT 24
Finished May 12 01:27:23 PM PDT 24
Peak memory 196048 kb
Host smart-6e1afcca-a5ac-4ffc-9a8f-95fc83a39045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393197939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2393197939
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1306729008
Short name T782
Test name
Test status
Simulation time 300209354 ps
CPU time 1.08 seconds
Started May 12 01:27:18 PM PDT 24
Finished May 12 01:27:19 PM PDT 24
Peak memory 198904 kb
Host smart-6efc82d6-8026-423b-8397-c68d94946def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306729008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1306729008
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.703105079
Short name T621
Test name
Test status
Simulation time 137950991481 ps
CPU time 291.13 seconds
Started May 12 01:27:21 PM PDT 24
Finished May 12 01:32:13 PM PDT 24
Peak memory 208724 kb
Host smart-364c757b-8b79-4701-9ef1-cf0b40a5a472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703105079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.703105079
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.777479585
Short name T505
Test name
Test status
Simulation time 15290978875 ps
CPU time 157.61 seconds
Started May 12 01:27:21 PM PDT 24
Finished May 12 01:29:59 PM PDT 24
Peak memory 208716 kb
Host smart-fe1105d5-9c03-45c1-b474-ee9741207cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777479585 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.777479585
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1131850462
Short name T434
Test name
Test status
Simulation time 569991161 ps
CPU time 2.08 seconds
Started May 12 01:27:19 PM PDT 24
Finished May 12 01:27:21 PM PDT 24
Peak memory 199376 kb
Host smart-b0716d73-da2c-4acf-8739-13c82c1304b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131850462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1131850462
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2869045690
Short name T382
Test name
Test status
Simulation time 46824575795 ps
CPU time 74.35 seconds
Started May 12 01:27:16 PM PDT 24
Finished May 12 01:28:32 PM PDT 24
Peak memory 200360 kb
Host smart-e2cc8f9e-c2d0-4938-b0e3-5fb55640b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869045690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2869045690
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2537861979
Short name T814
Test name
Test status
Simulation time 11667603 ps
CPU time 0.57 seconds
Started May 12 01:27:27 PM PDT 24
Finished May 12 01:27:28 PM PDT 24
Peak memory 195776 kb
Host smart-81df78bc-dffb-41e0-995a-af37de336626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537861979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2537861979
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2734637501
Short name T607
Test name
Test status
Simulation time 39135430034 ps
CPU time 65.66 seconds
Started May 12 01:27:26 PM PDT 24
Finished May 12 01:28:32 PM PDT 24
Peak memory 200376 kb
Host smart-c3640166-72af-494d-8942-2ddf0341be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734637501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2734637501
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2965168891
Short name T306
Test name
Test status
Simulation time 37389232393 ps
CPU time 63.44 seconds
Started May 12 01:27:22 PM PDT 24
Finished May 12 01:28:26 PM PDT 24
Peak memory 200308 kb
Host smart-ff926a13-3dc3-443d-be6b-1a5109e3bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965168891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2965168891
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.1291177748
Short name T643
Test name
Test status
Simulation time 871216808 ps
CPU time 1.88 seconds
Started May 12 01:27:23 PM PDT 24
Finished May 12 01:27:25 PM PDT 24
Peak memory 195868 kb
Host smart-b3c9e3cb-24ed-4884-8043-46973544adb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291177748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1291177748
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.509397894
Short name T1127
Test name
Test status
Simulation time 138937581627 ps
CPU time 767.14 seconds
Started May 12 01:27:28 PM PDT 24
Finished May 12 01:40:16 PM PDT 24
Peak memory 200256 kb
Host smart-0fb98c8e-0715-4110-89af-07a004b818c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509397894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.509397894
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1345525171
Short name T591
Test name
Test status
Simulation time 5289585611 ps
CPU time 15.18 seconds
Started May 12 01:27:26 PM PDT 24
Finished May 12 01:27:42 PM PDT 24
Peak memory 199036 kb
Host smart-c38f9767-a255-4136-a205-4cdb5ea60b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345525171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1345525171
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1416146948
Short name T28
Test name
Test status
Simulation time 90119926724 ps
CPU time 169.48 seconds
Started May 12 01:27:33 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 208468 kb
Host smart-7aa774ec-fd0a-4624-a1a0-8ce0f7a425d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416146948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1416146948
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3962805203
Short name T717
Test name
Test status
Simulation time 19869929303 ps
CPU time 443.61 seconds
Started May 12 01:27:28 PM PDT 24
Finished May 12 01:34:52 PM PDT 24
Peak memory 200216 kb
Host smart-9243f648-d7f8-48ab-abf8-0b946db1843f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962805203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3962805203
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3980504211
Short name T933
Test name
Test status
Simulation time 3890101957 ps
CPU time 29 seconds
Started May 12 01:27:24 PM PDT 24
Finished May 12 01:27:53 PM PDT 24
Peak memory 199288 kb
Host smart-3f7e7ca9-e894-484f-b141-613ff57802ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980504211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3980504211
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.989293452
Short name T748
Test name
Test status
Simulation time 22786515221 ps
CPU time 36.94 seconds
Started May 12 01:27:23 PM PDT 24
Finished May 12 01:28:01 PM PDT 24
Peak memory 200396 kb
Host smart-a5beec5e-076a-4062-a621-6f579eaa659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989293452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.989293452
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1127577983
Short name T433
Test name
Test status
Simulation time 34500110130 ps
CPU time 50.99 seconds
Started May 12 01:27:23 PM PDT 24
Finished May 12 01:28:14 PM PDT 24
Peak memory 196332 kb
Host smart-d3291135-d921-4723-9195-03d4c1735168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127577983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1127577983
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2244819400
Short name T791
Test name
Test status
Simulation time 886689869 ps
CPU time 3.72 seconds
Started May 12 01:27:25 PM PDT 24
Finished May 12 01:27:29 PM PDT 24
Peak memory 198644 kb
Host smart-044c797e-bdce-41d4-86d9-47f14355b724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244819400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2244819400
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2099394110
Short name T919
Test name
Test status
Simulation time 275921716916 ps
CPU time 957.25 seconds
Started May 12 01:27:30 PM PDT 24
Finished May 12 01:43:27 PM PDT 24
Peak memory 200264 kb
Host smart-672e3430-e93a-4371-bc75-19094c6d3245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099394110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2099394110
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.672427478
Short name T1093
Test name
Test status
Simulation time 339755327912 ps
CPU time 1298.6 seconds
Started May 12 01:27:29 PM PDT 24
Finished May 12 01:49:08 PM PDT 24
Peak memory 225564 kb
Host smart-aaf142fb-1305-4f9a-b53d-4761763ab32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672427478 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.672427478
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2488049045
Short name T376
Test name
Test status
Simulation time 9417036652 ps
CPU time 5.28 seconds
Started May 12 01:27:29 PM PDT 24
Finished May 12 01:27:35 PM PDT 24
Peak memory 200256 kb
Host smart-1f44a32f-13a7-42f5-a26a-4175e8086a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488049045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2488049045
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1614127996
Short name T1079
Test name
Test status
Simulation time 117592935405 ps
CPU time 51.66 seconds
Started May 12 01:27:24 PM PDT 24
Finished May 12 01:28:17 PM PDT 24
Peak memory 200340 kb
Host smart-2d4eb69a-4831-4d3a-b35e-4c1c75564e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614127996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1614127996
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1207139224
Short name T431
Test name
Test status
Simulation time 42072297 ps
CPU time 0.53 seconds
Started May 12 01:27:36 PM PDT 24
Finished May 12 01:27:37 PM PDT 24
Peak memory 194768 kb
Host smart-df3805c2-657b-4b6d-8ae7-d6bb3241c6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207139224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1207139224
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3025554710
Short name T860
Test name
Test status
Simulation time 34377915569 ps
CPU time 35.45 seconds
Started May 12 01:27:27 PM PDT 24
Finished May 12 01:28:02 PM PDT 24
Peak memory 200356 kb
Host smart-353b5fdd-a77d-41a2-a741-e085bf654a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025554710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3025554710
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.960808384
Short name T398
Test name
Test status
Simulation time 106677498814 ps
CPU time 262.02 seconds
Started May 12 01:27:29 PM PDT 24
Finished May 12 01:31:51 PM PDT 24
Peak memory 200384 kb
Host smart-70b423b5-a4c2-4906-8a34-1f7803ebc811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960808384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.960808384
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1422691781
Short name T1170
Test name
Test status
Simulation time 42139423057 ps
CPU time 66.34 seconds
Started May 12 01:27:28 PM PDT 24
Finished May 12 01:28:35 PM PDT 24
Peak memory 200272 kb
Host smart-c16c01d7-7cbf-473b-9b16-59d631cbd93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422691781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1422691781
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4090459494
Short name T662
Test name
Test status
Simulation time 72208634810 ps
CPU time 136.03 seconds
Started May 12 01:27:31 PM PDT 24
Finished May 12 01:29:48 PM PDT 24
Peak memory 200344 kb
Host smart-2c3b1a8c-58fe-4ffe-abed-528bc725f3dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090459494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4090459494
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4073578291
Short name T962
Test name
Test status
Simulation time 116758534992 ps
CPU time 662.38 seconds
Started May 12 01:27:30 PM PDT 24
Finished May 12 01:38:33 PM PDT 24
Peak memory 200316 kb
Host smart-db3898df-d373-48d7-961e-628cc3cd5af2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073578291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4073578291
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.276049947
Short name T604
Test name
Test status
Simulation time 5376806688 ps
CPU time 10.98 seconds
Started May 12 01:27:33 PM PDT 24
Finished May 12 01:27:44 PM PDT 24
Peak memory 199468 kb
Host smart-5f23b64d-8b13-4af6-8a6b-076e29afa739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276049947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.276049947
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3297636168
Short name T733
Test name
Test status
Simulation time 34949983744 ps
CPU time 20.05 seconds
Started May 12 01:27:30 PM PDT 24
Finished May 12 01:27:51 PM PDT 24
Peak memory 200376 kb
Host smart-1c0e093c-067f-4bc1-a658-a86dd06b1742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297636168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3297636168
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1555853691
Short name T589
Test name
Test status
Simulation time 11586967503 ps
CPU time 116.45 seconds
Started May 12 01:27:31 PM PDT 24
Finished May 12 01:29:28 PM PDT 24
Peak memory 200288 kb
Host smart-2f612576-7b3f-463d-81c1-04a911f4bec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555853691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1555853691
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2821142467
Short name T691
Test name
Test status
Simulation time 3691576780 ps
CPU time 10.82 seconds
Started May 12 01:27:29 PM PDT 24
Finished May 12 01:27:41 PM PDT 24
Peak memory 198632 kb
Host smart-1b507d7a-caba-4a68-9c34-e6aa51d734e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821142467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2821142467
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2710684523
Short name T535
Test name
Test status
Simulation time 21107964077 ps
CPU time 45.73 seconds
Started May 12 01:27:31 PM PDT 24
Finished May 12 01:28:18 PM PDT 24
Peak memory 200376 kb
Host smart-7849cdff-8f8e-4c25-be9c-f191abda954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710684523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2710684523
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3692737887
Short name T689
Test name
Test status
Simulation time 1761157937 ps
CPU time 1.46 seconds
Started May 12 01:27:32 PM PDT 24
Finished May 12 01:27:34 PM PDT 24
Peak memory 195764 kb
Host smart-4d7ae169-a06d-460e-a87b-4fb42ecb309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692737887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3692737887
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3002987399
Short name T696
Test name
Test status
Simulation time 6040446143 ps
CPU time 10.23 seconds
Started May 12 01:27:28 PM PDT 24
Finished May 12 01:27:39 PM PDT 24
Peak memory 200192 kb
Host smart-308e5201-072c-4edb-9e0d-665532c4364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002987399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3002987399
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2955359104
Short name T547
Test name
Test status
Simulation time 272070659122 ps
CPU time 1356.6 seconds
Started May 12 01:27:34 PM PDT 24
Finished May 12 01:50:11 PM PDT 24
Peak memory 200428 kb
Host smart-f4e7a683-64ec-481d-9d8d-624b0e30c4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955359104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2955359104
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2362039955
Short name T564
Test name
Test status
Simulation time 42198770220 ps
CPU time 573.38 seconds
Started May 12 01:27:33 PM PDT 24
Finished May 12 01:37:07 PM PDT 24
Peak memory 211200 kb
Host smart-52feae89-cd12-42c2-af4d-61ab0ff92331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362039955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2362039955
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3842703950
Short name T938
Test name
Test status
Simulation time 12099314308 ps
CPU time 16.36 seconds
Started May 12 01:27:31 PM PDT 24
Finished May 12 01:27:48 PM PDT 24
Peak memory 200228 kb
Host smart-c7f23608-2e6b-4e04-b383-fb7d1e84250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842703950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3842703950
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1030168468
Short name T850
Test name
Test status
Simulation time 36623214366 ps
CPU time 66.56 seconds
Started May 12 01:27:27 PM PDT 24
Finished May 12 01:28:34 PM PDT 24
Peak memory 200304 kb
Host smart-d235b79e-3ffe-45e5-a87b-37c72e20ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030168468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1030168468
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2375993040
Short name T32
Test name
Test status
Simulation time 30514608 ps
CPU time 0.55 seconds
Started May 12 01:27:39 PM PDT 24
Finished May 12 01:27:40 PM PDT 24
Peak memory 195772 kb
Host smart-113a78c5-ae36-4781-ace7-d73ca4802c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375993040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2375993040
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2070082555
Short name T775
Test name
Test status
Simulation time 107481947631 ps
CPU time 48.62 seconds
Started May 12 01:27:34 PM PDT 24
Finished May 12 01:28:23 PM PDT 24
Peak memory 200356 kb
Host smart-548502e9-ea51-4c07-8287-5112d604c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070082555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2070082555
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2538934887
Short name T1141
Test name
Test status
Simulation time 167165333284 ps
CPU time 149.8 seconds
Started May 12 01:27:34 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 200488 kb
Host smart-45fc348f-1817-4a04-8350-cdb3768e40ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538934887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2538934887
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3378464922
Short name T556
Test name
Test status
Simulation time 29018222064 ps
CPU time 24.73 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:28:09 PM PDT 24
Peak memory 200376 kb
Host smart-c94bdaa3-09b5-4d0f-8807-74e061d72b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378464922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3378464922
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3453784900
Short name T700
Test name
Test status
Simulation time 34969772938 ps
CPU time 15.55 seconds
Started May 12 01:27:37 PM PDT 24
Finished May 12 01:27:53 PM PDT 24
Peak memory 197544 kb
Host smart-85b8519d-8e24-41be-84be-6d08ac54574f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453784900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3453784900
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1077176369
Short name T51
Test name
Test status
Simulation time 122235074965 ps
CPU time 955.8 seconds
Started May 12 01:27:41 PM PDT 24
Finished May 12 01:43:38 PM PDT 24
Peak memory 200368 kb
Host smart-bd6f406e-f86a-4702-9cff-1141e88965ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077176369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1077176369
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2839702586
Short name T26
Test name
Test status
Simulation time 5350323823 ps
CPU time 10.45 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:27:54 PM PDT 24
Peak memory 200120 kb
Host smart-f2d323b0-d21c-40ce-84b6-3d59e38541c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839702586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2839702586
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3411808413
Short name T468
Test name
Test status
Simulation time 32954289524 ps
CPU time 14.71 seconds
Started May 12 01:27:36 PM PDT 24
Finished May 12 01:27:51 PM PDT 24
Peak memory 199084 kb
Host smart-8f9eadb0-c80c-406a-9535-0fc19b32037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411808413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3411808413
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2214428278
Short name T826
Test name
Test status
Simulation time 4794206663 ps
CPU time 141.31 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:30:06 PM PDT 24
Peak memory 200408 kb
Host smart-000574a6-e15a-46a9-980e-16f4deb0509f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214428278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2214428278
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4259506779
Short name T23
Test name
Test status
Simulation time 6070432897 ps
CPU time 47.43 seconds
Started May 12 01:27:37 PM PDT 24
Finished May 12 01:28:24 PM PDT 24
Peak memory 199380 kb
Host smart-c8000e00-84eb-404a-bbec-02d95fac6295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259506779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4259506779
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1562093597
Short name T550
Test name
Test status
Simulation time 152515598842 ps
CPU time 114.74 seconds
Started May 12 01:27:35 PM PDT 24
Finished May 12 01:29:30 PM PDT 24
Peak memory 200320 kb
Host smart-22e99657-d7f8-4143-a1fd-4313f9d13ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562093597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1562093597
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1976924941
Short name T393
Test name
Test status
Simulation time 3481118132 ps
CPU time 6.54 seconds
Started May 12 01:27:34 PM PDT 24
Finished May 12 01:27:41 PM PDT 24
Peak memory 196384 kb
Host smart-64a6dbbe-df99-41b7-9b7f-ec2513340163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976924941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1976924941
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.162316254
Short name T391
Test name
Test status
Simulation time 460630517 ps
CPU time 1.22 seconds
Started May 12 01:27:36 PM PDT 24
Finished May 12 01:27:37 PM PDT 24
Peak memory 198972 kb
Host smart-28a72256-c5a1-466f-bae4-f00f10c4d8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162316254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.162316254
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1576326023
Short name T330
Test name
Test status
Simulation time 70349000429 ps
CPU time 27.95 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:28:10 PM PDT 24
Peak memory 200416 kb
Host smart-4ca38c46-9049-4f3f-bf7b-67dbdfa7e1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576326023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1576326023
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2123486539
Short name T24
Test name
Test status
Simulation time 54007148466 ps
CPU time 119.18 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:29:44 PM PDT 24
Peak memory 213664 kb
Host smart-eb9f4fe9-c1cf-4164-8412-ccc92007584d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123486539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2123486539
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3548514727
Short name T309
Test name
Test status
Simulation time 7583171337 ps
CPU time 8.95 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:27:53 PM PDT 24
Peak memory 200332 kb
Host smart-55dc7d18-21b3-42db-9ec8-b1051c1ecd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548514727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3548514727
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.980666926
Short name T912
Test name
Test status
Simulation time 84143485133 ps
CPU time 72.97 seconds
Started May 12 01:27:35 PM PDT 24
Finished May 12 01:28:49 PM PDT 24
Peak memory 200344 kb
Host smart-b118e83a-b22d-4bae-8cd2-b25ed428e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980666926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.980666926
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1658118553
Short name T1177
Test name
Test status
Simulation time 38363835 ps
CPU time 0.55 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:27:43 PM PDT 24
Peak memory 195772 kb
Host smart-f398d099-7b4d-498c-a7de-0f84521f2059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658118553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1658118553
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1430282567
Short name T911
Test name
Test status
Simulation time 24658336615 ps
CPU time 41.95 seconds
Started May 12 01:27:40 PM PDT 24
Finished May 12 01:28:22 PM PDT 24
Peak memory 200276 kb
Host smart-4bead55a-62f1-4944-a8d8-e67c196cbed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430282567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1430282567
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.463517129
Short name T976
Test name
Test status
Simulation time 83212524600 ps
CPU time 23.11 seconds
Started May 12 01:27:43 PM PDT 24
Finished May 12 01:28:06 PM PDT 24
Peak memory 200316 kb
Host smart-ecc45352-9397-453e-9b7c-10f26f46f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463517129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.463517129
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.266577942
Short name T264
Test name
Test status
Simulation time 21326546735 ps
CPU time 19.74 seconds
Started May 12 01:27:40 PM PDT 24
Finished May 12 01:28:01 PM PDT 24
Peak memory 200392 kb
Host smart-e48fad38-8eb8-46f5-b608-1692950fba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266577942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.266577942
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3004919381
Short name T138
Test name
Test status
Simulation time 10625925184 ps
CPU time 10.07 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:27:52 PM PDT 24
Peak memory 197528 kb
Host smart-0acd710e-3418-4eca-9cb1-614ea51d49b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004919381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3004919381
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3275304126
Short name T274
Test name
Test status
Simulation time 123948789376 ps
CPU time 788.57 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:40:51 PM PDT 24
Peak memory 200416 kb
Host smart-c4bad60c-3a20-4250-88ef-097ac93d14ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275304126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3275304126
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4281117920
Short name T1022
Test name
Test status
Simulation time 3488377072 ps
CPU time 2.38 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:27:44 PM PDT 24
Peak memory 199660 kb
Host smart-d773ddde-0344-420e-b9d1-1a687d952fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281117920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4281117920
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2351762884
Short name T1105
Test name
Test status
Simulation time 29795344460 ps
CPU time 46.89 seconds
Started May 12 01:27:40 PM PDT 24
Finished May 12 01:28:28 PM PDT 24
Peak memory 198860 kb
Host smart-d5d8d486-925d-4449-a4de-c8f500632d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351762884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2351762884
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.179087165
Short name T514
Test name
Test status
Simulation time 16077488235 ps
CPU time 418.63 seconds
Started May 12 01:27:45 PM PDT 24
Finished May 12 01:34:44 PM PDT 24
Peak memory 200376 kb
Host smart-a95998f0-def7-4a81-abe4-b091862a9e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179087165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.179087165
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2989131785
Short name T1172
Test name
Test status
Simulation time 3200951059 ps
CPU time 3.44 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:27:48 PM PDT 24
Peak memory 198756 kb
Host smart-1f75bfdd-17a3-406b-8d24-946e22e8ce44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989131785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2989131785
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3960092685
Short name T946
Test name
Test status
Simulation time 26877156951 ps
CPU time 46.24 seconds
Started May 12 01:27:39 PM PDT 24
Finished May 12 01:28:26 PM PDT 24
Peak memory 200152 kb
Host smart-2b1518e7-5657-4a1e-9e63-5c3ea59928d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960092685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3960092685
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1764920566
Short name T540
Test name
Test status
Simulation time 633061407 ps
CPU time 1.62 seconds
Started May 12 01:27:41 PM PDT 24
Finished May 12 01:27:43 PM PDT 24
Peak memory 195748 kb
Host smart-f58beb8b-5d3a-478c-bc29-ef7934e9f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764920566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1764920566
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3024491924
Short name T599
Test name
Test status
Simulation time 5352209320 ps
CPU time 7.27 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:27:50 PM PDT 24
Peak memory 200224 kb
Host smart-49646b5e-3597-42e7-ac7c-f607606306d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024491924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3024491924
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3524401107
Short name T249
Test name
Test status
Simulation time 281313566930 ps
CPU time 396.62 seconds
Started May 12 01:27:43 PM PDT 24
Finished May 12 01:34:20 PM PDT 24
Peak memory 200400 kb
Host smart-617e5600-ab60-41d2-904f-fe3d2cf678ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524401107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3524401107
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1315638470
Short name T232
Test name
Test status
Simulation time 213067873177 ps
CPU time 644.56 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:38:28 PM PDT 24
Peak memory 225276 kb
Host smart-15d99a41-84bd-49d2-8bc6-196a672b013a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315638470 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1315638470
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1593859849
Short name T375
Test name
Test status
Simulation time 854307218 ps
CPU time 2.15 seconds
Started May 12 01:27:43 PM PDT 24
Finished May 12 01:27:46 PM PDT 24
Peak memory 198652 kb
Host smart-b766f270-cf7d-492e-a078-b51f3135103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593859849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1593859849
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1005374031
Short name T907
Test name
Test status
Simulation time 113941438786 ps
CPU time 390.96 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:34:14 PM PDT 24
Peak memory 200388 kb
Host smart-dd254be0-b351-4cd6-89c6-e0b2c869ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005374031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1005374031
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3937186107
Short name T705
Test name
Test status
Simulation time 11130308 ps
CPU time 0.53 seconds
Started May 12 01:27:50 PM PDT 24
Finished May 12 01:27:51 PM PDT 24
Peak memory 195132 kb
Host smart-bb744f9e-3ac1-4a32-8f59-f5a8295cd91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937186107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3937186107
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3619979202
Short name T887
Test name
Test status
Simulation time 70908149414 ps
CPU time 141.64 seconds
Started May 12 01:27:42 PM PDT 24
Finished May 12 01:30:04 PM PDT 24
Peak memory 200376 kb
Host smart-bcddc2f9-6bd2-461b-9b33-14806798afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619979202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3619979202
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3352631716
Short name T1112
Test name
Test status
Simulation time 60628033616 ps
CPU time 113.86 seconds
Started May 12 01:27:48 PM PDT 24
Finished May 12 01:29:42 PM PDT 24
Peak memory 200304 kb
Host smart-cdfa611d-e79f-4c61-8b37-b2f252031388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352631716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3352631716
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.3250691546
Short name T659
Test name
Test status
Simulation time 23480686241 ps
CPU time 8.69 seconds
Started May 12 01:27:46 PM PDT 24
Finished May 12 01:27:55 PM PDT 24
Peak memory 200316 kb
Host smart-8017a805-d352-40a8-b86e-00b27dd4d399
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250691546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3250691546
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.588855497
Short name T1073
Test name
Test status
Simulation time 129370994574 ps
CPU time 1049.55 seconds
Started May 12 01:27:51 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 200428 kb
Host smart-d90dcef9-9b32-488b-b700-63308f4d6d76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588855497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.588855497
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.684769498
Short name T770
Test name
Test status
Simulation time 3993224471 ps
CPU time 7.14 seconds
Started May 12 01:27:55 PM PDT 24
Finished May 12 01:28:02 PM PDT 24
Peak memory 197084 kb
Host smart-f85fbeb3-03bb-4035-a365-ce961fc12382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684769498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.684769498
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3084764978
Short name T579
Test name
Test status
Simulation time 207028705675 ps
CPU time 100.64 seconds
Started May 12 01:27:47 PM PDT 24
Finished May 12 01:29:27 PM PDT 24
Peak memory 200096 kb
Host smart-be3e153b-50f3-490a-bb55-5ee54eb97e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084764978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3084764978
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1903836343
Short name T583
Test name
Test status
Simulation time 17626720555 ps
CPU time 66.36 seconds
Started May 12 01:27:52 PM PDT 24
Finished May 12 01:28:59 PM PDT 24
Peak memory 200380 kb
Host smart-00526712-39b2-4d7e-980d-fda1b65b4433
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903836343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1903836343
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3360163598
Short name T3
Test name
Test status
Simulation time 2137550899 ps
CPU time 2.68 seconds
Started May 12 01:27:45 PM PDT 24
Finished May 12 01:27:48 PM PDT 24
Peak memory 198432 kb
Host smart-af8d23f7-cc7a-4eb6-a031-5d664592ce7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360163598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3360163598
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1937668716
Short name T1111
Test name
Test status
Simulation time 20121910080 ps
CPU time 10.12 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:28:07 PM PDT 24
Peak memory 199924 kb
Host smart-0f5273a7-0c42-4f76-b24c-3ccb6d817dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937668716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1937668716
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3806640014
Short name T311
Test name
Test status
Simulation time 3805672909 ps
CPU time 6.44 seconds
Started May 12 01:27:46 PM PDT 24
Finished May 12 01:27:53 PM PDT 24
Peak memory 196372 kb
Host smart-ef386dbe-e750-4754-afc0-a331a83df0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806640014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3806640014
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2333306595
Short name T343
Test name
Test status
Simulation time 991961936 ps
CPU time 1.18 seconds
Started May 12 01:27:43 PM PDT 24
Finished May 12 01:27:44 PM PDT 24
Peak memory 199160 kb
Host smart-2f645f00-c69b-4df4-9b53-2a4f977809ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333306595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2333306595
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3545684053
Short name T167
Test name
Test status
Simulation time 138311655722 ps
CPU time 218.53 seconds
Started May 12 01:27:50 PM PDT 24
Finished May 12 01:31:29 PM PDT 24
Peak memory 200408 kb
Host smart-eda04af9-6268-4cac-98ce-d589db707514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545684053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3545684053
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.868481173
Short name T687
Test name
Test status
Simulation time 161550738329 ps
CPU time 558.99 seconds
Started May 12 01:27:50 PM PDT 24
Finished May 12 01:37:10 PM PDT 24
Peak memory 217028 kb
Host smart-e89a9dbb-fd90-4876-ad24-efb00ffdbc9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868481173 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.868481173
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2688284143
Short name T1014
Test name
Test status
Simulation time 1881417922 ps
CPU time 3.86 seconds
Started May 12 01:27:55 PM PDT 24
Finished May 12 01:27:59 PM PDT 24
Peak memory 200016 kb
Host smart-d0da9d67-8ac0-4093-af07-266a8702169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688284143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2688284143
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1272275844
Short name T566
Test name
Test status
Simulation time 463747955562 ps
CPU time 66.39 seconds
Started May 12 01:27:44 PM PDT 24
Finished May 12 01:28:50 PM PDT 24
Peak memory 200332 kb
Host smart-002bb66c-8e83-4a57-8053-31e2612f6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272275844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1272275844
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.669200704
Short name T525
Test name
Test status
Simulation time 23285113 ps
CPU time 0.57 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:24:30 PM PDT 24
Peak memory 195672 kb
Host smart-da9fcb99-0326-44ec-ac96-e16c261ce1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669200704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.669200704
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1027722985
Short name T1087
Test name
Test status
Simulation time 185720911830 ps
CPU time 99.57 seconds
Started May 12 01:24:35 PM PDT 24
Finished May 12 01:26:16 PM PDT 24
Peak memory 200368 kb
Host smart-3be9ff48-e5a1-45a9-bc86-d2b37f150f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027722985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1027722985
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4072832512
Short name T758
Test name
Test status
Simulation time 11639535621 ps
CPU time 21.21 seconds
Started May 12 01:24:30 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 199812 kb
Host smart-df5dc37c-60c6-4614-a31e-f7f677006f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072832512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4072832512
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2208785229
Short name T153
Test name
Test status
Simulation time 152009219590 ps
CPU time 122.55 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:26:40 PM PDT 24
Peak memory 200384 kb
Host smart-3cd689e7-688d-46e7-94b3-772b375b9ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208785229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2208785229
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.57070008
Short name T1077
Test name
Test status
Simulation time 12536927508 ps
CPU time 21.68 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:24:51 PM PDT 24
Peak memory 200064 kb
Host smart-bcdf4d19-23e7-454b-ad47-eca3b5c649db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57070008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.57070008
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.939483048
Short name T856
Test name
Test status
Simulation time 118389321676 ps
CPU time 257.94 seconds
Started May 12 01:24:32 PM PDT 24
Finished May 12 01:28:52 PM PDT 24
Peak memory 200408 kb
Host smart-eff3af71-1275-4e9d-8a73-cae0d91ef080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939483048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.939483048
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.232960881
Short name T675
Test name
Test status
Simulation time 587694758 ps
CPU time 1.7 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 197556 kb
Host smart-b2af22de-14c9-421b-9f38-460c5626ca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232960881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.232960881
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.386935667
Short name T372
Test name
Test status
Simulation time 424424575596 ps
CPU time 96.56 seconds
Started May 12 01:24:30 PM PDT 24
Finished May 12 01:26:08 PM PDT 24
Peak memory 209872 kb
Host smart-debee13f-9300-433b-9e04-8ef7225ba5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386935667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.386935667
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3638078571
Short name T640
Test name
Test status
Simulation time 21784250365 ps
CPU time 49.44 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:25:17 PM PDT 24
Peak memory 200372 kb
Host smart-e317c080-30bf-419b-b225-1b3d87c099c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638078571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3638078571
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.264046452
Short name T355
Test name
Test status
Simulation time 6991890577 ps
CPU time 64.19 seconds
Started May 12 01:24:28 PM PDT 24
Finished May 12 01:25:33 PM PDT 24
Peak memory 199336 kb
Host smart-20fc1f39-d758-4b78-abfe-d78292fee1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264046452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.264046452
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3894873195
Short name T765
Test name
Test status
Simulation time 14581961479 ps
CPU time 22.97 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:24:53 PM PDT 24
Peak memory 200292 kb
Host smart-02bea671-69cb-4f1c-b5f2-1e01598da2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894873195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3894873195
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3399872905
Short name T703
Test name
Test status
Simulation time 2179746605 ps
CPU time 4 seconds
Started May 12 01:24:28 PM PDT 24
Finished May 12 01:24:33 PM PDT 24
Peak memory 195788 kb
Host smart-bb1c8057-4b60-47b7-bb89-8975e60cffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399872905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3399872905
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1600355281
Short name T386
Test name
Test status
Simulation time 664614485 ps
CPU time 1.91 seconds
Started May 12 01:24:27 PM PDT 24
Finished May 12 01:24:29 PM PDT 24
Peak memory 199116 kb
Host smart-f71ec802-d7c6-490d-b4af-a5b3eb443bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600355281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1600355281
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.529447316
Short name T781
Test name
Test status
Simulation time 77633940447 ps
CPU time 44.61 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:25:15 PM PDT 24
Peak memory 200420 kb
Host smart-21158716-b7b9-47e6-9ac4-52676da06838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529447316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.529447316
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4009539483
Short name T592
Test name
Test status
Simulation time 55110126315 ps
CPU time 475.17 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 225268 kb
Host smart-0b917e66-ef28-4769-99a9-32959b1289af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009539483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4009539483
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2797575923
Short name T19
Test name
Test status
Simulation time 667966952 ps
CPU time 3.23 seconds
Started May 12 01:24:30 PM PDT 24
Finished May 12 01:24:35 PM PDT 24
Peak memory 198656 kb
Host smart-7c7eefee-ad34-484a-8d75-ea87f5067e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797575923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2797575923
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1896002682
Short name T820
Test name
Test status
Simulation time 80491285908 ps
CPU time 138.39 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:26:56 PM PDT 24
Peak memory 200288 kb
Host smart-ad843c2d-4c67-4804-b871-236564999562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896002682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1896002682
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3274082043
Short name T657
Test name
Test status
Simulation time 32526760375 ps
CPU time 29.78 seconds
Started May 12 01:27:52 PM PDT 24
Finished May 12 01:28:22 PM PDT 24
Peak memory 200280 kb
Host smart-be194a02-9219-439d-92f1-a2277a0549b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274082043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3274082043
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.285849930
Short name T810
Test name
Test status
Simulation time 68553551951 ps
CPU time 951.93 seconds
Started May 12 01:27:55 PM PDT 24
Finished May 12 01:43:47 PM PDT 24
Peak memory 225240 kb
Host smart-9a5d267b-a188-4f5e-8fad-172132c65612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285849930 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.285849930
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2462468192
Short name T965
Test name
Test status
Simulation time 81491893374 ps
CPU time 119.31 seconds
Started May 12 01:27:49 PM PDT 24
Finished May 12 01:29:48 PM PDT 24
Peak memory 200344 kb
Host smart-f11b0d64-3168-4149-a1c7-66ef2ffbd223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462468192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2462468192
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1258707502
Short name T289
Test name
Test status
Simulation time 28810474611 ps
CPU time 641.91 seconds
Started May 12 01:27:52 PM PDT 24
Finished May 12 01:38:34 PM PDT 24
Peak memory 214668 kb
Host smart-fb03812a-1491-4113-810d-aaa509a84261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258707502 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1258707502
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1933499518
Short name T767
Test name
Test status
Simulation time 62270591611 ps
CPU time 25.91 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:28:22 PM PDT 24
Peak memory 200364 kb
Host smart-5cc65979-d864-4a34-a1e7-b53a0c870db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933499518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1933499518
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1025684024
Short name T186
Test name
Test status
Simulation time 290422650279 ps
CPU time 1303.55 seconds
Started May 12 01:27:50 PM PDT 24
Finished May 12 01:49:34 PM PDT 24
Peak memory 220072 kb
Host smart-7f3aa93d-e37f-423c-8524-99907d42b673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025684024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1025684024
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1944188837
Short name T70
Test name
Test status
Simulation time 75202663473 ps
CPU time 378.3 seconds
Started May 12 01:27:50 PM PDT 24
Finished May 12 01:34:09 PM PDT 24
Peak memory 212472 kb
Host smart-e289c5cf-8f83-4073-a83e-0d8be38e713b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944188837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1944188837
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2768337275
Short name T1003
Test name
Test status
Simulation time 32307502599 ps
CPU time 14.45 seconds
Started May 12 01:27:52 PM PDT 24
Finished May 12 01:28:06 PM PDT 24
Peak memory 200160 kb
Host smart-92700cc2-af14-4307-8d9f-d4e89009b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768337275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2768337275
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2550941774
Short name T1123
Test name
Test status
Simulation time 144509903506 ps
CPU time 132.14 seconds
Started May 12 01:27:53 PM PDT 24
Finished May 12 01:30:05 PM PDT 24
Peak memory 208652 kb
Host smart-3b3ed910-6263-45af-aae8-bdfa34c1c7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550941774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2550941774
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1100736059
Short name T863
Test name
Test status
Simulation time 25924102885 ps
CPU time 19.91 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:28:17 PM PDT 24
Peak memory 200348 kb
Host smart-2015739d-5ef2-4dff-831d-ff3d1aa663fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100736059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1100736059
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1359567542
Short name T180
Test name
Test status
Simulation time 271894306933 ps
CPU time 938.02 seconds
Started May 12 01:27:52 PM PDT 24
Finished May 12 01:43:31 PM PDT 24
Peak memory 231696 kb
Host smart-87cdc2ae-1978-494f-9ee8-026e8ab18050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359567542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1359567542
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1597448518
Short name T388
Test name
Test status
Simulation time 112749410720 ps
CPU time 125.62 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:30:03 PM PDT 24
Peak memory 200384 kb
Host smart-10a8d9fd-ec23-45cf-a8b1-68e757e8f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597448518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1597448518
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1286601171
Short name T63
Test name
Test status
Simulation time 260281255099 ps
CPU time 673.67 seconds
Started May 12 01:27:59 PM PDT 24
Finished May 12 01:39:13 PM PDT 24
Peak memory 217072 kb
Host smart-027dbadc-bea8-420f-9b15-c7be3fa00934
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286601171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1286601171
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.15312834
Short name T344
Test name
Test status
Simulation time 99501033838 ps
CPU time 23.63 seconds
Started May 12 01:27:53 PM PDT 24
Finished May 12 01:28:17 PM PDT 24
Peak memory 200392 kb
Host smart-171afa3c-8cdb-47cc-98b6-9190daa6ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15312834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.15312834
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1819662301
Short name T563
Test name
Test status
Simulation time 66729119502 ps
CPU time 745.96 seconds
Started May 12 01:27:54 PM PDT 24
Finished May 12 01:40:21 PM PDT 24
Peak memory 216904 kb
Host smart-a3692de0-1b44-42da-8c4d-123ec295f95a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819662301 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1819662301
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3483533199
Short name T971
Test name
Test status
Simulation time 30011480453 ps
CPU time 53.4 seconds
Started May 12 01:27:52 PM PDT 24
Finished May 12 01:28:46 PM PDT 24
Peak memory 200336 kb
Host smart-1c21acb5-7870-40e0-8e44-d5dfa9dae9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483533199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3483533199
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3670395394
Short name T682
Test name
Test status
Simulation time 262616977286 ps
CPU time 802.54 seconds
Started May 12 01:27:55 PM PDT 24
Finished May 12 01:41:18 PM PDT 24
Peak memory 216764 kb
Host smart-e41fc7fe-841f-45cf-8fa0-36deeaf575b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670395394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3670395394
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2968040623
Short name T683
Test name
Test status
Simulation time 84949678546 ps
CPU time 124.27 seconds
Started May 12 01:27:53 PM PDT 24
Finished May 12 01:29:58 PM PDT 24
Peak memory 200308 kb
Host smart-75ebfa82-dbf9-4eec-8ea6-5046623cffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968040623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2968040623
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3385020103
Short name T996
Test name
Test status
Simulation time 22187053061 ps
CPU time 180.25 seconds
Started May 12 01:27:54 PM PDT 24
Finished May 12 01:30:55 PM PDT 24
Peak memory 216036 kb
Host smart-d0ef2b24-4adf-4541-9685-95154e201f4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385020103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3385020103
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2893389900
Short name T412
Test name
Test status
Simulation time 37850581 ps
CPU time 0.55 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 195920 kb
Host smart-ae7f6f86-22da-45d2-854e-16d4e142105a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893389900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2893389900
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3811169977
Short name T975
Test name
Test status
Simulation time 41709808007 ps
CPU time 18.57 seconds
Started May 12 01:24:31 PM PDT 24
Finished May 12 01:24:51 PM PDT 24
Peak memory 200392 kb
Host smart-a108baa2-5c10-4476-80b9-7c0503dfbf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811169977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3811169977
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3633297631
Short name T154
Test name
Test status
Simulation time 113944000596 ps
CPU time 50.83 seconds
Started May 12 01:24:31 PM PDT 24
Finished May 12 01:25:23 PM PDT 24
Peak memory 200328 kb
Host smart-25571820-b442-4e56-915e-f00188a03b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633297631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3633297631
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3363386431
Short name T1096
Test name
Test status
Simulation time 85119411823 ps
CPU time 152.42 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:27:07 PM PDT 24
Peak memory 200356 kb
Host smart-855a85d7-de08-46f3-aeb2-85a0a3586592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363386431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3363386431
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4127850675
Short name T831
Test name
Test status
Simulation time 71761784922 ps
CPU time 145.66 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:27:00 PM PDT 24
Peak memory 200008 kb
Host smart-d03caee3-3fd0-4ce1-8c32-f40c976d0192
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127850675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4127850675
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1549151568
Short name T532
Test name
Test status
Simulation time 71586178838 ps
CPU time 230.35 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:28:25 PM PDT 24
Peak memory 200376 kb
Host smart-1a0983f7-0d08-4481-af77-b823a1605746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549151568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1549151568
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.4006572136
Short name T1042
Test name
Test status
Simulation time 9430876450 ps
CPU time 21.97 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:24:56 PM PDT 24
Peak memory 200032 kb
Host smart-c23f00c3-736b-4284-bb99-04fe6a9cacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006572136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4006572136
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.376314615
Short name T307
Test name
Test status
Simulation time 9456663397 ps
CPU time 13.86 seconds
Started May 12 01:24:35 PM PDT 24
Finished May 12 01:24:50 PM PDT 24
Peak memory 200360 kb
Host smart-c0ef01c2-c308-4948-87a0-510dcc8e9aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376314615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.376314615
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2221667987
Short name T1034
Test name
Test status
Simulation time 8805800016 ps
CPU time 401.56 seconds
Started May 12 01:24:30 PM PDT 24
Finished May 12 01:31:13 PM PDT 24
Peak memory 200428 kb
Host smart-47dbeed3-c1e0-4eb7-a78d-f03d5a9d4d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221667987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2221667987
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2152217003
Short name T736
Test name
Test status
Simulation time 3570976884 ps
CPU time 13.54 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:24:47 PM PDT 24
Peak memory 198804 kb
Host smart-be2dede3-12de-4f77-b118-72e4fae3b0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152217003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2152217003
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4062066243
Short name T27
Test name
Test status
Simulation time 100712633199 ps
CPU time 35.17 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:25:10 PM PDT 24
Peak memory 200324 kb
Host smart-c60c4cca-9d05-4526-ad39-acce7e6a5d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062066243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4062066243
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1186280793
Short name T957
Test name
Test status
Simulation time 42761101843 ps
CPU time 16.49 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:24:51 PM PDT 24
Peak memory 196124 kb
Host smart-74614d9b-bc04-4411-bcf8-7ec4ca96205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186280793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1186280793
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3355153935
Short name T837
Test name
Test status
Simulation time 6332119292 ps
CPU time 31.49 seconds
Started May 12 01:24:35 PM PDT 24
Finished May 12 01:25:07 PM PDT 24
Peak memory 200188 kb
Host smart-07633a18-1f4c-4cb7-a2d2-966d3a0fcaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355153935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3355153935
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2054434196
Short name T337
Test name
Test status
Simulation time 759656105178 ps
CPU time 262.09 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:28:59 PM PDT 24
Peak memory 200472 kb
Host smart-09ba288f-3be0-4d0a-8fff-69493e11041c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054434196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2054434196
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3809026054
Short name T972
Test name
Test status
Simulation time 124365179140 ps
CPU time 425.33 seconds
Started May 12 01:24:29 PM PDT 24
Finished May 12 01:31:36 PM PDT 24
Peak memory 217004 kb
Host smart-2942945f-7e96-47a8-9e52-962be0ccc679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809026054 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3809026054
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.834890683
Short name T678
Test name
Test status
Simulation time 2588348929 ps
CPU time 2.34 seconds
Started May 12 01:24:35 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 198648 kb
Host smart-d492c036-ff8a-4787-82f9-7bdf9b3e53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834890683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.834890683
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3558973
Short name T713
Test name
Test status
Simulation time 39676387347 ps
CPU time 66.62 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:25:44 PM PDT 24
Peak memory 200552 kb
Host smart-fc2b1f62-8818-4b4e-8e81-48cdf1b59468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3558973
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3094188714
Short name T891
Test name
Test status
Simulation time 183589425744 ps
CPU time 59.79 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200396 kb
Host smart-46324cf0-9416-42cc-93c2-c6cd5b3b0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094188714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3094188714
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2726030032
Short name T116
Test name
Test status
Simulation time 62185088818 ps
CPU time 326.71 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:33:24 PM PDT 24
Peak memory 217000 kb
Host smart-5ffc96e0-7691-4cd6-93c2-175443b65cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726030032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2726030032
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.620814842
Short name T61
Test name
Test status
Simulation time 74475728394 ps
CPU time 821.98 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:41:40 PM PDT 24
Peak memory 225252 kb
Host smart-6704c34f-c6b4-46ed-88b6-c7e7d6e66e99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620814842 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.620814842
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.60212361
Short name T483
Test name
Test status
Simulation time 168042793893 ps
CPU time 78.73 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:29:16 PM PDT 24
Peak memory 200328 kb
Host smart-b5971231-f5fe-487e-8e3d-93582d9895f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60212361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.60212361
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2781777547
Short name T1024
Test name
Test status
Simulation time 67319266310 ps
CPU time 91.29 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:29:29 PM PDT 24
Peak memory 200324 kb
Host smart-73b7759c-9fc7-4f1e-b95f-a7bb243801e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781777547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2781777547
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1549849186
Short name T67
Test name
Test status
Simulation time 111473240016 ps
CPU time 327.41 seconds
Started May 12 01:27:57 PM PDT 24
Finished May 12 01:33:25 PM PDT 24
Peak memory 216876 kb
Host smart-8b0a48a6-79ec-4fa0-8732-c919e643f7be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549849186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1549849186
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3380390846
Short name T546
Test name
Test status
Simulation time 19863967214 ps
CPU time 20.23 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:28:24 PM PDT 24
Peak memory 200420 kb
Host smart-987d37f8-ea75-4d6a-9a77-0fee5601376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380390846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3380390846
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1391636415
Short name T572
Test name
Test status
Simulation time 143169386261 ps
CPU time 258.81 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:32:16 PM PDT 24
Peak memory 200392 kb
Host smart-33fa875b-941c-4e82-8bfb-eca628d5d46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391636415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1391636415
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2220362729
Short name T536
Test name
Test status
Simulation time 64621257741 ps
CPU time 205.67 seconds
Started May 12 01:27:56 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 216904 kb
Host smart-be34ca30-050c-49cd-b847-8b86bc51fc7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220362729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2220362729
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2444739016
Short name T235
Test name
Test status
Simulation time 153991310196 ps
CPU time 172.18 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:30:56 PM PDT 24
Peak memory 200420 kb
Host smart-63c2434c-2acc-4145-a609-0050ef12244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444739016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2444739016
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3820640514
Short name T115
Test name
Test status
Simulation time 289807806491 ps
CPU time 880.12 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:42:44 PM PDT 24
Peak memory 231356 kb
Host smart-489ea7cf-2675-4911-a0a9-f5aac4254038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820640514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3820640514
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3072750460
Short name T1028
Test name
Test status
Simulation time 11098095463 ps
CPU time 18.3 seconds
Started May 12 01:27:55 PM PDT 24
Finished May 12 01:28:14 PM PDT 24
Peak memory 200316 kb
Host smart-99686761-5f52-483a-bba3-499614fb7b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072750460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3072750460
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2789218359
Short name T1173
Test name
Test status
Simulation time 476880695147 ps
CPU time 1235.26 seconds
Started May 12 01:27:59 PM PDT 24
Finished May 12 01:48:35 PM PDT 24
Peak memory 225012 kb
Host smart-50d3326e-f62f-44f2-a9df-c8e81fb6f2e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789218359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2789218359
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2819505980
Short name T207
Test name
Test status
Simulation time 26911083212 ps
CPU time 42.09 seconds
Started May 12 01:28:00 PM PDT 24
Finished May 12 01:28:42 PM PDT 24
Peak memory 200260 kb
Host smart-613e3a54-8249-4e00-aea4-58473de15db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819505980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2819505980
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.864525798
Short name T1076
Test name
Test status
Simulation time 530855229869 ps
CPU time 349.66 seconds
Started May 12 01:27:59 PM PDT 24
Finished May 12 01:33:49 PM PDT 24
Peak memory 216912 kb
Host smart-7d0aa976-d839-4ddd-b935-a058ba5d5ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864525798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.864525798
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.591013157
Short name T722
Test name
Test status
Simulation time 11791727 ps
CPU time 0.55 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:24:35 PM PDT 24
Peak memory 195156 kb
Host smart-48052781-f715-4fe7-aa3b-c07e19e127dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591013157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.591013157
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4244098669
Short name T1171
Test name
Test status
Simulation time 116290037008 ps
CPU time 75.62 seconds
Started May 12 01:24:31 PM PDT 24
Finished May 12 01:25:48 PM PDT 24
Peak memory 200396 kb
Host smart-f902fd13-f71b-47e9-a5c3-fd81f5535603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244098669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4244098669
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2798148734
Short name T188
Test name
Test status
Simulation time 35991944579 ps
CPU time 29.05 seconds
Started May 12 01:24:31 PM PDT 24
Finished May 12 01:25:02 PM PDT 24
Peak memory 200296 kb
Host smart-fab8dd32-0016-45ba-9f75-286d4b45295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798148734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2798148734
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2996454177
Short name T865
Test name
Test status
Simulation time 104914070081 ps
CPU time 69.19 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:25:51 PM PDT 24
Peak memory 200248 kb
Host smart-92f0d807-7057-4850-b4af-07a0293ce641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996454177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2996454177
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1575154965
Short name T908
Test name
Test status
Simulation time 9668996191 ps
CPU time 3.13 seconds
Started May 12 01:24:32 PM PDT 24
Finished May 12 01:24:36 PM PDT 24
Peak memory 197272 kb
Host smart-defc7ab4-bbbd-4a0e-b484-f4df1a7b99b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575154965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1575154965
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.4206509669
Short name T614
Test name
Test status
Simulation time 150814444956 ps
CPU time 1362.27 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:47:17 PM PDT 24
Peak memory 200288 kb
Host smart-b1a77872-77e4-45f8-aa57-e0efa397652a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206509669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.4206509669
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.856006847
Short name T1025
Test name
Test status
Simulation time 2737346471 ps
CPU time 5.35 seconds
Started May 12 01:24:31 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 196652 kb
Host smart-8b487314-3e6d-4470-8705-21fa11c012a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856006847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.856006847
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4254308196
Short name T936
Test name
Test status
Simulation time 5108233627 ps
CPU time 9.12 seconds
Started May 12 01:24:35 PM PDT 24
Finished May 12 01:24:45 PM PDT 24
Peak memory 200484 kb
Host smart-c47242e7-cde4-4342-af15-49ee0175ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254308196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4254308196
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.112598784
Short name T1085
Test name
Test status
Simulation time 9936565465 ps
CPU time 292.23 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:29:27 PM PDT 24
Peak memory 200404 kb
Host smart-5b979f06-5b29-46f1-bc18-3a70a755b799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112598784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.112598784
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3596771895
Short name T864
Test name
Test status
Simulation time 6306466645 ps
CPU time 28.28 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:25:10 PM PDT 24
Peak memory 199536 kb
Host smart-b3467abd-d704-427b-a08a-13561f860692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596771895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3596771895
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3742250488
Short name T124
Test name
Test status
Simulation time 73224550310 ps
CPU time 15.62 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:24:51 PM PDT 24
Peak memory 200256 kb
Host smart-587f9a12-2cf7-4423-9afc-28ea2c41d8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742250488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3742250488
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1111629478
Short name T780
Test name
Test status
Simulation time 5053515614 ps
CPU time 1.27 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:24:42 PM PDT 24
Peak memory 196284 kb
Host smart-76995ff4-1fc4-47dc-8cfa-72e284f60425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111629478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1111629478
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2652368733
Short name T1187
Test name
Test status
Simulation time 870281900 ps
CPU time 1.68 seconds
Started May 12 01:24:34 PM PDT 24
Finished May 12 01:24:37 PM PDT 24
Peak memory 198540 kb
Host smart-def80970-e86c-4d56-8b88-45e3426b3f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652368733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2652368733
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.389691400
Short name T847
Test name
Test status
Simulation time 74820610516 ps
CPU time 134.23 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:26:55 PM PDT 24
Peak memory 200260 kb
Host smart-42caee63-1cfd-4823-8fee-a30e36e440f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389691400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.389691400
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1329270294
Short name T876
Test name
Test status
Simulation time 111990880691 ps
CPU time 327.94 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:30:09 PM PDT 24
Peak memory 210424 kb
Host smart-181ecbf0-705c-42cf-a227-cfb998bd0f29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329270294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1329270294
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1085928018
Short name T345
Test name
Test status
Simulation time 896790729 ps
CPU time 3.62 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 200456 kb
Host smart-84903778-a2af-4ffa-ba15-5190b313d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085928018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1085928018
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2486715260
Short name T861
Test name
Test status
Simulation time 30416344363 ps
CPU time 51.14 seconds
Started May 12 01:24:33 PM PDT 24
Finished May 12 01:25:26 PM PDT 24
Peak memory 200420 kb
Host smart-bcc0cf99-af65-43c1-90ca-8514f8506204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486715260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2486715260
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3398275314
Short name T1040
Test name
Test status
Simulation time 266349348921 ps
CPU time 100.14 seconds
Started May 12 01:28:01 PM PDT 24
Finished May 12 01:29:41 PM PDT 24
Peak memory 200300 kb
Host smart-8818136c-9b02-429f-95ec-946595c62e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398275314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3398275314
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1584774757
Short name T685
Test name
Test status
Simulation time 44202245488 ps
CPU time 531.61 seconds
Started May 12 01:27:59 PM PDT 24
Finished May 12 01:36:51 PM PDT 24
Peak memory 216748 kb
Host smart-3a9415d3-13f5-4cee-9f06-f1c825461620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584774757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1584774757
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.833398327
Short name T613
Test name
Test status
Simulation time 31053997056 ps
CPU time 54.3 seconds
Started May 12 01:28:00 PM PDT 24
Finished May 12 01:28:54 PM PDT 24
Peak memory 200408 kb
Host smart-ac33aa15-4501-42ca-895a-d8b7b92bc0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833398327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.833398327
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3617385353
Short name T988
Test name
Test status
Simulation time 44255293145 ps
CPU time 215.96 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:31:39 PM PDT 24
Peak memory 216720 kb
Host smart-ee6cc5cc-fb67-4a1f-aae8-75167f41b5c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617385353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3617385353
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1932927290
Short name T9
Test name
Test status
Simulation time 83708785647 ps
CPU time 11.58 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:28:15 PM PDT 24
Peak memory 200016 kb
Host smart-8bb1adae-13f3-4739-b89a-3b0d1444f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932927290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1932927290
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3229358904
Short name T1049
Test name
Test status
Simulation time 278980123794 ps
CPU time 686.19 seconds
Started May 12 01:28:04 PM PDT 24
Finished May 12 01:39:31 PM PDT 24
Peak memory 216624 kb
Host smart-f87fc68a-6358-441b-860a-a15e75409dcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229358904 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3229358904
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4206828493
Short name T1121
Test name
Test status
Simulation time 33779807330 ps
CPU time 55.79 seconds
Started May 12 01:28:04 PM PDT 24
Finished May 12 01:29:00 PM PDT 24
Peak memory 200288 kb
Host smart-0145e7d5-216b-45b0-aa94-1fb7b269ea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206828493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4206828493
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3892073084
Short name T477
Test name
Test status
Simulation time 34222324992 ps
CPU time 313.02 seconds
Started May 12 01:28:04 PM PDT 24
Finished May 12 01:33:18 PM PDT 24
Peak memory 216832 kb
Host smart-7fe2b9f7-0602-495e-8b90-a86741d2ce13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892073084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3892073084
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2582337569
Short name T452
Test name
Test status
Simulation time 12217626996 ps
CPU time 7.6 seconds
Started May 12 01:28:04 PM PDT 24
Finished May 12 01:28:12 PM PDT 24
Peak memory 199648 kb
Host smart-c1afec07-c7ce-4d3b-a428-d580e10ec176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582337569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2582337569
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2857771639
Short name T1108
Test name
Test status
Simulation time 97828304092 ps
CPU time 386.76 seconds
Started May 12 01:28:08 PM PDT 24
Finished May 12 01:34:36 PM PDT 24
Peak memory 216812 kb
Host smart-f6732589-9651-45fc-b159-36dc8e6eeaf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857771639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2857771639
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.456579454
Short name T764
Test name
Test status
Simulation time 148006359063 ps
CPU time 370.89 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:34:15 PM PDT 24
Peak memory 200380 kb
Host smart-f240ad92-53e7-42bb-a78a-0237e8d76514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456579454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.456579454
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.128551431
Short name T693
Test name
Test status
Simulation time 75124486880 ps
CPU time 1447.08 seconds
Started May 12 01:28:04 PM PDT 24
Finished May 12 01:52:11 PM PDT 24
Peak memory 228252 kb
Host smart-f681571b-4cc7-4198-b831-11a45d22102a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128551431 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.128551431
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.479728953
Short name T166
Test name
Test status
Simulation time 54782450849 ps
CPU time 23.15 seconds
Started May 12 01:28:04 PM PDT 24
Finished May 12 01:28:27 PM PDT 24
Peak memory 200424 kb
Host smart-751d62aa-c94a-4abe-8cbc-05fb474ab469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479728953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.479728953
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3582594986
Short name T68
Test name
Test status
Simulation time 303085604723 ps
CPU time 1109.35 seconds
Started May 12 01:28:05 PM PDT 24
Finished May 12 01:46:34 PM PDT 24
Peak memory 225276 kb
Host smart-ff077497-5f99-405e-bc4a-c3e24a8fe1b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582594986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3582594986
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2329409687
Short name T392
Test name
Test status
Simulation time 113045820213 ps
CPU time 276.1 seconds
Started May 12 01:28:03 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 200372 kb
Host smart-31d57698-f4d2-48a4-82af-54c469cea64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329409687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2329409687
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3860137576
Short name T113
Test name
Test status
Simulation time 160142382928 ps
CPU time 392.67 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:34:43 PM PDT 24
Peak memory 217060 kb
Host smart-18ec9a28-7218-4510-bd20-3c509219b762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860137576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3860137576
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1054108769
Short name T588
Test name
Test status
Simulation time 120301058285 ps
CPU time 96.78 seconds
Started May 12 01:28:08 PM PDT 24
Finished May 12 01:29:46 PM PDT 24
Peak memory 200400 kb
Host smart-4976f9e7-5c77-41d1-addb-2e793c6afe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054108769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1054108769
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3821887050
Short name T1051
Test name
Test status
Simulation time 48175639292 ps
CPU time 447.72 seconds
Started May 12 01:28:08 PM PDT 24
Finished May 12 01:35:36 PM PDT 24
Peak memory 215884 kb
Host smart-4cfab0e4-98f9-4d27-a1c2-defe1d232fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821887050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3821887050
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2380749520
Short name T125
Test name
Test status
Simulation time 9752303963 ps
CPU time 17.53 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:28:28 PM PDT 24
Peak memory 198148 kb
Host smart-58b24510-e926-4bf3-a859-310910166aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380749520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2380749520
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.942748378
Short name T1178
Test name
Test status
Simulation time 11934486 ps
CPU time 0.56 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:24:44 PM PDT 24
Peak memory 194696 kb
Host smart-26dd4e33-c51f-48f7-ac42-fc536edbc491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942748378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.942748378
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2740219912
Short name T879
Test name
Test status
Simulation time 40797969474 ps
CPU time 15.16 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 200128 kb
Host smart-f8cde269-de1a-423f-afa4-a3929c8371f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740219912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2740219912
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2597192334
Short name T1067
Test name
Test status
Simulation time 23259026255 ps
CPU time 40.39 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:25:18 PM PDT 24
Peak memory 200340 kb
Host smart-9081c436-b6a4-4ffd-a47c-7b24baf2e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597192334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2597192334
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1472270700
Short name T595
Test name
Test status
Simulation time 110870721325 ps
CPU time 126.66 seconds
Started May 12 01:24:37 PM PDT 24
Finished May 12 01:26:44 PM PDT 24
Peak memory 200448 kb
Host smart-6074a093-7c7b-4205-8e52-d4d3c826863d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472270700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1472270700
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.536040880
Short name T904
Test name
Test status
Simulation time 69614456563 ps
CPU time 518.48 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:33:21 PM PDT 24
Peak memory 200400 kb
Host smart-8ddf29e6-df84-4260-ae3d-ae45da0f24f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536040880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.536040880
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1027606597
Short name T624
Test name
Test status
Simulation time 1770495967 ps
CPU time 4.58 seconds
Started May 12 01:24:37 PM PDT 24
Finished May 12 01:24:42 PM PDT 24
Peak memory 198904 kb
Host smart-74c5f630-ac02-4553-8981-ccd81f243c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027606597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1027606597
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.4033137652
Short name T1041
Test name
Test status
Simulation time 64521396665 ps
CPU time 29.16 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:25:06 PM PDT 24
Peak memory 200540 kb
Host smart-3c0135fb-2f1b-48bc-bf07-e7d3daf6c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033137652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.4033137652
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3506937314
Short name T1119
Test name
Test status
Simulation time 2762872192 ps
CPU time 72.98 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:25:57 PM PDT 24
Peak memory 200288 kb
Host smart-0f779a79-28e5-4b05-abe9-296e2cf438c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506937314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3506937314
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3181634999
Short name T766
Test name
Test status
Simulation time 6298073935 ps
CPU time 14.96 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 199716 kb
Host smart-79b48483-4f19-4066-8e76-6ab5e4fb53a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181634999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3181634999
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2793562251
Short name T1116
Test name
Test status
Simulation time 154826741378 ps
CPU time 206.61 seconds
Started May 12 01:24:37 PM PDT 24
Finished May 12 01:28:04 PM PDT 24
Peak memory 200316 kb
Host smart-70c61d6f-02ab-4a68-82cc-6c7cb998cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793562251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2793562251
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3872531901
Short name T665
Test name
Test status
Simulation time 4342367765 ps
CPU time 2.02 seconds
Started May 12 01:24:39 PM PDT 24
Finished May 12 01:24:41 PM PDT 24
Peak memory 196644 kb
Host smart-45db229b-bbe8-43f6-83b8-4f8c25fcb6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872531901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3872531901
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.469532882
Short name T998
Test name
Test status
Simulation time 687849702 ps
CPU time 1.69 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:24:38 PM PDT 24
Peak memory 199148 kb
Host smart-a3e93ec0-a615-4436-afae-434545aca6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469532882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.469532882
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.766134276
Short name T385
Test name
Test status
Simulation time 92781318950 ps
CPU time 165.01 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:27:29 PM PDT 24
Peak memory 200340 kb
Host smart-d1f3cbcc-a21b-429b-85fa-8f4503aea7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766134276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.766134276
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1288678555
Short name T1029
Test name
Test status
Simulation time 777752574 ps
CPU time 1.98 seconds
Started May 12 01:24:37 PM PDT 24
Finished May 12 01:24:40 PM PDT 24
Peak memory 198748 kb
Host smart-4ecf6c3c-2b68-462d-9013-ed433e4bd559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288678555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1288678555
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1563521928
Short name T1043
Test name
Test status
Simulation time 92540792529 ps
CPU time 174.09 seconds
Started May 12 01:24:36 PM PDT 24
Finished May 12 01:27:32 PM PDT 24
Peak memory 200424 kb
Host smart-0f740860-92bf-4c3a-8881-17823472a74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563521928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1563521928
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2668899279
Short name T270
Test name
Test status
Simulation time 54029213752 ps
CPU time 81.75 seconds
Started May 12 01:28:08 PM PDT 24
Finished May 12 01:29:30 PM PDT 24
Peak memory 200232 kb
Host smart-c9a45d5c-e183-4b8d-b009-50186b1bffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668899279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2668899279
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.352073544
Short name T668
Test name
Test status
Simulation time 20008043712 ps
CPU time 226.53 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:31:57 PM PDT 24
Peak memory 216948 kb
Host smart-dcdf4b23-6c8d-455f-b915-ec9558af649d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352073544 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.352073544
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3562047509
Short name T323
Test name
Test status
Simulation time 231769773120 ps
CPU time 766.28 seconds
Started May 12 01:28:08 PM PDT 24
Finished May 12 01:40:55 PM PDT 24
Peak memory 216852 kb
Host smart-1cbd8b72-2843-4498-92b5-136410c73186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562047509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3562047509
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.689953912
Short name T1089
Test name
Test status
Simulation time 101292710781 ps
CPU time 128.56 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:30:19 PM PDT 24
Peak memory 200420 kb
Host smart-037419be-a5f4-4bd8-b54f-16e8525f594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689953912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.689953912
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.380033377
Short name T112
Test name
Test status
Simulation time 97070509670 ps
CPU time 290.44 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:33:01 PM PDT 24
Peak memory 209268 kb
Host smart-a75f4cb3-aa69-44ba-8c88-023ec8979fbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380033377 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.380033377
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3917342033
Short name T239
Test name
Test status
Simulation time 16382207105 ps
CPU time 24.09 seconds
Started May 12 01:28:13 PM PDT 24
Finished May 12 01:28:37 PM PDT 24
Peak memory 200320 kb
Host smart-5e75f93c-b545-458a-acab-8f15104bd00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917342033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3917342033
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3962509436
Short name T1020
Test name
Test status
Simulation time 23999962035 ps
CPU time 587.52 seconds
Started May 12 01:28:12 PM PDT 24
Finished May 12 01:38:00 PM PDT 24
Peak memory 216856 kb
Host smart-4a45ee0e-9924-4e83-b4ac-2744763344d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962509436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3962509436
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3075449299
Short name T328
Test name
Test status
Simulation time 64085356244 ps
CPU time 24.69 seconds
Started May 12 01:28:13 PM PDT 24
Finished May 12 01:28:38 PM PDT 24
Peak memory 200360 kb
Host smart-b8386ccf-d5f7-4c2a-9898-607273b646a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075449299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3075449299
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2788434135
Short name T176
Test name
Test status
Simulation time 70300720927 ps
CPU time 21.54 seconds
Started May 12 01:28:12 PM PDT 24
Finished May 12 01:28:34 PM PDT 24
Peak memory 200412 kb
Host smart-e2ee8202-df37-4e8a-91cf-7afb09e55b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788434135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2788434135
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3700303188
Short name T298
Test name
Test status
Simulation time 171711694137 ps
CPU time 625.53 seconds
Started May 12 01:28:10 PM PDT 24
Finished May 12 01:38:37 PM PDT 24
Peak memory 225196 kb
Host smart-4d15421a-0652-4517-ad7c-24a1836af8bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700303188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3700303188
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3169148923
Short name T1149
Test name
Test status
Simulation time 24306322507 ps
CPU time 64.58 seconds
Started May 12 01:28:12 PM PDT 24
Finished May 12 01:29:17 PM PDT 24
Peak memory 200340 kb
Host smart-58916656-e93b-4e3f-909f-3dec016443b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169148923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3169148923
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3335057399
Short name T114
Test name
Test status
Simulation time 90666509007 ps
CPU time 194.67 seconds
Started May 12 01:28:11 PM PDT 24
Finished May 12 01:31:26 PM PDT 24
Peak memory 208732 kb
Host smart-19a3f597-d863-4077-8e3d-3367618e6b4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335057399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3335057399
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1281713577
Short name T334
Test name
Test status
Simulation time 204308274638 ps
CPU time 22.54 seconds
Started May 12 01:28:11 PM PDT 24
Finished May 12 01:28:34 PM PDT 24
Peak memory 200124 kb
Host smart-6a5a266e-4281-45cc-a1b8-e5219fa211f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281713577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1281713577
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1288302078
Short name T601
Test name
Test status
Simulation time 5240994894 ps
CPU time 65.81 seconds
Started May 12 01:28:16 PM PDT 24
Finished May 12 01:29:22 PM PDT 24
Peak memory 215956 kb
Host smart-a72d9f73-6d07-41f5-8704-560f70260b05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288302078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1288302078
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3227859942
Short name T65
Test name
Test status
Simulation time 71162681461 ps
CPU time 232.59 seconds
Started May 12 01:28:14 PM PDT 24
Finished May 12 01:32:07 PM PDT 24
Peak memory 215948 kb
Host smart-81f246ef-0f38-4def-a29d-d7f81985253c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227859942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3227859942
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2782078850
Short name T725
Test name
Test status
Simulation time 27653279 ps
CPU time 0.54 seconds
Started May 12 01:24:45 PM PDT 24
Finished May 12 01:24:47 PM PDT 24
Peak memory 194736 kb
Host smart-a1783d90-11a4-46e2-b2d3-65ee19d8166f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782078850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2782078850
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1584919022
Short name T699
Test name
Test status
Simulation time 93843596608 ps
CPU time 77.39 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:26:00 PM PDT 24
Peak memory 200340 kb
Host smart-0d0b5756-b153-479c-83a6-487d50e498b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584919022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1584919022
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.987381610
Short name T292
Test name
Test status
Simulation time 70733342555 ps
CPU time 16.17 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:24:59 PM PDT 24
Peak memory 200248 kb
Host smart-a94280ca-a3e9-455a-931d-b7d6fe0dd5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987381610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.987381610
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3686936869
Short name T658
Test name
Test status
Simulation time 10281828595 ps
CPU time 25.96 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:25:08 PM PDT 24
Peak memory 200328 kb
Host smart-c9f3a530-0aec-4709-a338-67e02a07d1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686936869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3686936869
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2572042908
Short name T870
Test name
Test status
Simulation time 229216766154 ps
CPU time 75.48 seconds
Started May 12 01:24:43 PM PDT 24
Finished May 12 01:26:00 PM PDT 24
Peak memory 197240 kb
Host smart-d25482f7-1fbc-4e50-aeaf-3ad8356e64b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572042908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2572042908
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2481563708
Short name T319
Test name
Test status
Simulation time 114453300647 ps
CPU time 968.35 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:40:51 PM PDT 24
Peak memory 200316 kb
Host smart-434fd84b-3d89-4901-865a-f8e24372bd7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481563708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2481563708
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2630539077
Short name T921
Test name
Test status
Simulation time 9019217139 ps
CPU time 10.82 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:56 PM PDT 24
Peak memory 200348 kb
Host smart-66264006-5c44-4242-917c-a9b8c519d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630539077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2630539077
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.300573925
Short name T980
Test name
Test status
Simulation time 28701136684 ps
CPU time 74.01 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:25:57 PM PDT 24
Peak memory 200568 kb
Host smart-22fe4a42-ad47-429b-9ac4-44442046c53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300573925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.300573925
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3497248220
Short name T950
Test name
Test status
Simulation time 18818898157 ps
CPU time 268.01 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:29:11 PM PDT 24
Peak memory 200368 kb
Host smart-2ef72b9a-7d6e-4aa3-a98e-ed05b7abcc1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497248220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3497248220
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2583542666
Short name T1053
Test name
Test status
Simulation time 2714413624 ps
CPU time 8.22 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:54 PM PDT 24
Peak memory 198548 kb
Host smart-7b4d3e7a-318c-4f89-a32f-42eb9c718dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583542666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2583542666
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1005811568
Short name T296
Test name
Test status
Simulation time 2995514335 ps
CPU time 5.84 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:24:52 PM PDT 24
Peak memory 196376 kb
Host smart-5ec02824-4928-4a8f-974a-1bd5c7d67334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005811568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1005811568
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.818478513
Short name T647
Test name
Test status
Simulation time 90578904 ps
CPU time 0.84 seconds
Started May 12 01:24:42 PM PDT 24
Finished May 12 01:24:45 PM PDT 24
Peak memory 197384 kb
Host smart-f30ef0ab-2881-4bad-ad65-e7a9c890d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818478513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.818478513
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1332840238
Short name T537
Test name
Test status
Simulation time 24923458112 ps
CPU time 377.26 seconds
Started May 12 01:24:44 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 217060 kb
Host smart-e2c12dd6-bfce-4731-b0ef-b672c0f03e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332840238 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1332840238
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4036881793
Short name T1005
Test name
Test status
Simulation time 1634695099 ps
CPU time 1.84 seconds
Started May 12 01:24:41 PM PDT 24
Finished May 12 01:24:43 PM PDT 24
Peak memory 198680 kb
Host smart-15fd1f02-1386-4817-b6c6-560a225816ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036881793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4036881793
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1815986683
Short name T1050
Test name
Test status
Simulation time 130503239263 ps
CPU time 201.88 seconds
Started May 12 01:24:40 PM PDT 24
Finished May 12 01:28:03 PM PDT 24
Peak memory 200352 kb
Host smart-18da364a-83e4-42c6-8f47-5efad2f4635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815986683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1815986683
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3611596900
Short name T953
Test name
Test status
Simulation time 9055052798 ps
CPU time 16.4 seconds
Started May 12 01:28:15 PM PDT 24
Finished May 12 01:28:32 PM PDT 24
Peak memory 200352 kb
Host smart-433240d2-91cd-4f57-bc24-a94dd0ce03da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611596900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3611596900
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1978036749
Short name T269
Test name
Test status
Simulation time 278091590449 ps
CPU time 820.06 seconds
Started May 12 01:28:16 PM PDT 24
Finished May 12 01:41:56 PM PDT 24
Peak memory 217052 kb
Host smart-a2bc8799-e429-4803-9c09-37cf5ae01980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978036749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1978036749
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2480911959
Short name T1160
Test name
Test status
Simulation time 12896914207 ps
CPU time 22.67 seconds
Started May 12 01:28:15 PM PDT 24
Finished May 12 01:28:38 PM PDT 24
Peak memory 200352 kb
Host smart-f1350499-6e04-48fd-9a1c-23d980031598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480911959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2480911959
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1540975173
Short name T979
Test name
Test status
Simulation time 117163185517 ps
CPU time 205.05 seconds
Started May 12 01:28:16 PM PDT 24
Finished May 12 01:31:41 PM PDT 24
Peak memory 200340 kb
Host smart-1f2a194e-8295-4095-a2b6-4ef94fb37a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540975173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1540975173
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3648762909
Short name T229
Test name
Test status
Simulation time 78560670713 ps
CPU time 156.77 seconds
Started May 12 01:28:15 PM PDT 24
Finished May 12 01:30:52 PM PDT 24
Peak memory 211700 kb
Host smart-787f118d-b66e-4753-9f57-7b5a80ca0985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648762909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3648762909
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2684374601
Short name T103
Test name
Test status
Simulation time 91066743347 ps
CPU time 12.75 seconds
Started May 12 01:28:17 PM PDT 24
Finished May 12 01:28:30 PM PDT 24
Peak memory 200428 kb
Host smart-f27fe0f0-42f7-4683-93b7-f123ba64ea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684374601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2684374601
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2841941223
Short name T64
Test name
Test status
Simulation time 368881904981 ps
CPU time 621.47 seconds
Started May 12 01:28:18 PM PDT 24
Finished May 12 01:38:40 PM PDT 24
Peak memory 229476 kb
Host smart-809f163c-1749-4796-8c5f-def4c0b7ca95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841941223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2841941223
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2356870134
Short name T526
Test name
Test status
Simulation time 24330308301 ps
CPU time 11.92 seconds
Started May 12 01:28:14 PM PDT 24
Finished May 12 01:28:27 PM PDT 24
Peak memory 200392 kb
Host smart-5a83e1e0-6dca-4970-b094-31ee0f099bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356870134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2356870134
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.704125010
Short name T179
Test name
Test status
Simulation time 290172521186 ps
CPU time 438.99 seconds
Started May 12 01:28:16 PM PDT 24
Finished May 12 01:35:35 PM PDT 24
Peak memory 217048 kb
Host smart-e1efcd35-f838-488f-9f69-96558dc09cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704125010 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.704125010
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.223183795
Short name T835
Test name
Test status
Simulation time 64711339225 ps
CPU time 58.86 seconds
Started May 12 01:28:20 PM PDT 24
Finished May 12 01:29:19 PM PDT 24
Peak memory 200324 kb
Host smart-448a2fba-7e9a-4a01-9362-99de1ebdf7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223183795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.223183795
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3874770113
Short name T952
Test name
Test status
Simulation time 38985588122 ps
CPU time 677.33 seconds
Started May 12 01:28:19 PM PDT 24
Finished May 12 01:39:37 PM PDT 24
Peak memory 216308 kb
Host smart-10980d34-9735-4eaa-9d68-8b06add5bf8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874770113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3874770113
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3490854662
Short name T1080
Test name
Test status
Simulation time 72081485396 ps
CPU time 33.38 seconds
Started May 12 01:28:24 PM PDT 24
Finished May 12 01:28:58 PM PDT 24
Peak memory 200324 kb
Host smart-d754e055-aeb7-41a6-92fa-5c65fd4f334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490854662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3490854662
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.485316509
Short name T830
Test name
Test status
Simulation time 132635151372 ps
CPU time 384.36 seconds
Started May 12 01:28:21 PM PDT 24
Finished May 12 01:34:45 PM PDT 24
Peak memory 217044 kb
Host smart-dde3a6da-e555-455d-8369-091b11d8c14a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485316509 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.485316509
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2258680857
Short name T263
Test name
Test status
Simulation time 122471019100 ps
CPU time 48.09 seconds
Started May 12 01:28:18 PM PDT 24
Finished May 12 01:29:07 PM PDT 24
Peak memory 200368 kb
Host smart-db655a88-64e4-40a9-bbca-51d71fc2984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258680857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2258680857
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1061844808
Short name T66
Test name
Test status
Simulation time 157464220838 ps
CPU time 378.67 seconds
Started May 12 01:28:18 PM PDT 24
Finished May 12 01:34:37 PM PDT 24
Peak memory 227560 kb
Host smart-cab737da-3f84-45cd-a6e9-4a154d7bcb6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061844808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1061844808
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.5123526
Short name T126
Test name
Test status
Simulation time 15498463677 ps
CPU time 8.64 seconds
Started May 12 01:28:19 PM PDT 24
Finished May 12 01:28:28 PM PDT 24
Peak memory 200252 kb
Host smart-85065413-a1e1-4c67-be10-79b404ebdb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5123526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.5123526
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2073502588
Short name T1000
Test name
Test status
Simulation time 239291708080 ps
CPU time 540.36 seconds
Started May 12 01:28:19 PM PDT 24
Finished May 12 01:37:20 PM PDT 24
Peak memory 225268 kb
Host smart-968ffc13-b5dc-41f3-876e-e62b5bfc04f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073502588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2073502588
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.745049559
Short name T519
Test name
Test status
Simulation time 27634716683 ps
CPU time 38.92 seconds
Started May 12 01:28:17 PM PDT 24
Finished May 12 01:28:56 PM PDT 24
Peak memory 200416 kb
Host smart-ae6ceeb5-cab4-4c66-83a8-010153f5bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745049559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.745049559
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1510424018
Short name T720
Test name
Test status
Simulation time 102115821301 ps
CPU time 279.69 seconds
Started May 12 01:28:19 PM PDT 24
Finished May 12 01:32:59 PM PDT 24
Peak memory 208672 kb
Host smart-228f61d3-dc0d-4b9a-ab2e-910e97729f48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510424018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1510424018
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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