Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	130326	1			T1	5		T2	2		T3	10
all_values[1]	130326	1			T1	5		T2	2		T3	10
all_values[2]	130326	1			T1	5		T2	2		T3	10
all_values[3]	130326	1			T1	5		T2	2		T3	10
all_values[4]	130326	1			T1	5		T2	2		T3	10
all_values[5]	130326	1			T1	5		T2	2		T3	10
all_values[6]	130326	1			T1	5		T2	2		T3	10
all_values[7]	130326	1			T1	5		T2	2		T3	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

530009

1

T1

23

T2

16

T3

51

auto[1]

512599

1

T1

17

T3

29

T4

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978748

1

T1

33

T2

13

T3

70

auto[1]

63860

1

T1

7

T2

3

T3

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38805	1			T5	20		T7	78		T8	68
all_values[0]	auto[0]	auto[1]	23123	1			T1	3		T2	2		T3	7
all_values[0]	auto[1]	auto[0]	39900	1			T3	3		T5	20		T7	3
all_values[0]	auto[1]	auto[1]	28498	1			T1	2		T4	1		T5	37
all_values[1]	auto[0]	auto[0]	64554	1			T1	5		T2	2		T3	7
all_values[1]	auto[0]	auto[1]	1537	1			T7	23		T12	9		T110	3
all_values[1]	auto[1]	auto[0]	62471	1			T3	3		T4	1		T5	27
all_values[1]	auto[1]	auto[1]	1764	1			T5	10		T7	7		T8	19
all_values[2]	auto[0]	auto[0]	69179	1			T1	3		T2	1		T3	4
all_values[2]	auto[0]	auto[1]	2977	1			T1	1		T2	1		T5	8
all_values[2]	auto[1]	auto[0]	55540	1			T3	4		T5	25		T6	26
all_values[2]	auto[1]	auto[1]	2630	1			T1	1		T3	2		T5	8
all_values[3]	auto[0]	auto[0]	65727	1			T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	347	1			T12	2		T13	3		T15	3
all_values[3]	auto[1]	auto[0]	63964	1			T1	3		T3	6		T4	1
all_values[3]	auto[1]	auto[1]	288	1			T3	1		T12	1		T13	6
all_values[4]	auto[0]	auto[0]	63078	1			T1	1		T2	2		T3	6
all_values[4]	auto[0]	auto[1]	533	1			T12	4		T13	11		T15	2
all_values[4]	auto[1]	auto[0]	66222	1			T1	4		T3	4		T4	1
all_values[4]	auto[1]	auto[1]	493	1			T12	6		T13	4		T15	2
all_values[5]	auto[0]	auto[0]	71397	1			T1	5		T2	2		T3	9
all_values[5]	auto[0]	auto[1]	175	1			T12	3		T15	1		T28	5
all_values[5]	auto[1]	auto[0]	58532	1			T3	1		T4	1		T5	44
all_values[5]	auto[1]	auto[1]	222	1			T12	6		T13	4		T15	3
all_values[6]	auto[0]	auto[0]	65812	1			T1	2		T2	2		T3	9
all_values[6]	auto[0]	auto[1]	201	1			T12	1		T13	3		T15	3
all_values[6]	auto[1]	auto[0]	64086	1			T1	3		T3	1		T4	1
all_values[6]	auto[1]	auto[1]	227	1			T12	10		T13	2		T15	2
all_values[7]	auto[0]	auto[0]	62144	1			T1	1		T2	2		T3	6
all_values[7]	auto[0]	auto[1]	420	1			T12	11		T13	1		T15	1
all_values[7]	auto[1]	auto[0]	67337	1			T1	4		T3	4		T5	34
all_values[7]	auto[1]	auto[1]	425	1			T12	3		T13	6		T15	3