Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
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Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv



Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] 2630 1 T1 1 T2 1 T3 1
auto[UartRx] 2630 1 T1 1 T2 1 T3 1



Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4605 1 T1 2 T2 2 T3 2
values[1] 52 1 T29 2 T32 3 T33 1
values[2] 47 1 T29 1 T33 1 T101 2
values[3] 62 1 T13 1 T31 1 T33 1
values[4] 69 1 T12 1 T13 1 T15 1
values[5] 67 1 T5 1 T13 2 T29 1
values[6] 65 1 T13 1 T28 3 T29 3
values[7] 66 1 T12 3 T28 1 T32 1
values[8] 59 1 T5 1 T12 2 T13 1
values[9] 66 1 T12 1 T13 1 T15 1
values[10] 84 1 T13 1 T15 1 T29 3



Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dircp_rst_posCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] values[0] 2409 1 T1 1 T2 1 T3 1
auto[UartTx] values[1] 15 1 T32 1 T33 1 T101 1
auto[UartTx] values[2] 17 1 T29 1 T33 1 T101 1
auto[UartTx] values[3] 25 1 T134 3 T39 2 T330 1
auto[UartTx] values[4] 22 1 T13 1 T31 1 T101 2
auto[UartTx] values[5] 18 1 T117 1 T151 1 T153 2
auto[UartTx] values[6] 21 1 T13 1 T28 2 T29 1
auto[UartTx] values[7] 24 1 T12 2 T28 1 T240 1
auto[UartTx] values[8] 25 1 T5 1 T13 1 T30 1
auto[UartTx] values[9] 21 1 T12 1 T30 1 T31 1
auto[UartTx] values[10] 27 1 T13 1 T30 1 T32 2
auto[UartRx] values[0] 2196 1 T1 1 T2 1 T3 1
auto[UartRx] values[1] 37 1 T29 2 T32 2 T117 1
auto[UartRx] values[2] 30 1 T101 1 T117 1 T240 1
auto[UartRx] values[3] 37 1 T13 1 T31 1 T33 1
auto[UartRx] values[4] 47 1 T12 1 T15 1 T31 1
auto[UartRx] values[5] 49 1 T5 1 T13 2 T29 1
auto[UartRx] values[6] 44 1 T28 1 T29 2 T30 1
auto[UartRx] values[7] 42 1 T12 1 T32 1 T101 2
auto[UartRx] values[8] 34 1 T12 2 T30 2 T31 1
auto[UartRx] values[9] 45 1 T13 1 T15 1 T30 1
auto[UartRx] values[10] 57 1 T15 1 T29 3 T32 1

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