Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
2630 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
2630 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
11 |
0 |
11 |
100.00 |
User Defined Bins for cp_rst_pos
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0] |
4605 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
values[1] |
52 |
1 |
|
|
T29 |
2 |
|
T32 |
3 |
|
T33 |
1 |
values[2] |
47 |
1 |
|
|
T29 |
1 |
|
T33 |
1 |
|
T101 |
2 |
values[3] |
62 |
1 |
|
|
T13 |
1 |
|
T31 |
1 |
|
T33 |
1 |
values[4] |
69 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T15 |
1 |
values[5] |
67 |
1 |
|
|
T5 |
1 |
|
T13 |
2 |
|
T29 |
1 |
values[6] |
65 |
1 |
|
|
T13 |
1 |
|
T28 |
3 |
|
T29 |
3 |
values[7] |
66 |
1 |
|
|
T12 |
3 |
|
T28 |
1 |
|
T32 |
1 |
values[8] |
59 |
1 |
|
|
T5 |
1 |
|
T12 |
2 |
|
T13 |
1 |
values[9] |
66 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T15 |
1 |
values[10] |
84 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T29 |
3 |
Summary for Cross uart_reset_cg_cc
Samples crossed: cp_dir cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
22 |
0 |
22 |
100.00 |
|
Automatically Generated Cross Bins for uart_reset_cg_cc
Bins
cp_dir | cp_rst_pos | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
values[0] |
2409 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartTx] |
values[1] |
15 |
1 |
|
|
T32 |
1 |
|
T33 |
1 |
|
T101 |
1 |
auto[UartTx] |
values[2] |
17 |
1 |
|
|
T29 |
1 |
|
T33 |
1 |
|
T101 |
1 |
auto[UartTx] |
values[3] |
25 |
1 |
|
|
T134 |
3 |
|
T39 |
2 |
|
T330 |
1 |
auto[UartTx] |
values[4] |
22 |
1 |
|
|
T13 |
1 |
|
T31 |
1 |
|
T101 |
2 |
auto[UartTx] |
values[5] |
18 |
1 |
|
|
T117 |
1 |
|
T151 |
1 |
|
T153 |
2 |
auto[UartTx] |
values[6] |
21 |
1 |
|
|
T13 |
1 |
|
T28 |
2 |
|
T29 |
1 |
auto[UartTx] |
values[7] |
24 |
1 |
|
|
T12 |
2 |
|
T28 |
1 |
|
T240 |
1 |
auto[UartTx] |
values[8] |
25 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T30 |
1 |
auto[UartTx] |
values[9] |
21 |
1 |
|
|
T12 |
1 |
|
T30 |
1 |
|
T31 |
1 |
auto[UartTx] |
values[10] |
27 |
1 |
|
|
T13 |
1 |
|
T30 |
1 |
|
T32 |
2 |
auto[UartRx] |
values[0] |
2196 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
values[1] |
37 |
1 |
|
|
T29 |
2 |
|
T32 |
2 |
|
T117 |
1 |
auto[UartRx] |
values[2] |
30 |
1 |
|
|
T101 |
1 |
|
T117 |
1 |
|
T240 |
1 |
auto[UartRx] |
values[3] |
37 |
1 |
|
|
T13 |
1 |
|
T31 |
1 |
|
T33 |
1 |
auto[UartRx] |
values[4] |
47 |
1 |
|
|
T12 |
1 |
|
T15 |
1 |
|
T31 |
1 |
auto[UartRx] |
values[5] |
49 |
1 |
|
|
T5 |
1 |
|
T13 |
2 |
|
T29 |
1 |
auto[UartRx] |
values[6] |
44 |
1 |
|
|
T28 |
1 |
|
T29 |
2 |
|
T30 |
1 |
auto[UartRx] |
values[7] |
42 |
1 |
|
|
T12 |
1 |
|
T32 |
1 |
|
T101 |
2 |
auto[UartRx] |
values[8] |
34 |
1 |
|
|
T12 |
2 |
|
T30 |
2 |
|
T31 |
1 |
auto[UartRx] |
values[9] |
45 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T30 |
1 |
auto[UartRx] |
values[10] |
57 |
1 |
|
|
T15 |
1 |
|
T29 |
3 |
|
T32 |
1 |