Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2356	1			T2	1		T3	3		T4	3
auto[BaudRate115200]	2168	1			T4	12		T5	7		T6	1
auto[BaudRate230400]	2136	1			T1	1		T3	2		T4	6
auto[BaudRate128Kbps]	2023	1			T1	3		T2	1		T3	2
auto[BaudRate256Kbps]	2311	1			T3	1		T4	3		T5	10
auto[BaudRate1Mbps]	1981	1			T1	3		T4	11		T5	5
auto[BaudRate1p5Mbps]	1520	1			T1	1		T4	3		T5	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1858	1			T11	2		T27	13		T36	7
freqs[25]	1174	1			T14	9		T34	9		T106	5
freqs[48]	504	1			T251	2		T119	10		T105	2
freqs[50]	947	1			T78	10		T18	39		T112	5
freqs[100]	1149	1			T1	8		T7	10		T21	16

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	321	1			T27	4		T36	4		T28	4
auto[BaudRate9600]	freqs[25]	200	1			T14	9		T106	1		T108	1
auto[BaudRate9600]	freqs[48]	69	1			T284	1		T113	3		T331	1
auto[BaudRate9600]	freqs[50]	125	1			T111	1		T332	3		T181	1
auto[BaudRate9600]	freqs[100]	184	1			T7	1		T21	5		T30	2
auto[BaudRate115200]	freqs[24]	251	1			T27	2		T36	1		T28	12
auto[BaudRate115200]	freqs[25]	187	1			T34	2		T106	2		T108	1
auto[BaudRate115200]	freqs[48]	79	1			T251	1		T119	2		T105	1
auto[BaudRate115200]	freqs[50]	128	1			T18	3		T111	3		T332	3
auto[BaudRate115200]	freqs[100]	158	1			T7	1		T21	5		T30	2
auto[BaudRate230400]	freqs[24]	319	1			T11	1		T27	2		T36	2
auto[BaudRate230400]	freqs[25]	200	1			T34	1		T106	2		T122	2
auto[BaudRate230400]	freqs[48]	75	1			T105	1		T113	1		T128	1
auto[BaudRate230400]	freqs[50]	126	1			T18	10		T112	1		T332	18
auto[BaudRate230400]	freqs[100]	142	1			T1	1		T7	2		T21	1
auto[BaudRate128Kbps]	freqs[24]	251	1			T28	14		T247	2		T333	6
auto[BaudRate128Kbps]	freqs[25]	162	1			T158	1		T118	1		T334	1
auto[BaudRate128Kbps]	freqs[48]	66	1			T119	1		T113	2		T304	1
auto[BaudRate128Kbps]	freqs[50]	131	1			T18	10		T112	1		T332	6
auto[BaudRate128Kbps]	freqs[100]	151	1			T1	3		T7	2		T21	2
auto[BaudRate256Kbps]	freqs[24]	301	1			T27	4		T28	16		T247	2
auto[BaudRate256Kbps]	freqs[25]	163	1			T34	4		T122	2		T335	3
auto[BaudRate256Kbps]	freqs[48]	77	1			T113	1		T128	2		T336	1
auto[BaudRate256Kbps]	freqs[50]	130	1			T78	4		T18	4		T332	6
auto[BaudRate256Kbps]	freqs[100]	172	1			T7	1		T21	2		T30	3
auto[BaudRate1Mbps]	freqs[24]	271	1			T11	1		T27	1		T28	5
auto[BaudRate1Mbps]	freqs[25]	180	1			T34	1		T158	1		T272	1
auto[BaudRate1Mbps]	freqs[48]	68	1			T119	6		T113	1		T128	3
auto[BaudRate1Mbps]	freqs[50]	161	1			T78	2		T18	3		T332	12
auto[BaudRate1Mbps]	freqs[100]	183	1			T1	3		T7	2		T21	1
auto[BaudRate1p5Mbps]	freqs[25]	82	1			T34	1		T335	3		T245	2
auto[BaudRate1p5Mbps]	freqs[48]	70	1			T251	1		T119	1		T284	1
auto[BaudRate1p5Mbps]	freqs[50]	146	1			T78	4		T18	9		T112	3
auto[BaudRate1p5Mbps]	freqs[100]	159	1			T1	1		T7	1		T30	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded