Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	16	114	87.69

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	16	114	87.69	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	37702997	1			T1	10		T3	49		T4	5
all_levels[1]	207142	1			T1	1		T5	26		T6	21
all_levels[2]	2470	1			T5	7		T6	2		T7	6
all_levels[3]	1064	1			T5	6		T7	2		T8	11
all_levels[4]	724	1			T5	5		T7	4		T8	4
all_levels[5]	575	1			T1	2		T5	3		T6	1
all_levels[6]	492	1			T5	2		T6	1		T7	2
all_levels[7]	419	1			T5	1		T6	1		T7	3
all_levels[8]	282	1			T5	1		T6	1		T7	1
all_levels[9]	280	1			T5	3		T6	1		T7	6
all_levels[10]	222	1			T7	3		T119	3		T18	1
all_levels[11]	207	1			T5	2		T27	1		T119	1
all_levels[12]	155	1			T5	1		T7	1		T119	1
all_levels[13]	156	1			T6	1		T7	2		T13	1
all_levels[14]	120	1			T7	4		T110	5		T28	1
all_levels[15]	124	1			T7	2		T110	1		T13	1
all_levels[16]	122	1			T10	1		T35	1		T30	1
all_levels[17]	94	1			T12	1		T109	1		T28	1
all_levels[18]	90	1			T7	2		T38	1		T32	1
all_levels[19]	88	1			T28	1		T37	1		T32	1
all_levels[20]	80	1			T3	1		T110	2		T13	1
all_levels[21]	72	1			T119	1		T120	1		T13	1
all_levels[22]	65	1			T119	1		T121	2		T32	1
all_levels[23]	58	1			T122	1		T123	1		T113	1
all_levels[24]	37	1			T124	1		T125	1		T126	1
all_levels[25]	42	1			T7	1		T35	1		T37	1
all_levels[26]	35	1			T7	1		T110	1		T122	1
all_levels[27]	37	1			T127	1		T128	2		T129	1
all_levels[28]	45	1			T35	1		T130	1		T131	1
all_levels[29]	43	1			T32	1		T132	1		T113	1
all_levels[30]	48	1			T109	1		T123	1		T113	1
all_levels[31]	32	1			T12	1		T113	1		T133	1
all_levels[32]	33	1			T3	1		T12	1		T28	5
all_levels[33]	30	1			T134	1		T122	1		T135	2
all_levels[34]	30	1			T134	1		T136	2		T128	1
all_levels[35]	21	1			T126	1		T137	1		T138	2
all_levels[36]	24	1			T110	1		T113	1		T116	1
all_levels[37]	29	1			T132	1		T126	1		T133	1
all_levels[38]	17	1			T115	1		T133	1		T139	1
all_levels[39]	17	1			T35	1		T140	2		T141	2
all_levels[40]	30	1			T18	1		T128	1		T137	2
all_levels[41]	20	1			T135	1		T116	1		T142	2
all_levels[42]	7	1			T143	1		T144	1		T145	1
all_levels[43]	11	1			T146	1		T147	1		T43	1
all_levels[44]	15	1			T115	1		T141	1		T148	2
all_levels[45]	12	1			T149	2		T150	1		T151	1
all_levels[46]	14	1			T126	2		T115	1		T104	1
all_levels[47]	17	1			T152	1		T153	1		T154	1
all_levels[48]	17	1			T155	1		T122	1		T156	1
all_levels[49]	20	1			T157	1		T158	2		T151	1
all_levels[50]	11	1			T123	1		T159	1		T160	2
all_levels[51]	5	1			T161	1		T162	1		T47	1
all_levels[52]	14	1			T152	1		T123	2		T116	1
all_levels[53]	8	1			T155	1		T99	1		T163	1
all_levels[54]	7	1			T58	1		T164	1		T47	1
all_levels[55]	6	1			T126	1		T139	2		T165	1
all_levels[56]	3	1			T166	1		T167	1		T168	1
all_levels[57]	4	1			T153	1		T169	1		T170	1
all_levels[58]	6	1			T120	1		T141	1		T171	1
all_levels[59]	6	1			T115	1		T163	1		T172	1
all_levels[60]	9	1			T141	1		T150	1		T63	1
all_levels[61]	5	1			T132	1		T173	1		T174	1
all_levels[62]	4	1			T159	1		T161	1		T58	1
all_levels[63]	7	1			T175	1		T147	1		T176	1
all_levels[64]	121	1			T3	3		T28	1		T152	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37914213

1

T1

6

T3

48

T5

5437

auto[1]

4784

1

T1

7

T3

6

T4

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	16	114	87.69	16

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[42] , all_levels[43]]	[auto[1]]	--	--	2
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52] , all_levels[53] , all_levels[54] , all_levels[55] , all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59]]	[auto[1]]	--	--	9
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	37698666	1			T1	4		T3	44		T5	5381
all_levels[0]	auto[1]	4331	1			T1	6		T3	5		T4	5
all_levels[1]	auto[0]	207071	1			T1	1		T5	26		T6	20
all_levels[1]	auto[1]	71	1			T6	1		T177	3		T178	1
all_levels[2]	auto[0]	2434	1			T5	7		T6	2		T7	6
all_levels[2]	auto[1]	36	1			T121	1		T179	1		T180	1
all_levels[3]	auto[0]	1041	1			T5	6		T7	2		T8	11
all_levels[3]	auto[1]	23	1			T178	1		T181	1		T171	1
all_levels[4]	auto[0]	707	1			T5	5		T7	4		T8	4
all_levels[4]	auto[1]	17	1			T136	1		T182	5		T183	2
all_levels[5]	auto[0]	561	1			T1	1		T5	3		T6	1
all_levels[5]	auto[1]	14	1			T1	1		T13	1		T152	2
all_levels[6]	auto[0]	478	1			T5	2		T6	1		T7	2
all_levels[6]	auto[1]	14	1			T106	2		T57	1		T184	1
all_levels[7]	auto[0]	395	1			T5	1		T6	1		T7	3
all_levels[7]	auto[1]	24	1			T121	1		T157	3		T178	2
all_levels[8]	auto[0]	275	1			T5	1		T6	1		T7	1
all_levels[8]	auto[1]	7	1			T180	1		T171	1		T56	1
all_levels[9]	auto[0]	257	1			T5	2		T6	1		T7	6
all_levels[9]	auto[1]	23	1			T5	1		T132	2		T185	1
all_levels[10]	auto[0]	207	1			T7	3		T119	3		T18	1
all_levels[10]	auto[1]	15	1			T111	1		T186	2		T187	1
all_levels[11]	auto[0]	197	1			T5	2		T27	1		T119	1
all_levels[11]	auto[1]	10	1			T178	1		T188	1		T189	3
all_levels[12]	auto[0]	141	1			T5	1		T7	1		T119	1
all_levels[12]	auto[1]	14	1			T13	1		T140	1		T98	1
all_levels[13]	auto[0]	148	1			T6	1		T7	2		T13	1
all_levels[13]	auto[1]	8	1			T163	1		T190	1		T164	1
all_levels[14]	auto[0]	111	1			T7	4		T110	1		T28	1
all_levels[14]	auto[1]	9	1			T110	4		T191	2		T192	1
all_levels[15]	auto[0]	117	1			T7	2		T110	1		T13	1
all_levels[15]	auto[1]	7	1			T136	1		T193	1		T194	1
all_levels[16]	auto[0]	104	1			T10	1		T35	1		T30	1
all_levels[16]	auto[1]	18	1			T185	1		T113	1		T195	1
all_levels[17]	auto[0]	90	1			T12	1		T109	1		T28	1
all_levels[17]	auto[1]	4	1			T180	1		T128	1		T196	1
all_levels[18]	auto[0]	88	1			T7	2		T38	1		T32	1
all_levels[18]	auto[1]	2	1			T197	1		T198	1		-	-
all_levels[19]	auto[0]	80	1			T28	1		T37	1		T32	1
all_levels[19]	auto[1]	8	1			T199	1		T200	1		T201	1
all_levels[20]	auto[0]	70	1			T3	1		T110	1		T13	1
all_levels[20]	auto[1]	10	1			T110	1		T202	1		T93	1
all_levels[21]	auto[0]	66	1			T119	1		T120	1		T13	1
all_levels[21]	auto[1]	6	1			T203	2		T204	1		T205	1
all_levels[22]	auto[0]	58	1			T119	1		T121	1		T32	1
all_levels[22]	auto[1]	7	1			T121	1		T206	1		T207	1
all_levels[23]	auto[0]	52	1			T122	1		T123	1		T113	1
all_levels[23]	auto[1]	6	1			T208	1		T209	2		T210	1
all_levels[24]	auto[0]	35	1			T124	1		T125	1		T126	1
all_levels[24]	auto[1]	2	1			T211	1		T212	1		-	-
all_levels[25]	auto[0]	37	1			T7	1		T35	1		T37	1
all_levels[25]	auto[1]	5	1			T202	1		T213	2		T214	2
all_levels[26]	auto[0]	31	1			T7	1		T110	1		T122	1
all_levels[26]	auto[1]	4	1			T142	1		T215	1		T216	1
all_levels[27]	auto[0]	33	1			T127	1		T128	2		T129	1
all_levels[27]	auto[1]	4	1			T217	3		T218	1		-	-
all_levels[28]	auto[0]	37	1			T35	1		T130	1		T131	1
all_levels[28]	auto[1]	8	1			T219	3		T220	4		T221	1
all_levels[29]	auto[0]	38	1			T32	1		T132	1		T113	1
all_levels[29]	auto[1]	5	1			T222	5		-	-		-	-
all_levels[30]	auto[0]	43	1			T109	1		T123	1		T113	1
all_levels[30]	auto[1]	5	1			T223	1		T224	1		T225	3
all_levels[31]	auto[0]	30	1			T12	1		T113	1		T133	1
all_levels[31]	auto[1]	2	1			T226	1		T224	1		-	-
all_levels[32]	auto[0]	28	1			T3	1		T12	1		T28	2
all_levels[32]	auto[1]	5	1			T28	3		T216	1		T227	1
all_levels[33]	auto[0]	30	1			T134	1		T122	1		T135	2
all_levels[34]	auto[0]	26	1			T134	1		T136	1		T128	1
all_levels[34]	auto[1]	4	1			T136	1		T219	1		T228	1
all_levels[35]	auto[0]	20	1			T126	1		T137	1		T138	1
all_levels[35]	auto[1]	1	1			T138	1		-	-		-	-
all_levels[36]	auto[0]	21	1			T110	1		T113	1		T116	1
all_levels[36]	auto[1]	3	1			T145	1		T229	1		T230	1
all_levels[37]	auto[0]	22	1			T132	1		T126	1		T133	1
all_levels[37]	auto[1]	7	1			T231	2		T232	1		T233	4
all_levels[38]	auto[0]	17	1			T115	1		T133	1		T139	1
all_levels[39]	auto[0]	16	1			T35	1		T140	2		T141	2
all_levels[39]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[40]	auto[0]	28	1			T18	1		T128	1		T137	2
all_levels[40]	auto[1]	2	1			T99	2		-	-		-	-
all_levels[41]	auto[0]	19	1			T135	1		T116	1		T142	1
all_levels[41]	auto[1]	1	1			T142	1		-	-		-	-
all_levels[42]	auto[0]	7	1			T143	1		T144	1		T145	1
all_levels[43]	auto[0]	11	1			T146	1		T147	1		T43	1
all_levels[44]	auto[0]	12	1			T115	1		T141	1		T148	1
all_levels[44]	auto[1]	3	1			T148	1		T213	2		-	-
all_levels[45]	auto[0]	11	1			T149	1		T150	1		T151	1
all_levels[45]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[46]	auto[0]	14	1			T126	2		T115	1		T104	1
all_levels[47]	auto[0]	12	1			T152	1		T153	1		T154	1
all_levels[47]	auto[1]	5	1			T235	5		-	-		-	-
all_levels[48]	auto[0]	11	1			T155	1		T122	1		T156	1
all_levels[48]	auto[1]	6	1			T236	1		T237	5		-	-
all_levels[49]	auto[0]	11	1			T157	1		T158	1		T151	1
all_levels[49]	auto[1]	9	1			T158	1		T238	3		T204	3
all_levels[50]	auto[0]	10	1			T123	1		T159	1		T160	1
all_levels[50]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[51]	auto[0]	5	1			T161	1		T162	1		T47	1
all_levels[52]	auto[0]	14	1			T152	1		T123	2		T116	1
all_levels[53]	auto[0]	8	1			T155	1		T99	1		T163	1
all_levels[54]	auto[0]	7	1			T58	1		T164	1		T47	1
all_levels[55]	auto[0]	6	1			T126	1		T139	2		T165	1
all_levels[56]	auto[0]	3	1			T166	1		T167	1		T168	1
all_levels[57]	auto[0]	4	1			T153	1		T169	1		T170	1
all_levels[58]	auto[0]	6	1			T120	1		T141	1		T171	1
all_levels[59]	auto[0]	6	1			T115	1		T163	1		T172	1
all_levels[60]	auto[0]	8	1			T141	1		T150	1		T63	1
all_levels[60]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T132	1		T173	1		T174	1
all_levels[62]	auto[0]	4	1			T159	1		T161	1		T58	1
all_levels[63]	auto[0]	5	1			T175	1		T147	1		T176	1
all_levels[63]	auto[1]	2	1			T162	2		-	-		-	-
all_levels[64]	auto[0]	108	1			T3	2		T28	1		T152	2
all_levels[64]	auto[1]	13	1			T3	1		T240	1		T139	2