Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1407 1 T5 10 T7 11 T8 19
all_levels[1] 670 1 T7 7 T110 3 T35 1
all_levels[2] 498 1 T7 12 T12 20 T111 21
all_levels[3] 332 1 T35 2 T112 19 T113 3
all_levels[4] 221 1 T18 8 T114 7 T115 1
all_levels[5] 105 1 T13 17 T116 2 T117 2
all_levels[6] 58 1 T29 2 T19 6 T118 4

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