Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	130326	1			T1	5		T2	2		T3	10
all_pins[1]	130326	1			T1	5		T2	2		T3	10
all_pins[2]	130326	1			T1	5		T2	2		T3	10
all_pins[3]	130326	1			T1	5		T2	2		T3	10
all_pins[4]	130326	1			T1	5		T2	2		T3	10
all_pins[5]	130326	1			T1	5		T2	2		T3	10
all_pins[6]	130326	1			T1	5		T2	2		T3	10
all_pins[7]	130326	1			T1	5		T2	2		T3	10

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1007129	1			T1	35		T2	16		T3	77
values[0x1]	35479	1			T1	5		T3	3		T4	1
transitions[0x0=>0x1]	34388	1			T1	5		T3	2		T4	1
transitions[0x1=>0x0]	33956	1			T1	4		T3	2		T5	64

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101755	1			T1	3		T2	2		T3	10
all_pins[0]	values[0x1]	28571	1			T1	2		T4	1		T5	41
all_pins[0]	transitions[0x0=>0x1]	28101	1			T1	2		T4	1		T5	41
all_pins[0]	transitions[0x1=>0x0]	1292	1			T5	10		T7	7		T8	19
all_pins[1]	values[0x0]	128564	1			T1	5		T2	2		T3	10
all_pins[1]	values[0x1]	1762	1			T5	10		T7	7		T8	19
all_pins[1]	transitions[0x0=>0x1]	1636	1			T5	10		T7	7		T8	19
all_pins[1]	transitions[0x1=>0x0]	2571	1			T1	1		T3	2		T5	8
all_pins[2]	values[0x0]	127629	1			T1	4		T2	2		T3	8
all_pins[2]	values[0x1]	2697	1			T1	1		T3	2		T5	8
all_pins[2]	transitions[0x0=>0x1]	2633	1			T1	1		T3	1		T5	8
all_pins[2]	transitions[0x1=>0x0]	224	1			T12	1		T13	3		T15	1
all_pins[3]	values[0x0]	130038	1			T1	5		T2	2		T3	9
all_pins[3]	values[0x1]	288	1			T3	1		T12	1		T13	6
all_pins[3]	transitions[0x0=>0x1]	247	1			T3	1		T12	1		T13	4
all_pins[3]	transitions[0x1=>0x0]	452	1			T12	6		T13	2		T15	2
all_pins[4]	values[0x0]	129833	1			T1	5		T2	2		T3	10
all_pins[4]	values[0x1]	493	1			T12	6		T13	4		T15	2
all_pins[4]	transitions[0x0=>0x1]	415	1			T12	5		T13	4		T15	2
all_pins[4]	transitions[0x1=>0x0]	197	1			T12	5		T13	5		T15	3
all_pins[5]	values[0x0]	130051	1			T1	5		T2	2		T3	10
all_pins[5]	values[0x1]	275	1			T12	6		T13	5		T15	3
all_pins[5]	transitions[0x0=>0x1]	218	1			T12	3		T13	4		T15	2
all_pins[5]	transitions[0x1=>0x0]	911	1			T1	2		T5	5		T10	13
all_pins[6]	values[0x0]	129358	1			T1	3		T2	2		T3	10
all_pins[6]	values[0x1]	968	1			T1	2		T5	5		T10	13
all_pins[6]	transitions[0x0=>0x1]	905	1			T1	2		T5	5		T10	13
all_pins[6]	transitions[0x1=>0x0]	362	1			T12	1		T13	6		T15	2
all_pins[7]	values[0x0]	129901	1			T1	5		T2	2		T3	10
all_pins[7]	values[0x1]	425	1			T12	3		T13	6		T15	3
all_pins[7]	transitions[0x0=>0x1]	233	1			T12	3		T13	5		T15	3
all_pins[7]	transitions[0x1=>0x0]	27947	1			T1	1		T5	41		T6	31