Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	10164682	1			T3	34		T5	112		T6	83
all_levels[1]	1315922	1			T3	9		T5	24		T7	15
all_levels[2]	352898	1			T5	18		T10	3		T21	8
all_levels[3]	490338	1			T5	19		T7	12		T21	1
all_levels[4]	518622	1			T5	15		T21	17		T12	570
all_levels[5]	261570	1			T1	2		T3	2		T5	18
all_levels[6]	300580	1			T1	4		T5	19		T6	3
all_levels[7]	718217	1			T5	22		T21	1		T12	323
all_levels[8]	472235	1			T5	4968		T7	8		T10	2
all_levels[9]	256530	1			T5	53		T21	2		T12	571
all_levels[10]	287371	1			T5	24		T12	406		T27	2
all_levels[11]	403768	1			T3	3		T5	12		T21	1
all_levels[12]	257939	1			T5	15		T6	1		T7	5
all_levels[13]	252074	1			T8	19		T21	257		T12	549
all_levels[14]	404145	1			T5	19		T7	1		T12	245
all_levels[15]	394861	1			T1	4		T5	33		T7	12
all_levels[16]	352508	1			T5	2		T10	2		T21	1
all_levels[17]	259140	1			T5	3		T10	1		T12	960
all_levels[18]	382081	1			T5	1		T12	793		T27	26
all_levels[19]	737199	1			T5	1		T7	14		T12	534
all_levels[20]	307718	1			T5	2		T7	20		T12	953
all_levels[21]	339751	1			T5	21		T12	951		T78	142
all_levels[22]	282792	1			T6	1		T7	17		T12	938
all_levels[23]	223693	1			T12	941		T110	5		T78	142
all_levels[24]	258431	1			T21	30		T12	489		T78	158
all_levels[25]	220851	1			T5	2		T6	2		T7	4
all_levels[26]	327950	1			T5	8		T7	5		T12	952
all_levels[27]	484213	1			T5	2		T12	805		T78	139
all_levels[28]	402231	1			T5	3		T12	559		T78	138
all_levels[29]	225516	1			T5	27		T12	950		T78	154
all_levels[30]	274934	1			T5	9		T12	953		T78	153
all_levels[31]	663592	1			T5	5		T21	1		T12	2033
all_levels[32]	15324144	1			T1	4		T3	8		T5	10

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37914213

1

T1

6

T3

48

T5

5437

auto[1]

4283

1

T1

8

T3

8

T5

30

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	10162516	1			T3	33		T5	91		T6	80
all_levels[0]	auto[1]	2166	1			T3	1		T5	21		T6	3
all_levels[1]	auto[0]	1315618	1			T3	6		T5	24		T7	15
all_levels[1]	auto[1]	304	1			T3	3		T30	1		T152	5
all_levels[2]	auto[0]	352852	1			T5	18		T10	2		T21	8
all_levels[2]	auto[1]	46	1			T10	1		T181	1		T272	1
all_levels[3]	auto[0]	490151	1			T5	19		T7	12		T21	1
all_levels[3]	auto[1]	187	1			T18	8		T157	1		T134	1
all_levels[4]	auto[0]	518585	1			T5	15		T21	17		T12	570
all_levels[4]	auto[1]	37	1			T13	1		T157	1		T245	1
all_levels[5]	auto[0]	261529	1			T1	1		T3	2		T5	18
all_levels[5]	auto[1]	41	1			T1	1		T121	1		T32	1
all_levels[6]	auto[0]	300555	1			T1	2		T5	19		T6	2
all_levels[6]	auto[1]	25	1			T1	2		T6	1		T13	1
all_levels[7]	auto[0]	718039	1			T5	15		T21	1		T12	323
all_levels[7]	auto[1]	178	1			T5	7		T13	12		T18	8
all_levels[8]	auto[0]	472211	1			T5	4968		T7	8		T10	2
all_levels[8]	auto[1]	24	1			T106	2		T121	1		T244	1
all_levels[9]	auto[0]	256511	1			T5	53		T21	2		T12	571
all_levels[9]	auto[1]	19	1			T338	1		T339	3		T139	1
all_levels[10]	auto[0]	287351	1			T5	24		T12	406		T27	2
all_levels[10]	auto[1]	20	1			T181	3		T340	1		T326	1
all_levels[11]	auto[0]	403737	1			T3	2		T5	12		T21	1
all_levels[11]	auto[1]	31	1			T3	1		T178	2		T308	1
all_levels[12]	auto[0]	257911	1			T5	15		T6	1		T7	5
all_levels[12]	auto[1]	28	1			T142	1		T129	1		T279	1
all_levels[13]	auto[0]	252054	1			T8	18		T21	257		T12	549
all_levels[13]	auto[1]	20	1			T8	1		T13	1		T127	1
all_levels[14]	auto[0]	404119	1			T5	18		T7	1		T12	245
all_levels[14]	auto[1]	26	1			T5	1		T38	1		T124	1
all_levels[15]	auto[0]	394643	1			T1	2		T5	33		T7	12
all_levels[15]	auto[1]	218	1			T1	2		T18	4		T33	8
all_levels[16]	auto[0]	352476	1			T5	2		T10	2		T21	1
all_levels[16]	auto[1]	32	1			T127	1		T341	3		T137	2
all_levels[17]	auto[0]	259124	1			T5	3		T10	1		T12	960
all_levels[17]	auto[1]	16	1			T137	1		T139	1		T173	2
all_levels[18]	auto[0]	382055	1			T5	1		T12	793		T27	26
all_levels[18]	auto[1]	26	1			T259	1		T158	1		T240	1
all_levels[19]	auto[0]	737182	1			T5	1		T7	14		T12	534
all_levels[19]	auto[1]	17	1			T286	1		T113	1		T179	1
all_levels[20]	auto[0]	307704	1			T5	2		T7	20		T12	953
all_levels[20]	auto[1]	14	1			T178	1		T313	1		T342	1
all_levels[21]	auto[0]	339729	1			T5	21		T12	951		T78	142
all_levels[21]	auto[1]	22	1			T136	1		T158	1		T208	2
all_levels[22]	auto[0]	282769	1			T6	1		T7	17		T12	938
all_levels[22]	auto[1]	23	1			T185	1		T280	1		T310	1
all_levels[23]	auto[0]	223668	1			T12	941		T110	3		T78	142
all_levels[23]	auto[1]	25	1			T110	2		T121	1		T343	1
all_levels[24]	auto[0]	258407	1			T21	30		T12	489		T78	158
all_levels[24]	auto[1]	24	1			T136	1		T321	2		T139	1
all_levels[25]	auto[0]	220831	1			T5	2		T6	2		T7	4
all_levels[25]	auto[1]	20	1			T344	3		T95	1		T211	1
all_levels[26]	auto[0]	327922	1			T5	8		T7	5		T12	952
all_levels[26]	auto[1]	28	1			T177	1		T259	2		T196	2
all_levels[27]	auto[0]	484186	1			T5	2		T12	805		T78	139
all_levels[27]	auto[1]	27	1			T120	1		T180	1		T131	2
all_levels[28]	auto[0]	402207	1			T5	3		T12	559		T78	138
all_levels[28]	auto[1]	24	1			T345	1		T208	1		T317	4
all_levels[29]	auto[0]	225499	1			T5	27		T12	950		T78	154
all_levels[29]	auto[1]	17	1			T178	1		T180	2		T163	1
all_levels[30]	auto[0]	274920	1			T5	9		T12	953		T78	153
all_levels[30]	auto[1]	14	1			T112	3		T341	1		T196	2
all_levels[31]	auto[0]	663580	1			T5	5		T21	1		T12	2033
all_levels[31]	auto[1]	12	1			T272	1		T171	1		T346	2
all_levels[32]	auto[0]	15323572	1			T1	1		T3	5		T5	9
all_levels[32]	auto[1]	572	1			T1	3		T3	3		T5	1