Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	878	1			T12	22		T13	11		T15	7
all_values[1]	878	1			T12	22		T13	11		T15	7
all_values[2]	878	1			T12	22		T13	11		T15	7
all_values[3]	878	1			T12	22		T13	11		T15	7
all_values[4]	878	1			T12	22		T13	11		T15	7
all_values[5]	878	1			T12	22		T13	11		T15	7
all_values[6]	878	1			T12	22		T13	11		T15	7
all_values[7]	878	1			T12	22		T13	11		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3714

1

T12

87

T13

34

T15

32

auto[1]

3310

1

T12

89

T13

54

T15

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2531

1

T12

60

T13

29

T15

19

auto[1]

4493

1

T12

116

T13

59

T15

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4135

1

T12

101

T13

51

T15

33

auto[1]

2889

1

T12

75

T13

37

T15

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	273	1			T12	9		T13	1		T15	4
all_values[0]	auto[0]	auto[1]	auto[1]	263	1			T12	3		T13	5		T15	2
all_values[0]	auto[1]	auto[0]	auto[1]	187	1			T12	6		T13	1		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	155	1			T12	4		T13	4		T28	1
all_values[1]	auto[0]	auto[0]	auto[0]	267	1			T12	8		T13	2		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	249	1			T12	7		T13	3		T15	2
all_values[1]	auto[1]	auto[0]	auto[1]	197	1			T12	5		T13	5		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T12	2		T13	1		T15	1
all_values[2]	auto[0]	auto[0]	auto[0]	176	1			T12	4		T13	2		T15	1
all_values[2]	auto[0]	auto[0]	auto[1]	97	1			T12	1		T28	1		T101	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T12	2		T13	1		T15	1
all_values[2]	auto[0]	auto[1]	auto[1]	106	1			T12	4		T13	5		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	192	1			T12	6		T15	2		T28	2
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T12	5		T13	3		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	191	1			T12	6		T13	3		T15	1
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T12	1		T15	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[0]	169	1			T12	10		T13	2		T15	1
all_values[3]	auto[0]	auto[1]	auto[1]	61	1			T12	1		T13	2		T15	1
all_values[3]	auto[1]	auto[0]	auto[1]	198	1			T12	2		T13	1		T15	3
all_values[3]	auto[1]	auto[1]	auto[1]	166	1			T12	2		T13	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T15	2		T18	1		T28	4
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T12	1		T13	1		T33	3
all_values[4]	auto[0]	auto[1]	auto[0]	155	1			T12	6		T13	1		T15	1
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T12	3		T13	3		T15	1
all_values[4]	auto[1]	auto[0]	auto[1]	215	1			T12	8		T13	4		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T12	4		T13	2		T15	1
all_values[5]	auto[0]	auto[0]	auto[0]	196	1			T12	3		T13	2		T15	3
all_values[5]	auto[0]	auto[0]	auto[1]	83	1			T12	2		T28	2		T33	1
all_values[5]	auto[0]	auto[1]	auto[0]	161	1			T12	5		T13	2		T28	2
all_values[5]	auto[0]	auto[1]	auto[1]	95	1			T12	4		T13	2		T18	2
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T12	2		T13	3		T15	2
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T12	6		T13	2		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T12	2		T13	2		T15	2
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T13	2		T15	1		T28	1
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T12	3		T13	2		T18	1
all_values[6]	auto[0]	auto[1]	auto[1]	101	1			T12	5		T13	1		T15	1
all_values[6]	auto[1]	auto[0]	auto[1]	192	1			T12	6		T13	1		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	177	1			T12	6		T13	3		T15	1
all_values[7]	auto[0]	auto[0]	auto[0]	190	1			T12	1		T13	3		T15	1
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T12	6		T18	1		T32	1
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T12	3		T13	4		T15	2
all_values[7]	auto[0]	auto[1]	auto[1]	91	1			T12	1		T15	2		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	199	1			T12	8		T13	1		T28	1
all_values[7]	auto[1]	auto[1]	auto[1]	171	1			T12	3		T13	3		T15	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal