Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.27 97.95 100.00 98.80 100.00 99.46


Total test records in report: 1320
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T1255 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4238026532 May 14 12:54:42 PM PDT 24 May 14 12:54:44 PM PDT 24 135923772 ps
T1256 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1776401766 May 14 12:54:30 PM PDT 24 May 14 12:54:36 PM PDT 24 36630612 ps
T1257 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1007469267 May 14 12:54:30 PM PDT 24 May 14 12:54:35 PM PDT 24 20652521 ps
T1258 /workspace/coverage/cover_reg_top/16.uart_tl_errors.4041568536 May 14 12:54:47 PM PDT 24 May 14 12:54:52 PM PDT 24 31534835 ps
T1259 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3618968237 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 92729968 ps
T1260 /workspace/coverage/cover_reg_top/11.uart_intr_test.3412631511 May 14 12:54:46 PM PDT 24 May 14 12:54:50 PM PDT 24 14541639 ps
T1261 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2010436439 May 14 12:54:45 PM PDT 24 May 14 12:54:49 PM PDT 24 98665879 ps
T1262 /workspace/coverage/cover_reg_top/37.uart_intr_test.1587804405 May 14 12:54:55 PM PDT 24 May 14 12:54:59 PM PDT 24 15670742 ps
T1263 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3627112762 May 14 12:54:23 PM PDT 24 May 14 12:54:28 PM PDT 24 38405593 ps
T1264 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4083394539 May 14 12:54:44 PM PDT 24 May 14 12:54:48 PM PDT 24 77454256 ps
T1265 /workspace/coverage/cover_reg_top/23.uart_intr_test.3405062412 May 14 12:54:46 PM PDT 24 May 14 12:54:50 PM PDT 24 19700474 ps
T1266 /workspace/coverage/cover_reg_top/41.uart_intr_test.3593269542 May 14 12:55:04 PM PDT 24 May 14 12:55:06 PM PDT 24 42548612 ps
T1267 /workspace/coverage/cover_reg_top/21.uart_intr_test.3807353 May 14 12:54:46 PM PDT 24 May 14 12:54:50 PM PDT 24 66194222 ps
T1268 /workspace/coverage/cover_reg_top/35.uart_intr_test.550275204 May 14 12:54:54 PM PDT 24 May 14 12:54:57 PM PDT 24 27054789 ps
T1269 /workspace/coverage/cover_reg_top/49.uart_intr_test.140482782 May 14 12:54:52 PM PDT 24 May 14 12:54:54 PM PDT 24 16155785 ps
T1270 /workspace/coverage/cover_reg_top/38.uart_intr_test.2656584786 May 14 12:55:10 PM PDT 24 May 14 12:55:12 PM PDT 24 12155045 ps
T1271 /workspace/coverage/cover_reg_top/4.uart_intr_test.683096196 May 14 12:54:46 PM PDT 24 May 14 12:54:50 PM PDT 24 16495662 ps
T1272 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2327704388 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 136206239 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_tl_errors.4193646418 May 14 12:54:48 PM PDT 24 May 14 12:54:53 PM PDT 24 31022437 ps
T1274 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2171230113 May 14 12:54:26 PM PDT 24 May 14 12:54:32 PM PDT 24 41167409 ps
T52 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2229466688 May 14 12:54:43 PM PDT 24 May 14 12:54:46 PM PDT 24 54219478 ps
T1275 /workspace/coverage/cover_reg_top/20.uart_intr_test.2438642730 May 14 12:54:52 PM PDT 24 May 14 12:54:55 PM PDT 24 56614372 ps
T1276 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3435406091 May 14 12:54:33 PM PDT 24 May 14 12:54:37 PM PDT 24 27082684 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4134546340 May 14 12:54:30 PM PDT 24 May 14 12:54:36 PM PDT 24 51752503 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2457842229 May 14 12:54:29 PM PDT 24 May 14 12:54:35 PM PDT 24 282784241 ps
T1279 /workspace/coverage/cover_reg_top/42.uart_intr_test.3004980646 May 14 12:54:56 PM PDT 24 May 14 12:55:00 PM PDT 24 106073494 ps
T1280 /workspace/coverage/cover_reg_top/1.uart_csr_rw.93668055 May 14 12:54:29 PM PDT 24 May 14 12:54:34 PM PDT 24 14330671 ps
T1281 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.67670983 May 14 12:54:43 PM PDT 24 May 14 12:54:45 PM PDT 24 127754764 ps
T1282 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.113440244 May 14 12:54:40 PM PDT 24 May 14 12:54:42 PM PDT 24 129897635 ps
T1283 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2703714142 May 14 12:54:45 PM PDT 24 May 14 12:54:50 PM PDT 24 29556247 ps
T1284 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3453192644 May 14 12:54:53 PM PDT 24 May 14 12:54:56 PM PDT 24 25064755 ps
T1285 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1867524726 May 14 12:54:43 PM PDT 24 May 14 12:54:46 PM PDT 24 30647111 ps
T1286 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3784672822 May 14 12:54:42 PM PDT 24 May 14 12:54:44 PM PDT 24 47294341 ps
T1287 /workspace/coverage/cover_reg_top/9.uart_intr_test.1513516470 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 36796184 ps
T1288 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3460174647 May 14 12:54:30 PM PDT 24 May 14 12:54:37 PM PDT 24 245980391 ps
T1289 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.84596514 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 115938789 ps
T1290 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1292010479 May 14 12:54:24 PM PDT 24 May 14 12:54:30 PM PDT 24 15202737 ps
T1291 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.693566259 May 14 12:54:45 PM PDT 24 May 14 12:54:50 PM PDT 24 208526129 ps
T1292 /workspace/coverage/cover_reg_top/12.uart_csr_rw.977899364 May 14 12:54:43 PM PDT 24 May 14 12:54:46 PM PDT 24 35013920 ps
T1293 /workspace/coverage/cover_reg_top/24.uart_intr_test.3397451537 May 14 12:54:56 PM PDT 24 May 14 12:55:00 PM PDT 24 11484540 ps
T1294 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2706735623 May 14 12:54:45 PM PDT 24 May 14 12:54:50 PM PDT 24 333677662 ps
T1295 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.794651668 May 14 12:54:40 PM PDT 24 May 14 12:54:43 PM PDT 24 128721110 ps
T1296 /workspace/coverage/cover_reg_top/48.uart_intr_test.4169760561 May 14 12:54:46 PM PDT 24 May 14 12:54:50 PM PDT 24 13672372 ps
T1297 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2202331108 May 14 12:54:31 PM PDT 24 May 14 12:54:36 PM PDT 24 140685540 ps
T1298 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3609073262 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 201146227 ps
T1299 /workspace/coverage/cover_reg_top/17.uart_intr_test.1185826551 May 14 12:54:55 PM PDT 24 May 14 12:54:58 PM PDT 24 14962331 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.330629010 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 128304528 ps
T1301 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2695212723 May 14 12:54:45 PM PDT 24 May 14 12:54:49 PM PDT 24 23896415 ps
T1302 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1604306724 May 14 12:54:56 PM PDT 24 May 14 12:55:00 PM PDT 24 98192719 ps
T1303 /workspace/coverage/cover_reg_top/13.uart_intr_test.2396086829 May 14 12:54:44 PM PDT 24 May 14 12:54:47 PM PDT 24 18672589 ps
T1304 /workspace/coverage/cover_reg_top/6.uart_intr_test.808091311 May 14 12:54:37 PM PDT 24 May 14 12:54:39 PM PDT 24 13344263 ps
T85 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2093840457 May 14 12:54:55 PM PDT 24 May 14 12:54:59 PM PDT 24 630000417 ps
T1305 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4201375453 May 14 12:54:34 PM PDT 24 May 14 12:54:38 PM PDT 24 98468705 ps
T1306 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3327166882 May 14 12:54:45 PM PDT 24 May 14 12:54:49 PM PDT 24 27812499 ps
T1307 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2328832809 May 14 12:54:45 PM PDT 24 May 14 12:54:48 PM PDT 24 48953607 ps
T1308 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.661519955 May 14 12:54:46 PM PDT 24 May 14 12:54:49 PM PDT 24 34786990 ps
T53 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2055850430 May 14 12:54:45 PM PDT 24 May 14 12:54:48 PM PDT 24 74419143 ps
T1309 /workspace/coverage/cover_reg_top/28.uart_intr_test.479920554 May 14 12:55:04 PM PDT 24 May 14 12:55:06 PM PDT 24 146710637 ps
T1310 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1603514363 May 14 12:54:28 PM PDT 24 May 14 12:54:35 PM PDT 24 478304448 ps
T1311 /workspace/coverage/cover_reg_top/7.uart_intr_test.3195329042 May 14 12:54:36 PM PDT 24 May 14 12:54:38 PM PDT 24 17610878 ps
T1312 /workspace/coverage/cover_reg_top/2.uart_intr_test.84543489 May 14 12:54:45 PM PDT 24 May 14 12:54:49 PM PDT 24 15149957 ps
T86 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1489745034 May 14 12:54:42 PM PDT 24 May 14 12:54:44 PM PDT 24 90311814 ps
T1313 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.596719291 May 14 12:54:51 PM PDT 24 May 14 12:54:54 PM PDT 24 58338177 ps
T1314 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3616343702 May 14 12:54:41 PM PDT 24 May 14 12:54:43 PM PDT 24 26529243 ps
T1315 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1000218326 May 14 12:54:50 PM PDT 24 May 14 12:54:53 PM PDT 24 19353620 ps
T1316 /workspace/coverage/cover_reg_top/6.uart_csr_rw.4151396236 May 14 12:54:39 PM PDT 24 May 14 12:54:41 PM PDT 24 14239988 ps
T1317 /workspace/coverage/cover_reg_top/10.uart_intr_test.472052568 May 14 12:54:44 PM PDT 24 May 14 12:54:47 PM PDT 24 21741027 ps
T1318 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.656592409 May 14 12:54:56 PM PDT 24 May 14 12:55:01 PM PDT 24 167335672 ps
T1319 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.434361216 May 14 12:54:24 PM PDT 24 May 14 12:54:30 PM PDT 24 48832172 ps
T1320 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3955525118 May 14 12:54:43 PM PDT 24 May 14 12:54:47 PM PDT 24 88446221 ps

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1972614871
Short name T5
Test name
Test status
Simulation time 269732685534 ps
CPU time 660.3 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:11:46 PM PDT 24
Peak memory 225356 kb
Host smart-69a87dd7-5694-4714-ad6d-24b45f98f69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972614871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1972614871
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1686406566
Short name T12
Test name
Test status
Simulation time 329992486775 ps
CPU time 1110.6 seconds
Started May 14 01:00:56 PM PDT 24
Finished May 14 01:19:31 PM PDT 24
Peak memory 225448 kb
Host smart-d99b9dae-19c1-42d0-b48f-92e84284a4b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686406566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1686406566
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.3987827503
Short name T127
Test name
Test status
Simulation time 366873438974 ps
CPU time 305.53 seconds
Started May 14 12:57:39 PM PDT 24
Finished May 14 01:02:46 PM PDT 24
Peak memory 200352 kb
Host smart-8062262a-9bb4-49c8-bda3-0bb3e493c91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987827503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3987827503
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all.2094342804
Short name T280
Test name
Test status
Simulation time 255474089374 ps
CPU time 529.53 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 01:08:07 PM PDT 24
Peak memory 208972 kb
Host smart-ffa3d270-81b8-49e2-9719-703e0bfbb4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094342804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2094342804
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1071609462
Short name T13
Test name
Test status
Simulation time 95746638048 ps
CPU time 834.28 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 216904 kb
Host smart-ac7f20d1-863c-4dfb-94d2-fb92fc0aa6cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071609462 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1071609462
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1948459039
Short name T262
Test name
Test status
Simulation time 179491048425 ps
CPU time 833.75 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 01:13:07 PM PDT 24
Peak memory 200500 kb
Host smart-d2de3495-3b59-4b48-9cb7-ca964ec24af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948459039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1948459039
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_stress_all.1856858347
Short name T124
Test name
Test status
Simulation time 284316925301 ps
CPU time 120.21 seconds
Started May 14 12:59:44 PM PDT 24
Finished May 14 01:02:05 PM PDT 24
Peak memory 200436 kb
Host smart-19ab6740-ef54-45e1-8dc1-6b5dfee50867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856858347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1856858347
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1275289016
Short name T113
Test name
Test status
Simulation time 132888821926 ps
CPU time 124.71 seconds
Started May 14 12:59:28 PM PDT 24
Finished May 14 01:02:03 PM PDT 24
Peak memory 200424 kb
Host smart-19e8fc9c-c43d-4e57-9362-663419eb55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275289016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1275289016
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2935417992
Short name T156
Test name
Test status
Simulation time 124287583140 ps
CPU time 1358.71 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 01:19:54 PM PDT 24
Peak memory 216856 kb
Host smart-c34cd085-e284-4215-a8ed-46e740d6de08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935417992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2935417992
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1913162467
Short name T24
Test name
Test status
Simulation time 67938091 ps
CPU time 0.78 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 218752 kb
Host smart-60a5f76d-70ac-4eab-96e1-62371d85689b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913162467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1913162467
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/17.uart_alert_test.1697131695
Short name T357
Test name
Test status
Simulation time 126635044 ps
CPU time 0.54 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:57:56 PM PDT 24
Peak memory 195860 kb
Host smart-e2617464-3c62-4fa3-9ca3-a07dcd4be615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697131695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1697131695
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.250794641
Short name T117
Test name
Test status
Simulation time 154090813739 ps
CPU time 654.92 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:11:51 PM PDT 24
Peak memory 225320 kb
Host smart-d2fc06b0-f4e9-4af3-b9fb-8535a4712333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250794641 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.250794641
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.1128231353
Short name T325
Test name
Test status
Simulation time 64901811888 ps
CPU time 974.93 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 01:13:43 PM PDT 24
Peak memory 200640 kb
Host smart-8fcf7b07-10cd-4373-b6ed-4272ef0e17eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128231353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1128231353
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all.4080419852
Short name T114
Test name
Test status
Simulation time 467152530105 ps
CPU time 339.38 seconds
Started May 14 12:57:43 PM PDT 24
Finished May 14 01:03:23 PM PDT 24
Peak memory 208972 kb
Host smart-fafd117a-74ee-4570-98c7-0101ada6f4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080419852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4080419852
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2378018879
Short name T37
Test name
Test status
Simulation time 157723882669 ps
CPU time 171.57 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 01:01:09 PM PDT 24
Peak memory 200428 kb
Host smart-a0545473-66b0-4230-bbac-eb0bea7291f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378018879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2378018879
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_stress_all.2199200805
Short name T139
Test name
Test status
Simulation time 205919921740 ps
CPU time 422.03 seconds
Started May 14 12:59:52 PM PDT 24
Finished May 14 01:07:09 PM PDT 24
Peak memory 217132 kb
Host smart-cbb16c16-13fd-4a22-99a2-d66b44ce84c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199200805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2199200805
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1033470187
Short name T82
Test name
Test status
Simulation time 92889091 ps
CPU time 1.34 seconds
Started May 14 12:54:35 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 199124 kb
Host smart-615533a4-9220-4b0c-8119-069e1eec3cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033470187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1033470187
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/47.uart_stress_all.2676113813
Short name T129
Test name
Test status
Simulation time 323917854494 ps
CPU time 684.55 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:11:36 PM PDT 24
Peak memory 208960 kb
Host smart-bfe8770a-bede-4de8-96e6-6a8e83556a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676113813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2676113813
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.2238732159
Short name T18
Test name
Test status
Simulation time 76272890270 ps
CPU time 554.7 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 200496 kb
Host smart-5553cf06-86fd-4a43-a71e-47acb3a3d2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238732159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2238732159
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1840134087
Short name T155
Test name
Test status
Simulation time 110457125853 ps
CPU time 27.35 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:58:07 PM PDT 24
Peak memory 200428 kb
Host smart-cb2fcf04-e0a9-4880-8e71-27fb57ab697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840134087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1840134087
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4122307420
Short name T301
Test name
Test status
Simulation time 101503590031 ps
CPU time 159 seconds
Started May 14 12:56:50 PM PDT 24
Finished May 14 12:59:30 PM PDT 24
Peak memory 200440 kb
Host smart-431ae545-6b09-42ba-85d9-27859ce5f4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122307420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4122307420
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_stress_all.3551882950
Short name T311
Test name
Test status
Simulation time 441436109915 ps
CPU time 389.67 seconds
Started May 14 12:57:31 PM PDT 24
Finished May 14 01:04:02 PM PDT 24
Peak memory 216464 kb
Host smart-eb99d988-1834-491a-88da-3295e8dad645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551882950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3551882950
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3999936002
Short name T40
Test name
Test status
Simulation time 70229817554 ps
CPU time 787.69 seconds
Started May 14 12:59:21 PM PDT 24
Finished May 14 01:13:03 PM PDT 24
Peak memory 225412 kb
Host smart-f412c202-7dc2-4cf5-9621-702b0d7d3b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999936002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3999936002
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2954278020
Short name T58
Test name
Test status
Simulation time 385946021907 ps
CPU time 67.37 seconds
Started May 14 12:57:55 PM PDT 24
Finished May 14 12:59:05 PM PDT 24
Peak memory 200452 kb
Host smart-1fb98dad-6ead-4488-91b2-5d8b08dca93d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954278020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2954278020
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.815972441
Short name T68
Test name
Test status
Simulation time 67829584 ps
CPU time 0.61 seconds
Started May 14 12:54:25 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 195176 kb
Host smart-46c43f33-0f55-4d0d-be87-ba41955c538c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815972441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.815972441
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1458976690
Short name T51
Test name
Test status
Simulation time 49083569 ps
CPU time 0.65 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 195256 kb
Host smart-1ef1501c-28ec-4a3b-ada2-7d47462cb557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458976690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1458976690
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2978701360
Short name T243
Test name
Test status
Simulation time 191197261091 ps
CPU time 94.85 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:59:28 PM PDT 24
Peak memory 200456 kb
Host smart-b4a45e0e-f3cd-42bf-9e2f-327ef68f0b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978701360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2978701360
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.608311808
Short name T259
Test name
Test status
Simulation time 39654642393 ps
CPU time 69.26 seconds
Started May 14 01:01:26 PM PDT 24
Finished May 14 01:02:37 PM PDT 24
Peak memory 200460 kb
Host smart-448715aa-d23e-4354-83e3-68c5b97be8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608311808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.608311808
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2093840457
Short name T85
Test name
Test status
Simulation time 630000417 ps
CPU time 1.23 seconds
Started May 14 12:54:55 PM PDT 24
Finished May 14 12:54:59 PM PDT 24
Peak memory 199072 kb
Host smart-93befdb2-307e-44b0-b213-3f9dadb62209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093840457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2093840457
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1435142050
Short name T151
Test name
Test status
Simulation time 423697957832 ps
CPU time 1430.62 seconds
Started May 14 01:00:45 PM PDT 24
Finished May 14 01:24:39 PM PDT 24
Peak memory 233564 kb
Host smart-5169df0a-df6f-4b43-bb16-247274e30c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435142050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1435142050
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.851666973
Short name T177
Test name
Test status
Simulation time 101037473883 ps
CPU time 79.18 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:03:03 PM PDT 24
Peak memory 200452 kb
Host smart-b6f7443a-7068-4bd1-8211-4b4d9cf16d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851666973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.851666973
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.843370447
Short name T136
Test name
Test status
Simulation time 35492574596 ps
CPU time 43.3 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:54 PM PDT 24
Peak memory 200452 kb
Host smart-1a08d67e-0577-4a67-a329-e256bb05ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843370447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.843370447
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.109981476
Short name T141
Test name
Test status
Simulation time 46511543747 ps
CPU time 18.45 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 12:57:47 PM PDT 24
Peak memory 200360 kb
Host smart-20b85863-7f27-401c-907c-228661a91475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109981476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.109981476
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3980999071
Short name T121
Test name
Test status
Simulation time 41919785197 ps
CPU time 66.22 seconds
Started May 14 01:01:24 PM PDT 24
Finished May 14 01:02:32 PM PDT 24
Peak memory 200412 kb
Host smart-257964e0-944b-424c-8979-d905c86e5e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980999071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3980999071
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_full.97187620
Short name T735
Test name
Test status
Simulation time 27188225295 ps
CPU time 42.77 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:00:53 PM PDT 24
Peak memory 200452 kb
Host smart-bd70a7bd-b4f4-4ff6-a7a7-cbcf78120630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97187620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.97187620
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3419113821
Short name T226
Test name
Test status
Simulation time 81340409677 ps
CPU time 59.06 seconds
Started May 14 01:00:56 PM PDT 24
Finished May 14 01:01:59 PM PDT 24
Peak memory 200440 kb
Host smart-6b667471-ae5f-43f2-8948-163ceaff8fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419113821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3419113821
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2776414795
Short name T181
Test name
Test status
Simulation time 28613655991 ps
CPU time 22.02 seconds
Started May 14 12:57:34 PM PDT 24
Finished May 14 12:57:58 PM PDT 24
Peak memory 199968 kb
Host smart-ed9c83bd-e23c-4df6-9380-eb69067e5ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776414795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2776414795
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3381293796
Short name T78
Test name
Test status
Simulation time 169424011718 ps
CPU time 872.28 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 01:12:14 PM PDT 24
Peak memory 200424 kb
Host smart-aa4e461e-7f68-429e-ba33-2d3ac510bbb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381293796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3381293796
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.555581005
Short name T180
Test name
Test status
Simulation time 22695412356 ps
CPU time 39.39 seconds
Started May 14 01:01:11 PM PDT 24
Finished May 14 01:01:53 PM PDT 24
Peak memory 200452 kb
Host smart-1f04e997-4935-4e14-aed7-6e4e3486dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555581005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.555581005
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3225535912
Short name T162
Test name
Test status
Simulation time 162225010244 ps
CPU time 667.18 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:11:52 PM PDT 24
Peak memory 216956 kb
Host smart-62d0ce19-08d3-4556-81b0-9b7c2910222f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225535912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3225535912
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1639319273
Short name T122
Test name
Test status
Simulation time 147886703039 ps
CPU time 63.69 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:58:38 PM PDT 24
Peak memory 200516 kb
Host smart-13165060-5909-4791-b4e6-e45f03063611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639319273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1639319273
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2800046407
Short name T186
Test name
Test status
Simulation time 208606764115 ps
CPU time 271.15 seconds
Started May 14 01:01:24 PM PDT 24
Finished May 14 01:05:57 PM PDT 24
Peak memory 200476 kb
Host smart-bebe7a8a-9ba2-44bb-b48f-5e2e1ef95e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800046407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2800046407
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_perf.661468769
Short name T289
Test name
Test status
Simulation time 13294423673 ps
CPU time 585.76 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:09:38 PM PDT 24
Peak memory 200304 kb
Host smart-5070cb1b-51e9-41c6-b3de-1f41b42a1a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661468769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.661468769
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1409160741
Short name T173
Test name
Test status
Simulation time 275866925782 ps
CPU time 47.84 seconds
Started May 14 01:01:16 PM PDT 24
Finished May 14 01:02:06 PM PDT 24
Peak memory 200440 kb
Host smart-eac8509b-4928-4a3b-9995-874b4a2a26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409160741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1409160741
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1767245780
Short name T999
Test name
Test status
Simulation time 9525681410 ps
CPU time 20.58 seconds
Started May 14 01:01:17 PM PDT 24
Finished May 14 01:01:39 PM PDT 24
Peak memory 200384 kb
Host smart-0af5b696-c70b-494d-8168-9f46dee60640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767245780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1767245780
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.988816632
Short name T216
Test name
Test status
Simulation time 120815689296 ps
CPU time 167.53 seconds
Started May 14 01:01:32 PM PDT 24
Finished May 14 01:04:21 PM PDT 24
Peak memory 200460 kb
Host smart-65c7447a-61da-4085-9be2-f287baa210d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988816632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.988816632
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.1760115965
Short name T448
Test name
Test status
Simulation time 291987128244 ps
CPU time 561.15 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:09:30 PM PDT 24
Peak memory 200448 kb
Host smart-df643136-7d69-4398-a4e6-82291e31f313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760115965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1760115965
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2367898927
Short name T102
Test name
Test status
Simulation time 166876026064 ps
CPU time 917.63 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:15:26 PM PDT 24
Peak memory 225420 kb
Host smart-0424ffaa-c2e0-4270-a16b-ebe8626c47d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367898927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2367898927
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.876156030
Short name T99
Test name
Test status
Simulation time 30236214031 ps
CPU time 46.12 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:58:26 PM PDT 24
Peak memory 200512 kb
Host smart-cef7a829-4b0f-4a94-b893-dc824353c6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876156030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.876156030
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1299459490
Short name T233
Test name
Test status
Simulation time 71082651679 ps
CPU time 644.57 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 01:08:24 PM PDT 24
Peak memory 216948 kb
Host smart-1ba02164-3129-4deb-9141-f8e5cec78dd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299459490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1299459490
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3293925278
Short name T197
Test name
Test status
Simulation time 181641059882 ps
CPU time 30.81 seconds
Started May 14 01:01:13 PM PDT 24
Finished May 14 01:01:46 PM PDT 24
Peak memory 200252 kb
Host smart-27cc7a7d-8776-4fd1-8ee7-e5087eb1a699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293925278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3293925278
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1072449710
Short name T773
Test name
Test status
Simulation time 436138642132 ps
CPU time 602.03 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 217156 kb
Host smart-e13fcac0-294d-4cdf-921d-7ceb197b9e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072449710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1072449710
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1823990219
Short name T346
Test name
Test status
Simulation time 99453945821 ps
CPU time 88.08 seconds
Started May 14 01:01:16 PM PDT 24
Finished May 14 01:02:46 PM PDT 24
Peak memory 200440 kb
Host smart-6a836277-526c-4ea0-abc7-d385b990938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823990219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1823990219
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.974360175
Short name T208
Test name
Test status
Simulation time 166348541141 ps
CPU time 39.79 seconds
Started May 14 01:01:35 PM PDT 24
Finished May 14 01:02:17 PM PDT 24
Peak memory 200516 kb
Host smart-fb1b66c8-d829-423c-88ae-13865e3ec44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974360175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.974360175
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1371991780
Short name T166
Test name
Test status
Simulation time 50551105499 ps
CPU time 22.79 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 12:58:43 PM PDT 24
Peak memory 200368 kb
Host smart-ad70a8c5-6dfa-4f16-a3bd-72080646b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371991780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1371991780
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2571225558
Short name T169
Test name
Test status
Simulation time 212908504929 ps
CPU time 164.61 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:04:28 PM PDT 24
Peak memory 200448 kb
Host smart-034b4eff-608b-4630-b821-c4bd53a5511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571225558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2571225558
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1459408444
Short name T677
Test name
Test status
Simulation time 72882137766 ps
CPU time 601.19 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:10:39 PM PDT 24
Peak memory 216120 kb
Host smart-62af4b93-805c-4899-b059-609adaa26b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459408444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1459408444
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2856828740
Short name T234
Test name
Test status
Simulation time 188386684723 ps
CPU time 70.9 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:01:56 PM PDT 24
Peak memory 200384 kb
Host smart-1dd32a9e-582e-4cef-b4d1-63c19d1d54fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856828740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2856828740
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2589177394
Short name T213
Test name
Test status
Simulation time 771454495281 ps
CPU time 568.39 seconds
Started May 14 01:00:53 PM PDT 24
Finished May 14 01:10:26 PM PDT 24
Peak memory 216952 kb
Host smart-13bb5c42-b0cd-41b1-8d5d-56d7da884308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589177394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2589177394
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1489745034
Short name T86
Test name
Test status
Simulation time 90311814 ps
CPU time 1.27 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 198932 kb
Host smart-b00e341f-874c-4b05-ab2f-4eb5c2875d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489745034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1489745034
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2495979803
Short name T546
Test name
Test status
Simulation time 30856006337 ps
CPU time 59.96 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:57:45 PM PDT 24
Peak memory 200444 kb
Host smart-9774a2fd-f9c7-48da-a990-11e42f56ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495979803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2495979803
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3218891125
Short name T389
Test name
Test status
Simulation time 194452013223 ps
CPU time 56.52 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 12:58:25 PM PDT 24
Peak memory 200396 kb
Host smart-c14eda56-8979-4f49-acbe-28124d34da07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218891125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3218891125
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2678575457
Short name T237
Test name
Test status
Simulation time 109783394926 ps
CPU time 39.94 seconds
Started May 14 01:00:55 PM PDT 24
Finished May 14 01:01:39 PM PDT 24
Peak memory 200448 kb
Host smart-65a5d745-9cd9-4248-987f-b38c55c268db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678575457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2678575457
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2819038361
Short name T909
Test name
Test status
Simulation time 99224333802 ps
CPU time 205.55 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:04:21 PM PDT 24
Peak memory 200400 kb
Host smart-241fcd15-510a-41ec-9340-1729ce3a9792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819038361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2819038361
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2246243063
Short name T61
Test name
Test status
Simulation time 84184078093 ps
CPU time 16.51 seconds
Started May 14 01:00:55 PM PDT 24
Finished May 14 01:01:16 PM PDT 24
Peak memory 200500 kb
Host smart-b03c1b77-44f6-43bb-95ff-6084f4758586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246243063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2246243063
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.7620973
Short name T219
Test name
Test status
Simulation time 9086329734 ps
CPU time 13.99 seconds
Started May 14 01:01:04 PM PDT 24
Finished May 14 01:01:21 PM PDT 24
Peak memory 200044 kb
Host smart-3c894926-9091-4568-a849-967035c275b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7620973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.7620973
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1558385414
Short name T149
Test name
Test status
Simulation time 63921690697 ps
CPU time 24.08 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:35 PM PDT 24
Peak memory 200204 kb
Host smart-16065cfd-fc2d-4892-972f-846c3b6aaa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558385414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1558385414
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1170417648
Short name T160
Test name
Test status
Simulation time 12988560994 ps
CPU time 11.68 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:01:33 PM PDT 24
Peak memory 200276 kb
Host smart-2f8b900d-a92e-4e60-b038-fa61259c00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170417648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1170417648
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1996733531
Short name T235
Test name
Test status
Simulation time 52705172472 ps
CPU time 23.61 seconds
Started May 14 01:01:16 PM PDT 24
Finished May 14 01:01:42 PM PDT 24
Peak memory 200484 kb
Host smart-db25af6b-17ee-4a54-86fb-698a91b28fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996733531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1996733531
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3342680804
Short name T217
Test name
Test status
Simulation time 14154262315 ps
CPU time 44.59 seconds
Started May 14 01:01:16 PM PDT 24
Finished May 14 01:02:03 PM PDT 24
Peak memory 200536 kb
Host smart-daac8468-fce6-4f72-9932-490818f39af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342680804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3342680804
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.918724395
Short name T225
Test name
Test status
Simulation time 53911864820 ps
CPU time 41.41 seconds
Started May 14 01:01:24 PM PDT 24
Finished May 14 01:02:07 PM PDT 24
Peak memory 200500 kb
Host smart-7064719c-6a97-46fb-a896-4aabf2dad922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918724395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.918724395
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.548554982
Short name T145
Test name
Test status
Simulation time 46506118026 ps
CPU time 42.47 seconds
Started May 14 01:01:27 PM PDT 24
Finished May 14 01:02:11 PM PDT 24
Peak memory 200428 kb
Host smart-a26ce39f-bdca-402f-bc45-0070a4b0c608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548554982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.548554982
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4160125226
Short name T211
Test name
Test status
Simulation time 148690405388 ps
CPU time 262.69 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 200456 kb
Host smart-cd519f82-4f34-4d9c-946f-2be684643c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160125226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4160125226
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3179203632
Short name T239
Test name
Test status
Simulation time 8917294488 ps
CPU time 16.54 seconds
Started May 14 12:59:21 PM PDT 24
Finished May 14 01:00:12 PM PDT 24
Peak memory 200276 kb
Host smart-48c92781-74ac-4762-a301-4f002513a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179203632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3179203632
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2191556794
Short name T222
Test name
Test status
Simulation time 194811789546 ps
CPU time 636.49 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:10:45 PM PDT 24
Peak memory 217188 kb
Host smart-1d9efdc3-7c25-4c5d-993f-c7d6877fc9a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191556794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2191556794
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3279095912
Short name T138
Test name
Test status
Simulation time 49698500947 ps
CPU time 84.84 seconds
Started May 14 01:00:17 PM PDT 24
Finished May 14 01:01:45 PM PDT 24
Peak memory 200496 kb
Host smart-e73566a4-59f8-4cbd-af04-1a3032e6ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279095912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3279095912
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1815548942
Short name T142
Test name
Test status
Simulation time 32857926794 ps
CPU time 71.81 seconds
Started May 14 01:00:32 PM PDT 24
Finished May 14 01:01:46 PM PDT 24
Peak memory 200516 kb
Host smart-678a7bbd-d6b6-4f98-b1f2-8276e8b50c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815548942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1815548942
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3435406091
Short name T1276
Test name
Test status
Simulation time 27082684 ps
CPU time 0.65 seconds
Started May 14 12:54:33 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 195476 kb
Host smart-4da714cd-a865-4381-bfa4-2f55fbfa8c00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435406091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3435406091
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1603514363
Short name T1310
Test name
Test status
Simulation time 478304448 ps
CPU time 2.23 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 197456 kb
Host smart-daaacb62-7250-4b37-a06b-7e5ed4d1c57a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603514363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1603514363
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1292010479
Short name T1290
Test name
Test status
Simulation time 15202737 ps
CPU time 0.62 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 195248 kb
Host smart-3c300f46-8edd-4d3e-a222-d332c6a8559d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292010479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1292010479
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2714028703
Short name T1196
Test name
Test status
Simulation time 23758647 ps
CPU time 0.79 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 199612 kb
Host smart-c4438e48-1198-414b-a763-462996a0e19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714028703 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2714028703
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.143979776
Short name T1239
Test name
Test status
Simulation time 17553315 ps
CPU time 0.58 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:33 PM PDT 24
Peak memory 194224 kb
Host smart-b92bb1ce-a200-4a4e-a333-fdf74a8cf30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143979776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.143979776
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.688057907
Short name T1235
Test name
Test status
Simulation time 112190366 ps
CPU time 0.6 seconds
Started May 14 12:54:25 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 195252 kb
Host smart-e3700b09-fc95-4b68-8e93-59cc0daf2c74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688057907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.688057907
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1776401766
Short name T1256
Test name
Test status
Simulation time 36630612 ps
CPU time 1.93 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 199840 kb
Host smart-1c8cbe7c-c39f-4ae6-8a84-9eefe223e0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776401766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1776401766
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2523379203
Short name T81
Test name
Test status
Simulation time 42016281 ps
CPU time 0.93 seconds
Started May 14 12:54:25 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 198852 kb
Host smart-fd88f393-5468-4ab0-a4d4-2885f32e7a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523379203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2523379203
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3616343702
Short name T1314
Test name
Test status
Simulation time 26529243 ps
CPU time 0.76 seconds
Started May 14 12:54:41 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 196148 kb
Host smart-5faabefb-28b4-41f0-bc8e-ce0298f38fd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616343702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3616343702
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.408373665
Short name T1207
Test name
Test status
Simulation time 218928508 ps
CPU time 2.26 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 197736 kb
Host smart-fdf65009-0086-4a07-ba43-cee6a550317e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408373665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.408373665
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1816379055
Short name T1206
Test name
Test status
Simulation time 15442062 ps
CPU time 0.58 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:32 PM PDT 24
Peak memory 195208 kb
Host smart-a3c2a1ed-df6a-4aa9-ba51-0b339b16d8fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816379055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1816379055
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2647824393
Short name T1209
Test name
Test status
Simulation time 37662049 ps
CPU time 0.7 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 198044 kb
Host smart-a026359d-72bc-4c27-bba3-f8b051969d50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647824393 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2647824393
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.93668055
Short name T1280
Test name
Test status
Simulation time 14330671 ps
CPU time 0.58 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 195208 kb
Host smart-b68cb665-e87d-4d3a-9866-8e9ad82b67a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93668055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.93668055
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1348355767
Short name T1188
Test name
Test status
Simulation time 12921493 ps
CPU time 0.62 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 194252 kb
Host smart-df06fc0b-a0fc-43a6-ab38-6f0070184fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348355767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1348355767
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2010436439
Short name T1261
Test name
Test status
Simulation time 98665879 ps
CPU time 0.78 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 196956 kb
Host smart-dd7ea902-9e54-4e81-885c-f770d149a09f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010436439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2010436439
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2171230113
Short name T1274
Test name
Test status
Simulation time 41167409 ps
CPU time 1.14 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:32 PM PDT 24
Peak memory 199628 kb
Host smart-369603a2-f9fe-4d83-805a-0f19dce62bad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171230113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2171230113
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1086733357
Short name T89
Test name
Test status
Simulation time 149112661 ps
CPU time 0.88 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:32 PM PDT 24
Peak memory 198740 kb
Host smart-02d1635b-87ac-4284-a1e0-c338ba7d398a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086733357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1086733357
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1007469267
Short name T1257
Test name
Test status
Simulation time 20652521 ps
CPU time 0.87 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 199640 kb
Host smart-f7cd9861-b911-42f3-94ef-03762779aa6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007469267 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1007469267
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3886047291
Short name T75
Test name
Test status
Simulation time 44391126 ps
CPU time 0.57 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 195168 kb
Host smart-f57266bd-e3c7-4a5b-9c92-d6dcc85da564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886047291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3886047291
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.472052568
Short name T1317
Test name
Test status
Simulation time 21741027 ps
CPU time 0.55 seconds
Started May 14 12:54:44 PM PDT 24
Finished May 14 12:54:47 PM PDT 24
Peak memory 194172 kb
Host smart-eade44ad-5d1b-462b-bce9-aa779a6aed66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472052568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.472052568
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2327704388
Short name T1272
Test name
Test status
Simulation time 136206239 ps
CPU time 0.71 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 197432 kb
Host smart-7ccbb547-5b59-4392-aecf-f08eda2c4080
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327704388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2327704388
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3955525118
Short name T1320
Test name
Test status
Simulation time 88446221 ps
CPU time 1.88 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:47 PM PDT 24
Peak memory 199856 kb
Host smart-cffc2a8a-fda6-4816-b65e-5a05ac569502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955525118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3955525118
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.794651668
Short name T1295
Test name
Test status
Simulation time 128721110 ps
CPU time 1.27 seconds
Started May 14 12:54:40 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 199068 kb
Host smart-3e03230e-cf6e-413e-8ece-2fa2be4a207e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794651668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.794651668
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4039293791
Short name T1229
Test name
Test status
Simulation time 126490089 ps
CPU time 0.9 seconds
Started May 14 12:54:53 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 199724 kb
Host smart-e1d85334-a89a-44a5-b809-d6130c0385fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039293791 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4039293791
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3308832079
Short name T1195
Test name
Test status
Simulation time 46022956 ps
CPU time 0.59 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 195216 kb
Host smart-da9b4218-2288-4876-8f5a-f35412d11899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308832079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3308832079
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3412631511
Short name T1260
Test name
Test status
Simulation time 14541639 ps
CPU time 0.57 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194200 kb
Host smart-881ab1fd-40a2-487a-bd08-53ff1065fb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412631511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3412631511
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.416177868
Short name T1248
Test name
Test status
Simulation time 14764197 ps
CPU time 0.69 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 196672 kb
Host smart-f62d0a8e-0054-440b-b720-030a2950301f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416177868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.416177868
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2844576479
Short name T1245
Test name
Test status
Simulation time 22654240 ps
CPU time 1.22 seconds
Started May 14 12:54:37 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 199868 kb
Host smart-12c72580-bc4d-4028-81b3-ce1fd733095b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844576479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2844576479
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.656592409
Short name T1318
Test name
Test status
Simulation time 167335672 ps
CPU time 0.93 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:01 PM PDT 24
Peak memory 198648 kb
Host smart-88f99a4e-0abb-47c5-ac2a-ce835de63897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656592409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.656592409
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.596719291
Short name T1313
Test name
Test status
Simulation time 58338177 ps
CPU time 0.85 seconds
Started May 14 12:54:51 PM PDT 24
Finished May 14 12:54:54 PM PDT 24
Peak memory 199664 kb
Host smart-e8e89e71-8a2d-446f-8ce3-96eae6b71571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596719291 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.596719291
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.977899364
Short name T1292
Test name
Test status
Simulation time 35013920 ps
CPU time 0.61 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:46 PM PDT 24
Peak memory 195248 kb
Host smart-86927bef-0d0e-4166-b338-2810f164ed06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977899364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.977899364
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2361325244
Short name T1226
Test name
Test status
Simulation time 231670506 ps
CPU time 0.58 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:00 PM PDT 24
Peak memory 193960 kb
Host smart-95798401-0874-4ddf-bc14-e082ea1e006d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361325244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2361325244
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2511209252
Short name T1244
Test name
Test status
Simulation time 16005548 ps
CPU time 0.68 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 195472 kb
Host smart-a8047285-2f7e-4586-94c9-7218bbdeda35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511209252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2511209252
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1605855382
Short name T1218
Test name
Test status
Simulation time 266804771 ps
CPU time 1.45 seconds
Started May 14 12:54:44 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 199880 kb
Host smart-5eec54a7-b309-4598-8e80-0439fee5eac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605855382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1605855382
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.330629010
Short name T1300
Test name
Test status
Simulation time 128304528 ps
CPU time 0.76 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 198912 kb
Host smart-c44e2f6f-a4f2-4731-976b-e007590b61ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330629010 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.330629010
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3453192644
Short name T1284
Test name
Test status
Simulation time 25064755 ps
CPU time 0.61 seconds
Started May 14 12:54:53 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 195304 kb
Host smart-6026b26a-548f-4465-b9a6-5ac3f6063772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453192644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3453192644
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2396086829
Short name T1303
Test name
Test status
Simulation time 18672589 ps
CPU time 0.54 seconds
Started May 14 12:54:44 PM PDT 24
Finished May 14 12:54:47 PM PDT 24
Peak memory 194168 kb
Host smart-a6062579-998f-45c1-ad08-d122ef022167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396086829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2396086829
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1604306724
Short name T1302
Test name
Test status
Simulation time 98192719 ps
CPU time 0.73 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:00 PM PDT 24
Peak memory 197564 kb
Host smart-2d62273b-7bdc-4b9d-8309-75db9059faf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604306724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1604306724
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3710871888
Short name T1254
Test name
Test status
Simulation time 130309542 ps
CPU time 1.79 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:01 PM PDT 24
Peak memory 199776 kb
Host smart-2d6312b0-73dc-4208-9ad6-79fe0d82e48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710871888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3710871888
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4083394539
Short name T1264
Test name
Test status
Simulation time 77454256 ps
CPU time 1.4 seconds
Started May 14 12:54:44 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 198904 kb
Host smart-4abf3aca-00e6-4322-8d66-e7c8e6788e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083394539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4083394539
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3327166882
Short name T1306
Test name
Test status
Simulation time 27812499 ps
CPU time 1.28 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 199940 kb
Host smart-d72df6e8-d27b-491b-b02f-f90ec1edec62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327166882 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3327166882
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.848071287
Short name T76
Test name
Test status
Simulation time 22987401 ps
CPU time 0.6 seconds
Started May 14 12:54:49 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 195308 kb
Host smart-a7fb66dd-aa00-48cf-a42f-0498c932a86b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848071287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.848071287
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.348100325
Short name T1216
Test name
Test status
Simulation time 30504985 ps
CPU time 0.57 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 194204 kb
Host smart-7fd29a33-5bee-4fc0-b1ca-cde1501f0f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348100325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.348100325
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1113571728
Short name T69
Test name
Test status
Simulation time 59926366 ps
CPU time 0.65 seconds
Started May 14 12:54:47 PM PDT 24
Finished May 14 12:54:51 PM PDT 24
Peak memory 195668 kb
Host smart-aebf47f7-b1ff-4dd9-b33d-5cf83a322789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113571728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1113571728
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2703714142
Short name T1283
Test name
Test status
Simulation time 29556247 ps
CPU time 1.31 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 199864 kb
Host smart-ed6b4ef3-f644-48fd-918b-ba53f73af943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703714142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2703714142
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2617566978
Short name T1193
Test name
Test status
Simulation time 57428350 ps
CPU time 0.64 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:54 PM PDT 24
Peak memory 197740 kb
Host smart-538c9e4e-707c-42ca-a177-07dc55c83af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617566978 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2617566978
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1000218326
Short name T1315
Test name
Test status
Simulation time 19353620 ps
CPU time 0.57 seconds
Started May 14 12:54:50 PM PDT 24
Finished May 14 12:54:53 PM PDT 24
Peak memory 195252 kb
Host smart-90b339cf-a8b9-497d-aff1-77bf24ea8aec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000218326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1000218326
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2603596145
Short name T1203
Test name
Test status
Simulation time 34018408 ps
CPU time 0.55 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 194208 kb
Host smart-df5cf263-2642-4eb8-93e8-b777c9e17499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603596145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2603596145
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.462412300
Short name T74
Test name
Test status
Simulation time 45295534 ps
CPU time 0.63 seconds
Started May 14 12:55:02 PM PDT 24
Finished May 14 12:55:05 PM PDT 24
Peak memory 194496 kb
Host smart-8d9011b4-8115-436f-8e68-0e5cc6a3797d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462412300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.462412300
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4013781729
Short name T1208
Test name
Test status
Simulation time 37394097 ps
CPU time 1.07 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:00 PM PDT 24
Peak memory 199696 kb
Host smart-28e40211-a186-4889-9488-8846ef249d07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013781729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4013781729
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.693566259
Short name T1291
Test name
Test status
Simulation time 208526129 ps
CPU time 0.96 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 198912 kb
Host smart-460baebf-630d-4f87-aff2-403aeb8295f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693566259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.693566259
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.661519955
Short name T1308
Test name
Test status
Simulation time 34786990 ps
CPU time 0.66 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 197380 kb
Host smart-7c6dcc45-901c-4a57-bb89-589d3fab01d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661519955 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.661519955
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2813667975
Short name T1240
Test name
Test status
Simulation time 12602633 ps
CPU time 0.56 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 194252 kb
Host smart-7db92e85-e838-49b7-a3a2-72859c1d1973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813667975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2813667975
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.113440244
Short name T1282
Test name
Test status
Simulation time 129897635 ps
CPU time 0.61 seconds
Started May 14 12:54:40 PM PDT 24
Finished May 14 12:54:42 PM PDT 24
Peak memory 195464 kb
Host smart-894f7003-4101-4ed7-bec8-baaffdc423db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113440244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.113440244
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4041568536
Short name T1258
Test name
Test status
Simulation time 31534835 ps
CPU time 1.48 seconds
Started May 14 12:54:47 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 199824 kb
Host smart-78a1227d-2176-4441-aeb5-803609a364f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041568536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4041568536
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3618968237
Short name T1259
Test name
Test status
Simulation time 92729968 ps
CPU time 0.92 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 198736 kb
Host smart-7223969e-a847-4d83-9326-8bde575f1a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618968237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3618968237
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.84596514
Short name T1289
Test name
Test status
Simulation time 115938789 ps
CPU time 0.88 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 199652 kb
Host smart-6d1d7abc-909a-4712-8068-507cf2a863ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84596514 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.84596514
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.902172000
Short name T50
Test name
Test status
Simulation time 33497154 ps
CPU time 0.63 seconds
Started May 14 12:54:54 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 195248 kb
Host smart-6d021ddc-d953-485a-9004-281ad69dc07d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902172000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.902172000
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1185826551
Short name T1299
Test name
Test status
Simulation time 14962331 ps
CPU time 0.57 seconds
Started May 14 12:54:55 PM PDT 24
Finished May 14 12:54:58 PM PDT 24
Peak memory 194268 kb
Host smart-f0a39647-82a9-41bd-89fd-ff93b384fa0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185826551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1185826551
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2328832809
Short name T1307
Test name
Test status
Simulation time 48953607 ps
CPU time 0.63 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 195444 kb
Host smart-dc38d6a0-0dfe-4cc1-ae67-fd452c1c25a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328832809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2328832809
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.574976237
Short name T1191
Test name
Test status
Simulation time 67097295 ps
CPU time 2.41 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 199884 kb
Host smart-45b868e9-4e79-450c-ba44-c7eee552b7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574976237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.574976237
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3125704670
Short name T241
Test name
Test status
Simulation time 177777386 ps
CPU time 1.22 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 199128 kb
Host smart-bcd3cc1e-3734-4812-b416-a5d7ecf26d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125704670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3125704670
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1126078462
Short name T1187
Test name
Test status
Simulation time 40897217 ps
CPU time 1.23 seconds
Started May 14 12:54:54 PM PDT 24
Finished May 14 12:54:58 PM PDT 24
Peak memory 199936 kb
Host smart-1a60fa6e-4988-491d-a171-5a9fb51e1711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126078462 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1126078462
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2646121304
Short name T1249
Test name
Test status
Simulation time 95989557 ps
CPU time 0.58 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 195236 kb
Host smart-89170925-4600-47b7-9513-c8539f1b2b3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646121304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2646121304
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2503670031
Short name T1201
Test name
Test status
Simulation time 14050747 ps
CPU time 0.56 seconds
Started May 14 12:54:53 PM PDT 24
Finished May 14 12:54:55 PM PDT 24
Peak memory 194180 kb
Host smart-e97003fc-0d43-4ded-a3dc-c31b57ada15e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503670031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2503670031
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1867524726
Short name T1285
Test name
Test status
Simulation time 30647111 ps
CPU time 0.79 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:46 PM PDT 24
Peak memory 197552 kb
Host smart-fb9c743a-2d10-4a02-a430-ac8e0b55c6ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867524726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1867524726
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.4193646418
Short name T1273
Test name
Test status
Simulation time 31022437 ps
CPU time 1.51 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:53 PM PDT 24
Peak memory 199864 kb
Host smart-b6c4eb96-e879-46cb-9031-64611235c0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193646418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4193646418
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2065881987
Short name T80
Test name
Test status
Simulation time 73613037 ps
CPU time 0.91 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:01 PM PDT 24
Peak memory 198492 kb
Host smart-49c185aa-af03-4da4-8513-bc9ba47a158d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065881987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2065881987
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.917184879
Short name T1217
Test name
Test status
Simulation time 144252570 ps
CPU time 0.92 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 199616 kb
Host smart-d544ce3f-b0b0-47ad-af64-c57aa6f77ac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917184879 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.917184879
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2695212723
Short name T1301
Test name
Test status
Simulation time 23896415 ps
CPU time 0.6 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 195304 kb
Host smart-54d7e755-42ba-4c3e-b1b9-60e70db80a3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695212723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2695212723
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3145794116
Short name T1232
Test name
Test status
Simulation time 105688045 ps
CPU time 0.55 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 194184 kb
Host smart-50d2a9d8-add6-445b-8559-794fb8649f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145794116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3145794116
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2140886049
Short name T70
Test name
Test status
Simulation time 54415281 ps
CPU time 0.7 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 196740 kb
Host smart-f419558f-3af2-4d7d-9fb5-35d2a8f981d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140886049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2140886049
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.970826939
Short name T1220
Test name
Test status
Simulation time 529960676 ps
CPU time 1.81 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 199836 kb
Host smart-0d30a86a-6063-408b-89b2-9db5236eed56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970826939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.970826939
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.852561188
Short name T88
Test name
Test status
Simulation time 45774801 ps
CPU time 0.9 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 198392 kb
Host smart-03e38771-b148-4fea-a8af-74c128bbd909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852561188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.852561188
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2325668907
Short name T1224
Test name
Test status
Simulation time 75216731 ps
CPU time 0.72 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 196112 kb
Host smart-f14d7ca9-4b55-4f5b-b973-e2db7bf57d73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325668907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2325668907
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1000600124
Short name T1215
Test name
Test status
Simulation time 582773236 ps
CPU time 2.14 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 197420 kb
Host smart-7640f737-f400-4e9c-ae8e-c9f1fc3b71c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000600124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1000600124
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3351193817
Short name T1184
Test name
Test status
Simulation time 14596386 ps
CPU time 0.57 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 195212 kb
Host smart-a50e7ecc-fc2a-4c2e-8242-bdc68dfc02cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351193817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3351193817
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2601937066
Short name T1225
Test name
Test status
Simulation time 83509315 ps
CPU time 0.75 seconds
Started May 14 12:54:51 PM PDT 24
Finished May 14 12:54:54 PM PDT 24
Peak memory 198136 kb
Host smart-6ac2c6fa-0318-4da3-80a2-7b5d7fae59a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601937066 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2601937066
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2345594833
Short name T72
Test name
Test status
Simulation time 17282584 ps
CPU time 0.59 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:33 PM PDT 24
Peak memory 195172 kb
Host smart-3662326b-2c08-4980-8569-048f07cb8de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345594833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2345594833
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.84543489
Short name T1312
Test name
Test status
Simulation time 15149957 ps
CPU time 0.59 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 194160 kb
Host smart-56fd72d5-4c8f-4710-acdc-d4f57fa3a359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84543489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.84543489
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2823990982
Short name T1238
Test name
Test status
Simulation time 69270017 ps
CPU time 0.65 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 195836 kb
Host smart-7f770f57-a614-4eb1-95de-eada12ffddf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823990982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2823990982
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2904076471
Short name T1228
Test name
Test status
Simulation time 193629200 ps
CPU time 2.01 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 199840 kb
Host smart-154edbee-dbaf-4518-bc12-425762e3a377
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904076471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2904076471
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2943703717
Short name T242
Test name
Test status
Simulation time 166176981 ps
CPU time 0.9 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 198548 kb
Host smart-9c12531b-ee97-4af2-832e-0799e3a47cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943703717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2943703717
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2438642730
Short name T1275
Test name
Test status
Simulation time 56614372 ps
CPU time 0.54 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:55 PM PDT 24
Peak memory 194176 kb
Host smart-3b3beaa8-f5ed-41a0-a83c-2bad72fd655a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438642730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2438642730
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3807353
Short name T1267
Test name
Test status
Simulation time 66194222 ps
CPU time 0.56 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194156 kb
Host smart-8f811027-9eaa-49f9-8235-b659426018f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3807353
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.4003030843
Short name T1214
Test name
Test status
Simulation time 25553408 ps
CPU time 0.56 seconds
Started May 14 12:54:55 PM PDT 24
Finished May 14 12:54:59 PM PDT 24
Peak memory 194124 kb
Host smart-c72333db-24bd-4fec-ba02-b3eb959ebe0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003030843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.4003030843
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3405062412
Short name T1265
Test name
Test status
Simulation time 19700474 ps
CPU time 0.55 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194188 kb
Host smart-48609a4e-2b89-44c2-b07d-13c80085608b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405062412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3405062412
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3397451537
Short name T1293
Test name
Test status
Simulation time 11484540 ps
CPU time 0.58 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:00 PM PDT 24
Peak memory 194240 kb
Host smart-2f4412a6-27e1-4d93-9745-0035c36c6584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397451537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3397451537
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.262156426
Short name T1197
Test name
Test status
Simulation time 30739712 ps
CPU time 0.55 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 194184 kb
Host smart-601e0464-c444-498b-bd8c-e6a03000d427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262156426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.262156426
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.858215362
Short name T1192
Test name
Test status
Simulation time 15110307 ps
CPU time 0.62 seconds
Started May 14 12:55:00 PM PDT 24
Finished May 14 12:55:03 PM PDT 24
Peak memory 194248 kb
Host smart-adf2b115-4ba7-4fbf-8732-2f141a8003a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858215362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.858215362
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3620716571
Short name T1221
Test name
Test status
Simulation time 42517096 ps
CPU time 0.55 seconds
Started May 14 12:54:51 PM PDT 24
Finished May 14 12:54:53 PM PDT 24
Peak memory 194172 kb
Host smart-06635ab9-d40b-4076-950f-aeb3c5f508d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620716571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3620716571
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.479920554
Short name T1309
Test name
Test status
Simulation time 146710637 ps
CPU time 0.63 seconds
Started May 14 12:55:04 PM PDT 24
Finished May 14 12:55:06 PM PDT 24
Peak memory 194068 kb
Host smart-03dbe8df-f583-4882-adf3-e6bff12a7841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479920554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.479920554
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.613522813
Short name T1243
Test name
Test status
Simulation time 38899077 ps
CPU time 0.58 seconds
Started May 14 12:54:51 PM PDT 24
Finished May 14 12:54:54 PM PDT 24
Peak memory 194196 kb
Host smart-b9e9ffdf-525b-45bb-a9d7-84502c9b3c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613522813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.613522813
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.81366486
Short name T1242
Test name
Test status
Simulation time 47282338 ps
CPU time 0.68 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 195192 kb
Host smart-ab7bc0a7-198a-46b3-bed8-48a3b04bc13a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81366486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.81366486
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4266210176
Short name T1213
Test name
Test status
Simulation time 347670256 ps
CPU time 2.48 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 197424 kb
Host smart-03a42e5f-4f6f-4280-a529-d801e91984e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266210176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4266210176
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3212850792
Short name T67
Test name
Test status
Simulation time 38631231 ps
CPU time 0.59 seconds
Started May 14 12:54:50 PM PDT 24
Finished May 14 12:54:53 PM PDT 24
Peak memory 195212 kb
Host smart-034c549f-5c61-463e-8ade-3001e69f2353
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212850792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3212850792
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.900453951
Short name T1223
Test name
Test status
Simulation time 116356465 ps
CPU time 0.91 seconds
Started May 14 12:54:44 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 199668 kb
Host smart-0de82a30-e216-41bc-a7f8-774cd6dc4090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900453951 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.900453951
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3627112762
Short name T1263
Test name
Test status
Simulation time 38405593 ps
CPU time 0.59 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:28 PM PDT 24
Peak memory 195248 kb
Host smart-0bdf7105-cec5-4d28-b8de-8701c3a246f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627112762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3627112762
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.4069775342
Short name T1211
Test name
Test status
Simulation time 54150960 ps
CPU time 0.56 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194232 kb
Host smart-142f3398-c347-4ea0-8abd-603b421dd0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069775342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4069775342
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3884397251
Short name T77
Test name
Test status
Simulation time 32487039 ps
CPU time 0.81 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 196932 kb
Host smart-90e330ce-3ec8-4c10-945e-dbf6a97cadb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884397251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3884397251
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2457842229
Short name T1278
Test name
Test status
Simulation time 282784241 ps
CPU time 1.65 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 199868 kb
Host smart-801a055f-ef72-40f7-bb3f-66a9cd9fe62e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457842229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2457842229
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1221360515
Short name T79
Test name
Test status
Simulation time 173996120 ps
CPU time 1.24 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 199164 kb
Host smart-f3777dae-d8ff-4d4b-b595-8112a8dc03c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221360515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1221360515
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3822311303
Short name T1190
Test name
Test status
Simulation time 47826522 ps
CPU time 0.61 seconds
Started May 14 12:54:57 PM PDT 24
Finished May 14 12:55:01 PM PDT 24
Peak memory 194172 kb
Host smart-d20a8fce-3e16-4271-b181-738770bf3359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822311303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3822311303
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3832614152
Short name T1246
Test name
Test status
Simulation time 18224506 ps
CPU time 0.57 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:55 PM PDT 24
Peak memory 194152 kb
Host smart-a239b123-a79e-43c3-a4ca-55c8ed67a599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832614152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3832614152
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2238181033
Short name T1230
Test name
Test status
Simulation time 61706983 ps
CPU time 0.55 seconds
Started May 14 12:54:57 PM PDT 24
Finished May 14 12:55:01 PM PDT 24
Peak memory 194268 kb
Host smart-dc160dcf-9fad-41ba-800a-c3d1facfc546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238181033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2238181033
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2534626270
Short name T1210
Test name
Test status
Simulation time 26782919 ps
CPU time 0.56 seconds
Started May 14 12:54:58 PM PDT 24
Finished May 14 12:55:02 PM PDT 24
Peak memory 194096 kb
Host smart-dab33e26-3648-40c5-ba3c-ddff488cdcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534626270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2534626270
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1213522629
Short name T1253
Test name
Test status
Simulation time 92741934 ps
CPU time 0.58 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194288 kb
Host smart-cadd91b0-e1e4-4201-8c01-8567c39c2054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213522629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1213522629
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.550275204
Short name T1268
Test name
Test status
Simulation time 27054789 ps
CPU time 0.58 seconds
Started May 14 12:54:54 PM PDT 24
Finished May 14 12:54:57 PM PDT 24
Peak memory 194208 kb
Host smart-449d9637-56c3-4c09-b8b5-ccb0ec4e8d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550275204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.550275204
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4058787467
Short name T1241
Test name
Test status
Simulation time 33608909 ps
CPU time 0.59 seconds
Started May 14 12:55:08 PM PDT 24
Finished May 14 12:55:10 PM PDT 24
Peak memory 194312 kb
Host smart-4890a563-45fe-4cb5-b183-2fd57ac9b945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058787467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4058787467
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1587804405
Short name T1262
Test name
Test status
Simulation time 15670742 ps
CPU time 0.6 seconds
Started May 14 12:54:55 PM PDT 24
Finished May 14 12:54:59 PM PDT 24
Peak memory 194232 kb
Host smart-d1609758-6b80-43e9-8b83-fe532f9c2fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587804405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1587804405
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2656584786
Short name T1270
Test name
Test status
Simulation time 12155045 ps
CPU time 0.56 seconds
Started May 14 12:55:10 PM PDT 24
Finished May 14 12:55:12 PM PDT 24
Peak memory 194180 kb
Host smart-bd1306d2-4fb1-4fa3-b8e9-2a6444dcbf93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656584786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2656584786
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1444519586
Short name T1194
Test name
Test status
Simulation time 15112281 ps
CPU time 0.56 seconds
Started May 14 12:54:47 PM PDT 24
Finished May 14 12:54:51 PM PDT 24
Peak memory 194148 kb
Host smart-80b73ac9-9a3c-4a3e-87b2-cd22d8c97a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444519586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1444519586
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2658099474
Short name T1204
Test name
Test status
Simulation time 43835394 ps
CPU time 0.63 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 194540 kb
Host smart-dd40fe69-438c-47b6-b17d-aca4886f5f68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658099474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2658099474
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2522439796
Short name T1200
Test name
Test status
Simulation time 137940855 ps
CPU time 1.4 seconds
Started May 14 12:54:32 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 197712 kb
Host smart-aadb9f0b-a315-4be9-9299-249bb1e975d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522439796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2522439796
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3581625578
Short name T1205
Test name
Test status
Simulation time 36038457 ps
CPU time 0.56 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 195228 kb
Host smart-e4140efc-cea2-4a10-ac98-6819b5fb8d74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581625578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3581625578
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2090558888
Short name T1199
Test name
Test status
Simulation time 25755669 ps
CPU time 0.77 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 198196 kb
Host smart-489fcf74-b0ff-4c22-bee6-f969b94aff6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090558888 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2090558888
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2229466688
Short name T52
Test name
Test status
Simulation time 54219478 ps
CPU time 0.62 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:46 PM PDT 24
Peak memory 195300 kb
Host smart-00901e53-ee7b-41ca-bb15-4a43ed867045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229466688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2229466688
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.683096196
Short name T1271
Test name
Test status
Simulation time 16495662 ps
CPU time 0.66 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194172 kb
Host smart-6bff3ee2-c577-444d-b859-7314f6595060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683096196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.683096196
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4201375453
Short name T1305
Test name
Test status
Simulation time 98468705 ps
CPU time 0.73 seconds
Started May 14 12:54:34 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 196736 kb
Host smart-8a983d92-f2e5-42ae-8475-c982b451d7ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201375453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4201375453
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3485042823
Short name T1233
Test name
Test status
Simulation time 28880321 ps
CPU time 1.48 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 199820 kb
Host smart-177dbafd-e2b9-4730-8cca-752c31afbec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485042823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3485042823
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.434361216
Short name T1319
Test name
Test status
Simulation time 48832172 ps
CPU time 1 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 198832 kb
Host smart-34b5e003-e6ec-4d6f-8184-e66970945329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434361216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.434361216
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3584320677
Short name T1219
Test name
Test status
Simulation time 12666773 ps
CPU time 0.58 seconds
Started May 14 12:54:58 PM PDT 24
Finished May 14 12:55:02 PM PDT 24
Peak memory 194220 kb
Host smart-8cc3d1ec-ce6a-47f1-9539-21752bf1793f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584320677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3584320677
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3593269542
Short name T1266
Test name
Test status
Simulation time 42548612 ps
CPU time 0.61 seconds
Started May 14 12:55:04 PM PDT 24
Finished May 14 12:55:06 PM PDT 24
Peak memory 194160 kb
Host smart-a688c6d8-7d40-44fe-917e-1216865cc3f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593269542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3593269542
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3004980646
Short name T1279
Test name
Test status
Simulation time 106073494 ps
CPU time 0.59 seconds
Started May 14 12:54:56 PM PDT 24
Finished May 14 12:55:00 PM PDT 24
Peak memory 194204 kb
Host smart-f3a1b73e-e164-424a-8c74-39e052b67cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004980646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3004980646
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.171900324
Short name T1237
Test name
Test status
Simulation time 24959824 ps
CPU time 0.56 seconds
Started May 14 12:54:47 PM PDT 24
Finished May 14 12:54:51 PM PDT 24
Peak memory 194212 kb
Host smart-a98e2324-edb5-4d4e-85bc-ffb311bd3dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171900324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.171900324
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1318336289
Short name T1189
Test name
Test status
Simulation time 18654572 ps
CPU time 0.58 seconds
Started May 14 12:54:53 PM PDT 24
Finished May 14 12:54:56 PM PDT 24
Peak memory 194200 kb
Host smart-4a7c96e7-5f4f-4754-b4ac-5779c1d66150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318336289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1318336289
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.4179310122
Short name T1186
Test name
Test status
Simulation time 25523843 ps
CPU time 0.59 seconds
Started May 14 12:54:49 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 194144 kb
Host smart-f8dca21e-f97f-4bc6-826b-0e22bc9f2747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179310122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4179310122
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1565019978
Short name T1227
Test name
Test status
Simulation time 12457981 ps
CPU time 0.58 seconds
Started May 14 12:54:55 PM PDT 24
Finished May 14 12:54:59 PM PDT 24
Peak memory 194228 kb
Host smart-8076d573-e5ef-4dfb-856e-8abfea6677d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565019978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1565019978
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.806320608
Short name T1247
Test name
Test status
Simulation time 43224564 ps
CPU time 0.58 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194204 kb
Host smart-d652a4c0-5946-454a-9b83-a296f0e009dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806320608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.806320608
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4169760561
Short name T1296
Test name
Test status
Simulation time 13672372 ps
CPU time 0.58 seconds
Started May 14 12:54:46 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 194252 kb
Host smart-04917877-342f-46c2-aa47-a11b2717c4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169760561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4169760561
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.140482782
Short name T1269
Test name
Test status
Simulation time 16155785 ps
CPU time 0.59 seconds
Started May 14 12:54:52 PM PDT 24
Finished May 14 12:54:54 PM PDT 24
Peak memory 194248 kb
Host smart-07f40fcc-fc54-4838-9bfe-74bbf5f20a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140482782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.140482782
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3399801615
Short name T1198
Test name
Test status
Simulation time 96594496 ps
CPU time 1.28 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 199820 kb
Host smart-3fbf77fe-9a47-47b8-b1ad-95d6f436fa1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399801615 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3399801615
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2764934072
Short name T1212
Test name
Test status
Simulation time 123534414 ps
CPU time 0.6 seconds
Started May 14 12:54:37 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 195220 kb
Host smart-312a48f2-289d-4499-9cdf-6807f96caca7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764934072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2764934072
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3245196415
Short name T1185
Test name
Test status
Simulation time 23243943 ps
CPU time 0.56 seconds
Started May 14 12:54:37 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 194120 kb
Host smart-5a8c4ae9-1b1b-4c4e-a589-757ae913a659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245196415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3245196415
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.823876239
Short name T1234
Test name
Test status
Simulation time 64650335 ps
CPU time 0.67 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 195068 kb
Host smart-676236fe-0d74-4b0b-b510-e38e7469023a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823876239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.823876239
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3460174647
Short name T1288
Test name
Test status
Simulation time 245980391 ps
CPU time 2.24 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 199824 kb
Host smart-6fdb8bfb-448f-4096-ad7e-6a5ef2e50247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460174647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3460174647
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.838986660
Short name T1231
Test name
Test status
Simulation time 94189110 ps
CPU time 1 seconds
Started May 14 12:54:41 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 199008 kb
Host smart-6750bde9-7e4e-4c5c-a3bd-10e44395b1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838986660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.838986660
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2509413971
Short name T1252
Test name
Test status
Simulation time 86532698 ps
CPU time 0.77 seconds
Started May 14 12:54:41 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 198324 kb
Host smart-0d6fbf73-eb93-476c-b18e-0a91fab05678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509413971 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2509413971
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4151396236
Short name T1316
Test name
Test status
Simulation time 14239988 ps
CPU time 0.58 seconds
Started May 14 12:54:39 PM PDT 24
Finished May 14 12:54:41 PM PDT 24
Peak memory 195152 kb
Host smart-01213757-0dba-48fd-8d6e-4061c2c67d98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151396236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4151396236
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.808091311
Short name T1304
Test name
Test status
Simulation time 13344263 ps
CPU time 0.56 seconds
Started May 14 12:54:37 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 194176 kb
Host smart-974f77ed-12bb-4c4d-9260-f509379659b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808091311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.808091311
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.67670983
Short name T1281
Test name
Test status
Simulation time 127754764 ps
CPU time 0.75 seconds
Started May 14 12:54:43 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 195752 kb
Host smart-8bd4c015-7acb-4c08-a7cf-d23f2dc03b3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67670983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_o
utstanding.67670983
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2706735623
Short name T1294
Test name
Test status
Simulation time 333677662 ps
CPU time 1.49 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 199872 kb
Host smart-823aab9c-54b6-4a0e-ba29-5f5544477cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706735623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2706735623
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3497798112
Short name T87
Test name
Test status
Simulation time 241407026 ps
CPU time 1.21 seconds
Started May 14 12:54:34 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 199156 kb
Host smart-7500e3be-4d3e-4840-878c-ee8acde1e141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497798112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3497798112
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1285337634
Short name T1251
Test name
Test status
Simulation time 30903639 ps
CPU time 0.67 seconds
Started May 14 12:54:33 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 197532 kb
Host smart-b624f667-dc2c-4be0-bf31-46b1cea69d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285337634 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1285337634
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3784672822
Short name T1286
Test name
Test status
Simulation time 47294341 ps
CPU time 0.65 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 195252 kb
Host smart-b77abf20-3456-4e61-8ce6-7d29ca01e131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784672822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3784672822
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3195329042
Short name T1311
Test name
Test status
Simulation time 17610878 ps
CPU time 0.57 seconds
Started May 14 12:54:36 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 194092 kb
Host smart-7b7d2c9b-e4ec-4dce-89e7-ff685eaeb9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195329042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3195329042
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4134546340
Short name T1277
Test name
Test status
Simulation time 51752503 ps
CPU time 0.75 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 197004 kb
Host smart-47266419-5979-4d05-b1da-b895c72ca820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134546340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.4134546340
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3690539876
Short name T1250
Test name
Test status
Simulation time 82489405 ps
CPU time 2.15 seconds
Started May 14 12:54:40 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 199884 kb
Host smart-2ae628d7-bd15-4331-8e09-14d40975dc23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690539876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3690539876
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4238026532
Short name T1255
Test name
Test status
Simulation time 135923772 ps
CPU time 1.1 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 199700 kb
Host smart-22a755d2-f290-43e8-98ba-e5b62b45a053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238026532 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4238026532
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2055850430
Short name T53
Test name
Test status
Simulation time 74419143 ps
CPU time 0.64 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 195372 kb
Host smart-e819a5d2-82c0-4a55-8b0e-8e99b30108bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055850430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2055850430
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1215317129
Short name T1236
Test name
Test status
Simulation time 42224648 ps
CPU time 0.58 seconds
Started May 14 12:54:37 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 194168 kb
Host smart-f44944ec-cb21-4747-81b4-a327889bfceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215317129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1215317129
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3872646467
Short name T71
Test name
Test status
Simulation time 34090079 ps
CPU time 0.72 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:54:48 PM PDT 24
Peak memory 196732 kb
Host smart-35cf3789-512a-4d70-a024-4b89b744e318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872646467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3872646467
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2202331108
Short name T1297
Test name
Test status
Simulation time 140685540 ps
CPU time 1.11 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 199700 kb
Host smart-59db892b-a7b6-4a04-85a1-49d27c27a9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202331108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2202331108
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3446400908
Short name T84
Test name
Test status
Simulation time 79944025 ps
CPU time 1.2 seconds
Started May 14 12:54:30 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 199136 kb
Host smart-1472a367-444f-4f33-9a03-3c351ed109b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446400908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3446400908
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3609073262
Short name T1298
Test name
Test status
Simulation time 201146227 ps
CPU time 0.91 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 199632 kb
Host smart-59028972-5881-442c-b085-ad5eb86a10c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609073262 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3609073262
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3673286279
Short name T1222
Test name
Test status
Simulation time 72927851 ps
CPU time 0.6 seconds
Started May 14 12:54:42 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 195180 kb
Host smart-ed84a72c-2747-4220-8310-a1f20057471d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673286279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3673286279
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1513516470
Short name T1287
Test name
Test status
Simulation time 36796184 ps
CPU time 0.57 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 194072 kb
Host smart-f528bd4e-2738-4e4c-9ffa-3f52de191a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513516470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1513516470
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2322850658
Short name T73
Test name
Test status
Simulation time 33004313 ps
CPU time 0.77 seconds
Started May 14 12:54:36 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 196860 kb
Host smart-f2c8db03-8c46-487f-a2d7-3f269950f5d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322850658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2322850658
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.522123644
Short name T1202
Test name
Test status
Simulation time 625252842 ps
CPU time 2.16 seconds
Started May 14 12:54:34 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 199820 kb
Host smart-a8ac5b7b-3cd5-4564-b499-dd33ccc43fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522123644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.522123644
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3870125978
Short name T83
Test name
Test status
Simulation time 79920187 ps
CPU time 1.27 seconds
Started May 14 12:54:41 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 199200 kb
Host smart-ca71acbf-7e7d-45ed-a29d-47cffd585a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870125978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3870125978
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1963192530
Short name T445
Test name
Test status
Simulation time 59845992 ps
CPU time 0.58 seconds
Started May 14 12:56:51 PM PDT 24
Finished May 14 12:56:52 PM PDT 24
Peak memory 195864 kb
Host smart-8f43cf39-d2c7-4a11-991c-0cb1d3b3af87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963192530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1963192530
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1207319689
Short name T1113
Test name
Test status
Simulation time 85923180966 ps
CPU time 69.43 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 200372 kb
Host smart-3d0d50d0-3c17-4f09-8b3a-ca23c6f5ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207319689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1207319689
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1012597795
Short name T731
Test name
Test status
Simulation time 100024734344 ps
CPU time 182.86 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:59:48 PM PDT 24
Peak memory 200292 kb
Host smart-6a5e92f2-ad4a-431a-bc7e-955806581f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012597795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1012597795
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1668649259
Short name T60
Test name
Test status
Simulation time 47279917811 ps
CPU time 69.64 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:57:58 PM PDT 24
Peak memory 200512 kb
Host smart-46621922-62e3-4a1f-badb-4bf5136b3b07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668649259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1668649259
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1902666485
Short name T643
Test name
Test status
Simulation time 108445837936 ps
CPU time 412.49 seconds
Started May 14 12:56:48 PM PDT 24
Finished May 14 01:03:42 PM PDT 24
Peak memory 200556 kb
Host smart-41dc6771-6f59-4d3a-ae97-c5535a581083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902666485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1902666485
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2794210109
Short name T619
Test name
Test status
Simulation time 6270472667 ps
CPU time 12.95 seconds
Started May 14 12:56:48 PM PDT 24
Finished May 14 12:57:03 PM PDT 24
Peak memory 200100 kb
Host smart-50023451-f6b7-4bb3-8363-7ce897941950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794210109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2794210109
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1744891347
Short name T994
Test name
Test status
Simulation time 94155038482 ps
CPU time 171.65 seconds
Started May 14 12:56:48 PM PDT 24
Finished May 14 12:59:41 PM PDT 24
Peak memory 200368 kb
Host smart-df4cd13e-f250-42b7-9e57-aeb2b11f74e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744891347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1744891347
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.253927881
Short name T891
Test name
Test status
Simulation time 26850218875 ps
CPU time 89.64 seconds
Started May 14 12:56:46 PM PDT 24
Finished May 14 12:58:17 PM PDT 24
Peak memory 200436 kb
Host smart-02ef33a2-89ce-42cb-989a-e45a6cb91f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253927881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.253927881
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3846816498
Short name T1083
Test name
Test status
Simulation time 4977635791 ps
CPU time 46.31 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 198664 kb
Host smart-8cbc190f-1962-4d4b-bbef-9d228613764d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846816498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3846816498
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.845190172
Short name T1102
Test name
Test status
Simulation time 134691966372 ps
CPU time 174.17 seconds
Started May 14 12:56:48 PM PDT 24
Finished May 14 12:59:44 PM PDT 24
Peak memory 200424 kb
Host smart-0772ab61-e353-40e8-8ff5-e3b62e1a133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845190172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.845190172
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2593138021
Short name T653
Test name
Test status
Simulation time 42883888229 ps
CPU time 70.66 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:57:59 PM PDT 24
Peak memory 196496 kb
Host smart-cffd931f-6921-4c06-a0da-9a4fe6e87731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593138021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2593138021
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.4230116100
Short name T782
Test name
Test status
Simulation time 475714316 ps
CPU time 2.3 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 199620 kb
Host smart-1f43392a-dd0b-42e6-b31f-017df7b9c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230116100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4230116100
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2969098863
Short name T482
Test name
Test status
Simulation time 40749137162 ps
CPU time 78.48 seconds
Started May 14 12:56:49 PM PDT 24
Finished May 14 12:58:09 PM PDT 24
Peak memory 200500 kb
Host smart-f982236e-8cc5-43c9-871e-a4c1a0e99602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969098863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2969098863
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.484635685
Short name T1098
Test name
Test status
Simulation time 40053945399 ps
CPU time 236.13 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 01:00:45 PM PDT 24
Peak memory 217232 kb
Host smart-c33e00e6-13c1-4b1d-bee3-b82dbbb1282c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484635685 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.484635685
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3724292136
Short name T304
Test name
Test status
Simulation time 1773244292 ps
CPU time 4.4 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:56:53 PM PDT 24
Peak memory 199308 kb
Host smart-c834b252-b503-4297-904d-5f169cde4d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724292136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3724292136
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3650669857
Short name T651
Test name
Test status
Simulation time 131937862645 ps
CPU time 74.34 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:58:00 PM PDT 24
Peak memory 200444 kb
Host smart-4f154744-764f-497d-8f8e-cf0fe0655dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650669857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3650669857
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1889893718
Short name T892
Test name
Test status
Simulation time 27541826 ps
CPU time 0.54 seconds
Started May 14 12:56:55 PM PDT 24
Finished May 14 12:56:57 PM PDT 24
Peak memory 194792 kb
Host smart-337207b9-6918-4c14-a514-f3b54fd6b720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889893718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1889893718
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2846512205
Short name T995
Test name
Test status
Simulation time 57391224398 ps
CPU time 27.89 seconds
Started May 14 12:56:50 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 200424 kb
Host smart-f88ddfdd-a164-49b5-af38-4cfa2dad61f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846512205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2846512205
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3395625677
Short name T193
Test name
Test status
Simulation time 121143550582 ps
CPU time 50.16 seconds
Started May 14 12:56:50 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 200456 kb
Host smart-84f16477-f597-4add-b434-c831d18e3763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395625677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3395625677
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3902877932
Short name T873
Test name
Test status
Simulation time 42545015712 ps
CPU time 16.7 seconds
Started May 14 12:56:48 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 200216 kb
Host smart-e5935225-7ca3-4125-90a0-cbfdaca81aa2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902877932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3902877932
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.4115640539
Short name T570
Test name
Test status
Simulation time 167128657775 ps
CPU time 295.14 seconds
Started May 14 12:56:55 PM PDT 24
Finished May 14 01:01:51 PM PDT 24
Peak memory 200480 kb
Host smart-c07c5378-b8a7-47fd-820a-3c29db69f949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115640539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4115640539
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2559101450
Short name T419
Test name
Test status
Simulation time 10076234574 ps
CPU time 6.04 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:57:01 PM PDT 24
Peak memory 199396 kb
Host smart-d79fb9a4-8b51-4583-897f-9c351100ad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559101450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2559101450
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2932469466
Short name T279
Test name
Test status
Simulation time 82857823647 ps
CPU time 114.21 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:58:42 PM PDT 24
Peak memory 200484 kb
Host smart-ac3280d6-dfee-427e-aa9f-370ae9664360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932469466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2932469466
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.4090135087
Short name T742
Test name
Test status
Simulation time 13719873033 ps
CPU time 792.14 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 01:10:07 PM PDT 24
Peak memory 200456 kb
Host smart-653c94da-1898-45aa-a1cd-f5060d86f75a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090135087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4090135087
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2757414844
Short name T400
Test name
Test status
Simulation time 2401834056 ps
CPU time 11.03 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:57:00 PM PDT 24
Peak memory 199292 kb
Host smart-f3c5abdc-841e-4c9b-ab87-c79d7411d98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757414844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2757414844
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.629982726
Short name T780
Test name
Test status
Simulation time 24650519095 ps
CPU time 27.63 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:57:23 PM PDT 24
Peak memory 200412 kb
Host smart-3807951d-e135-44cf-ab20-f11bfe33d8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629982726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.629982726
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.106567056
Short name T861
Test name
Test status
Simulation time 3660251145 ps
CPU time 6.45 seconds
Started May 14 12:56:51 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 196788 kb
Host smart-e8e5aefc-d183-4648-a746-ba93b5dca3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106567056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.106567056
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2336189801
Short name T90
Test name
Test status
Simulation time 145090870 ps
CPU time 0.82 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 219100 kb
Host smart-20962d47-2d27-4058-83da-f1cdbdd87760
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336189801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2336189801
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3187875077
Short name T543
Test name
Test status
Simulation time 488347913 ps
CPU time 2.24 seconds
Started May 14 12:56:49 PM PDT 24
Finished May 14 12:56:52 PM PDT 24
Peak memory 199984 kb
Host smart-b63b350f-a4fd-427b-8947-696857163eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187875077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3187875077
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2432183574
Short name T1052
Test name
Test status
Simulation time 162926905262 ps
CPU time 373.29 seconds
Started May 14 12:56:55 PM PDT 24
Finished May 14 01:03:09 PM PDT 24
Peak memory 208952 kb
Host smart-93ecfa94-60ab-4010-8015-9c453113fcbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432183574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2432183574
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2424427584
Short name T638
Test name
Test status
Simulation time 58588672583 ps
CPU time 719.83 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 01:08:56 PM PDT 24
Peak memory 217160 kb
Host smart-ef1664f9-c466-4e1b-b47a-61c34f728e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424427584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2424427584
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.584788163
Short name T516
Test name
Test status
Simulation time 1114509123 ps
CPU time 4.32 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:57:00 PM PDT 24
Peak memory 199264 kb
Host smart-0223747b-2fe1-4ee4-a80f-8463019b0349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584788163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.584788163
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2947576602
Short name T418
Test name
Test status
Simulation time 80809042082 ps
CPU time 133.17 seconds
Started May 14 12:56:47 PM PDT 24
Finished May 14 12:59:01 PM PDT 24
Peak memory 200404 kb
Host smart-48eb9665-737c-45ea-b7e9-576654818c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947576602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2947576602
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3109664047
Short name T439
Test name
Test status
Simulation time 24935015 ps
CPU time 0.54 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 12:57:26 PM PDT 24
Peak memory 195848 kb
Host smart-70e957c6-0d95-4f66-a446-7f8c254f7367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109664047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3109664047
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3456180414
Short name T312
Test name
Test status
Simulation time 193756729125 ps
CPU time 421.3 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 01:04:22 PM PDT 24
Peak memory 200492 kb
Host smart-4ac3227a-187a-445d-8345-622619239ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456180414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3456180414
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3708311911
Short name T165
Test name
Test status
Simulation time 253012751153 ps
CPU time 432.73 seconds
Started May 14 12:57:22 PM PDT 24
Finished May 14 01:04:36 PM PDT 24
Peak memory 200476 kb
Host smart-00cc1fa7-a6db-4fe0-b6c8-f1cc003302dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708311911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3708311911
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3620943027
Short name T148
Test name
Test status
Simulation time 102680235628 ps
CPU time 155.1 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 01:00:02 PM PDT 24
Peak memory 200472 kb
Host smart-322295ed-0ab5-4b53-9f39-1479a3c228e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620943027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3620943027
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3403213369
Short name T405
Test name
Test status
Simulation time 216554282095 ps
CPU time 68.39 seconds
Started May 14 12:57:27 PM PDT 24
Finished May 14 12:58:37 PM PDT 24
Peak memory 200532 kb
Host smart-ef43b509-f0b7-4ccb-8742-354e4a4cf25c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403213369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3403213369
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2428599815
Short name T771
Test name
Test status
Simulation time 89200408790 ps
CPU time 79.83 seconds
Started May 14 12:57:27 PM PDT 24
Finished May 14 12:58:49 PM PDT 24
Peak memory 200468 kb
Host smart-f861b76f-4b1a-46a9-8b92-75dc50980e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428599815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2428599815
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2426702119
Short name T451
Test name
Test status
Simulation time 8152251745 ps
CPU time 14.8 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 12:57:43 PM PDT 24
Peak memory 200080 kb
Host smart-6a33bc48-76ff-4546-88cf-39144d2dcb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426702119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2426702119
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.731393047
Short name T412
Test name
Test status
Simulation time 307194273720 ps
CPU time 57.38 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 12:58:23 PM PDT 24
Peak memory 216416 kb
Host smart-326521af-4114-4ab2-b553-508ff9d3e79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731393047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.731393047
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.953989569
Short name T383
Test name
Test status
Simulation time 15990072867 ps
CPU time 379.54 seconds
Started May 14 12:57:22 PM PDT 24
Finished May 14 01:03:43 PM PDT 24
Peak memory 200472 kb
Host smart-a2d09616-f4aa-4695-a921-599eb72fe13a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953989569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.953989569
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3921409312
Short name T1183
Test name
Test status
Simulation time 2324534229 ps
CPU time 12.71 seconds
Started May 14 12:57:31 PM PDT 24
Finished May 14 12:57:45 PM PDT 24
Peak memory 198788 kb
Host smart-2e0e579b-6901-4cb1-8848-d6d969290343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921409312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3921409312
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3173996408
Short name T669
Test name
Test status
Simulation time 8457663645 ps
CPU time 15.38 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 12:57:40 PM PDT 24
Peak memory 200260 kb
Host smart-49dd29ec-3a6e-42b7-8a19-f1e02c0aa8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173996408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3173996408
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3828117268
Short name T294
Test name
Test status
Simulation time 43316648246 ps
CPU time 16.71 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:43 PM PDT 24
Peak memory 196432 kb
Host smart-18373fbc-21d6-4381-b4ea-8ed0ddb5e721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828117268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3828117268
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.799150763
Short name T598
Test name
Test status
Simulation time 5604332909 ps
CPU time 5.42 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 12:57:33 PM PDT 24
Peak memory 200320 kb
Host smart-6bfb6804-c4e3-4ac0-b994-f274062c0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799150763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.799150763
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1074090767
Short name T819
Test name
Test status
Simulation time 18455433776 ps
CPU time 248.17 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 01:01:33 PM PDT 24
Peak memory 208660 kb
Host smart-136d31b3-ae8a-44da-9005-8b6d85b8b766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074090767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1074090767
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1688325116
Short name T805
Test name
Test status
Simulation time 6381266054 ps
CPU time 17.57 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:57:48 PM PDT 24
Peak memory 199932 kb
Host smart-a0a3ea1d-c46a-49d0-8627-9759c9a5dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688325116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1688325116
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3010001204
Short name T460
Test name
Test status
Simulation time 75971831991 ps
CPU time 160.41 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 01:00:05 PM PDT 24
Peak memory 200492 kb
Host smart-770eb094-ee76-4e17-a729-6c8a0af26df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010001204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3010001204
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.118379534
Short name T1
Test name
Test status
Simulation time 12624936944 ps
CPU time 31.88 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:01:28 PM PDT 24
Peak memory 200492 kb
Host smart-18cc3b03-873c-4f25-a12a-6efa0115cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118379534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.118379534
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2448121771
Short name T163
Test name
Test status
Simulation time 28798443749 ps
CPU time 49.4 seconds
Started May 14 01:00:57 PM PDT 24
Finished May 14 01:01:51 PM PDT 24
Peak memory 200468 kb
Host smart-2975cacd-ac8c-4f44-8dfe-f57697659807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448121771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2448121771
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4263535080
Short name T158
Test name
Test status
Simulation time 35680846770 ps
CPU time 17.98 seconds
Started May 14 01:00:56 PM PDT 24
Finished May 14 01:01:18 PM PDT 24
Peak memory 200540 kb
Host smart-338f2584-62e0-4300-a435-2879b39d4cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263535080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4263535080
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.159778324
Short name T510
Test name
Test status
Simulation time 18508003123 ps
CPU time 37.6 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:01:40 PM PDT 24
Peak memory 200400 kb
Host smart-9a5516e0-84e8-4a55-8be4-f3e718927db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159778324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.159778324
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.400765846
Short name T647
Test name
Test status
Simulation time 81542967565 ps
CPU time 47.3 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:01:49 PM PDT 24
Peak memory 200168 kb
Host smart-c44302db-9800-4f5b-af93-d65502166795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400765846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.400765846
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1011475631
Short name T940
Test name
Test status
Simulation time 41396744935 ps
CPU time 20.15 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:15 PM PDT 24
Peak memory 200488 kb
Host smart-8d3530d3-666f-4d1a-b14b-9224a9dc9815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011475631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1011475631
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1349435132
Short name T608
Test name
Test status
Simulation time 123761945302 ps
CPU time 19.09 seconds
Started May 14 01:00:50 PM PDT 24
Finished May 14 01:01:11 PM PDT 24
Peak memory 200376 kb
Host smart-d29bfc07-ab7e-4ec7-b915-29deb8445b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349435132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1349435132
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1865088396
Short name T1095
Test name
Test status
Simulation time 18451587727 ps
CPU time 35.51 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:01:32 PM PDT 24
Peak memory 200452 kb
Host smart-6075d168-116a-475d-b406-84abe8b94db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865088396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1865088396
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.884846141
Short name T1094
Test name
Test status
Simulation time 25482779277 ps
CPU time 59.37 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:01:55 PM PDT 24
Peak memory 200472 kb
Host smart-ad3d1391-dd0e-48be-8d10-c1dccf17fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884846141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.884846141
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3024660233
Short name T189
Test name
Test status
Simulation time 41536687814 ps
CPU time 20.86 seconds
Started May 14 01:00:56 PM PDT 24
Finished May 14 01:01:21 PM PDT 24
Peak memory 200540 kb
Host smart-cc44b34d-0a41-4715-8db9-36e36b5aeea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024660233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3024660233
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3910513574
Short name T443
Test name
Test status
Simulation time 15045737 ps
CPU time 0.57 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 12:57:29 PM PDT 24
Peak memory 195792 kb
Host smart-fd6e0f1e-dbb7-47ab-9b62-27f70abbc811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910513574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3910513574
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.463046170
Short name T874
Test name
Test status
Simulation time 20650492048 ps
CPU time 35.16 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:58:01 PM PDT 24
Peak memory 200520 kb
Host smart-3c31d11f-9210-4363-ad64-cf541ba73abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463046170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.463046170
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1440569617
Short name T404
Test name
Test status
Simulation time 321582955978 ps
CPU time 90.15 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 12:58:59 PM PDT 24
Peak memory 198768 kb
Host smart-df4b62d2-1f63-4a16-a102-d0c232efdec4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440569617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1440569617
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2482566029
Short name T817
Test name
Test status
Simulation time 214315605886 ps
CPU time 1768.56 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 01:26:53 PM PDT 24
Peak memory 200452 kb
Host smart-ce205f19-c7c5-4f4f-9ca7-d8e358ac0320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482566029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2482566029
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.887226932
Short name T674
Test name
Test status
Simulation time 2506794133 ps
CPU time 4.87 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:57:36 PM PDT 24
Peak memory 196836 kb
Host smart-c6ad051a-6221-4237-96c2-c28d1133ad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887226932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.887226932
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2980738911
Short name T914
Test name
Test status
Simulation time 71805132137 ps
CPU time 39.73 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:58:06 PM PDT 24
Peak memory 200268 kb
Host smart-5c393dcf-efeb-4fcd-8a9c-7c67ecc0826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980738911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2980738911
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3391178130
Short name T897
Test name
Test status
Simulation time 31117169833 ps
CPU time 791.89 seconds
Started May 14 12:57:31 PM PDT 24
Finished May 14 01:10:44 PM PDT 24
Peak memory 200512 kb
Host smart-968eabe6-a001-46ed-a880-322308f78243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391178130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3391178130
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.485984887
Short name T426
Test name
Test status
Simulation time 3341426293 ps
CPU time 29.16 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:55 PM PDT 24
Peak memory 199628 kb
Host smart-e8d592ba-cc7b-4f25-8d5c-1ddaa0250e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485984887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.485984887
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1267430269
Short name T125
Test name
Test status
Simulation time 28352513066 ps
CPU time 22.21 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 199924 kb
Host smart-b7588fef-1955-4380-86e8-8ec7f533232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267430269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1267430269
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2729772003
Short name T1045
Test name
Test status
Simulation time 1513055483 ps
CPU time 1.4 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:27 PM PDT 24
Peak memory 195920 kb
Host smart-c91688fc-9af4-4d0f-b006-46e1ab19eee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729772003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2729772003
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2825918638
Short name T724
Test name
Test status
Simulation time 768336049 ps
CPU time 1.83 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:28 PM PDT 24
Peak memory 198748 kb
Host smart-12e09700-3b0e-42e9-8181-acdd149c5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825918638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2825918638
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2151631905
Short name T587
Test name
Test status
Simulation time 140640254002 ps
CPU time 359.4 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 01:03:27 PM PDT 24
Peak memory 228228 kb
Host smart-db19e60f-7b95-4347-8b75-974fde6541e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151631905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2151631905
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.16882743
Short name T498
Test name
Test status
Simulation time 9194820952 ps
CPU time 5.74 seconds
Started May 14 12:57:30 PM PDT 24
Finished May 14 12:57:37 PM PDT 24
Peak memory 199864 kb
Host smart-ac038706-a67d-4131-957f-a96075af8af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16882743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.16882743
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.358123495
Short name T930
Test name
Test status
Simulation time 54461617829 ps
CPU time 83.07 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:58:50 PM PDT 24
Peak memory 200472 kb
Host smart-1f583968-c719-4469-a16f-6225bac95f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358123495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.358123495
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.535294045
Short name T464
Test name
Test status
Simulation time 104031271999 ps
CPU time 38.55 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:33 PM PDT 24
Peak memory 200324 kb
Host smart-be86baad-326e-46e9-ac05-0183981e7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535294045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.535294045
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1820112460
Short name T527
Test name
Test status
Simulation time 105833077964 ps
CPU time 50.66 seconds
Started May 14 01:00:56 PM PDT 24
Finished May 14 01:01:51 PM PDT 24
Peak memory 200452 kb
Host smart-6a741f11-3f23-4f04-a59b-2c462de040b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820112460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1820112460
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3934977621
Short name T877
Test name
Test status
Simulation time 107240424614 ps
CPU time 193.63 seconds
Started May 14 01:00:57 PM PDT 24
Finished May 14 01:04:15 PM PDT 24
Peak memory 200400 kb
Host smart-81d00b10-9a71-42ff-9c88-f47b23f2fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934977621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3934977621
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1839592968
Short name T1111
Test name
Test status
Simulation time 21456699352 ps
CPU time 43.53 seconds
Started May 14 01:00:54 PM PDT 24
Finished May 14 01:01:42 PM PDT 24
Peak memory 200500 kb
Host smart-609a1d1b-fe90-4a6f-af4e-60fadaa68ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839592968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1839592968
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3912391002
Short name T501
Test name
Test status
Simulation time 101748857270 ps
CPU time 143.94 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:03:21 PM PDT 24
Peak memory 200508 kb
Host smart-88bd7794-5af4-4cfe-bd69-924938286b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912391002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3912391002
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.92806938
Short name T1043
Test name
Test status
Simulation time 124140396194 ps
CPU time 41.98 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:01:38 PM PDT 24
Peak memory 200504 kb
Host smart-ae363506-df3a-4755-af81-5fd3fbec0a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92806938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.92806938
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4278066312
Short name T196
Test name
Test status
Simulation time 105744025764 ps
CPU time 168.82 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:03:50 PM PDT 24
Peak memory 200408 kb
Host smart-e705c826-1131-40ae-b444-49072f546de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278066312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4278066312
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3174796870
Short name T421
Test name
Test status
Simulation time 16316168 ps
CPU time 0.61 seconds
Started May 14 12:57:27 PM PDT 24
Finished May 14 12:57:30 PM PDT 24
Peak memory 195844 kb
Host smart-b58db73d-6d23-4a20-8c44-4414b1cb5627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174796870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3174796870
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3193736519
Short name T576
Test name
Test status
Simulation time 103313101497 ps
CPU time 372.85 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 01:03:41 PM PDT 24
Peak memory 200516 kb
Host smart-1a805d3e-de6e-464c-bc13-067eef15ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193736519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3193736519
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2096346544
Short name T665
Test name
Test status
Simulation time 41430061773 ps
CPU time 34.41 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:58:05 PM PDT 24
Peak memory 200516 kb
Host smart-4c2b9c1a-6f37-4809-a0e6-4ec3ec9bd048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096346544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2096346544
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1740487087
Short name T1155
Test name
Test status
Simulation time 25843045600 ps
CPU time 3.22 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:57:34 PM PDT 24
Peak memory 199176 kb
Host smart-3e43afaf-6aac-4bda-81f2-47010d881441
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740487087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1740487087
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.867179258
Short name T815
Test name
Test status
Simulation time 123141169914 ps
CPU time 444.23 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 200428 kb
Host smart-69823784-bffb-4812-b64f-2e57f04bb3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867179258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.867179258
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1613372348
Short name T1118
Test name
Test status
Simulation time 3592963600 ps
CPU time 4.32 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:57:35 PM PDT 24
Peak memory 199252 kb
Host smart-1b6c2cb5-d80e-46b0-854f-0c25ab82f124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613372348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1613372348
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.18560724
Short name T1123
Test name
Test status
Simulation time 91475186003 ps
CPU time 17.38 seconds
Started May 14 12:57:29 PM PDT 24
Finished May 14 12:57:48 PM PDT 24
Peak memory 200056 kb
Host smart-cdc1202e-61d5-438b-98cb-a9dd323acbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18560724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.18560724
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1713322402
Short name T928
Test name
Test status
Simulation time 9236948133 ps
CPU time 65.21 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 12:58:33 PM PDT 24
Peak memory 200396 kb
Host smart-f828c8dc-0bb7-49ef-bfa3-cafd31186cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713322402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1713322402
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1985604756
Short name T590
Test name
Test status
Simulation time 2641996283 ps
CPU time 21.02 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 12:57:46 PM PDT 24
Peak memory 198704 kb
Host smart-d99d800e-db23-46dd-ab79-7786fdca1718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985604756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1985604756
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2863769393
Short name T1089
Test name
Test status
Simulation time 40116418739 ps
CPU time 16.42 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:43 PM PDT 24
Peak memory 199040 kb
Host smart-d873fa5a-e511-4271-8e19-772cb6988bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863769393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2863769393
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2498583413
Short name T628
Test name
Test status
Simulation time 5246380595 ps
CPU time 2.73 seconds
Started May 14 12:57:31 PM PDT 24
Finished May 14 12:57:35 PM PDT 24
Peak memory 196772 kb
Host smart-7e685c29-2efe-4d20-b444-d17d621626c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498583413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2498583413
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2234342459
Short name T550
Test name
Test status
Simulation time 458067838 ps
CPU time 1.29 seconds
Started May 14 12:57:28 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 199760 kb
Host smart-1a44d37b-8941-484d-b83f-cfb8fdc3b4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234342459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2234342459
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1382896748
Short name T191
Test name
Test status
Simulation time 387146546004 ps
CPU time 4179.46 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 02:07:07 PM PDT 24
Peak memory 200524 kb
Host smart-c5c9ba61-5187-413b-b790-258c73cc47ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382896748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1382896748
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1741657546
Short name T754
Test name
Test status
Simulation time 37165782038 ps
CPU time 413.12 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 01:04:22 PM PDT 24
Peak memory 216872 kb
Host smart-44408e3f-a204-4b09-906f-a1183f7fd14e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741657546 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1741657546
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1834508330
Short name T17
Test name
Test status
Simulation time 553778068 ps
CPU time 2.91 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:29 PM PDT 24
Peak memory 199720 kb
Host smart-bd3beee1-58f0-484f-aaa5-8f9e7967c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834508330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1834508330
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2066219822
Short name T972
Test name
Test status
Simulation time 9388891564 ps
CPU time 4.77 seconds
Started May 14 12:57:24 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 200400 kb
Host smart-fab30644-9b9a-4f72-be82-51050a0c1d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066219822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2066219822
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1001660728
Short name T766
Test name
Test status
Simulation time 20489551799 ps
CPU time 10.28 seconds
Started May 14 01:00:57 PM PDT 24
Finished May 14 01:01:11 PM PDT 24
Peak memory 200376 kb
Host smart-0aacf96d-8bab-4b81-bc25-4ba90862b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001660728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1001660728
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1472334572
Short name T571
Test name
Test status
Simulation time 135367776700 ps
CPU time 182.09 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:03:58 PM PDT 24
Peak memory 200424 kb
Host smart-2697372b-d0cc-4d2d-8c43-c40211834719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472334572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1472334572
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2160885768
Short name T1114
Test name
Test status
Simulation time 89953200373 ps
CPU time 122.95 seconds
Started May 14 01:00:55 PM PDT 24
Finished May 14 01:03:03 PM PDT 24
Peak memory 200560 kb
Host smart-85c39222-1aaa-42ae-bbe4-462c367eaf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160885768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2160885768
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4092553615
Short name T591
Test name
Test status
Simulation time 138066233757 ps
CPU time 268.03 seconds
Started May 14 01:00:55 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 200480 kb
Host smart-d29ddbce-00ff-4d5f-808d-b212836c83c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092553615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4092553615
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2224568717
Short name T481
Test name
Test status
Simulation time 38188729695 ps
CPU time 74.05 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:02:09 PM PDT 24
Peak memory 200504 kb
Host smart-247c5ec1-508e-452c-ac52-8024ffa1fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224568717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2224568717
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4076038545
Short name T986
Test name
Test status
Simulation time 16898497903 ps
CPU time 21.06 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:16 PM PDT 24
Peak memory 200476 kb
Host smart-d62eac0f-0f4c-491d-8a10-93620c646e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076038545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4076038545
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3628090405
Short name T1024
Test name
Test status
Simulation time 100588566508 ps
CPU time 102.82 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:02:40 PM PDT 24
Peak memory 200488 kb
Host smart-f30b1aff-54ca-486f-8627-b39f406eae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628090405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3628090405
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1737868797
Short name T455
Test name
Test status
Simulation time 34219022597 ps
CPU time 55.22 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:01:58 PM PDT 24
Peak memory 200372 kb
Host smart-7a179a38-7bec-48c6-b3bd-11f4896abdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737868797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1737868797
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3669857941
Short name T582
Test name
Test status
Simulation time 118772588712 ps
CPU time 279.61 seconds
Started May 14 01:01:01 PM PDT 24
Finished May 14 01:05:44 PM PDT 24
Peak memory 200456 kb
Host smart-388067b6-fa63-44e0-b4de-6c51f58e54ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669857941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3669857941
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.315286325
Short name T867
Test name
Test status
Simulation time 36540843 ps
CPU time 0.57 seconds
Started May 14 12:57:35 PM PDT 24
Finished May 14 12:57:37 PM PDT 24
Peak memory 195844 kb
Host smart-6d56fb62-eed0-4bc0-aa0c-d43b28c36b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315286325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.315286325
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.243418315
Short name T35
Test name
Test status
Simulation time 34489186315 ps
CPU time 60.19 seconds
Started May 14 12:57:27 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 200484 kb
Host smart-dc800c86-4142-4cf1-87c7-ca310eed2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243418315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.243418315
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3745151718
Short name T900
Test name
Test status
Simulation time 21222485622 ps
CPU time 39.43 seconds
Started May 14 12:57:35 PM PDT 24
Finished May 14 12:58:16 PM PDT 24
Peak memory 200396 kb
Host smart-34e030d4-e3b0-494b-809a-4ea5ff0a385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745151718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3745151718
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.1888321516
Short name T517
Test name
Test status
Simulation time 19698591279 ps
CPU time 27.11 seconds
Started May 14 12:57:32 PM PDT 24
Finished May 14 12:58:01 PM PDT 24
Peak memory 199076 kb
Host smart-8519dad6-3da2-4735-a2d6-201cac350671
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888321516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1888321516
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3274869999
Short name T268
Test name
Test status
Simulation time 70716728859 ps
CPU time 422.41 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 01:04:37 PM PDT 24
Peak memory 200508 kb
Host smart-59157630-59aa-455b-8657-a71d58dfb995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274869999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3274869999
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1248232490
Short name T749
Test name
Test status
Simulation time 1830399879 ps
CPU time 1.43 seconds
Started May 14 12:57:35 PM PDT 24
Finished May 14 12:57:38 PM PDT 24
Peak memory 195956 kb
Host smart-1c5f95e7-3b11-4bd9-85f5-55726c847ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248232490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1248232490
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3902950862
Short name T913
Test name
Test status
Simulation time 127727443530 ps
CPU time 61.22 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:58:36 PM PDT 24
Peak memory 200716 kb
Host smart-bb2f47bd-e634-43d3-9264-4ab4d888900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902950862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3902950862
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3708885811
Short name T720
Test name
Test status
Simulation time 20684281121 ps
CPU time 224.24 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 01:01:18 PM PDT 24
Peak memory 200456 kb
Host smart-0851a8f2-837b-4bb0-8431-c6abdbb5327b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708885811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3708885811
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4018238112
Short name T723
Test name
Test status
Simulation time 5693314889 ps
CPU time 50.46 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:58:25 PM PDT 24
Peak memory 199552 kb
Host smart-8430279b-e015-425d-a62a-52e6ae6c1732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4018238112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4018238112
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.536864655
Short name T1064
Test name
Test status
Simulation time 77892055217 ps
CPU time 35.31 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 200408 kb
Host smart-04a53774-90f9-4e26-97b5-3c7374e4d41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536864655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.536864655
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3786025688
Short name T757
Test name
Test status
Simulation time 4726115258 ps
CPU time 4.11 seconds
Started May 14 12:57:35 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 196472 kb
Host smart-8f6dfd93-9928-4193-8687-98f222a8727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786025688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3786025688
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4224643219
Short name T1124
Test name
Test status
Simulation time 509789519 ps
CPU time 1.22 seconds
Started May 14 12:57:28 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 198720 kb
Host smart-929215cc-8be9-4c5c-9be2-a6d8533426ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224643219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4224643219
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3314183221
Short name T523
Test name
Test status
Simulation time 59981062891 ps
CPU time 111.03 seconds
Started May 14 12:57:39 PM PDT 24
Finished May 14 12:59:31 PM PDT 24
Peak memory 200404 kb
Host smart-5ae72954-57f5-4772-98fb-292c474aca9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314183221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3314183221
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1454882987
Short name T990
Test name
Test status
Simulation time 43034074189 ps
CPU time 201.36 seconds
Started May 14 12:57:32 PM PDT 24
Finished May 14 01:00:55 PM PDT 24
Peak memory 214212 kb
Host smart-18ed480e-7df1-45f0-beb6-a886947cd0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454882987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1454882987
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.63355159
Short name T384
Test name
Test status
Simulation time 369829891 ps
CPU time 1.48 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 199016 kb
Host smart-b8a0edf4-6f14-4b96-bcb8-93e1f2cbcc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63355159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.63355159
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3825220334
Short name T1017
Test name
Test status
Simulation time 37631585217 ps
CPU time 62.17 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 12:58:30 PM PDT 24
Peak memory 200516 kb
Host smart-dd0fbd68-4f8d-4943-ac7b-4f205c4a8962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825220334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3825220334
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2800188819
Short name T288
Test name
Test status
Simulation time 40218540644 ps
CPU time 66.18 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:02:09 PM PDT 24
Peak memory 200488 kb
Host smart-cd5f7fd4-6fe4-43a8-ae47-29ff73c8c4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800188819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2800188819
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3439043182
Short name T1101
Test name
Test status
Simulation time 29975014049 ps
CPU time 21.28 seconds
Started May 14 01:01:03 PM PDT 24
Finished May 14 01:01:27 PM PDT 24
Peak memory 200020 kb
Host smart-847ea89e-a1fa-402c-ab19-c07f22cc70e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439043182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3439043182
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3680299439
Short name T190
Test name
Test status
Simulation time 170603120032 ps
CPU time 407.01 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:07:50 PM PDT 24
Peak memory 200484 kb
Host smart-c270b695-dea7-4d83-8d4c-04d707d739fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680299439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3680299439
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2605445543
Short name T185
Test name
Test status
Simulation time 27755325526 ps
CPU time 11.85 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:01:14 PM PDT 24
Peak memory 200376 kb
Host smart-0265a4b5-611d-441e-a775-805a22774481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605445543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2605445543
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2335407997
Short name T920
Test name
Test status
Simulation time 16575267689 ps
CPU time 15.21 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:01:18 PM PDT 24
Peak memory 200260 kb
Host smart-3d861279-9762-46a6-ae98-2d1f23fbbf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335407997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2335407997
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1716287510
Short name T689
Test name
Test status
Simulation time 131609430789 ps
CPU time 344.34 seconds
Started May 14 01:01:01 PM PDT 24
Finished May 14 01:06:49 PM PDT 24
Peak memory 200468 kb
Host smart-092304b9-c145-469e-bd1b-8715a7bb2954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716287510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1716287510
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2735787487
Short name T1069
Test name
Test status
Simulation time 21802564268 ps
CPU time 5.23 seconds
Started May 14 01:01:04 PM PDT 24
Finished May 14 01:01:12 PM PDT 24
Peak memory 200436 kb
Host smart-1de93ad1-0960-4262-ac37-bcd10cd5b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735787487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2735787487
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.725918
Short name T131
Test name
Test status
Simulation time 11412405891 ps
CPU time 17.76 seconds
Started May 14 01:01:03 PM PDT 24
Finished May 14 01:01:24 PM PDT 24
Peak memory 200436 kb
Host smart-c3b4811a-ba18-49c6-b93a-8805fe31a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.725918
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2259110236
Short name T1025
Test name
Test status
Simulation time 174527634384 ps
CPU time 91.48 seconds
Started May 14 01:01:03 PM PDT 24
Finished May 14 01:02:38 PM PDT 24
Peak memory 200480 kb
Host smart-dcc64d3d-0daf-4f1a-ab43-cd9f55235e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259110236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2259110236
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3931399122
Short name T869
Test name
Test status
Simulation time 20108987 ps
CPU time 0.58 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:57:40 PM PDT 24
Peak memory 195884 kb
Host smart-50bd16ac-6840-4c26-a20d-2c57881557ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931399122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3931399122
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2463506272
Short name T899
Test name
Test status
Simulation time 195486207446 ps
CPU time 134.12 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:59:49 PM PDT 24
Peak memory 200368 kb
Host smart-0bee136a-d704-44f7-92ed-32f2a8c877b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463506272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2463506272
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3189570220
Short name T254
Test name
Test status
Simulation time 252233131148 ps
CPU time 55.22 seconds
Started May 14 12:57:32 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 200396 kb
Host smart-b992d30a-f508-4c8f-b9aa-c9a7b9fc5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189570220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3189570220
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2887233459
Short name T317
Test name
Test status
Simulation time 28390283975 ps
CPU time 16.31 seconds
Started May 14 12:57:36 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 200408 kb
Host smart-d2e5830d-1410-4588-b05c-ec06c01e4a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887233459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2887233459
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3248001968
Short name T452
Test name
Test status
Simulation time 26202177357 ps
CPU time 21.08 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:57:55 PM PDT 24
Peak memory 200444 kb
Host smart-3f5e2303-8da2-458f-b5bd-89fc1764c4d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248001968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3248001968
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1642233309
Short name T1001
Test name
Test status
Simulation time 83765681556 ps
CPU time 190.76 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 01:00:45 PM PDT 24
Peak memory 200440 kb
Host smart-445aa5e7-19e3-466e-b49a-60443194fdd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642233309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1642233309
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1543268791
Short name T963
Test name
Test status
Simulation time 5144469386 ps
CPU time 6.41 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 200484 kb
Host smart-f5e4191e-ddce-4a90-8358-b465fea6d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543268791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1543268791
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.4178374428
Short name T1164
Test name
Test status
Simulation time 176301956778 ps
CPU time 37.57 seconds
Started May 14 12:57:36 PM PDT 24
Finished May 14 12:58:15 PM PDT 24
Peak memory 200724 kb
Host smart-5796fbcb-a6ed-4c0f-8007-0d1b7ef7685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178374428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4178374428
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.838251103
Short name T1108
Test name
Test status
Simulation time 12762181276 ps
CPU time 186.22 seconds
Started May 14 12:57:32 PM PDT 24
Finished May 14 01:00:40 PM PDT 24
Peak memory 200408 kb
Host smart-929280f5-51ad-4e6a-aaee-00d34bf0372f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838251103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.838251103
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1908024340
Short name T1085
Test name
Test status
Simulation time 3869940134 ps
CPU time 12.83 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:57:47 PM PDT 24
Peak memory 198808 kb
Host smart-2d70e942-0d8f-438a-bac4-9a9c3bf840e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908024340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1908024340
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.67735780
Short name T1074
Test name
Test status
Simulation time 112985932524 ps
CPU time 185.6 seconds
Started May 14 12:57:34 PM PDT 24
Finished May 14 01:00:41 PM PDT 24
Peak memory 200716 kb
Host smart-cab5c3fb-a088-4e82-9874-91b6beb1b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67735780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.67735780
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3751220932
Short name T980
Test name
Test status
Simulation time 3585679186 ps
CPU time 6.2 seconds
Started May 14 12:57:34 PM PDT 24
Finished May 14 12:57:42 PM PDT 24
Peak memory 196440 kb
Host smart-2830652d-657b-42d2-b7af-03faac67d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751220932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3751220932
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2406700366
Short name T425
Test name
Test status
Simulation time 109911097 ps
CPU time 0.98 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 199620 kb
Host smart-0eda866a-2279-4a07-8f5e-4a48bc7eb1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406700366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2406700366
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3508181285
Short name T31
Test name
Test status
Simulation time 33143195676 ps
CPU time 96.85 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:59:16 PM PDT 24
Peak memory 216940 kb
Host smart-c02bb762-2d51-4a94-929c-fca105395ded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508181285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3508181285
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2942724444
Short name T437
Test name
Test status
Simulation time 1833193026 ps
CPU time 2.7 seconds
Started May 14 12:57:33 PM PDT 24
Finished May 14 12:57:37 PM PDT 24
Peak memory 199452 kb
Host smart-7c895afa-527b-4865-a034-61ea5e9fcf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942724444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2942724444
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2576424996
Short name T1122
Test name
Test status
Simulation time 92841590075 ps
CPU time 46.7 seconds
Started May 14 12:57:35 PM PDT 24
Finished May 14 12:58:23 PM PDT 24
Peak memory 200556 kb
Host smart-858ff7a6-85d3-4690-bd17-9414718d0b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576424996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2576424996
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3069496999
Short name T1037
Test name
Test status
Simulation time 71077907404 ps
CPU time 318.9 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:06:22 PM PDT 24
Peak memory 200500 kb
Host smart-e38d3eb8-53f4-46d7-b82c-79a78e34d292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069496999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3069496999
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1193811870
Short name T846
Test name
Test status
Simulation time 126333373509 ps
CPU time 198.6 seconds
Started May 14 01:01:01 PM PDT 24
Finished May 14 01:04:23 PM PDT 24
Peak memory 200404 kb
Host smart-94d3ebf4-06f4-46c6-ba8a-f1d32c289c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193811870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1193811870
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.4293242325
Short name T207
Test name
Test status
Simulation time 154370519550 ps
CPU time 116.01 seconds
Started May 14 01:01:03 PM PDT 24
Finished May 14 01:03:02 PM PDT 24
Peak memory 200548 kb
Host smart-37a0f844-5fc9-4455-af31-09641af1a5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293242325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.4293242325
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.990192478
Short name T531
Test name
Test status
Simulation time 98692309053 ps
CPU time 44.3 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:01:47 PM PDT 24
Peak memory 200464 kb
Host smart-085a3088-2de4-410c-b221-3151cb6c7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990192478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.990192478
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1808366806
Short name T98
Test name
Test status
Simulation time 116855088694 ps
CPU time 90.26 seconds
Started May 14 01:01:00 PM PDT 24
Finished May 14 01:02:34 PM PDT 24
Peak memory 200428 kb
Host smart-3af9fa71-7ca7-42d6-b924-a52ec7634464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808366806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1808366806
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1414358327
Short name T267
Test name
Test status
Simulation time 136748899168 ps
CPU time 61.28 seconds
Started May 14 01:01:00 PM PDT 24
Finished May 14 01:02:04 PM PDT 24
Peak memory 200428 kb
Host smart-ce8d72c4-ea63-4bfb-9239-e172dcfe438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414358327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1414358327
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3870551453
Short name T750
Test name
Test status
Simulation time 84694772455 ps
CPU time 123.62 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:03:06 PM PDT 24
Peak memory 200536 kb
Host smart-cf1e887b-2166-4edc-8c03-347903e25bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870551453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3870551453
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1842780909
Short name T1062
Test name
Test status
Simulation time 58060777410 ps
CPU time 109.46 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:02:52 PM PDT 24
Peak memory 200436 kb
Host smart-c9886731-2160-44b1-948d-8b61fbc0e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842780909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1842780909
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4155958780
Short name T513
Test name
Test status
Simulation time 158119465042 ps
CPU time 132.63 seconds
Started May 14 01:01:04 PM PDT 24
Finished May 14 01:03:19 PM PDT 24
Peak memory 200496 kb
Host smart-d55f52f4-8e76-4f25-80bd-a56c1ba04499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155958780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4155958780
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2328928704
Short name T344
Test name
Test status
Simulation time 50053860293 ps
CPU time 24.5 seconds
Started May 14 01:01:03 PM PDT 24
Finished May 14 01:01:31 PM PDT 24
Peak memory 200424 kb
Host smart-33ad276a-c32c-4ae0-8f84-b8a7060f526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328928704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2328928704
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2504026610
Short name T371
Test name
Test status
Simulation time 15565704 ps
CPU time 0.55 seconds
Started May 14 12:57:39 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 196060 kb
Host smart-83ae1623-be40-4c03-a027-09d64fd39712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504026610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2504026610
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.539072596
Short name T801
Test name
Test status
Simulation time 76602055958 ps
CPU time 125.42 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:59:45 PM PDT 24
Peak memory 200396 kb
Host smart-a4828ce1-92e8-4d28-9f46-f4835d6f461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539072596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.539072596
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2040480330
Short name T1019
Test name
Test status
Simulation time 56747845791 ps
CPU time 112.31 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 12:59:34 PM PDT 24
Peak memory 200452 kb
Host smart-56d9d82d-92aa-46e6-a577-8458ca225620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040480330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2040480330
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.577880169
Short name T406
Test name
Test status
Simulation time 178676754203 ps
CPU time 87.56 seconds
Started May 14 12:57:49 PM PDT 24
Finished May 14 12:59:19 PM PDT 24
Peak memory 200288 kb
Host smart-ae328763-9884-4013-b1ed-0709d497486f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577880169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.577880169
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.70177268
Short name T567
Test name
Test status
Simulation time 159001990671 ps
CPU time 575.77 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 01:07:17 PM PDT 24
Peak memory 200348 kb
Host smart-18bacc37-cd18-4661-a1c2-ecf760cff25f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70177268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.70177268
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2907857021
Short name T459
Test name
Test status
Simulation time 4167177329 ps
CPU time 1.7 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 12:57:44 PM PDT 24
Peak memory 198204 kb
Host smart-b51718b3-aaa6-4126-abd1-a6db7ebf6a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907857021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2907857021
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.293982789
Short name T573
Test name
Test status
Simulation time 97434344158 ps
CPU time 138.76 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 01:00:00 PM PDT 24
Peak memory 199884 kb
Host smart-44f763e7-4cf9-42d2-a59d-38f6c23fb1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293982789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.293982789
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1465129443
Short name T253
Test name
Test status
Simulation time 10622727616 ps
CPU time 164.88 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 01:00:27 PM PDT 24
Peak memory 200464 kb
Host smart-91c64574-5795-4a83-87a4-887ec08b2149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465129443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1465129443
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.501752054
Short name T1157
Test name
Test status
Simulation time 6261792933 ps
CPU time 54.29 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:58:34 PM PDT 24
Peak memory 199856 kb
Host smart-cbccac60-5817-4ca8-b4f4-58cd89ecf524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501752054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.501752054
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.304776844
Short name T601
Test name
Test status
Simulation time 30809890346 ps
CPU time 36.87 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 12:58:19 PM PDT 24
Peak memory 200452 kb
Host smart-75203678-687e-4464-a6ba-56c45f50ef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304776844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.304776844
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.293810839
Short name T366
Test name
Test status
Simulation time 42085325753 ps
CPU time 15.74 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 196468 kb
Host smart-7b019766-f183-4dbf-9249-7dca324087bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293810839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.293810839
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1995805311
Short name T707
Test name
Test status
Simulation time 473150616 ps
CPU time 2 seconds
Started May 14 12:57:49 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 198648 kb
Host smart-45d2c8ac-cfd2-459b-891a-5bede5d106a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995805311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1995805311
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3558921619
Short name T672
Test name
Test status
Simulation time 107592060334 ps
CPU time 373.78 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 01:03:55 PM PDT 24
Peak memory 200480 kb
Host smart-3efea1bd-bb3f-4b1c-9a78-8c1b3de9d7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558921619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3558921619
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2313017187
Short name T752
Test name
Test status
Simulation time 6329978672 ps
CPU time 12.5 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 12:57:55 PM PDT 24
Peak memory 200248 kb
Host smart-062c375a-b750-4519-855d-bdc9686091e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313017187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2313017187
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2863335866
Short name T276
Test name
Test status
Simulation time 7854528539 ps
CPU time 15.17 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:57:54 PM PDT 24
Peak memory 200360 kb
Host smart-803d357f-0643-4c0b-9c74-f98596e44189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863335866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2863335866
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.547635810
Short name T738
Test name
Test status
Simulation time 185978056290 ps
CPU time 339.48 seconds
Started May 14 01:00:59 PM PDT 24
Finished May 14 01:06:42 PM PDT 24
Peak memory 200548 kb
Host smart-11a7ab07-f6b8-4fb0-a705-baef2a8bc880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547635810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.547635810
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3053502685
Short name T1072
Test name
Test status
Simulation time 107676329370 ps
CPU time 411.23 seconds
Started May 14 01:01:01 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 200504 kb
Host smart-af1f62a4-d876-4241-91ab-a5f3d43b3232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053502685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3053502685
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.539859844
Short name T706
Test name
Test status
Simulation time 35367299507 ps
CPU time 24.94 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:35 PM PDT 24
Peak memory 200424 kb
Host smart-42a74503-e851-4c1d-ae7a-b28ab5dfcb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539859844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.539859844
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1662803489
Short name T1081
Test name
Test status
Simulation time 196517045984 ps
CPU time 127.77 seconds
Started May 14 01:01:12 PM PDT 24
Finished May 14 01:03:22 PM PDT 24
Peak memory 200460 kb
Host smart-44a1e556-b9d9-4a41-bb60-69b36b104781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662803489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1662803489
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4025204554
Short name T409
Test name
Test status
Simulation time 37004446632 ps
CPU time 41.46 seconds
Started May 14 01:01:08 PM PDT 24
Finished May 14 01:01:51 PM PDT 24
Peak memory 200468 kb
Host smart-7df8f35f-940a-4126-bae0-b511597eaf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025204554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4025204554
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2962927662
Short name T363
Test name
Test status
Simulation time 12469634572 ps
CPU time 5.89 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:17 PM PDT 24
Peak memory 200424 kb
Host smart-2fac21f3-9434-40d1-abf1-878d12f9c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962927662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2962927662
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2248108766
Short name T991
Test name
Test status
Simulation time 171450551175 ps
CPU time 60.57 seconds
Started May 14 01:01:11 PM PDT 24
Finished May 14 01:02:13 PM PDT 24
Peak memory 200512 kb
Host smart-4bf2ed0f-ffa5-455f-b961-880c6dc11668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248108766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2248108766
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.427816847
Short name T1047
Test name
Test status
Simulation time 78676369774 ps
CPU time 37.18 seconds
Started May 14 01:01:08 PM PDT 24
Finished May 14 01:01:46 PM PDT 24
Peak memory 200352 kb
Host smart-216b56bf-fd8a-4bfa-aec9-174c39aad45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427816847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.427816847
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.529015497
Short name T3
Test name
Test status
Simulation time 155480184843 ps
CPU time 44.2 seconds
Started May 14 01:01:13 PM PDT 24
Finished May 14 01:02:00 PM PDT 24
Peak memory 199624 kb
Host smart-af49e2de-68a9-4872-a9f5-49d393dee4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529015497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.529015497
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2435987028
Short name T1136
Test name
Test status
Simulation time 52242511 ps
CPU time 0.55 seconds
Started May 14 12:57:43 PM PDT 24
Finished May 14 12:57:45 PM PDT 24
Peak memory 195864 kb
Host smart-a2c98b1a-3601-4cc5-a83d-03447b68487a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435987028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2435987028
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3258917324
Short name T772
Test name
Test status
Simulation time 113332733525 ps
CPU time 200.67 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 01:01:04 PM PDT 24
Peak memory 200464 kb
Host smart-9943ddee-1090-4b40-949e-10f504c6a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258917324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3258917324
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1688248514
Short name T128
Test name
Test status
Simulation time 49514752820 ps
CPU time 43.3 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 12:58:24 PM PDT 24
Peak memory 200384 kb
Host smart-8879919a-eb4f-4866-b548-276125530272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688248514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1688248514
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3955626077
Short name T399
Test name
Test status
Simulation time 11228701874 ps
CPU time 4.93 seconds
Started May 14 12:57:37 PM PDT 24
Finished May 14 12:57:43 PM PDT 24
Peak memory 197620 kb
Host smart-638b7749-aa6b-4e60-b5cd-d403d00e491b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955626077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3955626077
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_loopback.2043672802
Short name T807
Test name
Test status
Simulation time 3755744449 ps
CPU time 6.4 seconds
Started May 14 12:57:51 PM PDT 24
Finished May 14 12:57:59 PM PDT 24
Peak memory 197156 kb
Host smart-39d4cc1f-06a7-4be3-85b2-cc844feb16fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043672802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2043672802
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.547112622
Short name T974
Test name
Test status
Simulation time 451679849895 ps
CPU time 72.84 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:58:52 PM PDT 24
Peak memory 200948 kb
Host smart-559b3649-f58a-4819-9343-f84efb9204b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547112622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.547112622
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.181309869
Short name T296
Test name
Test status
Simulation time 15021657494 ps
CPU time 747.79 seconds
Started May 14 12:57:39 PM PDT 24
Finished May 14 01:10:09 PM PDT 24
Peak memory 200408 kb
Host smart-489ab01e-885a-435e-bfd2-22aeb849c18a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181309869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.181309869
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2449567240
Short name T840
Test name
Test status
Simulation time 7511126479 ps
CPU time 16.23 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 12:57:59 PM PDT 24
Peak memory 200220 kb
Host smart-e9ef119b-85fc-4eb6-bc54-f2dd770e3305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449567240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2449567240
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.828605612
Short name T1028
Test name
Test status
Simulation time 71068114566 ps
CPU time 31.31 seconds
Started May 14 12:57:39 PM PDT 24
Finished May 14 12:58:12 PM PDT 24
Peak memory 199952 kb
Host smart-c38491c8-2418-4ac5-b0cd-46c06be08dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828605612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.828605612
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1935374870
Short name T11
Test name
Test status
Simulation time 2087561917 ps
CPU time 1.49 seconds
Started May 14 12:57:37 PM PDT 24
Finished May 14 12:57:40 PM PDT 24
Peak memory 195812 kb
Host smart-e57e410f-8c38-40d6-b6f5-a18b75d09c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935374870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1935374870
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2461810944
Short name T814
Test name
Test status
Simulation time 6283719327 ps
CPU time 20.79 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 200324 kb
Host smart-c15019da-d343-4f33-9678-38970ef8c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461810944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2461810944
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1707820806
Short name T629
Test name
Test status
Simulation time 240711165001 ps
CPU time 425.2 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 01:04:44 PM PDT 24
Peak memory 208952 kb
Host smart-b34d9439-0ba2-4f32-8514-9db50ca2ef55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707820806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1707820806
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.668319020
Short name T489
Test name
Test status
Simulation time 77233947628 ps
CPU time 265.9 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 01:02:08 PM PDT 24
Peak memory 215868 kb
Host smart-e7012f5a-4d95-4dc1-8405-0725a040593e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668319020 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.668319020
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2474975678
Short name T743
Test name
Test status
Simulation time 1145982576 ps
CPU time 1.49 seconds
Started May 14 12:57:39 PM PDT 24
Finished May 14 12:57:42 PM PDT 24
Peak memory 198652 kb
Host smart-3bd0ff81-ebaf-4509-99a4-e49fb3e78a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474975678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2474975678
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1679734548
Short name T1162
Test name
Test status
Simulation time 16576836421 ps
CPU time 28.29 seconds
Started May 14 12:57:38 PM PDT 24
Finished May 14 12:58:08 PM PDT 24
Peak memory 200472 kb
Host smart-865e5958-9977-4690-b21b-b33f0a489118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679734548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1679734548
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.610616431
Short name T227
Test name
Test status
Simulation time 24154563934 ps
CPU time 41.04 seconds
Started May 14 01:01:13 PM PDT 24
Finished May 14 01:01:57 PM PDT 24
Peak memory 200480 kb
Host smart-35a00e13-d905-466b-98d4-2ac30336f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610616431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.610616431
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.878299448
Short name T1013
Test name
Test status
Simulation time 88698956501 ps
CPU time 147.38 seconds
Started May 14 01:01:10 PM PDT 24
Finished May 14 01:03:40 PM PDT 24
Peak memory 200504 kb
Host smart-9599b7f1-9360-48c2-9d67-0fc3b5aa052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878299448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.878299448
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.503437438
Short name T154
Test name
Test status
Simulation time 76297668295 ps
CPU time 35.96 seconds
Started May 14 01:01:10 PM PDT 24
Finished May 14 01:01:48 PM PDT 24
Peak memory 200428 kb
Host smart-e3d5e2d6-9454-4050-93ae-a34bc22e87af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503437438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.503437438
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3855951243
Short name T853
Test name
Test status
Simulation time 162706684500 ps
CPU time 15.08 seconds
Started May 14 01:01:10 PM PDT 24
Finished May 14 01:01:27 PM PDT 24
Peak memory 200488 kb
Host smart-cec396e9-347e-4199-abbd-e48668a356fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855951243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3855951243
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2454005810
Short name T1131
Test name
Test status
Simulation time 114775128676 ps
CPU time 139.12 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:03:29 PM PDT 24
Peak memory 200480 kb
Host smart-ddb6e590-2a7f-4f91-b89a-2c1fe19f1dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454005810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2454005810
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1803815551
Short name T987
Test name
Test status
Simulation time 18571843139 ps
CPU time 10.45 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:21 PM PDT 24
Peak memory 200428 kb
Host smart-c64ea4dc-1ca2-415b-b1e2-cc2a5d7e012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803815551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1803815551
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2397402886
Short name T908
Test name
Test status
Simulation time 153544276381 ps
CPU time 267.87 seconds
Started May 14 01:01:13 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 199828 kb
Host smart-1d215da7-b434-404b-9e00-633294691d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397402886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2397402886
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1728103431
Short name T176
Test name
Test status
Simulation time 5510652440 ps
CPU time 10.78 seconds
Started May 14 01:01:13 PM PDT 24
Finished May 14 01:01:26 PM PDT 24
Peak memory 200464 kb
Host smart-36599106-6304-42bd-9230-4f1775283078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728103431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1728103431
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.676589620
Short name T486
Test name
Test status
Simulation time 19416603011 ps
CPU time 7.91 seconds
Started May 14 12:57:48 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 200240 kb
Host smart-22f0a993-50c7-4ea3-a9ed-1b31df789c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676589620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.676589620
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2958737879
Short name T655
Test name
Test status
Simulation time 40319861088 ps
CPU time 71.66 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:59:07 PM PDT 24
Peak memory 200500 kb
Host smart-e0a9efa8-fba3-42b4-b25b-75b2a4fbd0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958737879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2958737879
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2396653459
Short name T491
Test name
Test status
Simulation time 42453845235 ps
CPU time 20.33 seconds
Started May 14 12:57:45 PM PDT 24
Finished May 14 12:58:07 PM PDT 24
Peak memory 200360 kb
Host smart-7a723c86-b29d-4875-92ec-05fbc904c880
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396653459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2396653459
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2587230094
Short name T696
Test name
Test status
Simulation time 124886599505 ps
CPU time 702.41 seconds
Started May 14 12:57:45 PM PDT 24
Finished May 14 01:09:28 PM PDT 24
Peak memory 200376 kb
Host smart-f1a81c6a-59cc-489e-b29a-6e1fb87d039c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587230094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2587230094
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2873416969
Short name T640
Test name
Test status
Simulation time 80687284 ps
CPU time 0.62 seconds
Started May 14 12:57:44 PM PDT 24
Finished May 14 12:57:46 PM PDT 24
Peak memory 196272 kb
Host smart-b642a43e-4e80-48d6-837f-4f64c5001e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873416969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2873416969
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3313293891
Short name T701
Test name
Test status
Simulation time 30380197324 ps
CPU time 65.07 seconds
Started May 14 12:57:46 PM PDT 24
Finished May 14 12:58:52 PM PDT 24
Peak memory 200624 kb
Host smart-82a8fedb-c0e9-42c7-9a68-1d60b178522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313293891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3313293891
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.176416722
Short name T258
Test name
Test status
Simulation time 7063911012 ps
CPU time 45.47 seconds
Started May 14 12:57:46 PM PDT 24
Finished May 14 12:58:33 PM PDT 24
Peak memory 200504 kb
Host smart-6de3ab80-1e8d-41f7-a60a-48383cd507c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176416722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.176416722
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.640123056
Short name T1175
Test name
Test status
Simulation time 5922972131 ps
CPU time 47.71 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:58:41 PM PDT 24
Peak memory 199060 kb
Host smart-728abdd0-b9fa-42e6-8911-88d9b67358f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640123056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.640123056
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2587522510
Short name T679
Test name
Test status
Simulation time 222450368642 ps
CPU time 430.36 seconds
Started May 14 12:57:49 PM PDT 24
Finished May 14 01:05:02 PM PDT 24
Peak memory 200504 kb
Host smart-6564190c-9584-44c1-9a1c-ea82aa75517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587522510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2587522510
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1574040132
Short name T2
Test name
Test status
Simulation time 40977256688 ps
CPU time 22.39 seconds
Started May 14 12:57:45 PM PDT 24
Finished May 14 12:58:08 PM PDT 24
Peak memory 196176 kb
Host smart-b78f0779-ae27-4e2c-a1e9-9022e227a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574040132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1574040132
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1613589671
Short name T777
Test name
Test status
Simulation time 1019668170 ps
CPU time 1.1 seconds
Started May 14 12:57:41 PM PDT 24
Finished May 14 12:57:44 PM PDT 24
Peak memory 198888 kb
Host smart-f8b90b41-cba3-4034-8d8a-42b2fa9a32cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613589671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1613589671
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3089208517
Short name T1147
Test name
Test status
Simulation time 114097438087 ps
CPU time 215.08 seconds
Started May 14 12:57:46 PM PDT 24
Finished May 14 01:01:22 PM PDT 24
Peak memory 217032 kb
Host smart-4fd0ce45-f9cb-4ca0-9f76-8f3df010ccf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089208517 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3089208517
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2478087551
Short name T979
Test name
Test status
Simulation time 2997372934 ps
CPU time 2.95 seconds
Started May 14 12:57:45 PM PDT 24
Finished May 14 12:57:49 PM PDT 24
Peak memory 199516 kb
Host smart-72a42f07-6ac9-4406-a34a-1925f2e69848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478087551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2478087551
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3125213873
Short name T649
Test name
Test status
Simulation time 59679794260 ps
CPU time 29.29 seconds
Started May 14 12:57:40 PM PDT 24
Finished May 14 12:58:11 PM PDT 24
Peak memory 200416 kb
Host smart-2ac5ed60-fc67-4b52-88e4-fc72241c86d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125213873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3125213873
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3402500348
Short name T228
Test name
Test status
Simulation time 23898456611 ps
CPU time 40.31 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:51 PM PDT 24
Peak memory 200432 kb
Host smart-894f919a-b685-4ebf-995a-a780f06cb8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402500348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3402500348
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3487781002
Short name T834
Test name
Test status
Simulation time 112561496935 ps
CPU time 24.45 seconds
Started May 14 01:01:09 PM PDT 24
Finished May 14 01:01:35 PM PDT 24
Peak memory 200396 kb
Host smart-841a689e-6035-441d-b397-3fb3fb455a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487781002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3487781002
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3583146388
Short name T420
Test name
Test status
Simulation time 24631610952 ps
CPU time 41.54 seconds
Started May 14 01:01:22 PM PDT 24
Finished May 14 01:02:06 PM PDT 24
Peak memory 200396 kb
Host smart-dbf331fa-3bc4-4034-bb34-966ac1daa66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583146388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3583146388
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2154049059
Short name T286
Test name
Test status
Simulation time 12629557992 ps
CPU time 24.92 seconds
Started May 14 01:01:21 PM PDT 24
Finished May 14 01:01:49 PM PDT 24
Peak memory 200456 kb
Host smart-13177ee8-c69c-4886-98c2-84295face6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154049059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2154049059
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.940986689
Short name T621
Test name
Test status
Simulation time 56086570657 ps
CPU time 59.77 seconds
Started May 14 01:01:20 PM PDT 24
Finished May 14 01:02:23 PM PDT 24
Peak memory 200404 kb
Host smart-337cc31a-e987-4c3c-9304-8aa4d4ec762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940986689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.940986689
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3420853832
Short name T182
Test name
Test status
Simulation time 143353872504 ps
CPU time 28.23 seconds
Started May 14 01:01:16 PM PDT 24
Finished May 14 01:01:47 PM PDT 24
Peak memory 200484 kb
Host smart-a7cff203-f338-4843-a421-db3c6ba78b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420853832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3420853832
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1079992385
Short name T905
Test name
Test status
Simulation time 84328067106 ps
CPU time 85.12 seconds
Started May 14 01:01:22 PM PDT 24
Finished May 14 01:02:50 PM PDT 24
Peak memory 200528 kb
Host smart-eb1966de-c18e-49bd-8a8d-45097a9dc975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079992385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1079992385
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.333426896
Short name T710
Test name
Test status
Simulation time 27363251823 ps
CPU time 17.54 seconds
Started May 14 01:01:18 PM PDT 24
Finished May 14 01:01:39 PM PDT 24
Peak memory 200456 kb
Host smart-ee140882-82cf-45e7-bf59-5477fba17cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333426896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.333426896
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3628597472
Short name T1153
Test name
Test status
Simulation time 6429679625 ps
CPU time 11.43 seconds
Started May 14 01:01:26 PM PDT 24
Finished May 14 01:01:39 PM PDT 24
Peak memory 200128 kb
Host smart-a5cb85a7-7637-468b-8022-37928c0b70ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628597472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3628597472
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.607826053
Short name T361
Test name
Test status
Simulation time 11778122 ps
CPU time 0.63 seconds
Started May 14 12:57:47 PM PDT 24
Finished May 14 12:57:50 PM PDT 24
Peak memory 195896 kb
Host smart-52144af6-c109-452e-bb1d-306a2d52cf80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607826053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.607826053
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2203841662
Short name T1144
Test name
Test status
Simulation time 212033389626 ps
CPU time 196.06 seconds
Started May 14 12:57:47 PM PDT 24
Finished May 14 01:01:05 PM PDT 24
Peak memory 200388 kb
Host smart-3e862952-9225-42f4-b151-db6313ccfeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203841662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2203841662
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2470460989
Short name T116
Test name
Test status
Simulation time 44976910100 ps
CPU time 66.26 seconds
Started May 14 12:57:46 PM PDT 24
Finished May 14 12:58:53 PM PDT 24
Peak memory 200456 kb
Host smart-47cd5652-a839-4d5f-a964-bc204749e8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470460989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2470460989
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3793874785
Short name T520
Test name
Test status
Simulation time 167833392193 ps
CPU time 73.85 seconds
Started May 14 12:57:45 PM PDT 24
Finished May 14 12:59:00 PM PDT 24
Peak memory 200404 kb
Host smart-b836b7ee-a478-44cb-a19d-79dc5b54d88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793874785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3793874785
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2144194208
Short name T811
Test name
Test status
Simulation time 12923437966 ps
CPU time 5.81 seconds
Started May 14 12:57:46 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 197104 kb
Host smart-0a109eeb-5968-459a-86ae-e7a057a1fcbe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144194208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2144194208
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2760640112
Short name T732
Test name
Test status
Simulation time 178957772787 ps
CPU time 549.58 seconds
Started May 14 12:57:48 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 200448 kb
Host smart-0f3daa1b-b317-4164-bfcf-b60a95db329b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760640112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2760640112
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2579724872
Short name T20
Test name
Test status
Simulation time 3833809586 ps
CPU time 9.28 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 198792 kb
Host smart-a74d7e74-9cc2-466c-b772-f64bdfa42ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579724872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2579724872
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3647647146
Short name T962
Test name
Test status
Simulation time 24651456544 ps
CPU time 36.37 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:58:32 PM PDT 24
Peak memory 200708 kb
Host smart-a10841a7-c961-4ac4-9c92-04d3b5ee5224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647647146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3647647146
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.813396291
Short name T822
Test name
Test status
Simulation time 11422243291 ps
CPU time 51.72 seconds
Started May 14 12:57:49 PM PDT 24
Finished May 14 12:58:42 PM PDT 24
Peak memory 200528 kb
Host smart-44e02eaa-b5e3-4b74-ab0e-0f5832e4de85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813396291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.813396291
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2491803411
Short name T378
Test name
Test status
Simulation time 7244307245 ps
CPU time 12.13 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:58:06 PM PDT 24
Peak memory 198692 kb
Host smart-9c63cc05-cb96-4efc-aedc-69295eab6299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491803411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2491803411
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2646155529
Short name T880
Test name
Test status
Simulation time 65626700924 ps
CPU time 200.67 seconds
Started May 14 12:57:47 PM PDT 24
Finished May 14 01:01:10 PM PDT 24
Peak memory 200396 kb
Host smart-f9733482-c5eb-43ce-af48-fb297c011ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646155529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2646155529
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1491272450
Short name T307
Test name
Test status
Simulation time 6458675193 ps
CPU time 10.89 seconds
Started May 14 12:57:45 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 196464 kb
Host smart-0e349b8a-9384-47e9-8542-8e8ffcc69069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491272450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1491272450
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4176053022
Short name T847
Test name
Test status
Simulation time 655867968 ps
CPU time 2.04 seconds
Started May 14 12:57:49 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 199660 kb
Host smart-2c64c4a8-c0c3-44da-8609-e0f85fc61727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176053022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4176053022
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1402944281
Short name T911
Test name
Test status
Simulation time 342738641485 ps
CPU time 641.01 seconds
Started May 14 12:57:44 PM PDT 24
Finished May 14 01:08:26 PM PDT 24
Peak memory 200420 kb
Host smart-e86bdf68-0f90-4983-b3ae-c568c2dfd93a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402944281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1402944281
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4085792663
Short name T472
Test name
Test status
Simulation time 8084375554 ps
CPU time 9.77 seconds
Started May 14 12:57:47 PM PDT 24
Finished May 14 12:57:58 PM PDT 24
Peak memory 199724 kb
Host smart-da621ae3-81da-4570-9b67-26dbca50fa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085792663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4085792663
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.109592830
Short name T776
Test name
Test status
Simulation time 34160031776 ps
CPU time 28.97 seconds
Started May 14 12:57:46 PM PDT 24
Finished May 14 12:58:17 PM PDT 24
Peak memory 200444 kb
Host smart-ad56b75c-f3d4-4951-9a33-cca311187e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109592830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.109592830
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1683077316
Short name T788
Test name
Test status
Simulation time 20687674199 ps
CPU time 20.92 seconds
Started May 14 01:01:21 PM PDT 24
Finished May 14 01:01:45 PM PDT 24
Peak memory 200488 kb
Host smart-fec74596-92fb-4645-9699-8acbad40976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683077316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1683077316
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3002639159
Short name T1168
Test name
Test status
Simulation time 145984712950 ps
CPU time 59.9 seconds
Started May 14 01:01:18 PM PDT 24
Finished May 14 01:02:21 PM PDT 24
Peak memory 200420 kb
Host smart-7e3d6945-1130-4b43-bb6a-cb8dbb0e1563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002639159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3002639159
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2609433016
Short name T453
Test name
Test status
Simulation time 15710361405 ps
CPU time 12.63 seconds
Started May 14 01:01:17 PM PDT 24
Finished May 14 01:01:32 PM PDT 24
Peak memory 200004 kb
Host smart-221fb4cf-6909-4662-8527-1dc80ee4db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609433016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2609433016
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2647116762
Short name T200
Test name
Test status
Simulation time 16186657644 ps
CPU time 23.96 seconds
Started May 14 01:01:21 PM PDT 24
Finished May 14 01:01:48 PM PDT 24
Peak memory 200440 kb
Host smart-77f89b74-aeae-4a89-8861-635b5b0ec49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647116762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2647116762
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3785928412
Short name T1179
Test name
Test status
Simulation time 28794821309 ps
CPU time 53.9 seconds
Started May 14 01:01:22 PM PDT 24
Finished May 14 01:02:18 PM PDT 24
Peak memory 200504 kb
Host smart-b191764f-9392-4fc5-b2a6-6c6d7e4c755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785928412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3785928412
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.592743757
Short name T968
Test name
Test status
Simulation time 83142356835 ps
CPU time 33.11 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:01:55 PM PDT 24
Peak memory 200356 kb
Host smart-f9fcb459-bd25-4fd2-9c2b-29263baa8732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592743757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.592743757
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3795070900
Short name T904
Test name
Test status
Simulation time 31324073808 ps
CPU time 14.91 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:01:37 PM PDT 24
Peak memory 200028 kb
Host smart-91a6c5e4-2e1d-4e33-9410-3e4486ddb7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795070900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3795070900
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1578754265
Short name T898
Test name
Test status
Simulation time 14646468 ps
CPU time 0.56 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 12:57:58 PM PDT 24
Peak memory 195884 kb
Host smart-7600096b-2556-4bda-8e9c-3d7e195ba0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578754265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1578754265
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.668500070
Short name T509
Test name
Test status
Simulation time 117578164507 ps
CPU time 64.19 seconds
Started May 14 12:57:47 PM PDT 24
Finished May 14 12:58:52 PM PDT 24
Peak memory 200440 kb
Host smart-d09de7fc-fa22-4c5f-be9e-9b8e52c65f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668500070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.668500070
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2038220001
Short name T508
Test name
Test status
Simulation time 116492733646 ps
CPU time 27.62 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:58:21 PM PDT 24
Peak memory 200108 kb
Host smart-03410a51-3509-4ba6-a536-3a8261af4000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038220001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2038220001
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.456175509
Short name T526
Test name
Test status
Simulation time 105871808628 ps
CPU time 184.79 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 01:00:59 PM PDT 24
Peak memory 200456 kb
Host smart-cfc2dac0-d891-4c2b-8693-6b4156e83a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456175509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.456175509
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1268858290
Short name T767
Test name
Test status
Simulation time 25787288826 ps
CPU time 42.58 seconds
Started May 14 12:57:56 PM PDT 24
Finished May 14 12:58:41 PM PDT 24
Peak memory 198920 kb
Host smart-502f51fe-b0bc-4b05-bcec-33d0ec15393e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268858290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1268858290
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3481735235
Short name T719
Test name
Test status
Simulation time 96469718892 ps
CPU time 720.78 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 01:09:55 PM PDT 24
Peak memory 200444 kb
Host smart-94622385-7e24-4666-b0f7-637620fa10c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481735235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3481735235
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1081437722
Short name T370
Test name
Test status
Simulation time 2951569876 ps
CPU time 3.44 seconds
Started May 14 12:57:55 PM PDT 24
Finished May 14 12:58:01 PM PDT 24
Peak memory 199412 kb
Host smart-21098c0c-51a9-4312-8877-d254d1bc11ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081437722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1081437722
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1632943180
Short name T770
Test name
Test status
Simulation time 30451584317 ps
CPU time 60.9 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 12:58:58 PM PDT 24
Peak memory 200636 kb
Host smart-a4de03f0-492a-430a-9587-9565a53eaffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632943180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1632943180
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1963062419
Short name T1134
Test name
Test status
Simulation time 15338484515 ps
CPU time 203.06 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 01:01:18 PM PDT 24
Peak memory 200420 kb
Host smart-7f3f272c-fccc-441c-bdf0-6c422654a7b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963062419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1963062419
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1261704109
Short name T1116
Test name
Test status
Simulation time 6997511607 ps
CPU time 16.5 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 12:58:13 PM PDT 24
Peak memory 199604 kb
Host smart-cbf25be6-a858-46c4-8384-537e938deeac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261704109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1261704109
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1114209524
Short name T329
Test name
Test status
Simulation time 10046902704 ps
CPU time 17.1 seconds
Started May 14 12:57:55 PM PDT 24
Finished May 14 12:58:15 PM PDT 24
Peak memory 200344 kb
Host smart-080b5614-7a98-4d01-b733-424002112b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114209524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1114209524
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.860276365
Short name T96
Test name
Test status
Simulation time 4316637097 ps
CPU time 7.75 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:58:04 PM PDT 24
Peak memory 196408 kb
Host smart-d01b3b56-8a2c-45cf-9579-a0893e15c769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860276365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.860276365
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1240561756
Short name T605
Test name
Test status
Simulation time 466679746 ps
CPU time 1.32 seconds
Started May 14 12:57:49 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 199152 kb
Host smart-02c2cdeb-1717-4921-9d81-87cc540b9f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240561756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1240561756
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2105034579
Short name T589
Test name
Test status
Simulation time 200525417823 ps
CPU time 411.85 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 01:04:48 PM PDT 24
Peak memory 200504 kb
Host smart-ed79ca05-6c86-4e65-b5d1-df021be1e3e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105034579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2105034579
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.873345401
Short name T785
Test name
Test status
Simulation time 175753995846 ps
CPU time 396.66 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 01:04:33 PM PDT 24
Peak memory 216924 kb
Host smart-925cd61d-cf2e-4571-9e44-63b804fee0bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873345401 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.873345401
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.373881000
Short name T402
Test name
Test status
Simulation time 409403613 ps
CPU time 1.43 seconds
Started May 14 12:57:56 PM PDT 24
Finished May 14 12:58:00 PM PDT 24
Peak memory 198496 kb
Host smart-af265731-e4ab-4877-95d3-36265a45a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373881000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.373881000
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3197251730
Short name T319
Test name
Test status
Simulation time 33962547873 ps
CPU time 53.71 seconds
Started May 14 12:57:47 PM PDT 24
Finished May 14 12:58:42 PM PDT 24
Peak memory 200412 kb
Host smart-c5c274a3-a0fe-4963-b021-4c0f46877f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197251730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3197251730
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2915818681
Short name T195
Test name
Test status
Simulation time 144452328638 ps
CPU time 69.92 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:02:32 PM PDT 24
Peak memory 200360 kb
Host smart-eae2bfed-d7ec-4f4f-8832-cbacec30345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915818681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2915818681
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1747317041
Short name T1050
Test name
Test status
Simulation time 169789963701 ps
CPU time 73.93 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:02:36 PM PDT 24
Peak memory 200356 kb
Host smart-4c8d5988-698f-4715-b720-b21814cf0a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747317041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1747317041
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4095325662
Short name T765
Test name
Test status
Simulation time 34117362220 ps
CPU time 14.54 seconds
Started May 14 01:01:18 PM PDT 24
Finished May 14 01:01:36 PM PDT 24
Peak memory 200284 kb
Host smart-c41b5906-f926-474b-9d2c-5946505c85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095325662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4095325662
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3425076402
Short name T287
Test name
Test status
Simulation time 129948102127 ps
CPU time 104.66 seconds
Started May 14 01:01:22 PM PDT 24
Finished May 14 01:03:09 PM PDT 24
Peak memory 200168 kb
Host smart-d985e81b-b37e-46c4-b2d0-3c27c2c24e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425076402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3425076402
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.384894602
Short name T556
Test name
Test status
Simulation time 104173837433 ps
CPU time 918.82 seconds
Started May 14 01:01:17 PM PDT 24
Finished May 14 01:16:39 PM PDT 24
Peak memory 200436 kb
Host smart-08ab3589-87da-4768-8df9-30b9d75a5afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384894602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.384894602
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.439213179
Short name T537
Test name
Test status
Simulation time 92600039615 ps
CPU time 148.55 seconds
Started May 14 01:01:18 PM PDT 24
Finished May 14 01:03:49 PM PDT 24
Peak memory 200460 kb
Host smart-6a13eaaa-78c8-4d30-99b2-9c02569ba866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439213179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.439213179
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3451105166
Short name T642
Test name
Test status
Simulation time 347445143170 ps
CPU time 64.53 seconds
Started May 14 01:01:20 PM PDT 24
Finished May 14 01:02:28 PM PDT 24
Peak memory 200448 kb
Host smart-7406c815-747e-4d2e-8e35-ba3e444cf6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451105166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3451105166
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.452540660
Short name T843
Test name
Test status
Simulation time 10892708 ps
CPU time 0.57 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:56:55 PM PDT 24
Peak memory 195720 kb
Host smart-c7219d43-78c0-4967-8bfd-77bfcecfefdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452540660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.452540660
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.598875113
Short name T275
Test name
Test status
Simulation time 42088990409 ps
CPU time 18.39 seconds
Started May 14 12:56:58 PM PDT 24
Finished May 14 12:57:18 PM PDT 24
Peak memory 200444 kb
Host smart-72167830-22b8-4c1d-9018-a3bc362899bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598875113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.598875113
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3461598824
Short name T985
Test name
Test status
Simulation time 53189637162 ps
CPU time 42.33 seconds
Started May 14 12:56:57 PM PDT 24
Finished May 14 12:57:42 PM PDT 24
Peak memory 200408 kb
Host smart-e355242d-3626-4d1a-8dba-45720d15171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461598824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3461598824
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1829796874
Short name T386
Test name
Test status
Simulation time 53193637982 ps
CPU time 87.2 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:58:23 PM PDT 24
Peak memory 200464 kb
Host smart-f20c4aeb-2ba0-4137-913b-28f8d6078d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829796874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1829796874
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1054079241
Short name T755
Test name
Test status
Simulation time 33002749333 ps
CPU time 15.28 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 12:57:13 PM PDT 24
Peak memory 200156 kb
Host smart-0f380750-ae7b-423c-9dd3-09e184f1550a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054079241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1054079241
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.647619048
Short name T373
Test name
Test status
Simulation time 164922797683 ps
CPU time 1328.63 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 01:19:07 PM PDT 24
Peak memory 200416 kb
Host smart-d4082be9-2c9e-413b-a556-ac6879646a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647619048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.647619048
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3584240639
Short name T416
Test name
Test status
Simulation time 2683518526 ps
CPU time 5.62 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:57:01 PM PDT 24
Peak memory 199272 kb
Host smart-57dc89fd-dae6-47d0-8f70-3b229f5f0b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584240639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3584240639
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2003283371
Short name T336
Test name
Test status
Simulation time 94512921831 ps
CPU time 93.16 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:58:37 PM PDT 24
Peak memory 200684 kb
Host smart-3b89ac61-6187-445e-aa1f-bbb6300d3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003283371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2003283371
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.761409267
Short name T585
Test name
Test status
Simulation time 11096497778 ps
CPU time 122 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 12:59:00 PM PDT 24
Peak memory 200488 kb
Host smart-d7596279-6ded-4773-ac72-4da2c0d7beb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761409267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.761409267
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2310180721
Short name T529
Test name
Test status
Simulation time 1909689855 ps
CPU time 12.82 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:57:09 PM PDT 24
Peak memory 199588 kb
Host smart-86ee2a10-3364-47ef-b43e-df22f4e48f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310180721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2310180721
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.230133788
Short name T747
Test name
Test status
Simulation time 31545761957 ps
CPU time 35.1 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 12:57:33 PM PDT 24
Peak memory 200376 kb
Host smart-84f4d78b-41a3-49e5-9a16-381cc98797ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230133788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.230133788
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2473625915
Short name T924
Test name
Test status
Simulation time 1415659371 ps
CPU time 3.06 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 196080 kb
Host smart-7b1b6002-6aef-4ac8-bf20-de1401d0c3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473625915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2473625915
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4080205715
Short name T26
Test name
Test status
Simulation time 140683551 ps
CPU time 0.79 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 218900 kb
Host smart-fe1ec662-cf21-4f53-bc67-ae656ac30bf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080205715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4080205715
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2244526296
Short name T836
Test name
Test status
Simulation time 106634391 ps
CPU time 0.94 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:05 PM PDT 24
Peak memory 198120 kb
Host smart-8a281b61-33bd-4c24-a182-b3bb19de38a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244526296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2244526296
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3411187059
Short name T745
Test name
Test status
Simulation time 97239933010 ps
CPU time 89.39 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:58:26 PM PDT 24
Peak memory 208956 kb
Host smart-4e5f7a12-60c1-4686-8682-29d7e5f80ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411187059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3411187059
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3198504986
Short name T48
Test name
Test status
Simulation time 425831309465 ps
CPU time 821.21 seconds
Started May 14 12:56:57 PM PDT 24
Finished May 14 01:10:40 PM PDT 24
Peak memory 225396 kb
Host smart-c883ab2e-7705-4b92-a3b8-fb2dd73cb374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198504986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3198504986
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3089009945
Short name T480
Test name
Test status
Simulation time 2537059546 ps
CPU time 1.46 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 199140 kb
Host smart-7db58802-2d84-4309-a807-b5dd35609162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089009945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3089009945
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.611430306
Short name T476
Test name
Test status
Simulation time 63648683462 ps
CPU time 98.57 seconds
Started May 14 12:56:52 PM PDT 24
Finished May 14 12:58:32 PM PDT 24
Peak memory 200480 kb
Host smart-d74ec5d7-edf0-4073-9222-56259697b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611430306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.611430306
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.818372241
Short name T351
Test name
Test status
Simulation time 31747755 ps
CPU time 0.55 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 195868 kb
Host smart-1ec7217a-b3d2-4667-b6ab-7a26467b8727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818372241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.818372241
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1557096202
Short name T779
Test name
Test status
Simulation time 34966603269 ps
CPU time 31.71 seconds
Started May 14 12:57:55 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 200448 kb
Host smart-1f9b4a8d-973c-4e24-9ece-fb65bc99d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557096202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1557096202
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2650897757
Short name T270
Test name
Test status
Simulation time 18448800523 ps
CPU time 28.7 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:58:25 PM PDT 24
Peak memory 200432 kb
Host smart-50a21143-4a6d-4fa0-98f2-7a0ef85c4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650897757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2650897757
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2172416143
Short name T872
Test name
Test status
Simulation time 127420052284 ps
CPU time 705.88 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 01:09:42 PM PDT 24
Peak memory 200372 kb
Host smart-19bf5774-bf5d-4999-b3cd-a7af80b26c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172416143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2172416143
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3470736320
Short name T741
Test name
Test status
Simulation time 32704042573 ps
CPU time 50.7 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:58:47 PM PDT 24
Peak memory 200388 kb
Host smart-a95e7e12-b9fc-4597-8e2f-e1810e156e10
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470736320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3470736320
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.911954129
Short name T548
Test name
Test status
Simulation time 82641506661 ps
CPU time 824.57 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 01:11:39 PM PDT 24
Peak memory 200504 kb
Host smart-6667b83f-9fac-4e26-96d3-eae1de1f635b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911954129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.911954129
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3602726448
Short name T374
Test name
Test status
Simulation time 6054459185 ps
CPU time 11.56 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 12:58:09 PM PDT 24
Peak memory 198968 kb
Host smart-73abda3a-e647-4214-b2fc-9f597bf2be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602726448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3602726448
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.236834531
Short name T967
Test name
Test status
Simulation time 37839001187 ps
CPU time 57.94 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 12:58:55 PM PDT 24
Peak memory 200316 kb
Host smart-9f8dd4f7-9562-4686-bdca-22c1e59107b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236834531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.236834531
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.518114056
Short name T1082
Test name
Test status
Simulation time 4270154685 ps
CPU time 74.44 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:59:10 PM PDT 24
Peak memory 200448 kb
Host smart-4083659e-c41b-4834-825d-106434466d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518114056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.518114056
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.181756737
Short name T440
Test name
Test status
Simulation time 2427344385 ps
CPU time 4.45 seconds
Started May 14 12:57:52 PM PDT 24
Finished May 14 12:58:00 PM PDT 24
Peak memory 197704 kb
Host smart-a64d1761-c636-430c-bb0d-d05a28a3c6d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181756737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.181756737
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2370938500
Short name T492
Test name
Test status
Simulation time 84440447324 ps
CPU time 38.96 seconds
Started May 14 12:57:55 PM PDT 24
Finished May 14 12:58:37 PM PDT 24
Peak memory 200420 kb
Host smart-64299712-49ab-42a7-a717-d5b067ba4dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370938500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2370938500
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2105888313
Short name T264
Test name
Test status
Simulation time 81698713031 ps
CPU time 43.93 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 12:58:41 PM PDT 24
Peak memory 196204 kb
Host smart-7c38e393-174b-4f1a-a0af-59d9ac690a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105888313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2105888313
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4189254489
Short name T1084
Test name
Test status
Simulation time 6107779673 ps
CPU time 4.96 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:58:01 PM PDT 24
Peak memory 200188 kb
Host smart-836c3771-b542-4ec4-9120-34ecf7bcb18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189254489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4189254489
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.504270543
Short name T65
Test name
Test status
Simulation time 31534609511 ps
CPU time 339.76 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 01:03:36 PM PDT 24
Peak memory 216020 kb
Host smart-54ed6d18-8a21-4e2e-b5d1-369553caaa11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504270543 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.504270543
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2989758606
Short name T722
Test name
Test status
Simulation time 1510068747 ps
CPU time 1.86 seconds
Started May 14 12:57:53 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 198680 kb
Host smart-8faa9cd6-94a0-49b8-af67-3eca6c1121e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989758606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2989758606
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2035439626
Short name T343
Test name
Test status
Simulation time 89450783048 ps
CPU time 137.88 seconds
Started May 14 12:57:54 PM PDT 24
Finished May 14 01:00:15 PM PDT 24
Peak memory 200400 kb
Host smart-87a49b47-44bf-48ea-b389-6d29cf3f3634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035439626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2035439626
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.378552668
Short name T596
Test name
Test status
Simulation time 110171035979 ps
CPU time 92.36 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:02:55 PM PDT 24
Peak memory 200420 kb
Host smart-70a1d64d-8987-4a27-af14-ce84ee620eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378552668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.378552668
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.22480294
Short name T209
Test name
Test status
Simulation time 130010818019 ps
CPU time 216.47 seconds
Started May 14 01:01:19 PM PDT 24
Finished May 14 01:04:58 PM PDT 24
Peak memory 200512 kb
Host smart-726ee245-a4e3-4194-89ed-705354fbcb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22480294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.22480294
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.597332083
Short name T342
Test name
Test status
Simulation time 27823612909 ps
CPU time 50.03 seconds
Started May 14 01:01:18 PM PDT 24
Finished May 14 01:02:11 PM PDT 24
Peak memory 200336 kb
Host smart-9e6b336f-452f-4a90-b03e-4811c7700e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597332083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.597332083
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1308836597
Short name T272
Test name
Test status
Simulation time 86249004577 ps
CPU time 77.53 seconds
Started May 14 01:01:28 PM PDT 24
Finished May 14 01:02:47 PM PDT 24
Peak memory 200476 kb
Host smart-0ee9868d-8b31-4516-b31f-e60d40629819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308836597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1308836597
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1551589266
Short name T187
Test name
Test status
Simulation time 198764979295 ps
CPU time 501.02 seconds
Started May 14 01:01:25 PM PDT 24
Finished May 14 01:09:48 PM PDT 24
Peak memory 200504 kb
Host smart-dec7669c-b6ec-42f3-b6ed-7d2b4815a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551589266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1551589266
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3705133275
Short name T1070
Test name
Test status
Simulation time 73811162352 ps
CPU time 35.19 seconds
Started May 14 01:01:25 PM PDT 24
Finished May 14 01:02:02 PM PDT 24
Peak memory 200448 kb
Host smart-e551e11f-d1f6-4255-bb4b-b45543261b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705133275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3705133275
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1834282887
Short name T345
Test name
Test status
Simulation time 16316819683 ps
CPU time 12.78 seconds
Started May 14 01:01:27 PM PDT 24
Finished May 14 01:01:41 PM PDT 24
Peak memory 200328 kb
Host smart-50ea56d6-68f6-46b3-843d-2ae54f669a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834282887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1834282887
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2229803725
Short name T442
Test name
Test status
Simulation time 97309488510 ps
CPU time 36.03 seconds
Started May 14 01:01:28 PM PDT 24
Finished May 14 01:02:05 PM PDT 24
Peak memory 200476 kb
Host smart-b672893d-7179-4a2b-afe4-7c1955a22f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229803725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2229803725
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1280543592
Short name T1086
Test name
Test status
Simulation time 29155717213 ps
CPU time 51.06 seconds
Started May 14 01:01:23 PM PDT 24
Finished May 14 01:02:16 PM PDT 24
Peak memory 200436 kb
Host smart-ea7c480b-df88-4f42-8cf2-437ba6552c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280543592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1280543592
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.429567458
Short name T433
Test name
Test status
Simulation time 46051556 ps
CPU time 0.6 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 195848 kb
Host smart-977c010c-7cb8-4950-b8c3-a6459c65676b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429567458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.429567458
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.890712837
Short name T119
Test name
Test status
Simulation time 82913306597 ps
CPU time 76.7 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:59:19 PM PDT 24
Peak memory 200416 kb
Host smart-6e756291-493f-403d-b808-0e01eae01d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890712837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.890712837
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3571744325
Short name T161
Test name
Test status
Simulation time 25904837721 ps
CPU time 44.62 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 12:58:49 PM PDT 24
Peak memory 200420 kb
Host smart-bc88b2f8-d155-441a-92fe-b62c3ee3f887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571744325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3571744325
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2485489783
Short name T673
Test name
Test status
Simulation time 23421279172 ps
CPU time 44.02 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:47 PM PDT 24
Peak memory 200412 kb
Host smart-2f454000-8bcf-490d-a0e5-44bd8cc75375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485489783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2485489783
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3585555888
Short name T637
Test name
Test status
Simulation time 40105601876 ps
CPU time 39.16 seconds
Started May 14 12:58:06 PM PDT 24
Finished May 14 12:58:47 PM PDT 24
Peak memory 200352 kb
Host smart-6dc5bfa9-304b-4393-b7be-c04f24599126
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585555888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3585555888
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2349416058
Short name T1015
Test name
Test status
Simulation time 80240678668 ps
CPU time 249.96 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 200484 kb
Host smart-bc04462f-28f1-4ef4-9b7b-dbcfcee49c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349416058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2349416058
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.949484867
Short name T352
Test name
Test status
Simulation time 4697968994 ps
CPU time 11.06 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:13 PM PDT 24
Peak memory 198944 kb
Host smart-cc965a18-83d3-49d9-aa83-2d0da8347ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949484867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.949484867
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.25148538
Short name T901
Test name
Test status
Simulation time 128366860481 ps
CPU time 33.7 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:37 PM PDT 24
Peak memory 208912 kb
Host smart-c80aa770-d9e8-47f7-a9b1-9bf588e7b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25148538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.25148538
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3222701027
Short name T1173
Test name
Test status
Simulation time 14105116308 ps
CPU time 738.42 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 01:10:20 PM PDT 24
Peak memory 200528 kb
Host smart-16219c9a-9331-4a64-82fb-c70cff706515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222701027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3222701027
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1222645456
Short name T796
Test name
Test status
Simulation time 5055588197 ps
CPU time 4.15 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:58:05 PM PDT 24
Peak memory 199160 kb
Host smart-4b37cb55-8eb2-4d93-8e87-44389d62c524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222645456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1222645456
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.255577839
Short name T936
Test name
Test status
Simulation time 37915463204 ps
CPU time 30.3 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 12:58:34 PM PDT 24
Peak memory 200528 kb
Host smart-bb1ff800-c120-4139-9a0d-a01df9b8a8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255577839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.255577839
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.4001307659
Short name T105
Test name
Test status
Simulation time 4754784801 ps
CPU time 4.64 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:58:06 PM PDT 24
Peak memory 196464 kb
Host smart-76913cf3-ee89-42ea-bbec-a7d63a0f06fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001307659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4001307659
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2987741991
Short name T108
Test name
Test status
Simulation time 5689834155 ps
CPU time 9.27 seconds
Started May 14 12:57:59 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 200224 kb
Host smart-da860802-80af-4e5d-9739-235b2b8ee28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987741991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2987741991
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2272597555
Short name T1048
Test name
Test status
Simulation time 37976222884 ps
CPU time 29.27 seconds
Started May 14 12:57:59 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 200504 kb
Host smart-eed13cd5-bfa8-4803-8aab-200e713e75c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272597555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2272597555
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.274477726
Short name T1053
Test name
Test status
Simulation time 239861722743 ps
CPU time 2173.38 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 01:34:17 PM PDT 24
Peak memory 226584 kb
Host smart-ae5a19ee-726c-41f5-a392-0100b54e62b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274477726 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.274477726
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2543689448
Short name T703
Test name
Test status
Simulation time 6612168159 ps
CPU time 17.87 seconds
Started May 14 12:58:06 PM PDT 24
Finished May 14 12:58:24 PM PDT 24
Peak memory 200164 kb
Host smart-0d1879b6-d539-497c-baaf-e2497a0223dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543689448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2543689448
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.51211720
Short name T282
Test name
Test status
Simulation time 56361344226 ps
CPU time 102.68 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:59:44 PM PDT 24
Peak memory 200420 kb
Host smart-db47c8ad-7b56-4057-8e65-8509973175ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51211720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.51211720
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3952633503
Short name T678
Test name
Test status
Simulation time 38967735940 ps
CPU time 174.97 seconds
Started May 14 01:01:24 PM PDT 24
Finished May 14 01:04:21 PM PDT 24
Peak memory 200652 kb
Host smart-75156d08-08e9-49f2-a06f-637cd7fd8238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952633503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3952633503
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3927823533
Short name T365
Test name
Test status
Simulation time 29367932189 ps
CPU time 46.47 seconds
Started May 14 01:01:25 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 200412 kb
Host smart-eb49b6d1-48b4-4906-bcf9-5304da898b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927823533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3927823533
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2286865491
Short name T1067
Test name
Test status
Simulation time 17111566695 ps
CPU time 7.71 seconds
Started May 14 01:01:26 PM PDT 24
Finished May 14 01:01:36 PM PDT 24
Peak memory 200300 kb
Host smart-13c65b15-5c2f-4297-a952-4ea99d5c0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286865491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2286865491
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.310662626
Short name T581
Test name
Test status
Simulation time 96456350873 ps
CPU time 139.6 seconds
Started May 14 01:01:24 PM PDT 24
Finished May 14 01:03:46 PM PDT 24
Peak memory 200440 kb
Host smart-7f5498c7-ee54-434c-8887-f3dbe6e7584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310662626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.310662626
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2068617165
Short name T856
Test name
Test status
Simulation time 12873306403 ps
CPU time 3.71 seconds
Started May 14 01:01:24 PM PDT 24
Finished May 14 01:01:30 PM PDT 24
Peak memory 198884 kb
Host smart-83dbb4ba-1fbf-4b9f-864b-2b36bd11b971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068617165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2068617165
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2008072518
Short name T490
Test name
Test status
Simulation time 39563200372 ps
CPU time 5.47 seconds
Started May 14 01:01:34 PM PDT 24
Finished May 14 01:01:42 PM PDT 24
Peak memory 200364 kb
Host smart-48101ec2-2ac8-4bfc-a995-b03f04f86d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008072518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2008072518
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2016046802
Short name T496
Test name
Test status
Simulation time 14554575 ps
CPU time 0.56 seconds
Started May 14 12:58:06 PM PDT 24
Finished May 14 12:58:08 PM PDT 24
Peak memory 195772 kb
Host smart-c1affbe5-ecb2-4dfb-b853-a833ff3f530e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016046802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2016046802
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2962827140
Short name T316
Test name
Test status
Simulation time 155327179995 ps
CPU time 58.01 seconds
Started May 14 12:58:04 PM PDT 24
Finished May 14 12:59:03 PM PDT 24
Peak memory 200508 kb
Host smart-d0d88852-ed1c-4872-a5a3-814210529c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962827140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2962827140
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.369740911
Short name T1026
Test name
Test status
Simulation time 7712906737 ps
CPU time 7.53 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 198676 kb
Host smart-36fc30ed-b05e-4e3f-98d2-2ff995fa0124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369740911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.369740911
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2827053792
Short name T120
Test name
Test status
Simulation time 41072723953 ps
CPU time 17.87 seconds
Started May 14 12:58:04 PM PDT 24
Finished May 14 12:58:23 PM PDT 24
Peak memory 200488 kb
Host smart-94f68faa-edb6-487e-914c-7b44f5ed3409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827053792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2827053792
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1945553479
Short name T305
Test name
Test status
Simulation time 14680969708 ps
CPU time 24.11 seconds
Started May 14 12:57:59 PM PDT 24
Finished May 14 12:58:24 PM PDT 24
Peak memory 200064 kb
Host smart-8e0aa5cc-3f14-4115-8728-79f9191cf96c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945553479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1945553479
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2562707273
Short name T1140
Test name
Test status
Simulation time 65578834952 ps
CPU time 210.27 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 01:01:34 PM PDT 24
Peak memory 200468 kb
Host smart-ea448275-617c-4de0-b28a-3b12dd4615d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562707273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2562707273
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3993810813
Short name T709
Test name
Test status
Simulation time 8767932619 ps
CPU time 7.43 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 200464 kb
Host smart-7882add2-8e66-4a4d-86e5-dd757e390996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993810813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3993810813
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.494835507
Short name T939
Test name
Test status
Simulation time 92586882733 ps
CPU time 44.15 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:47 PM PDT 24
Peak memory 208784 kb
Host smart-6b64fe28-cfcf-4382-9978-4ff9ab3cd2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494835507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.494835507
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.440657066
Short name T894
Test name
Test status
Simulation time 5420433512 ps
CPU time 96.36 seconds
Started May 14 12:58:06 PM PDT 24
Finished May 14 12:59:44 PM PDT 24
Peak memory 200320 kb
Host smart-4fc4add7-071c-463e-baea-9ff6202036d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440657066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.440657066
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2951454496
Short name T541
Test name
Test status
Simulation time 4129825197 ps
CPU time 9.01 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 199104 kb
Host smart-ef1ffbc4-9d28-4a6e-bcc1-8727354bcd6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951454496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2951454496
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2849283137
Short name T552
Test name
Test status
Simulation time 54364707486 ps
CPU time 100.06 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:59:41 PM PDT 24
Peak memory 200408 kb
Host smart-2814cf3a-e4e0-4e71-ba61-880e507d0ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849283137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2849283137
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1784472234
Short name T549
Test name
Test status
Simulation time 4126445360 ps
CPU time 1.6 seconds
Started May 14 12:58:06 PM PDT 24
Finished May 14 12:58:09 PM PDT 24
Peak memory 196384 kb
Host smart-549f4537-cc40-4d09-a995-42f23c917a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784472234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1784472234
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.956824338
Short name T624
Test name
Test status
Simulation time 706456246 ps
CPU time 1.1 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 199064 kb
Host smart-d5decd06-9b78-4bf0-ace1-db91e42ecb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956824338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.956824338
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.126448687
Short name T631
Test name
Test status
Simulation time 23654842437 ps
CPU time 39.17 seconds
Started May 14 12:58:01 PM PDT 24
Finished May 14 12:58:42 PM PDT 24
Peak memory 200500 kb
Host smart-a2793579-d9c7-4b03-8231-ea8c4a53e1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126448687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.126448687
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2687661629
Short name T988
Test name
Test status
Simulation time 67569541348 ps
CPU time 1085.37 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 225412 kb
Host smart-d6912e9c-a31e-4e54-b24a-38b626829cbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687661629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2687661629
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2149369972
Short name T890
Test name
Test status
Simulation time 994808172 ps
CPU time 3.39 seconds
Started May 14 12:58:02 PM PDT 24
Finished May 14 12:58:08 PM PDT 24
Peak memory 198744 kb
Host smart-a746e9ed-13cf-415d-be7b-483206742347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149369972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2149369972
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1059825934
Short name T444
Test name
Test status
Simulation time 57688864779 ps
CPU time 30.46 seconds
Started May 14 12:58:00 PM PDT 24
Finished May 14 12:58:32 PM PDT 24
Peak memory 200480 kb
Host smart-0b7e4a11-8278-4e36-bd03-ead0b62acfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059825934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1059825934
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2220546292
Short name T763
Test name
Test status
Simulation time 34251321219 ps
CPU time 23.18 seconds
Started May 14 01:01:33 PM PDT 24
Finished May 14 01:01:58 PM PDT 24
Peak memory 200536 kb
Host smart-502865c9-f4bc-4f08-8c5a-f8becb4a575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220546292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2220546292
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3418824927
Short name T606
Test name
Test status
Simulation time 28678901496 ps
CPU time 25.72 seconds
Started May 14 01:01:34 PM PDT 24
Finished May 14 01:02:01 PM PDT 24
Peak memory 200472 kb
Host smart-176e1ee1-19ea-4234-a6d6-72392fde74d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418824927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3418824927
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.807454448
Short name T183
Test name
Test status
Simulation time 13962245086 ps
CPU time 20.93 seconds
Started May 14 01:01:35 PM PDT 24
Finished May 14 01:01:57 PM PDT 24
Peak memory 199444 kb
Host smart-4208968b-b624-4f0b-9bcb-a47bfe5d1063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807454448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.807454448
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.244003819
Short name T769
Test name
Test status
Simulation time 145534483289 ps
CPU time 67.64 seconds
Started May 14 01:01:35 PM PDT 24
Finished May 14 01:02:45 PM PDT 24
Peak memory 200032 kb
Host smart-124cf559-6d0c-45a0-9aca-6bec75019087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244003819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.244003819
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3146575077
Short name T595
Test name
Test status
Simulation time 19966938488 ps
CPU time 16.82 seconds
Started May 14 01:01:33 PM PDT 24
Finished May 14 01:01:52 PM PDT 24
Peak memory 200232 kb
Host smart-319161c7-16eb-4947-a0eb-6b03d241090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146575077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3146575077
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1427384047
Short name T199
Test name
Test status
Simulation time 31529263026 ps
CPU time 13.74 seconds
Started May 14 01:01:32 PM PDT 24
Finished May 14 01:01:47 PM PDT 24
Peak memory 199704 kb
Host smart-6567a8d6-8508-49b1-99f3-48571ad41711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427384047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1427384047
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.4068737008
Short name T221
Test name
Test status
Simulation time 8524509920 ps
CPU time 17.04 seconds
Started May 14 01:01:35 PM PDT 24
Finished May 14 01:01:54 PM PDT 24
Peak memory 200124 kb
Host smart-734761ab-bdfb-45f9-859d-28c938b7e1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068737008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.4068737008
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3698571195
Short name T140
Test name
Test status
Simulation time 32441938295 ps
CPU time 37.9 seconds
Started May 14 01:01:35 PM PDT 24
Finished May 14 01:02:15 PM PDT 24
Peak memory 200456 kb
Host smart-d267a203-b2a4-4e55-afbd-0f934de21bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698571195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3698571195
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2193772902
Short name T575
Test name
Test status
Simulation time 137837511604 ps
CPU time 59.98 seconds
Started May 14 01:01:36 PM PDT 24
Finished May 14 01:02:37 PM PDT 24
Peak memory 200512 kb
Host smart-5dfd8ed8-4d27-456c-b268-1cd68d877172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193772902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2193772902
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2386741305
Short name T355
Test name
Test status
Simulation time 34924398 ps
CPU time 0.6 seconds
Started May 14 12:58:08 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 195868 kb
Host smart-cde2aba1-4d4a-48cc-bf5c-f97d5808bf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386741305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2386741305
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3643140900
Short name T910
Test name
Test status
Simulation time 78723917907 ps
CPU time 139.12 seconds
Started May 14 12:58:11 PM PDT 24
Finished May 14 01:00:31 PM PDT 24
Peak memory 200468 kb
Host smart-59988e82-e370-43b5-a295-1465b4859ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643140900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3643140900
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.53638833
Short name T379
Test name
Test status
Simulation time 9945273805 ps
CPU time 18.69 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 199852 kb
Host smart-339f7063-80c5-46cf-8d55-dc2fe858e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53638833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.53638833
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3391468207
Short name T340
Test name
Test status
Simulation time 170108960195 ps
CPU time 159.6 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 01:00:51 PM PDT 24
Peak memory 200420 kb
Host smart-3a0cbdb6-bd13-4918-a5d6-23b9c392b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391468207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3391468207
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3270681977
Short name T926
Test name
Test status
Simulation time 69244935203 ps
CPU time 14.59 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:58:25 PM PDT 24
Peak memory 199564 kb
Host smart-338687ff-aba2-4cb0-8fc1-2e27aa2d84b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270681977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3270681977
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1964674939
Short name T736
Test name
Test status
Simulation time 99856483321 ps
CPU time 553.75 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 01:07:24 PM PDT 24
Peak memory 200484 kb
Host smart-10b637d6-a128-44aa-ad8a-5ed2dcf1bd82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964674939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1964674939
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3157947924
Short name T839
Test name
Test status
Simulation time 3110594949 ps
CPU time 3.45 seconds
Started May 14 12:58:11 PM PDT 24
Finished May 14 12:58:16 PM PDT 24
Peak memory 200404 kb
Host smart-46a07638-02ca-48ec-ac36-945a44136587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157947924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3157947924
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2315626438
Short name T740
Test name
Test status
Simulation time 104991039811 ps
CPU time 50.96 seconds
Started May 14 12:58:11 PM PDT 24
Finished May 14 12:59:03 PM PDT 24
Peak memory 200152 kb
Host smart-67b6f62f-e387-4d2d-9c1b-4d01a8e5d8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315626438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2315626438
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1617180027
Short name T306
Test name
Test status
Simulation time 22940790151 ps
CPU time 303.94 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 01:03:16 PM PDT 24
Peak memory 200484 kb
Host smart-16567785-8134-474a-a929-8a5e69ac6c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617180027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1617180027
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3445961053
Short name T650
Test name
Test status
Simulation time 6391192266 ps
CPU time 14.68 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:58:25 PM PDT 24
Peak memory 199684 kb
Host smart-f8997921-dad6-4393-8235-94ecbdf91f32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445961053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3445961053
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1973811310
Short name T970
Test name
Test status
Simulation time 180203898549 ps
CPU time 140.84 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 01:00:32 PM PDT 24
Peak memory 200492 kb
Host smart-679a1706-f340-4a08-8134-06e87bd67c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973811310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1973811310
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1482954155
Short name T1163
Test name
Test status
Simulation time 2628892492 ps
CPU time 2.55 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:58:13 PM PDT 24
Peak memory 196456 kb
Host smart-4e616c0a-9882-4df9-aff0-cbd9adf53cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482954155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1482954155
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1028249791
Short name T917
Test name
Test status
Simulation time 956335071 ps
CPU time 1.97 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 12:58:14 PM PDT 24
Peak memory 198744 kb
Host smart-25a7920a-06b6-470b-bd3a-174593cd0e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028249791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1028249791
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3200848895
Short name T1041
Test name
Test status
Simulation time 152771726219 ps
CPU time 200.74 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 01:01:31 PM PDT 24
Peak memory 200440 kb
Host smart-8f73f7d9-c359-468a-8495-1f4ca1022c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200848895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3200848895
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1155099764
Short name T28
Test name
Test status
Simulation time 99576155036 ps
CPU time 299.41 seconds
Started May 14 12:58:13 PM PDT 24
Finished May 14 01:03:14 PM PDT 24
Peak memory 217000 kb
Host smart-ca30795f-23eb-411e-8dc9-8c432d7a6620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155099764 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1155099764
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1353575501
Short name T583
Test name
Test status
Simulation time 1066583351 ps
CPU time 1.76 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:58:12 PM PDT 24
Peak memory 198680 kb
Host smart-e1047b55-664a-4def-b18c-927b4262cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353575501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1353575501
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1336034687
Short name T922
Test name
Test status
Simulation time 46929583952 ps
CPU time 20.28 seconds
Started May 14 12:58:08 PM PDT 24
Finished May 14 12:58:30 PM PDT 24
Peak memory 200400 kb
Host smart-d85c3ee5-df8c-4118-a7e7-44d9f5b8d546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336034687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1336034687
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2814991645
Short name T708
Test name
Test status
Simulation time 122350053971 ps
CPU time 276.04 seconds
Started May 14 01:01:32 PM PDT 24
Finished May 14 01:06:10 PM PDT 24
Peak memory 200516 kb
Host smart-58a3c917-c9c1-457c-8c39-6b051349381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814991645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2814991645
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.473308553
Short name T1182
Test name
Test status
Simulation time 233114621946 ps
CPU time 98.25 seconds
Started May 14 01:01:36 PM PDT 24
Finished May 14 01:03:15 PM PDT 24
Peak memory 200520 kb
Host smart-dc61f301-8650-40ea-a910-3841a45b7aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473308553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.473308553
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4009759098
Short name T1127
Test name
Test status
Simulation time 96869714667 ps
CPU time 157.27 seconds
Started May 14 01:01:32 PM PDT 24
Finished May 14 01:04:11 PM PDT 24
Peak memory 200468 kb
Host smart-5da4be71-4503-49b3-993d-2ae7adbe7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009759098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4009759098
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1226212348
Short name T860
Test name
Test status
Simulation time 93866485773 ps
CPU time 43.88 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:02:28 PM PDT 24
Peak memory 200440 kb
Host smart-de718663-ea91-4331-a406-3202fec3711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226212348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1226212348
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2488426949
Short name T465
Test name
Test status
Simulation time 15772843770 ps
CPU time 8.94 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:01:52 PM PDT 24
Peak memory 200128 kb
Host smart-7f0e9274-2fe3-425b-a5ca-73886b3b1de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488426949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2488426949
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3175822671
Short name T260
Test name
Test status
Simulation time 114512695231 ps
CPU time 106.01 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:03:31 PM PDT 24
Peak memory 200448 kb
Host smart-05183460-fbe1-4050-b4d0-b4d549449d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175822671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3175822671
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2678427952
Short name T954
Test name
Test status
Simulation time 24198647519 ps
CPU time 42.98 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:02:28 PM PDT 24
Peak memory 200396 kb
Host smart-1a7b68ec-d1be-4c0e-a158-5bb48bda1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678427952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2678427952
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3366269492
Short name T931
Test name
Test status
Simulation time 117957942513 ps
CPU time 184.86 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 200412 kb
Host smart-102975d0-9e83-4501-870f-84b856635b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366269492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3366269492
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3029630505
Short name T232
Test name
Test status
Simulation time 17786985298 ps
CPU time 29.66 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 200360 kb
Host smart-08c40bc6-04d3-457a-9493-ba4ee31e3387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029630505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3029630505
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1665753018
Short name T699
Test name
Test status
Simulation time 12775093 ps
CPU time 0.56 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 12:58:21 PM PDT 24
Peak memory 195812 kb
Host smart-9d34efd2-ed47-4edd-894d-e09e4926dfd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665753018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1665753018
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2676317533
Short name T322
Test name
Test status
Simulation time 55157244030 ps
CPU time 51.19 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:59:02 PM PDT 24
Peak memory 200484 kb
Host smart-4ddbfd5c-bbb1-437a-941d-15d4261332ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676317533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2676317533
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3449511474
Short name T290
Test name
Test status
Simulation time 159948821127 ps
CPU time 69.71 seconds
Started May 14 12:58:12 PM PDT 24
Finished May 14 12:59:23 PM PDT 24
Peak memory 200332 kb
Host smart-620d3b60-06f9-4601-9586-72010d87d51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449511474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3449511474
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3121162073
Short name T825
Test name
Test status
Simulation time 208080482788 ps
CPU time 66.64 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 12:59:18 PM PDT 24
Peak memory 200356 kb
Host smart-06a895e0-3b81-4089-b309-ee3626859b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121162073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3121162073
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4004207160
Short name T19
Test name
Test status
Simulation time 390542873730 ps
CPU time 579.85 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 01:07:52 PM PDT 24
Peak memory 199064 kb
Host smart-6a7fc0f9-9d75-4b8d-9d0d-e91d8914d19d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004207160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4004207160
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1624561381
Short name T958
Test name
Test status
Simulation time 90604742344 ps
CPU time 527.68 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 200500 kb
Host smart-a5e87c7e-09b1-4fbc-b4a1-8b4764333cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624561381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1624561381
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1950035552
Short name T1010
Test name
Test status
Simulation time 13139074098 ps
CPU time 22.66 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 12:58:41 PM PDT 24
Peak memory 200364 kb
Host smart-9b3e45dd-16e1-432b-80a8-11d35c29abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950035552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1950035552
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.17184964
Short name T27
Test name
Test status
Simulation time 195920887448 ps
CPU time 100.36 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 12:59:52 PM PDT 24
Peak memory 200652 kb
Host smart-2f9d3962-5ea4-421e-b4d3-02e16b6cc2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17184964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.17184964
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1796728701
Short name T1115
Test name
Test status
Simulation time 7854675780 ps
CPU time 82.85 seconds
Started May 14 12:58:20 PM PDT 24
Finished May 14 12:59:44 PM PDT 24
Peak memory 200528 kb
Host smart-524f636b-c529-4a97-8010-dcb27e41ffe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796728701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1796728701
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.424652820
Short name T851
Test name
Test status
Simulation time 6742883509 ps
CPU time 15.73 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 12:58:28 PM PDT 24
Peak memory 198532 kb
Host smart-3e34e18c-d6b1-44fe-919f-28ef06111307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424652820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.424652820
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.271912734
Short name T411
Test name
Test status
Simulation time 51836202143 ps
CPU time 95.08 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:59:45 PM PDT 24
Peak memory 200404 kb
Host smart-fdd7c550-3ed5-4f72-bdb1-230d007741b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271912734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.271912734
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3930800449
Short name T983
Test name
Test status
Simulation time 3573479973 ps
CPU time 6.23 seconds
Started May 14 12:58:08 PM PDT 24
Finished May 14 12:58:14 PM PDT 24
Peak memory 196452 kb
Host smart-ef2e53b8-2f8a-49b0-9229-5799107010fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930800449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3930800449
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1904304928
Short name T648
Test name
Test status
Simulation time 484844634 ps
CPU time 2.17 seconds
Started May 14 12:58:09 PM PDT 24
Finished May 14 12:58:13 PM PDT 24
Peak memory 200128 kb
Host smart-333f2c08-7f8b-49db-86d6-42ff8fc04ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904304928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1904304928
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3845333685
Short name T966
Test name
Test status
Simulation time 368090864443 ps
CPU time 184.61 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 01:01:26 PM PDT 24
Peak memory 200416 kb
Host smart-082064ed-981f-4453-a124-e3c486a7a258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845333685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3845333685
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1620900375
Short name T339
Test name
Test status
Simulation time 64451481215 ps
CPU time 1448.49 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 01:22:27 PM PDT 24
Peak memory 225428 kb
Host smart-5fb8ddf9-4928-43d1-a239-d5e2d5ed801a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620900375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1620900375
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3707496303
Short name T427
Test name
Test status
Simulation time 3013467989 ps
CPU time 2.71 seconds
Started May 14 12:58:08 PM PDT 24
Finished May 14 12:58:12 PM PDT 24
Peak memory 200296 kb
Host smart-dd71620a-1b01-4a82-806d-f6ea1b177f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707496303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3707496303
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3109139841
Short name T21
Test name
Test status
Simulation time 109559459614 ps
CPU time 239.94 seconds
Started May 14 12:58:10 PM PDT 24
Finished May 14 01:02:11 PM PDT 24
Peak memory 200500 kb
Host smart-b7becc28-ade5-4253-b4e1-deba18c7446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109139841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3109139841
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.670180178
Short name T164
Test name
Test status
Simulation time 147930534230 ps
CPU time 65.61 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:02:49 PM PDT 24
Peak memory 200496 kb
Host smart-ee690122-203a-4e75-8cac-605375ac90ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670180178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.670180178
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1991884861
Short name T935
Test name
Test status
Simulation time 108264686350 ps
CPU time 85.1 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:03:10 PM PDT 24
Peak memory 200496 kb
Host smart-3adf6589-182f-4840-8c9d-abd05169cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991884861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1991884861
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2954294153
Short name T198
Test name
Test status
Simulation time 23556990777 ps
CPU time 29.84 seconds
Started May 14 01:01:43 PM PDT 24
Finished May 14 01:02:16 PM PDT 24
Peak memory 200384 kb
Host smart-0186a440-3156-4252-ab67-c0eaf94253af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954294153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2954294153
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.376856111
Short name T144
Test name
Test status
Simulation time 237318719566 ps
CPU time 382.02 seconds
Started May 14 01:01:40 PM PDT 24
Finished May 14 01:08:05 PM PDT 24
Peak memory 200512 kb
Host smart-c690f5ea-9679-40cd-b3b8-e03f842b9b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376856111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.376856111
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3470458156
Short name T551
Test name
Test status
Simulation time 34476236596 ps
CPU time 58.26 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:02:43 PM PDT 24
Peak memory 200504 kb
Host smart-627bb4c3-3178-4d85-8149-a02fe5323921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470458156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3470458156
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3962002274
Short name T1150
Test name
Test status
Simulation time 42512157436 ps
CPU time 36.68 seconds
Started May 14 01:01:40 PM PDT 24
Finished May 14 01:02:20 PM PDT 24
Peak memory 200224 kb
Host smart-2bac3c37-c3f9-4d00-bfd8-2c8207de3c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962002274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3962002274
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.451272241
Short name T912
Test name
Test status
Simulation time 284481925725 ps
CPU time 138.63 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:04:03 PM PDT 24
Peak memory 200552 kb
Host smart-a8f5ed77-0322-4e2c-8aff-71bfcfdb2f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451272241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.451272241
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.75517593
Short name T285
Test name
Test status
Simulation time 73913692669 ps
CPU time 229.95 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 200448 kb
Host smart-9bf920b5-fea2-4d17-9592-29049d5a7634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75517593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.75517593
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2176944629
Short name T178
Test name
Test status
Simulation time 42609964141 ps
CPU time 71.42 seconds
Started May 14 01:01:43 PM PDT 24
Finished May 14 01:02:57 PM PDT 24
Peak memory 200396 kb
Host smart-d9ca9d79-5b15-409e-acc9-aeb4ee4cdde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176944629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2176944629
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4285159446
Short name T457
Test name
Test status
Simulation time 15808047 ps
CPU time 0.54 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 12:58:22 PM PDT 24
Peak memory 194784 kb
Host smart-ae86d5a0-4648-46f3-a17b-b4591484a0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285159446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4285159446
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.950758388
Short name T849
Test name
Test status
Simulation time 60404367508 ps
CPU time 50.18 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 12:59:11 PM PDT 24
Peak memory 200692 kb
Host smart-622e353c-f210-40a1-a44a-711cc387d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950758388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.950758388
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.626095757
Short name T683
Test name
Test status
Simulation time 35738115273 ps
CPU time 32.01 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:58:52 PM PDT 24
Peak memory 200436 kb
Host smart-9b09b7c9-3baf-40fa-a888-7d50abb18e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626095757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.626095757
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1664676210
Short name T1077
Test name
Test status
Simulation time 31034390949 ps
CPU time 17.88 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 12:58:37 PM PDT 24
Peak memory 200344 kb
Host smart-28db7cc9-cb94-472e-8880-1f366048f4a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664676210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1664676210
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.676738167
Short name T534
Test name
Test status
Simulation time 145424404482 ps
CPU time 1050.72 seconds
Started May 14 12:58:21 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 200384 kb
Host smart-5310febf-31e4-4fff-b3a3-92b14b869cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676738167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.676738167
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.655912524
Short name T879
Test name
Test status
Simulation time 4884101328 ps
CPU time 10.21 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:58:30 PM PDT 24
Peak memory 200484 kb
Host smart-b7f0ab4d-e3f5-4503-8ead-abfcd00b8236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655912524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.655912524
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3761660064
Short name T748
Test name
Test status
Simulation time 19593188514 ps
CPU time 35.08 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:58:55 PM PDT 24
Peak memory 199604 kb
Host smart-2933bb22-075d-4f10-9e2c-21bdad0f806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761660064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3761660064
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.4039146739
Short name T303
Test name
Test status
Simulation time 18157504660 ps
CPU time 820.62 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 01:11:59 PM PDT 24
Peak memory 200512 kb
Host smart-297f67ac-1637-42b0-8c60-b70e51cc75c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039146739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4039146739
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1955326060
Short name T454
Test name
Test status
Simulation time 3324987338 ps
CPU time 3.32 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 12:58:24 PM PDT 24
Peak memory 198508 kb
Host smart-acea9c12-7cc6-49d9-a2ef-8de987d82bf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955326060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1955326060
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4089213297
Short name T580
Test name
Test status
Simulation time 6355598003 ps
CPU time 9.28 seconds
Started May 14 12:58:20 PM PDT 24
Finished May 14 12:58:31 PM PDT 24
Peak memory 196512 kb
Host smart-4c205bd7-048d-490b-8170-1261f76de173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089213297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4089213297
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.43958498
Short name T656
Test name
Test status
Simulation time 268214729 ps
CPU time 1.6 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 12:58:22 PM PDT 24
Peak memory 200604 kb
Host smart-6b6e6fb9-7d88-4696-b729-a54210c51a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43958498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.43958498
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2420486118
Short name T1097
Test name
Test status
Simulation time 12594212444 ps
CPU time 13.18 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 12:58:31 PM PDT 24
Peak memory 200460 kb
Host smart-649bd36d-207b-4225-8498-ba08c7b7a052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420486118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2420486118
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1845790552
Short name T41
Test name
Test status
Simulation time 87188347669 ps
CPU time 1295.11 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 01:19:54 PM PDT 24
Peak memory 232160 kb
Host smart-0e78c7ec-5ba1-423b-b418-baf6126e427e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845790552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1845790552
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3211455311
Short name T1087
Test name
Test status
Simulation time 7241709746 ps
CPU time 9.93 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 200460 kb
Host smart-77f10370-8961-4730-9f23-65b3fba84b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211455311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3211455311
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3862941277
Short name T497
Test name
Test status
Simulation time 88633321651 ps
CPU time 162.43 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 01:01:01 PM PDT 24
Peak memory 200444 kb
Host smart-deaaf855-af26-42a6-afd5-29e488ece59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862941277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3862941277
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3166156832
Short name T845
Test name
Test status
Simulation time 188159912347 ps
CPU time 104.6 seconds
Started May 14 01:01:42 PM PDT 24
Finished May 14 01:03:29 PM PDT 24
Peak memory 200508 kb
Host smart-3c625800-bd15-419f-a0a2-80a8a107abab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166156832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3166156832
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2070793598
Short name T367
Test name
Test status
Simulation time 177258946785 ps
CPU time 31.3 seconds
Started May 14 01:01:41 PM PDT 24
Finished May 14 01:02:15 PM PDT 24
Peak memory 200564 kb
Host smart-b2975333-719b-40d1-a6c2-35b7aa9911e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070793598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2070793598
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3198580267
Short name T231
Test name
Test status
Simulation time 72078964894 ps
CPU time 28.88 seconds
Started May 14 01:01:40 PM PDT 24
Finished May 14 01:02:12 PM PDT 24
Peak memory 200472 kb
Host smart-cd0eb639-096e-4ad0-ac65-c99a42dab4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198580267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3198580267
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2418751221
Short name T461
Test name
Test status
Simulation time 142895016217 ps
CPU time 55.87 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:02:51 PM PDT 24
Peak memory 200396 kb
Host smart-75db0119-4b85-48fe-971e-088bdce142ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418751221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2418751221
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4070921266
Short name T704
Test name
Test status
Simulation time 112092572862 ps
CPU time 31.18 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:02:27 PM PDT 24
Peak memory 200500 kb
Host smart-50816a30-b0c0-44d9-b0dc-905f241c5923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070921266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4070921266
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2439039570
Short name T1143
Test name
Test status
Simulation time 21135627971 ps
CPU time 10.72 seconds
Started May 14 01:01:50 PM PDT 24
Finished May 14 01:02:03 PM PDT 24
Peak memory 200216 kb
Host smart-92f1f06d-6971-4cb5-a69a-cd36ebe47055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439039570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2439039570
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1827523172
Short name T218
Test name
Test status
Simulation time 76428916915 ps
CPU time 33.1 seconds
Started May 14 01:01:55 PM PDT 24
Finished May 14 01:02:32 PM PDT 24
Peak memory 200436 kb
Host smart-d38f69b8-f595-4a8d-b8fd-d809df88839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827523172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1827523172
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.941430170
Short name T532
Test name
Test status
Simulation time 70620789518 ps
CPU time 75.98 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:03:13 PM PDT 24
Peak memory 200432 kb
Host smart-afb545d6-033a-4e81-927e-eac8cd5828ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941430170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.941430170
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.965009919
Short name T1027
Test name
Test status
Simulation time 17113539 ps
CPU time 0.53 seconds
Started May 14 12:58:29 PM PDT 24
Finished May 14 12:58:42 PM PDT 24
Peak memory 194868 kb
Host smart-52ffdc2a-9284-4cce-acd3-e2dc47f10e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965009919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.965009919
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.204004131
Short name T392
Test name
Test status
Simulation time 70859397607 ps
CPU time 37.9 seconds
Started May 14 12:58:23 PM PDT 24
Finished May 14 12:59:01 PM PDT 24
Peak memory 200500 kb
Host smart-e17c1168-3d01-4fed-9aa2-b5bebc628c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204004131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.204004131
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4183575831
Short name T756
Test name
Test status
Simulation time 79235791572 ps
CPU time 38.98 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 12:58:57 PM PDT 24
Peak memory 199944 kb
Host smart-d5d9faa2-5452-48e6-b040-626954fb9f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183575831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4183575831
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2916271324
Short name T170
Test name
Test status
Simulation time 53332639601 ps
CPU time 124.73 seconds
Started May 14 12:58:20 PM PDT 24
Finished May 14 01:00:26 PM PDT 24
Peak memory 200436 kb
Host smart-281e2dee-af36-4fbb-ba83-a6fc8b1e0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916271324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2916271324
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2736037033
Short name T561
Test name
Test status
Simulation time 12578801578 ps
CPU time 6.11 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 12:58:24 PM PDT 24
Peak memory 200128 kb
Host smart-21b0333b-ad82-4f29-b6e8-e8264f9c59a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736037033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2736037033
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1479370351
Short name T1059
Test name
Test status
Simulation time 93043360383 ps
CPU time 649.81 seconds
Started May 14 12:58:19 PM PDT 24
Finished May 14 01:09:10 PM PDT 24
Peak memory 200520 kb
Host smart-6782abea-f5a0-471f-b37d-2960b71992ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479370351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1479370351
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1576703301
Short name T538
Test name
Test status
Simulation time 8429259521 ps
CPU time 9.42 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 199948 kb
Host smart-acf09d95-ddd2-4d56-8115-18afed1d7b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576703301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1576703301
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1306548147
Short name T787
Test name
Test status
Simulation time 23460314145 ps
CPU time 45.71 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:59:05 PM PDT 24
Peak memory 200688 kb
Host smart-9e044621-146d-4006-9777-d8d7fb7a5a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306548147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1306548147
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1011206789
Short name T430
Test name
Test status
Simulation time 23480930503 ps
CPU time 677.09 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 01:09:36 PM PDT 24
Peak memory 200416 kb
Host smart-d19825a7-f5b4-4329-833b-79c9a98f8b1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011206789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1011206789
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1365182885
Short name T663
Test name
Test status
Simulation time 1810369710 ps
CPU time 3.6 seconds
Started May 14 12:58:16 PM PDT 24
Finished May 14 12:58:21 PM PDT 24
Peak memory 199556 kb
Host smart-ad6a473b-e056-4c8f-b04d-5618ea092c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365182885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1365182885
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3761573758
Short name T159
Test name
Test status
Simulation time 26372802619 ps
CPU time 9.77 seconds
Started May 14 12:58:21 PM PDT 24
Finished May 14 12:58:32 PM PDT 24
Peak memory 200380 kb
Host smart-92ff7bdc-5e57-474d-a921-e1928ed79aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761573758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3761573758
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.889019698
Short name T535
Test name
Test status
Simulation time 31724216879 ps
CPU time 45.68 seconds
Started May 14 12:58:17 PM PDT 24
Finished May 14 12:59:03 PM PDT 24
Peak memory 196180 kb
Host smart-1caa5d03-8270-4c07-871e-5a3522cf4e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889019698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.889019698
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.18297353
Short name T314
Test name
Test status
Simulation time 5896670552 ps
CPU time 16.3 seconds
Started May 14 12:58:20 PM PDT 24
Finished May 14 12:58:38 PM PDT 24
Peak memory 200500 kb
Host smart-63a393e0-cf93-4c74-bef8-0c88500b655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18297353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.18297353
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2504504359
Short name T1152
Test name
Test status
Simulation time 170535222736 ps
CPU time 331.33 seconds
Started May 14 12:58:25 PM PDT 24
Finished May 14 01:03:59 PM PDT 24
Peak memory 200908 kb
Host smart-510d8d63-5746-42ce-82c5-ee9b39ca0044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504504359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2504504359
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1082210172
Short name T539
Test name
Test status
Simulation time 681809465862 ps
CPU time 524.18 seconds
Started May 14 12:58:25 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 214440 kb
Host smart-6e589d7a-1350-4b75-8579-eddd780d213a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082210172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1082210172
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2991058776
Short name T618
Test name
Test status
Simulation time 683150878 ps
CPU time 2.67 seconds
Started May 14 12:58:20 PM PDT 24
Finished May 14 12:58:24 PM PDT 24
Peak memory 200372 kb
Host smart-2ee6c185-8db0-403a-90ac-492a23c5faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991058776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2991058776
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.4237806744
Short name T92
Test name
Test status
Simulation time 6980845914 ps
CPU time 12.67 seconds
Started May 14 12:58:18 PM PDT 24
Finished May 14 12:58:32 PM PDT 24
Peak memory 200252 kb
Host smart-bc82d7df-13b1-4bfe-843f-5d8e38d7bf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237806744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.4237806744
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3747960705
Short name T902
Test name
Test status
Simulation time 48788019822 ps
CPU time 84.19 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:03:20 PM PDT 24
Peak memory 200404 kb
Host smart-75f0866f-0ac6-487b-a575-18367301cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747960705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3747960705
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1422362325
Short name T313
Test name
Test status
Simulation time 34561144503 ps
CPU time 16.04 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:02:13 PM PDT 24
Peak memory 200452 kb
Host smart-285ac1d1-da8e-456f-8d64-10e1abdf0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422362325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1422362325
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3043297178
Short name T56
Test name
Test status
Simulation time 223640038449 ps
CPU time 41.15 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:02:38 PM PDT 24
Peak memory 200424 kb
Host smart-243a5a7c-003a-4d0c-a22e-de3d85604f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043297178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3043297178
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1145904406
Short name T174
Test name
Test status
Simulation time 37469424216 ps
CPU time 41.39 seconds
Started May 14 01:01:56 PM PDT 24
Finished May 14 01:02:41 PM PDT 24
Peak memory 200348 kb
Host smart-e2cdc30d-4ee9-4cbb-9a11-7414078a0dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145904406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1145904406
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.263312451
Short name T201
Test name
Test status
Simulation time 52178516892 ps
CPU time 69.65 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:03:06 PM PDT 24
Peak memory 200420 kb
Host smart-6965a8de-9dc7-498f-9ca1-2cc5978a6810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263312451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.263312451
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2093769023
Short name T202
Test name
Test status
Simulation time 7598642555 ps
CPU time 13.13 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:02:09 PM PDT 24
Peak memory 200344 kb
Host smart-71102412-bd79-4820-9534-085d5c5707d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093769023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2093769023
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2305664974
Short name T168
Test name
Test status
Simulation time 26503901543 ps
CPU time 18.29 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 200164 kb
Host smart-a07972e9-4e8f-4f5e-b516-f6f246f940a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305664974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2305664974
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.571820239
Short name T676
Test name
Test status
Simulation time 8940389486 ps
CPU time 24.72 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:02:22 PM PDT 24
Peak memory 200444 kb
Host smart-765bc337-fae7-43ea-b40c-4b0c6b91c576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571820239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.571820239
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1494365285
Short name T957
Test name
Test status
Simulation time 81718695863 ps
CPU time 17.67 seconds
Started May 14 01:01:56 PM PDT 24
Finished May 14 01:02:17 PM PDT 24
Peak memory 200344 kb
Host smart-a0f49166-ba29-4cbb-bbc8-6e4b01bbb191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494365285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1494365285
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1819656710
Short name T229
Test name
Test status
Simulation time 56489400326 ps
CPU time 21.67 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:02:18 PM PDT 24
Peak memory 200444 kb
Host smart-96dd9922-6204-4e56-9117-26c877fa6f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819656710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1819656710
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.268429689
Short name T810
Test name
Test status
Simulation time 23423770 ps
CPU time 0.55 seconds
Started May 14 12:58:25 PM PDT 24
Finished May 14 12:58:28 PM PDT 24
Peak memory 194788 kb
Host smart-ad7e9526-6655-4eba-94f3-00b6d576338d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268429689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.268429689
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3786447100
Short name T1174
Test name
Test status
Simulation time 80366334762 ps
CPU time 64.77 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 12:59:38 PM PDT 24
Peak memory 200508 kb
Host smart-959f9911-11f8-48b5-aedb-1a12c5a11fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786447100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3786447100
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3418792671
Short name T7
Test name
Test status
Simulation time 93860233448 ps
CPU time 217.74 seconds
Started May 14 12:58:25 PM PDT 24
Finished May 14 01:02:05 PM PDT 24
Peak memory 200384 kb
Host smart-c5d13871-45d2-4d99-8449-ac62a3d74e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418792671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3418792671
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.80392336
Short name T1004
Test name
Test status
Simulation time 134065538729 ps
CPU time 264.73 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 01:03:01 PM PDT 24
Peak memory 200500 kb
Host smart-c51ea82e-bfca-4c7e-8434-8a50e3608474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80392336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.80392336
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2032468989
Short name T975
Test name
Test status
Simulation time 57014178835 ps
CPU time 84.11 seconds
Started May 14 12:58:24 PM PDT 24
Finished May 14 12:59:49 PM PDT 24
Peak memory 200368 kb
Host smart-aff7e4f1-feab-4bf3-91c1-42f2390f70a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032468989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2032468989
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3704202250
Short name T744
Test name
Test status
Simulation time 75485793445 ps
CPU time 600.17 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 01:08:32 PM PDT 24
Peak memory 200424 kb
Host smart-5016c64b-1905-4a52-be6a-f48043fe1b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704202250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3704202250
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3987777129
Short name T1146
Test name
Test status
Simulation time 939800763 ps
CPU time 1.13 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 12:58:38 PM PDT 24
Peak memory 197604 kb
Host smart-56c60262-3aba-4252-925a-eddf21e467b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987777129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3987777129
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2816095209
Short name T579
Test name
Test status
Simulation time 165234336080 ps
CPU time 273.63 seconds
Started May 14 12:58:27 PM PDT 24
Finished May 14 01:03:04 PM PDT 24
Peak memory 217016 kb
Host smart-c3e21732-d792-4139-a3fb-c3ee252085fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816095209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2816095209
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1450025467
Short name T564
Test name
Test status
Simulation time 31826943318 ps
CPU time 1604.21 seconds
Started May 14 12:58:26 PM PDT 24
Finished May 14 01:25:14 PM PDT 24
Peak memory 200468 kb
Host smart-da6fe2c2-8bea-4549-a664-b6d721972477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450025467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1450025467
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3771000347
Short name T945
Test name
Test status
Simulation time 6873160508 ps
CPU time 28.57 seconds
Started May 14 12:58:32 PM PDT 24
Finished May 14 12:59:22 PM PDT 24
Peak memory 199312 kb
Host smart-0c278a97-e2c6-4a8c-a167-52d0c80882b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771000347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3771000347
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.263332975
Short name T1029
Test name
Test status
Simulation time 18185659949 ps
CPU time 23.48 seconds
Started May 14 12:58:24 PM PDT 24
Finished May 14 12:58:48 PM PDT 24
Peak memory 200332 kb
Host smart-11e7f2d1-ec22-43d8-8dcf-78bf9a8b5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263332975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.263332975
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2753268166
Short name T394
Test name
Test status
Simulation time 3803972223 ps
CPU time 3.63 seconds
Started May 14 12:58:27 PM PDT 24
Finished May 14 12:58:35 PM PDT 24
Peak memory 196452 kb
Host smart-85fed40a-fd32-4e81-8773-4a27ed2d87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753268166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2753268166
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1426646407
Short name T1099
Test name
Test status
Simulation time 5966703991 ps
CPU time 29.96 seconds
Started May 14 12:58:27 PM PDT 24
Finished May 14 12:59:02 PM PDT 24
Peak memory 200264 kb
Host smart-d8345085-6ce0-4906-9ab7-159bc1d85f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426646407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1426646407
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.659509587
Short name T783
Test name
Test status
Simulation time 280340778727 ps
CPU time 288.9 seconds
Started May 14 12:58:27 PM PDT 24
Finished May 14 01:03:20 PM PDT 24
Peak memory 200500 kb
Host smart-d0c8e3e7-8f44-4729-8063-930898dea6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659509587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.659509587
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3677229747
Short name T615
Test name
Test status
Simulation time 169605007747 ps
CPU time 881.02 seconds
Started May 14 12:58:25 PM PDT 24
Finished May 14 01:13:09 PM PDT 24
Peak memory 228948 kb
Host smart-637cb648-f018-4c1b-94cd-94a2e52e9b93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677229747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3677229747
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1925013334
Short name T1096
Test name
Test status
Simulation time 6536829329 ps
CPU time 7.2 seconds
Started May 14 12:58:31 PM PDT 24
Finished May 14 12:58:56 PM PDT 24
Peak memory 199748 kb
Host smart-4daf95b6-a09f-4d63-a663-1981c8c20fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925013334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1925013334
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1351141754
Short name T884
Test name
Test status
Simulation time 32711040969 ps
CPU time 55.52 seconds
Started May 14 12:58:30 PM PDT 24
Finished May 14 12:59:41 PM PDT 24
Peak memory 200416 kb
Host smart-0c364123-4bec-4a15-853a-4172d5a49e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351141754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1351141754
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3317362169
Short name T473
Test name
Test status
Simulation time 51504535085 ps
CPU time 64.36 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:03:01 PM PDT 24
Peak memory 200456 kb
Host smart-95fc4ebf-9f38-4fac-b149-55f2bcfd7baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317362169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3317362169
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2048185620
Short name T607
Test name
Test status
Simulation time 116009964617 ps
CPU time 52.47 seconds
Started May 14 01:01:51 PM PDT 24
Finished May 14 01:02:47 PM PDT 24
Peak memory 200444 kb
Host smart-f780898a-e274-483f-b890-bc7bc4b41a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048185620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2048185620
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3743216351
Short name T778
Test name
Test status
Simulation time 115299386458 ps
CPU time 233.33 seconds
Started May 14 01:01:54 PM PDT 24
Finished May 14 01:05:51 PM PDT 24
Peak memory 200412 kb
Host smart-d78d5d17-1697-4c6f-8553-b7c0926f9b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743216351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3743216351
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2714822965
Short name T1103
Test name
Test status
Simulation time 113336102937 ps
CPU time 34.69 seconds
Started May 14 01:01:50 PM PDT 24
Finished May 14 01:02:27 PM PDT 24
Peak memory 200500 kb
Host smart-3b3af93b-ab6f-40d6-a26f-23bb650a16aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714822965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2714822965
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3688311934
Short name T111
Test name
Test status
Simulation time 96754259500 ps
CPU time 80.26 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:03:16 PM PDT 24
Peak memory 200536 kb
Host smart-b3d18063-9f2f-4ff9-bf41-c39e2e558dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688311934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3688311934
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2553002099
Short name T559
Test name
Test status
Simulation time 242340594073 ps
CPU time 186.99 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:05:04 PM PDT 24
Peak memory 200412 kb
Host smart-f54e2f5c-6eb3-417c-b46c-fc7f36bf2252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553002099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2553002099
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.802954708
Short name T921
Test name
Test status
Simulation time 14427787273 ps
CPU time 25.49 seconds
Started May 14 01:01:50 PM PDT 24
Finished May 14 01:02:18 PM PDT 24
Peak memory 200228 kb
Host smart-9d6848eb-630d-4761-a585-e14ccf1a5657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802954708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.802954708
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.909108011
Short name T137
Test name
Test status
Simulation time 45236161563 ps
CPU time 73.56 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:03:10 PM PDT 24
Peak memory 200448 kb
Host smart-4eef4ed3-f284-433b-b500-546526290414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909108011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.909108011
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1121307404
Short name T1022
Test name
Test status
Simulation time 111914728015 ps
CPU time 204.11 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:05:21 PM PDT 24
Peak memory 200512 kb
Host smart-a589ece4-bc08-47fd-9e5a-a5833d386cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121307404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1121307404
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1436509335
Short name T171
Test name
Test status
Simulation time 33625252577 ps
CPU time 53.32 seconds
Started May 14 01:01:52 PM PDT 24
Finished May 14 01:02:50 PM PDT 24
Peak memory 200496 kb
Host smart-1f247ecc-a956-4de5-9d21-167d56449754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436509335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1436509335
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3993781848
Short name T675
Test name
Test status
Simulation time 20165079 ps
CPU time 0.6 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 12:58:34 PM PDT 24
Peak memory 195832 kb
Host smart-97ca0938-9973-435c-9873-02756b7e941e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993781848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3993781848
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1269923930
Short name T249
Test name
Test status
Simulation time 130400693824 ps
CPU time 102.53 seconds
Started May 14 12:58:32 PM PDT 24
Finished May 14 01:00:36 PM PDT 24
Peak memory 200472 kb
Host smart-8b52ff72-2d5b-4330-84fb-d730d7ccc1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269923930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1269923930
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1478073078
Short name T844
Test name
Test status
Simulation time 218025666114 ps
CPU time 263.08 seconds
Started May 14 12:58:27 PM PDT 24
Finished May 14 01:02:55 PM PDT 24
Peak memory 200424 kb
Host smart-3588264a-0050-431e-926c-c59ea0323a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478073078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1478073078
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3507933168
Short name T236
Test name
Test status
Simulation time 268559527886 ps
CPU time 248.81 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 01:02:42 PM PDT 24
Peak memory 200504 kb
Host smart-5a4ac8ca-0d2e-4dcf-9b8a-ac8ca9f8283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507933168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3507933168
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2100205202
Short name T804
Test name
Test status
Simulation time 73213507853 ps
CPU time 38.28 seconds
Started May 14 12:58:24 PM PDT 24
Finished May 14 12:59:04 PM PDT 24
Peak memory 200436 kb
Host smart-49e5b8b9-c444-4ad1-9c7b-e74902cfacfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100205202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2100205202
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1117354885
Short name T597
Test name
Test status
Simulation time 237384463724 ps
CPU time 68.6 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 200512 kb
Host smart-12064e42-be94-4481-a724-307341212578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117354885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1117354885
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.66650140
Short name T956
Test name
Test status
Simulation time 7482783012 ps
CPU time 14.6 seconds
Started May 14 12:58:26 PM PDT 24
Finished May 14 12:58:44 PM PDT 24
Peak memory 199364 kb
Host smart-a168c042-71df-4b3e-b19b-04793a7e4ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66650140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.66650140
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2216749146
Short name T503
Test name
Test status
Simulation time 26908585011 ps
CPU time 27.68 seconds
Started May 14 12:58:27 PM PDT 24
Finished May 14 12:58:57 PM PDT 24
Peak memory 200712 kb
Host smart-e401ac7a-6393-4e23-9723-3956bf636fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216749146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2216749146
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2767177197
Short name T871
Test name
Test status
Simulation time 28791532346 ps
CPU time 1569.91 seconds
Started May 14 12:58:31 PM PDT 24
Finished May 14 01:24:59 PM PDT 24
Peak memory 200364 kb
Host smart-18a2972b-8f54-4b26-a63a-244777dc963a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767177197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2767177197
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1298105046
Short name T826
Test name
Test status
Simulation time 7127903909 ps
CPU time 16.13 seconds
Started May 14 12:58:26 PM PDT 24
Finished May 14 12:58:45 PM PDT 24
Peak memory 199692 kb
Host smart-a2a2ed7d-cbbc-40fe-a2a7-b2fc616c3b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298105046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1298105046
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3610650142
Short name T993
Test name
Test status
Simulation time 131518795516 ps
CPU time 26.39 seconds
Started May 14 12:58:32 PM PDT 24
Finished May 14 12:59:20 PM PDT 24
Peak memory 200440 kb
Host smart-60cfa3c4-4dd9-4361-a069-b7eb51edbf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610650142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3610650142
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1876352823
Short name T530
Test name
Test status
Simulation time 647757857 ps
CPU time 0.85 seconds
Started May 14 12:58:26 PM PDT 24
Finished May 14 12:58:30 PM PDT 24
Peak memory 195780 kb
Host smart-00dbc851-f480-484f-a0c0-e98289b13f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876352823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1876352823
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3600710110
Short name T300
Test name
Test status
Simulation time 490771427 ps
CPU time 2.45 seconds
Started May 14 12:58:26 PM PDT 24
Finished May 14 12:58:31 PM PDT 24
Peak memory 198736 kb
Host smart-ace5d0b1-825b-4328-91dc-06e23f457169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600710110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3600710110
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2118693020
Short name T184
Test name
Test status
Simulation time 406450843136 ps
CPU time 482.35 seconds
Started May 14 12:58:31 PM PDT 24
Finished May 14 01:06:51 PM PDT 24
Peak memory 216652 kb
Host smart-faf4bef4-a40e-49b6-993f-fabb73100965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118693020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2118693020
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2282846704
Short name T886
Test name
Test status
Simulation time 239484040977 ps
CPU time 908.01 seconds
Started May 14 12:58:25 PM PDT 24
Finished May 14 01:13:35 PM PDT 24
Peak memory 216956 kb
Host smart-dcc92850-8ae9-4d1e-9fcb-5a85597b1740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282846704 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2282846704
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2692616668
Short name T946
Test name
Test status
Simulation time 8336667930 ps
CPU time 9.19 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 12:58:44 PM PDT 24
Peak memory 199896 kb
Host smart-5c7b41df-3587-4a16-ad8c-e9d2b59f6f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692616668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2692616668
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3815946056
Short name T600
Test name
Test status
Simulation time 331521513433 ps
CPU time 87.66 seconds
Started May 14 12:58:28 PM PDT 24
Finished May 14 01:00:01 PM PDT 24
Peak memory 200504 kb
Host smart-dd1ae953-878d-470a-a8a8-5ffeb8122bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815946056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3815946056
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3479693798
Short name T695
Test name
Test status
Simulation time 149707636555 ps
CPU time 56.04 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:02:53 PM PDT 24
Peak memory 200484 kb
Host smart-9a1a9953-1244-4c43-bc8b-f6079041f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479693798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3479693798
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1916235018
Short name T906
Test name
Test status
Simulation time 127300169870 ps
CPU time 36.16 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:02:33 PM PDT 24
Peak memory 200520 kb
Host smart-1a8dcea6-1fc5-4303-a20a-b3f05838a84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916235018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1916235018
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1390162105
Short name T206
Test name
Test status
Simulation time 9563935082 ps
CPU time 16.63 seconds
Started May 14 01:01:53 PM PDT 24
Finished May 14 01:02:13 PM PDT 24
Peak memory 200056 kb
Host smart-4e8c3fe2-aab4-4f2e-9a3d-36ccc3080e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390162105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1390162105
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4236889362
Short name T1055
Test name
Test status
Simulation time 22100579493 ps
CPU time 37.52 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:05:12 PM PDT 24
Peak memory 200508 kb
Host smart-07348ddd-2b95-472c-8e21-447ab511c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236889362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4236889362
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.782370729
Short name T613
Test name
Test status
Simulation time 54569584140 ps
CPU time 40.43 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:05:14 PM PDT 24
Peak memory 200508 kb
Host smart-0ffe4cab-7df1-47b2-bc80-1b6e9b9a3a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782370729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.782370729
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3200066114
Short name T188
Test name
Test status
Simulation time 23828807715 ps
CPU time 40.22 seconds
Started May 14 01:04:40 PM PDT 24
Finished May 14 01:05:21 PM PDT 24
Peak memory 200416 kb
Host smart-5b534df7-1365-45a2-9732-b632f4e754db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200066114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3200066114
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3282616518
Short name T645
Test name
Test status
Simulation time 58616611577 ps
CPU time 94.61 seconds
Started May 14 01:04:34 PM PDT 24
Finished May 14 01:06:10 PM PDT 24
Peak memory 200248 kb
Host smart-9d53eda1-f663-4cf2-8bed-8fb0bd840868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282616518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3282616518
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1688653980
Short name T953
Test name
Test status
Simulation time 50108346407 ps
CPU time 23.17 seconds
Started May 14 01:04:37 PM PDT 24
Finished May 14 01:05:02 PM PDT 24
Peak memory 200472 kb
Host smart-0f1943d7-39a0-495e-88e0-9efb23ae9cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688653980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1688653980
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.4272642751
Short name T179
Test name
Test status
Simulation time 188888113597 ps
CPU time 95.26 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:06:09 PM PDT 24
Peak memory 200324 kb
Host smart-643b5a14-6bc6-4557-99a7-27336ecc7f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272642751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4272642751
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1630307584
Short name T10
Test name
Test status
Simulation time 23097407769 ps
CPU time 37.64 seconds
Started May 14 01:04:37 PM PDT 24
Finished May 14 01:05:16 PM PDT 24
Peak memory 200428 kb
Host smart-24efc6de-6833-4b9c-8438-98155292f976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630307584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1630307584
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.280348433
Short name T519
Test name
Test status
Simulation time 14610362 ps
CPU time 0.55 seconds
Started May 14 12:58:36 PM PDT 24
Finished May 14 12:59:04 PM PDT 24
Peak memory 195668 kb
Host smart-8aae5861-5f73-4c88-bfc5-479475542139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280348433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.280348433
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2071827730
Short name T255
Test name
Test status
Simulation time 120223675686 ps
CPU time 105.78 seconds
Started May 14 12:58:32 PM PDT 24
Finished May 14 01:00:39 PM PDT 24
Peak memory 200532 kb
Host smart-cf553a95-46bd-4202-9cce-f7a328f9c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071827730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2071827730
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.63151896
Short name T685
Test name
Test status
Simulation time 20507653747 ps
CPU time 31.27 seconds
Started May 14 12:58:24 PM PDT 24
Finished May 14 12:58:57 PM PDT 24
Peak memory 200300 kb
Host smart-f61609a8-47c4-42c0-9008-6f0b08942175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63151896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.63151896
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3010972240
Short name T385
Test name
Test status
Simulation time 16962125971 ps
CPU time 23.62 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 12:59:24 PM PDT 24
Peak memory 200412 kb
Host smart-22e73d43-363b-491d-9e5e-7f2e0d4c0226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010972240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3010972240
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.661337906
Short name T397
Test name
Test status
Simulation time 231693012846 ps
CPU time 106.15 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 01:00:43 PM PDT 24
Peak memory 200516 kb
Host smart-aa585e98-c140-4925-a929-c2f369f0da70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661337906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.661337906
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3552561039
Short name T499
Test name
Test status
Simulation time 59653139492 ps
CPU time 406.35 seconds
Started May 14 12:58:37 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 200432 kb
Host smart-05526d0a-42ed-40c4-9d59-1ce286eb7b1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552561039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3552561039
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3926278554
Short name T1088
Test name
Test status
Simulation time 9247223362 ps
CPU time 8.83 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 12:59:06 PM PDT 24
Peak memory 200440 kb
Host smart-7f284ada-01c0-44c4-b479-cbccde8d9a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926278554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3926278554
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1577457389
Short name T308
Test name
Test status
Simulation time 153918874233 ps
CPU time 69.92 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 01:00:09 PM PDT 24
Peak memory 208916 kb
Host smart-0f86c877-1f70-4c1a-a2e9-e5e38ff052a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577457389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1577457389
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1229842159
Short name T753
Test name
Test status
Simulation time 6665260785 ps
CPU time 91.26 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 01:00:28 PM PDT 24
Peak memory 200340 kb
Host smart-a093b0af-fa3f-448d-bfc3-781ca84f55e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229842159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1229842159
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1901398739
Short name T388
Test name
Test status
Simulation time 1593913745 ps
CPU time 9.19 seconds
Started May 14 12:58:36 PM PDT 24
Finished May 14 12:59:12 PM PDT 24
Peak memory 198592 kb
Host smart-57054464-3ca2-42e2-9bc8-86b3baf7704a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901398739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1901398739
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1116203922
Short name T789
Test name
Test status
Simulation time 37500129688 ps
CPU time 18.22 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 12:59:17 PM PDT 24
Peak memory 200308 kb
Host smart-9ffa2b28-999e-49ba-80e3-32b704e8d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116203922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1116203922
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1962838797
Short name T1035
Test name
Test status
Simulation time 2224903709 ps
CPU time 4.16 seconds
Started May 14 12:58:36 PM PDT 24
Finished May 14 12:59:06 PM PDT 24
Peak memory 195952 kb
Host smart-c768a41a-967d-4841-ad20-0cf2ffb72635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962838797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1962838797
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.762508771
Short name T660
Test name
Test status
Simulation time 668814510 ps
CPU time 1.72 seconds
Started May 14 12:58:31 PM PDT 24
Finished May 14 12:58:51 PM PDT 24
Peak memory 199056 kb
Host smart-67b6eae4-2902-4890-bb53-3dcdbe818288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762508771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.762508771
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.942260488
Short name T315
Test name
Test status
Simulation time 92203704674 ps
CPU time 160.99 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 01:01:53 PM PDT 24
Peak memory 200432 kb
Host smart-02a5d853-3bd9-4dca-8f01-fd6b8e6ac72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942260488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.942260488
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3894341338
Short name T463
Test name
Test status
Simulation time 126756303723 ps
CPU time 266.5 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 01:03:26 PM PDT 24
Peak memory 216928 kb
Host smart-175d21c1-110e-4b85-aa31-dc24e5071c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894341338 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3894341338
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1258631407
Short name T702
Test name
Test status
Simulation time 1467820153 ps
CPU time 1.84 seconds
Started May 14 12:58:37 PM PDT 24
Finished May 14 12:59:09 PM PDT 24
Peak memory 199556 kb
Host smart-4dfb3eda-884f-4e36-9737-46c75dd900d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258631407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1258631407
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1376800571
Short name T266
Test name
Test status
Simulation time 100966496848 ps
CPU time 176.04 seconds
Started May 14 12:58:26 PM PDT 24
Finished May 14 01:01:24 PM PDT 24
Peak memory 200480 kb
Host smart-7f82c10c-f775-4c5a-91c6-6dc1ab97059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376800571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1376800571
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.892520847
Short name T245
Test name
Test status
Simulation time 62644670844 ps
CPU time 51.5 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:05:26 PM PDT 24
Peak memory 200492 kb
Host smart-e6284cf5-cc82-422d-9035-fcfd9243d492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892520847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.892520847
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3531883959
Short name T687
Test name
Test status
Simulation time 16072580415 ps
CPU time 29.64 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:05:03 PM PDT 24
Peak memory 200448 kb
Host smart-d5dfa18f-0485-4f38-af31-1ac4e1da7a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531883959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3531883959
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2086402762
Short name T1030
Test name
Test status
Simulation time 106409186437 ps
CPU time 93.82 seconds
Started May 14 01:04:37 PM PDT 24
Finished May 14 01:06:13 PM PDT 24
Peak memory 200436 kb
Host smart-f917c028-aa29-4a0f-aba4-4b6fede5e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086402762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2086402762
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1126743317
Short name T883
Test name
Test status
Simulation time 12065713796 ps
CPU time 20.74 seconds
Started May 14 01:04:37 PM PDT 24
Finished May 14 01:05:00 PM PDT 24
Peak memory 200104 kb
Host smart-d43668a7-cf41-408b-b6ca-8619f04e043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126743317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1126743317
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.583104922
Short name T923
Test name
Test status
Simulation time 60476805387 ps
CPU time 69.54 seconds
Started May 14 01:04:33 PM PDT 24
Finished May 14 01:05:44 PM PDT 24
Peak memory 200512 kb
Host smart-7fbd1893-380b-4ff8-b033-1fd519d8678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583104922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.583104922
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.949581828
Short name T146
Test name
Test status
Simulation time 46501161860 ps
CPU time 83.56 seconds
Started May 14 01:04:34 PM PDT 24
Finished May 14 01:05:59 PM PDT 24
Peak memory 200424 kb
Host smart-aa87b45e-00fc-478f-8be0-85dcc56bf76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949581828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.949581828
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.767444549
Short name T692
Test name
Test status
Simulation time 106439061880 ps
CPU time 28.48 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:05:03 PM PDT 24
Peak memory 200500 kb
Host smart-d18b5cd7-987b-4e28-ba35-468e64bbf9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767444549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.767444549
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1283695632
Short name T751
Test name
Test status
Simulation time 135156513268 ps
CPU time 120.2 seconds
Started May 14 01:04:31 PM PDT 24
Finished May 14 01:06:33 PM PDT 24
Peak memory 200448 kb
Host smart-0c88d07e-31c6-49eb-9e8e-f7952bed0f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283695632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1283695632
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1134069627
Short name T682
Test name
Test status
Simulation time 33942286062 ps
CPU time 58 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:05:32 PM PDT 24
Peak memory 200392 kb
Host smart-53fe2fc4-0a53-4bf3-9dc5-eecce4ef151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134069627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1134069627
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3804738036
Short name T882
Test name
Test status
Simulation time 67983215843 ps
CPU time 64.02 seconds
Started May 14 01:04:33 PM PDT 24
Finished May 14 01:05:39 PM PDT 24
Peak memory 200724 kb
Host smart-09104db3-ad07-4307-8de7-565098abeaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804738036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3804738036
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2563797760
Short name T9
Test name
Test status
Simulation time 26732119 ps
CPU time 0.56 seconds
Started May 14 12:57:01 PM PDT 24
Finished May 14 12:57:03 PM PDT 24
Peak memory 195848 kb
Host smart-bb951601-368d-4b2f-ab64-4fbc6966d78a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563797760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2563797760
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1303563345
Short name T611
Test name
Test status
Simulation time 28181193597 ps
CPU time 10.77 seconds
Started May 14 12:56:52 PM PDT 24
Finished May 14 12:57:04 PM PDT 24
Peak memory 200436 kb
Host smart-eff4ce0a-db32-4816-a252-d0c74c36303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303563345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1303563345
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1670349179
Short name T602
Test name
Test status
Simulation time 29514163181 ps
CPU time 26.38 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:57:22 PM PDT 24
Peak memory 200420 kb
Host smart-a68b27fa-eefa-47de-b0c0-1e23d8409ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670349179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1670349179
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.465412746
Short name T978
Test name
Test status
Simulation time 123574566097 ps
CPU time 58.79 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 200452 kb
Host smart-bc224862-834a-4862-9569-45089a8a90e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465412746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.465412746
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1484731272
Short name T588
Test name
Test status
Simulation time 38791132444 ps
CPU time 40.55 seconds
Started May 14 12:56:55 PM PDT 24
Finished May 14 12:57:38 PM PDT 24
Peak memory 200340 kb
Host smart-4faf18dd-fbf0-45b0-b6b0-da69885937b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484731272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1484731272
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.591725432
Short name T929
Test name
Test status
Simulation time 75742295268 ps
CPU time 600.11 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 200384 kb
Host smart-ef881485-a8ad-4242-8855-cda68fd0b360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591725432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.591725432
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1573104367
Short name T938
Test name
Test status
Simulation time 1081608012 ps
CPU time 2.52 seconds
Started May 14 12:57:05 PM PDT 24
Finished May 14 12:57:09 PM PDT 24
Peak memory 195932 kb
Host smart-0c230c0f-1bef-47bb-a609-e326eb15dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573104367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1573104367
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.577752826
Short name T1011
Test name
Test status
Simulation time 144193210947 ps
CPU time 35.57 seconds
Started May 14 12:56:54 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 200224 kb
Host smart-a959df22-5b2f-4931-9e9d-43e077ef00b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577752826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.577752826
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.25457395
Short name T1137
Test name
Test status
Simulation time 9002189063 ps
CPU time 526.91 seconds
Started May 14 12:57:01 PM PDT 24
Finished May 14 01:05:51 PM PDT 24
Peak memory 200432 kb
Host smart-cb2c8b36-ad41-4503-909b-63b11c801b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25457395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.25457395
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1140422790
Short name T14
Test name
Test status
Simulation time 4005422052 ps
CPU time 8.64 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 199604 kb
Host smart-92a5481d-2a5c-4f81-9914-4ad02eb746d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140422790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1140422790
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1894863514
Short name T813
Test name
Test status
Simulation time 104339350674 ps
CPU time 99.9 seconds
Started May 14 12:56:56 PM PDT 24
Finished May 14 12:58:38 PM PDT 24
Peak memory 200324 kb
Host smart-6438d762-ce40-4fd4-8b28-436c02392a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894863514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1894863514
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4194933404
Short name T977
Test name
Test status
Simulation time 4813608423 ps
CPU time 8.38 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 196468 kb
Host smart-ddbcbce5-3e35-4390-a62c-4152bf52b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194933404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4194933404
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.778735732
Short name T91
Test name
Test status
Simulation time 151618593 ps
CPU time 0.77 seconds
Started May 14 12:57:04 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 218912 kb
Host smart-01db7ff1-2398-4ecc-a260-c5b9edfda518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778735732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.778735732
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.125768163
Short name T971
Test name
Test status
Simulation time 721564340 ps
CPU time 1.62 seconds
Started May 14 12:56:53 PM PDT 24
Finished May 14 12:56:56 PM PDT 24
Peak memory 198792 kb
Host smart-79196a72-e057-4522-a7a6-cff51422aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125768163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.125768163
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3191330598
Short name T450
Test name
Test status
Simulation time 342484022002 ps
CPU time 553.92 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 01:06:18 PM PDT 24
Peak memory 208900 kb
Host smart-3258383e-59be-4d16-9bef-f57c8c21a683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191330598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3191330598
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.616917728
Short name T560
Test name
Test status
Simulation time 243835182064 ps
CPU time 246.9 seconds
Started May 14 12:57:06 PM PDT 24
Finished May 14 01:01:14 PM PDT 24
Peak memory 216492 kb
Host smart-e2487027-987a-4150-9bf2-582b468413bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616917728 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.616917728
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3497072829
Short name T320
Test name
Test status
Simulation time 638569952 ps
CPU time 2.63 seconds
Started May 14 12:57:03 PM PDT 24
Finished May 14 12:57:08 PM PDT 24
Peak memory 199000 kb
Host smart-cf91c1b5-ccd1-46cd-aa5a-3254f988ee48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497072829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3497072829
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1411713735
Short name T797
Test name
Test status
Simulation time 67340353823 ps
CPU time 76.19 seconds
Started May 14 12:56:57 PM PDT 24
Finished May 14 12:58:16 PM PDT 24
Peak memory 200384 kb
Host smart-1642fbc0-b66d-4818-8122-757354f8c6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411713735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1411713735
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1907944525
Short name T919
Test name
Test status
Simulation time 152705757 ps
CPU time 0.54 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 12:59:00 PM PDT 24
Peak memory 195812 kb
Host smart-67e03d90-03b3-4da3-bc56-af9989cb0c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907944525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1907944525
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2662717648
Short name T147
Test name
Test status
Simulation time 145746921890 ps
CPU time 71.58 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 01:00:09 PM PDT 24
Peak memory 200504 kb
Host smart-fd55dec7-8b5f-4360-abea-af18964d68c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662717648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2662717648
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3274402281
Short name T372
Test name
Test status
Simulation time 9363787716 ps
CPU time 17.09 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 12:59:15 PM PDT 24
Peak memory 200280 kb
Host smart-48d7eb2b-947c-41d3-9c4e-5aa45e8f300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274402281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3274402281
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2331410178
Short name T341
Test name
Test status
Simulation time 61548088185 ps
CPU time 24.06 seconds
Started May 14 12:58:33 PM PDT 24
Finished May 14 12:59:21 PM PDT 24
Peak memory 200340 kb
Host smart-ca3847d4-1435-4219-9b45-220e8c86384f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331410178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2331410178
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2464874793
Short name T318
Test name
Test status
Simulation time 54148429963 ps
CPU time 88.35 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 01:00:26 PM PDT 24
Peak memory 200424 kb
Host smart-9ac30b83-dd15-49b5-b903-9353ff814b62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464874793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2464874793
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_loopback.1576576127
Short name T332
Test name
Test status
Simulation time 7457614250 ps
CPU time 8.74 seconds
Started May 14 12:58:36 PM PDT 24
Finished May 14 12:59:11 PM PDT 24
Peak memory 200260 kb
Host smart-061c312f-0cf8-4584-b0c5-f657d399e69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576576127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1576576127
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3246048401
Short name T907
Test name
Test status
Simulation time 9724613081 ps
CPU time 13.78 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 12:59:27 PM PDT 24
Peak memory 197544 kb
Host smart-3056659a-42eb-4fef-8495-5dcedeb32e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246048401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3246048401
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1862634297
Short name T1154
Test name
Test status
Simulation time 5983511429 ps
CPU time 172.09 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 01:01:53 PM PDT 24
Peak memory 200380 kb
Host smart-ad6e34f8-d8db-43d3-8188-25d718f9d6cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862634297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1862634297
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1974446863
Short name T1172
Test name
Test status
Simulation time 4344974780 ps
CPU time 35.22 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 12:59:33 PM PDT 24
Peak memory 200348 kb
Host smart-f0c591fb-3543-4f3d-a509-aa468be37214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974446863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1974446863
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2375851788
Short name T661
Test name
Test status
Simulation time 50482155344 ps
CPU time 42.08 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 200236 kb
Host smart-9871db2b-1c1e-4a23-8a2b-2ffa2d8bd027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375851788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2375851788
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3667192771
Short name T850
Test name
Test status
Simulation time 30981203392 ps
CPU time 52.34 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 12:59:50 PM PDT 24
Peak memory 196212 kb
Host smart-593d182c-4ead-4e41-8ac6-4c60f34edadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667192771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3667192771
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1246835440
Short name T298
Test name
Test status
Simulation time 5889740437 ps
CPU time 8.29 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 12:59:20 PM PDT 24
Peak memory 200420 kb
Host smart-330f37ae-560f-4d5d-afb9-4dcbd136125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246835440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1246835440
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2316132648
Short name T1007
Test name
Test status
Simulation time 84376019687 ps
CPU time 445.09 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 200484 kb
Host smart-09f5fd1e-036c-4842-b0d8-4a7f05e8faa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316132648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2316132648
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1227166326
Short name T104
Test name
Test status
Simulation time 117796892545 ps
CPU time 667.62 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 01:10:09 PM PDT 24
Peak memory 225452 kb
Host smart-4f51666e-5e20-4e0c-9f6f-d7856080a7a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227166326 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1227166326
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2148145533
Short name T798
Test name
Test status
Simulation time 1090730928 ps
CPU time 4.22 seconds
Started May 14 12:58:35 PM PDT 24
Finished May 14 12:59:04 PM PDT 24
Peak memory 200348 kb
Host smart-7a5407c2-be74-4985-a3c3-390d669977e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148145533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2148145533
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2818186403
Short name T1138
Test name
Test status
Simulation time 37245229010 ps
CPU time 52.46 seconds
Started May 14 12:58:36 PM PDT 24
Finished May 14 12:59:56 PM PDT 24
Peak memory 200368 kb
Host smart-4bd479b1-e37d-4feb-a00c-23a30ab99db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818186403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2818186403
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1042592101
Short name T511
Test name
Test status
Simulation time 12993042 ps
CPU time 0.57 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 12:59:12 PM PDT 24
Peak memory 195336 kb
Host smart-3e413c8c-f7c0-4e82-a06e-4215357ab8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042592101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1042592101
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2647420714
Short name T466
Test name
Test status
Simulation time 76798277675 ps
CPU time 37.45 seconds
Started May 14 12:58:33 PM PDT 24
Finished May 14 12:59:32 PM PDT 24
Peak memory 200460 kb
Host smart-ca75fb83-a299-445e-b161-0fbdeba67ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647420714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2647420714
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3975485555
Short name T714
Test name
Test status
Simulation time 74161695058 ps
CPU time 107.5 seconds
Started May 14 12:58:40 PM PDT 24
Finished May 14 01:00:59 PM PDT 24
Peak memory 199740 kb
Host smart-88f042ff-dc62-4de1-94b0-bfaa69c905e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975485555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3975485555
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1762465789
Short name T110
Test name
Test status
Simulation time 13382059614 ps
CPU time 24.68 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 12:59:36 PM PDT 24
Peak memory 200436 kb
Host smart-6435b036-91fd-426b-8ff7-0670ca6bd67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762465789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1762465789
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.887633227
Short name T62
Test name
Test status
Simulation time 24956128520 ps
CPU time 10.73 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 12:59:24 PM PDT 24
Peak memory 197608 kb
Host smart-ec637bdf-4a9c-4937-8014-7ce9fe220630
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887633227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.887633227
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3660914391
Short name T903
Test name
Test status
Simulation time 45577123085 ps
CPU time 499.08 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 01:07:36 PM PDT 24
Peak memory 200664 kb
Host smart-a5753a69-26c1-41f5-bf40-55114d96f983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660914391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3660914391
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.4110668400
Short name T1057
Test name
Test status
Simulation time 3647065124 ps
CPU time 3.64 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 12:59:17 PM PDT 24
Peak memory 200308 kb
Host smart-352727c9-2b99-4245-9552-21757053d6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110668400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.4110668400
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2453716387
Short name T281
Test name
Test status
Simulation time 193870126073 ps
CPU time 304.48 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 01:04:22 PM PDT 24
Peak memory 199660 kb
Host smart-a4386941-6578-40d0-af4b-cec926734d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453716387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2453716387
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3628890119
Short name T376
Test name
Test status
Simulation time 12753548927 ps
CPU time 732.03 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 01:11:31 PM PDT 24
Peak memory 200380 kb
Host smart-2dde1036-5ed7-48fd-9e13-7fe8d7e6785c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628890119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3628890119
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2870941186
Short name T1018
Test name
Test status
Simulation time 7595527784 ps
CPU time 43.09 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 12:59:57 PM PDT 24
Peak memory 199624 kb
Host smart-a72e6382-c1e6-4c19-a4f8-aacca6d8063d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870941186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2870941186
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3648641423
Short name T1181
Test name
Test status
Simulation time 99113608181 ps
CPU time 49.06 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 01:00:04 PM PDT 24
Peak memory 200464 kb
Host smart-a3e59098-5af0-4ed8-839e-3fd68d958734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648641423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3648641423
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3111414174
Short name T700
Test name
Test status
Simulation time 1929279217 ps
CPU time 3.51 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 12:59:19 PM PDT 24
Peak memory 195748 kb
Host smart-c12d93fd-72df-466c-81e6-dee0da330beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111414174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3111414174
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2011262302
Short name T1112
Test name
Test status
Simulation time 479321446 ps
CPU time 1.18 seconds
Started May 14 12:58:34 PM PDT 24
Finished May 14 12:58:58 PM PDT 24
Peak memory 198948 kb
Host smart-c810b145-5895-4ba1-aa93-9c50df55b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011262302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2011262302
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3635352844
Short name T150
Test name
Test status
Simulation time 202419140137 ps
CPU time 312.88 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 01:04:30 PM PDT 24
Peak memory 200376 kb
Host smart-e198253c-8621-4b79-8353-d7eddfb56ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635352844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3635352844
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3846615029
Short name T512
Test name
Test status
Simulation time 36951729848 ps
CPU time 324.52 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 01:04:42 PM PDT 24
Peak memory 216908 kb
Host smart-232581f5-b855-4f93-a609-3905769490f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846615029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3846615029
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.124376581
Short name T870
Test name
Test status
Simulation time 1121104816 ps
CPU time 5.35 seconds
Started May 14 12:58:40 PM PDT 24
Finished May 14 12:59:17 PM PDT 24
Peak memory 199336 kb
Host smart-0ba4224c-7433-4cdd-842d-ed310195fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124376581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.124376581
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.743131799
Short name T401
Test name
Test status
Simulation time 105990956075 ps
CPU time 53.45 seconds
Started May 14 12:58:36 PM PDT 24
Finished May 14 12:59:57 PM PDT 24
Peak memory 200216 kb
Host smart-0bae8246-ec1b-4aee-82eb-849755e7276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743131799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.743131799
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2209060174
Short name T390
Test name
Test status
Simulation time 12212211 ps
CPU time 0.56 seconds
Started May 14 12:58:40 PM PDT 24
Finished May 14 12:59:12 PM PDT 24
Peak memory 195840 kb
Host smart-aaed5d2b-8271-448c-8750-0fde4dad146f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209060174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2209060174
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2005598076
Short name T175
Test name
Test status
Simulation time 329242078885 ps
CPU time 33.91 seconds
Started May 14 12:58:45 PM PDT 24
Finished May 14 12:59:53 PM PDT 24
Peak memory 200460 kb
Host smart-5d2912b8-3643-45df-9d5e-48d8b2244577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005598076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2005598076
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2658972337
Short name T398
Test name
Test status
Simulation time 67999266180 ps
CPU time 29.5 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 12:59:47 PM PDT 24
Peak memory 200168 kb
Host smart-2f275e0b-0d29-4d8f-ac9d-a252cf13fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658972337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2658972337
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2618015245
Short name T130
Test name
Test status
Simulation time 11633629799 ps
CPU time 22.38 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 12:59:38 PM PDT 24
Peak memory 200212 kb
Host smart-55640128-39fd-49d5-b083-5ef807c2220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618015245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2618015245
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4246110152
Short name T359
Test name
Test status
Simulation time 153889116066 ps
CPU time 49.22 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 01:00:04 PM PDT 24
Peak memory 196640 kb
Host smart-ac4b3f6e-7483-4ef4-bbf7-4f025499bdac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246110152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4246110152
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.679480844
Short name T603
Test name
Test status
Simulation time 158755074294 ps
CPU time 81.19 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 01:00:35 PM PDT 24
Peak memory 200512 kb
Host smart-557ba279-0f9c-40d4-a190-6c12ce9d55ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679480844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.679480844
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3822829176
Short name T358
Test name
Test status
Simulation time 4003057456 ps
CPU time 8.11 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 12:59:21 PM PDT 24
Peak memory 196264 kb
Host smart-f7b38253-bf49-461d-80bf-dabf6575bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822829176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3822829176
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3349788881
Short name T584
Test name
Test status
Simulation time 65560533312 ps
CPU time 137.12 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 01:01:34 PM PDT 24
Peak memory 208828 kb
Host smart-b701a47a-f422-4855-8a7b-c46c3e70d06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349788881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3349788881
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2757893023
Short name T885
Test name
Test status
Simulation time 18277916637 ps
CPU time 574.94 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 200436 kb
Host smart-3fd4cce3-f2bf-4fa7-9b15-3a8ee1a9761c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757893023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2757893023
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1791478280
Short name T1066
Test name
Test status
Simulation time 4075832668 ps
CPU time 25.24 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 12:59:44 PM PDT 24
Peak memory 199104 kb
Host smart-2b9cfa1a-3d3b-4478-b689-d7a7a7807b59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791478280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1791478280
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2569410788
Short name T563
Test name
Test status
Simulation time 87886460356 ps
CPU time 141.68 seconds
Started May 14 12:58:44 PM PDT 24
Finished May 14 01:01:39 PM PDT 24
Peak memory 200316 kb
Host smart-e255a11a-88a9-4162-8d61-b0b2f656de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569410788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2569410788
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2820089460
Short name T462
Test name
Test status
Simulation time 5928928632 ps
CPU time 2.13 seconds
Started May 14 12:58:45 PM PDT 24
Finished May 14 12:59:21 PM PDT 24
Peak memory 196484 kb
Host smart-8653f6ee-2faf-42e3-bcaa-bab313bb917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820089460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2820089460
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3147687010
Short name T1169
Test name
Test status
Simulation time 482209932 ps
CPU time 1.72 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 12:59:15 PM PDT 24
Peak memory 198852 kb
Host smart-ac9fd4da-ee1b-4ab4-8a30-b699ad760893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147687010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3147687010
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2134854013
Short name T705
Test name
Test status
Simulation time 10807175868 ps
CPU time 126.46 seconds
Started May 14 12:58:45 PM PDT 24
Finished May 14 01:01:25 PM PDT 24
Peak memory 209964 kb
Host smart-0f329fd4-4559-4eb4-bd2e-05f92f2aef50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134854013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2134854013
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.598304418
Short name T1128
Test name
Test status
Simulation time 6845896791 ps
CPU time 11.54 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 12:59:27 PM PDT 24
Peak memory 200176 kb
Host smart-1d78ddd7-ee92-4855-9117-c92b1be546b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598304418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.598304418
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2283800187
Short name T635
Test name
Test status
Simulation time 82209490885 ps
CPU time 35.06 seconds
Started May 14 12:58:43 PM PDT 24
Finished May 14 12:59:51 PM PDT 24
Peak memory 200424 kb
Host smart-9c53c569-3cc2-4518-a606-450adc71b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283800187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2283800187
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1206555646
Short name T554
Test name
Test status
Simulation time 12784958 ps
CPU time 0.54 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 12:59:29 PM PDT 24
Peak memory 194832 kb
Host smart-3f59bb70-74cb-460f-83c0-9767f966b25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206555646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1206555646
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3002649495
Short name T504
Test name
Test status
Simulation time 80054312528 ps
CPU time 132.37 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 01:01:43 PM PDT 24
Peak memory 200456 kb
Host smart-e967ad35-4cee-40ab-bee9-d62c90a2a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002649495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3002649495
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1642820804
Short name T362
Test name
Test status
Simulation time 21086909967 ps
CPU time 37.74 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 200228 kb
Host smart-e286e76a-c8cf-470d-8076-356b023634fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642820804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1642820804
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1135735063
Short name T246
Test name
Test status
Simulation time 9395417231 ps
CPU time 15.63 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 12:59:45 PM PDT 24
Peak memory 200256 kb
Host smart-cd9df4ca-af10-4dfd-bb0a-6387b1e7d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135735063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1135735063
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.947605944
Short name T278
Test name
Test status
Simulation time 227226197659 ps
CPU time 323.07 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 01:04:52 PM PDT 24
Peak memory 200336 kb
Host smart-5bc97932-7226-43d7-8f03-7edd2e156c74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947605944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.947605944
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1747277771
Short name T382
Test name
Test status
Simulation time 75657538563 ps
CPU time 379 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 01:05:49 PM PDT 24
Peak memory 200452 kb
Host smart-2c23b3f8-6f31-4db6-aadb-8cd026edc6b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747277771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1747277771
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3190258241
Short name T1120
Test name
Test status
Simulation time 7457039305 ps
CPU time 13.25 seconds
Started May 14 12:58:49 PM PDT 24
Finished May 14 12:59:40 PM PDT 24
Peak memory 199340 kb
Host smart-7e0c2f73-eb15-49c8-9985-b705816dcbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190258241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3190258241
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1638263516
Short name T662
Test name
Test status
Simulation time 181274185621 ps
CPU time 98.7 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 01:01:09 PM PDT 24
Peak memory 200656 kb
Host smart-e4ac5727-83cd-48ef-8c5b-a3e2596686c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638263516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1638263516
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1374812789
Short name T525
Test name
Test status
Simulation time 29303230085 ps
CPU time 371.83 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 01:05:41 PM PDT 24
Peak memory 200328 kb
Host smart-541ca578-6aee-4f6e-bda7-db941711d1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374812789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1374812789
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3340750685
Short name T1003
Test name
Test status
Simulation time 4396351649 ps
CPU time 36.98 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 01:00:05 PM PDT 24
Peak memory 199600 kb
Host smart-596f19ea-32d9-4b07-afe9-d8871774c234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340750685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3340750685
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4135967805
Short name T761
Test name
Test status
Simulation time 55669578524 ps
CPU time 24.71 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 12:59:57 PM PDT 24
Peak memory 200392 kb
Host smart-928e8737-f43d-4e4b-af32-461b60a97f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135967805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4135967805
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4264375588
Short name T474
Test name
Test status
Simulation time 1945373225 ps
CPU time 1.47 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 12:59:33 PM PDT 24
Peak memory 196124 kb
Host smart-dc5aab2c-e00f-4a9a-a358-a7ee3d6ecebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264375588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4264375588
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1907609911
Short name T759
Test name
Test status
Simulation time 137727059 ps
CPU time 0.78 seconds
Started May 14 12:58:41 PM PDT 24
Finished May 14 12:59:12 PM PDT 24
Peak memory 197768 kb
Host smart-0bcd39d8-49de-4d7a-b8bf-53ca5db27164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907609911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1907609911
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2493919085
Short name T309
Test name
Test status
Simulation time 55828946603 ps
CPU time 89.13 seconds
Started May 14 12:58:49 PM PDT 24
Finished May 14 01:00:56 PM PDT 24
Peak memory 200460 kb
Host smart-5f404c47-8675-47f4-9360-72a505691a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493919085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2493919085
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.411128356
Short name T39
Test name
Test status
Simulation time 54594885422 ps
CPU time 535.97 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 01:08:25 PM PDT 24
Peak memory 225432 kb
Host smart-7340e4b2-1386-403c-83d6-21db6e4e6b26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411128356 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.411128356
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2221944183
Short name T586
Test name
Test status
Simulation time 1798380243 ps
CPU time 2.07 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 12:59:32 PM PDT 24
Peak memory 200344 kb
Host smart-ad8b0ee0-ec06-4563-a88e-4f723ffd43c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221944183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2221944183
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2721120480
Short name T375
Test name
Test status
Simulation time 128484784077 ps
CPU time 91.21 seconds
Started May 14 12:58:42 PM PDT 24
Finished May 14 01:00:46 PM PDT 24
Peak memory 200456 kb
Host smart-ed67dffc-7679-4c73-801f-75f0f77ab456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721120480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2721120480
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.373628391
Short name T521
Test name
Test status
Simulation time 152492406 ps
CPU time 0.55 seconds
Started May 14 12:58:49 PM PDT 24
Finished May 14 12:59:27 PM PDT 24
Peak memory 195812 kb
Host smart-6ecca794-0b65-423c-bbf7-f7fa2fa1c1a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373628391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.373628391
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.11520925
Short name T1177
Test name
Test status
Simulation time 70736188488 ps
CPU time 100.54 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 01:01:11 PM PDT 24
Peak memory 200476 kb
Host smart-d6fe90ca-8899-4994-bed4-5e1434213308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11520925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.11520925
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1298842532
Short name T431
Test name
Test status
Simulation time 56725121843 ps
CPU time 54.79 seconds
Started May 14 12:58:49 PM PDT 24
Finished May 14 01:00:21 PM PDT 24
Peak memory 200440 kb
Host smart-7384f921-4217-474d-bba2-81c65dc32e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298842532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1298842532
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3677560138
Short name T577
Test name
Test status
Simulation time 40080273092 ps
CPU time 17.53 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 12:59:50 PM PDT 24
Peak memory 200416 kb
Host smart-60e0e059-6709-4141-b62e-dd271796220b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677560138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3677560138
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2728098051
Short name T718
Test name
Test status
Simulation time 14676225111 ps
CPU time 23.05 seconds
Started May 14 12:58:53 PM PDT 24
Finished May 14 12:59:55 PM PDT 24
Peak memory 199816 kb
Host smart-14982abb-a159-4452-b533-530bf178db1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728098051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2728098051
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2811238456
Short name T434
Test name
Test status
Simulation time 74767918538 ps
CPU time 488.68 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 01:07:39 PM PDT 24
Peak memory 200528 kb
Host smart-2b3dec96-1227-4b52-8754-052d49c8f9a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811238456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2811238456
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1393603846
Short name T821
Test name
Test status
Simulation time 3743056241 ps
CPU time 2.22 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 12:59:33 PM PDT 24
Peak memory 196848 kb
Host smart-ba5cce77-92b7-4d06-95a4-c5b834422e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393603846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1393603846
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1470060857
Short name T625
Test name
Test status
Simulation time 34135020707 ps
CPU time 54.82 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 01:00:25 PM PDT 24
Peak memory 198384 kb
Host smart-0030b07c-e637-4278-ac9f-a1a711815076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470060857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1470060857
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1165268650
Short name T364
Test name
Test status
Simulation time 3843196436 ps
CPU time 74.46 seconds
Started May 14 12:58:49 PM PDT 24
Finished May 14 01:00:41 PM PDT 24
Peak memory 200456 kb
Host smart-fab8aa34-19f6-4d04-9573-d4c9ad3bed48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165268650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1165268650
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2473825206
Short name T447
Test name
Test status
Simulation time 6558331743 ps
CPU time 13.99 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 199668 kb
Host smart-b4dc3539-3ff5-4c42-8c89-06e2e5b6b121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473825206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2473825206
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2888326167
Short name T283
Test name
Test status
Simulation time 201197106714 ps
CPU time 52.75 seconds
Started May 14 12:58:52 PM PDT 24
Finished May 14 01:00:23 PM PDT 24
Peak memory 200372 kb
Host smart-e5725465-d638-444b-803a-f7a47c66d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888326167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2888326167
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3232321876
Short name T734
Test name
Test status
Simulation time 3470919725 ps
CPU time 5.56 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 12:59:34 PM PDT 24
Peak memory 196544 kb
Host smart-bc11e1ee-df92-4db9-86e5-f1545dd2e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232321876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3232321876
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.836434933
Short name T1016
Test name
Test status
Simulation time 312830567 ps
CPU time 1.7 seconds
Started May 14 12:58:53 PM PDT 24
Finished May 14 12:59:34 PM PDT 24
Peak memory 198812 kb
Host smart-a3d34450-3e5c-4d27-8eae-c569cec4c184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836434933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.836434933
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3667361196
Short name T916
Test name
Test status
Simulation time 356522021570 ps
CPU time 117.83 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 01:01:27 PM PDT 24
Peak memory 200380 kb
Host smart-87dd2e4c-a17c-47c5-a41b-413ef2f43212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667361196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3667361196
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1730645079
Short name T944
Test name
Test status
Simulation time 39465809912 ps
CPU time 520.89 seconds
Started May 14 12:58:50 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 216944 kb
Host smart-c7c5e88e-ca35-473c-8a28-0e428019b61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730645079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1730645079
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3754763279
Short name T831
Test name
Test status
Simulation time 863245682 ps
CPU time 4.91 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 12:59:35 PM PDT 24
Peak memory 200152 kb
Host smart-ecfbc5fa-b9ac-49a3-a34b-d508f0e32222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754763279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3754763279
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1620596767
Short name T1159
Test name
Test status
Simulation time 305106517561 ps
CPU time 84.59 seconds
Started May 14 12:58:51 PM PDT 24
Finished May 14 01:00:54 PM PDT 24
Peak memory 200420 kb
Host smart-a103a578-4476-4ff7-afa6-a849f456876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620596767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1620596767
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2811452361
Short name T387
Test name
Test status
Simulation time 13747551 ps
CPU time 0.56 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 12:59:41 PM PDT 24
Peak memory 195860 kb
Host smart-e030631e-0b26-4686-a3a9-2fa412f25164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811452361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2811452361
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2216026408
Short name T302
Test name
Test status
Simulation time 65390911894 ps
CPU time 111.98 seconds
Started May 14 12:59:00 PM PDT 24
Finished May 14 01:01:33 PM PDT 24
Peak memory 200436 kb
Host smart-999fb280-b7b0-4718-936d-57a558e746ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216026408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2216026408
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3413487978
Short name T1023
Test name
Test status
Simulation time 25532442967 ps
CPU time 51.85 seconds
Started May 14 12:58:58 PM PDT 24
Finished May 14 01:00:32 PM PDT 24
Peak memory 200424 kb
Host smart-1dc29724-c945-4a2f-9d7e-f5f50ca941aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413487978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3413487978
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4131484030
Short name T467
Test name
Test status
Simulation time 34099886748 ps
CPU time 28.14 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 01:00:09 PM PDT 24
Peak memory 198932 kb
Host smart-9e1d04b5-c3bd-427f-a6e3-0f7df056499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131484030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4131484030
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.669853461
Short name T441
Test name
Test status
Simulation time 16974265878 ps
CPU time 15.44 seconds
Started May 14 12:58:56 PM PDT 24
Finished May 14 12:59:53 PM PDT 24
Peak memory 197464 kb
Host smart-0ee03665-72bc-44ac-9249-aa05a91a603e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669853461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.669853461
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.476759190
Short name T634
Test name
Test status
Simulation time 132961836163 ps
CPU time 1338.69 seconds
Started May 14 12:59:01 PM PDT 24
Finished May 14 01:22:02 PM PDT 24
Peak memory 200420 kb
Host smart-edf47c26-2516-4944-a426-c2488025e53b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476759190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.476759190
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2983374185
Short name T952
Test name
Test status
Simulation time 3551529367 ps
CPU time 3.15 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 12:59:42 PM PDT 24
Peak memory 200464 kb
Host smart-dacda4d1-902d-45ef-88f2-ef2b66e83c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983374185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2983374185
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4176207058
Short name T762
Test name
Test status
Simulation time 271328645861 ps
CPU time 121.73 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 01:01:41 PM PDT 24
Peak memory 216180 kb
Host smart-a5b7e4de-b497-40a6-a4ac-b06f0b98a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176207058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4176207058
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.837417724
Short name T293
Test name
Test status
Simulation time 16814773412 ps
CPU time 71.86 seconds
Started May 14 12:59:00 PM PDT 24
Finished May 14 01:00:55 PM PDT 24
Peak memory 200476 kb
Host smart-05c00e29-a2a0-488a-8cfb-d43471daae22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837417724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.837417724
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1449612730
Short name T488
Test name
Test status
Simulation time 4000774583 ps
CPU time 6.51 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 12:59:48 PM PDT 24
Peak memory 198724 kb
Host smart-c78be659-2ea3-4700-aeea-0181b063f144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449612730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1449612730
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2224257795
Short name T328
Test name
Test status
Simulation time 128429478387 ps
CPU time 54.9 seconds
Started May 14 12:58:58 PM PDT 24
Finished May 14 01:00:35 PM PDT 24
Peak memory 200400 kb
Host smart-4ab33ec0-ba55-4cc2-9f5b-b86973979b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224257795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2224257795
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3930597447
Short name T360
Test name
Test status
Simulation time 2177753531 ps
CPU time 1.39 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 195916 kb
Host smart-94a53cc0-039f-4423-b1bd-9d3e6bcece89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930597447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3930597447
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1632970273
Short name T1079
Test name
Test status
Simulation time 652461067 ps
CPU time 3.18 seconds
Started May 14 12:58:58 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 199268 kb
Host smart-9724bda4-7ec3-4359-b235-2fe51094a525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632970273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1632970273
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3657377686
Short name T1104
Test name
Test status
Simulation time 163596786757 ps
CPU time 160.17 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 01:02:21 PM PDT 24
Peak memory 208896 kb
Host smart-33ac92f6-e29b-4f62-ae75-b4247265af34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657377686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3657377686
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.383679650
Short name T30
Test name
Test status
Simulation time 35268781759 ps
CPU time 312 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 01:04:53 PM PDT 24
Peak memory 209700 kb
Host smart-f33ea2a1-6ea5-4bfa-8eea-74889a155cd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383679650 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.383679650
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2008800267
Short name T599
Test name
Test status
Simulation time 2039807661 ps
CPU time 1.56 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 12:59:39 PM PDT 24
Peak memory 198892 kb
Host smart-392015d0-ac9d-4b89-85dd-ef192a4e0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008800267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2008800267
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1819315898
Short name T269
Test name
Test status
Simulation time 78151223535 ps
CPU time 63.23 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 01:00:41 PM PDT 24
Peak memory 200400 kb
Host smart-49efdc71-3da5-43b1-b3a8-fffeeeffee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819315898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1819315898
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2047755516
Short name T505
Test name
Test status
Simulation time 14011454 ps
CPU time 0.53 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 12:59:48 PM PDT 24
Peak memory 195868 kb
Host smart-ad8a8ac8-a573-4a5f-a51e-4212c4904c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047755516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2047755516
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1736383527
Short name T115
Test name
Test status
Simulation time 107319784395 ps
CPU time 142.06 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 01:02:00 PM PDT 24
Peak memory 200464 kb
Host smart-738522f9-4b02-440a-9027-f6364b0d81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736383527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1736383527
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1337887702
Short name T133
Test name
Test status
Simulation time 31239032252 ps
CPU time 52.82 seconds
Started May 14 12:58:58 PM PDT 24
Finished May 14 01:00:33 PM PDT 24
Peak memory 200416 kb
Host smart-bfccb342-a24a-430f-a332-6daa1bba9c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337887702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1337887702
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3191736411
Short name T210
Test name
Test status
Simulation time 121749952167 ps
CPU time 51.53 seconds
Started May 14 12:59:01 PM PDT 24
Finished May 14 01:00:34 PM PDT 24
Peak memory 200420 kb
Host smart-541c4016-25fe-4928-9d76-13f64bd45f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191736411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3191736411
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1129045358
Short name T1073
Test name
Test status
Simulation time 178938480887 ps
CPU time 159.11 seconds
Started May 14 12:58:56 PM PDT 24
Finished May 14 01:02:17 PM PDT 24
Peak memory 200132 kb
Host smart-e1ed8dfa-7a30-4daa-94db-55594c89a3d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129045358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1129045358
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3178441602
Short name T1012
Test name
Test status
Simulation time 45886802823 ps
CPU time 146.33 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:02:13 PM PDT 24
Peak memory 200424 kb
Host smart-6f838a65-fba2-499f-acdd-3381df11e545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178441602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3178441602
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.341542
Short name T333
Test name
Test status
Simulation time 7009699599 ps
CPU time 4.18 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 12:59:51 PM PDT 24
Peak memory 199200 kb
Host smart-79c93baa-cd69-4642-b01f-de95964d8c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.341542
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1962622379
Short name T1126
Test name
Test status
Simulation time 239122726830 ps
CPU time 129.86 seconds
Started May 14 12:58:58 PM PDT 24
Finished May 14 01:01:50 PM PDT 24
Peak memory 200288 kb
Host smart-fca0d355-f1f0-493c-b978-c8aa15bf5dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962622379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1962622379
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1848966727
Short name T646
Test name
Test status
Simulation time 24140745070 ps
CPU time 223.77 seconds
Started May 14 12:59:07 PM PDT 24
Finished May 14 01:03:32 PM PDT 24
Peak memory 200480 kb
Host smart-0f2f12c9-5abc-4a12-adfe-488841c23d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848966727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1848966727
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1244465786
Short name T786
Test name
Test status
Simulation time 6270359413 ps
CPU time 14.88 seconds
Started May 14 12:58:59 PM PDT 24
Finished May 14 12:59:56 PM PDT 24
Peak memory 198620 kb
Host smart-1b81177b-6802-42ae-bd36-097d4bee3e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244465786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1244465786
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1682585254
Short name T927
Test name
Test status
Simulation time 121409057631 ps
CPU time 319.5 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 01:05:07 PM PDT 24
Peak memory 200532 kb
Host smart-e349ddda-313a-414f-9c56-d51a2fd9ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682585254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1682585254
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.75265335
Short name T1071
Test name
Test status
Simulation time 77052465229 ps
CPU time 29.55 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:00:16 PM PDT 24
Peak memory 196228 kb
Host smart-3c0b50b1-e591-4cbd-ba0c-6c25ce41e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75265335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.75265335
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2219732786
Short name T848
Test name
Test status
Simulation time 710931159 ps
CPU time 2.02 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 12:59:41 PM PDT 24
Peak memory 199552 kb
Host smart-2419d325-0817-4574-b72f-39409b5f9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219732786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2219732786
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4067452845
Short name T866
Test name
Test status
Simulation time 390093126874 ps
CPU time 451.81 seconds
Started May 14 12:59:07 PM PDT 24
Finished May 14 01:07:20 PM PDT 24
Peak memory 208944 kb
Host smart-59023cf2-5136-4f53-a49a-d4d8157c83be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067452845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4067452845
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2668448041
Short name T134
Test name
Test status
Simulation time 34391841250 ps
CPU time 397.66 seconds
Started May 14 12:59:03 PM PDT 24
Finished May 14 01:06:23 PM PDT 24
Peak memory 216180 kb
Host smart-484b05d3-56f8-42fb-8567-453ac218a243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668448041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2668448041
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.606480628
Short name T691
Test name
Test status
Simulation time 1873028042 ps
CPU time 2.26 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 12:59:50 PM PDT 24
Peak memory 200052 kb
Host smart-e92231a0-c050-4305-a9ae-f77b09bd9a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606480628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.606480628
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1777626542
Short name T257
Test name
Test status
Simulation time 15055269258 ps
CPU time 25.42 seconds
Started May 14 12:58:57 PM PDT 24
Finished May 14 01:00:05 PM PDT 24
Peak memory 200440 kb
Host smart-ac6bb732-3269-43e4-8f26-9997799ef140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777626542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1777626542
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3441641747
Short name T604
Test name
Test status
Simulation time 51781921 ps
CPU time 0.53 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 12:59:47 PM PDT 24
Peak memory 194844 kb
Host smart-862e4e1c-5ad6-4822-a8dc-eb14b2d13206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441641747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3441641747
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3821397386
Short name T507
Test name
Test status
Simulation time 21512254284 ps
CPU time 12.87 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:00:05 PM PDT 24
Peak memory 200492 kb
Host smart-d8b0f837-1177-43eb-a382-1e6dd395601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821397386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3821397386
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3614377433
Short name T553
Test name
Test status
Simulation time 214816852027 ps
CPU time 394.39 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:06:26 PM PDT 24
Peak memory 200284 kb
Host smart-411808fd-2be4-432d-a7b5-5fd34e5968c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614377433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3614377433
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1126267801
Short name T664
Test name
Test status
Simulation time 12730644902 ps
CPU time 24.72 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:00:17 PM PDT 24
Peak memory 200484 kb
Host smart-4286197a-b903-4338-80b7-e3a39b8214b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126267801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1126267801
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2649693335
Short name T996
Test name
Test status
Simulation time 48311110171 ps
CPU time 80.92 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:01:07 PM PDT 24
Peak memory 200432 kb
Host smart-5b4ab700-0b5d-4b0f-8749-71278627fa3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649693335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2649693335
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4252499169
Short name T950
Test name
Test status
Simulation time 51773375552 ps
CPU time 295.65 seconds
Started May 14 12:59:06 PM PDT 24
Finished May 14 01:04:44 PM PDT 24
Peak memory 200492 kb
Host smart-32bc487d-0e65-4c57-9dbe-128cc40a1d49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252499169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4252499169
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2093045985
Short name T1002
Test name
Test status
Simulation time 4990888922 ps
CPU time 5.43 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 12:59:58 PM PDT 24
Peak memory 200208 kb
Host smart-36833bc4-edbf-4255-adff-8cd6771091eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093045985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2093045985
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1651829662
Short name T247
Test name
Test status
Simulation time 87647092275 ps
CPU time 42.7 seconds
Started May 14 12:59:06 PM PDT 24
Finished May 14 01:00:31 PM PDT 24
Peak memory 208860 kb
Host smart-f9a7f2a1-c9c3-4ad3-8109-e188adb075e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651829662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1651829662
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1357930717
Short name T413
Test name
Test status
Simulation time 12113931330 ps
CPU time 134.5 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 01:02:01 PM PDT 24
Peak memory 200456 kb
Host smart-601b6efa-e21b-4de8-b3db-a74381a42a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357930717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1357930717
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3203529348
Short name T1049
Test name
Test status
Simulation time 6377931509 ps
CPU time 14.34 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:00:01 PM PDT 24
Peak memory 198720 kb
Host smart-a34bd7b5-01a8-4e12-8815-f04de2331b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203529348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3203529348
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1360378446
Short name T1006
Test name
Test status
Simulation time 90469846267 ps
CPU time 158.93 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 01:02:26 PM PDT 24
Peak memory 200396 kb
Host smart-307640a2-34b7-453b-a5e8-f2d20596ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360378446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1360378446
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2920369385
Short name T781
Test name
Test status
Simulation time 3028790700 ps
CPU time 5.03 seconds
Started May 14 12:59:03 PM PDT 24
Finished May 14 12:59:50 PM PDT 24
Peak memory 196256 kb
Host smart-f9b72dda-edc8-47b4-96b7-81923486a37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920369385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2920369385
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.717138674
Short name T468
Test name
Test status
Simulation time 761604264 ps
CPU time 1.06 seconds
Started May 14 12:59:05 PM PDT 24
Finished May 14 12:59:48 PM PDT 24
Peak memory 198780 kb
Host smart-c17f034e-4cf8-440b-ac42-0315ba44d7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717138674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.717138674
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4244536755
Short name T1056
Test name
Test status
Simulation time 153152378355 ps
CPU time 1045.44 seconds
Started May 14 12:59:06 PM PDT 24
Finished May 14 01:17:14 PM PDT 24
Peak memory 200468 kb
Host smart-62d860c7-e63b-426d-ae16-8fc614ab4468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244536755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4244536755
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1288472373
Short name T44
Test name
Test status
Simulation time 42744471276 ps
CPU time 1073.7 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:17:41 PM PDT 24
Peak memory 216924 kb
Host smart-c58a5d59-f1a0-4630-8d19-3f4c6979104f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288472373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1288472373
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1115754532
Short name T487
Test name
Test status
Simulation time 6751937974 ps
CPU time 9.33 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:00:01 PM PDT 24
Peak memory 200420 kb
Host smart-028b55be-4eef-447d-974e-b51de1ebd098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115754532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1115754532
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2000753888
Short name T256
Test name
Test status
Simulation time 8017799733 ps
CPU time 15.39 seconds
Started May 14 12:59:06 PM PDT 24
Finished May 14 01:00:04 PM PDT 24
Peak memory 200456 kb
Host smart-31645ed4-7c64-4b24-bcbe-1e35096c6872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000753888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2000753888
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4072669320
Short name T1009
Test name
Test status
Simulation time 23289427 ps
CPU time 0.55 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 12:59:52 PM PDT 24
Peak memory 195828 kb
Host smart-b251a6ab-17e6-47c4-8e78-ec06bcac4dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072669320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4072669320
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2116381258
Short name T250
Test name
Test status
Simulation time 61882721200 ps
CPU time 51.57 seconds
Started May 14 12:59:06 PM PDT 24
Finished May 14 01:00:39 PM PDT 24
Peak memory 200456 kb
Host smart-a24b7fa1-7b44-44e4-8af5-d9319b91e5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116381258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2116381258
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1192010085
Short name T143
Test name
Test status
Simulation time 22999069352 ps
CPU time 49.2 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:00:36 PM PDT 24
Peak memory 200400 kb
Host smart-f7c7f1df-fddc-4388-aed5-243ee1d92e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192010085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1192010085
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3561169950
Short name T157
Test name
Test status
Simulation time 78695326184 ps
CPU time 24.47 seconds
Started May 14 12:59:03 PM PDT 24
Finished May 14 01:00:11 PM PDT 24
Peak memory 200408 kb
Host smart-5c655e07-17e7-4553-af3a-ba6f6d844ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561169950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3561169950
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3738483402
Short name T654
Test name
Test status
Simulation time 420672152718 ps
CPU time 720.97 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:11:52 PM PDT 24
Peak memory 200120 kb
Host smart-98d38579-9786-4182-8bcb-0aeac324edff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738483402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3738483402
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1016520413
Short name T568
Test name
Test status
Simulation time 29977657095 ps
CPU time 111.24 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:01:42 PM PDT 24
Peak memory 200452 kb
Host smart-ed9386af-ac29-4635-8585-306f9d43e87b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016520413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1016520413
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1863709780
Short name T1106
Test name
Test status
Simulation time 1870844206 ps
CPU time 3.19 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 12:59:54 PM PDT 24
Peak memory 198588 kb
Host smart-e99730a9-17e6-49de-a8e6-87ae885014ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863709780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1863709780
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2389566673
Short name T407
Test name
Test status
Simulation time 105902144478 ps
CPU time 59.28 seconds
Started May 14 12:59:15 PM PDT 24
Finished May 14 01:00:52 PM PDT 24
Peak memory 200708 kb
Host smart-f433e735-34da-4018-8cae-0b78ee42acff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389566673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2389566673
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2459647289
Short name T858
Test name
Test status
Simulation time 5091977275 ps
CPU time 5.78 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 12:59:52 PM PDT 24
Peak memory 199288 kb
Host smart-337a2118-253e-4afd-9494-cd3689a82799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459647289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2459647289
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1783635339
Short name T1092
Test name
Test status
Simulation time 229376477073 ps
CPU time 152.71 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:02:24 PM PDT 24
Peak memory 200476 kb
Host smart-24158561-4779-4ff9-8c2e-c3e0b1c0fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783635339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1783635339
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2825145120
Short name T1171
Test name
Test status
Simulation time 4071123572 ps
CPU time 6.58 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 12:59:58 PM PDT 24
Peak memory 196424 kb
Host smart-5c50d45b-185a-4b91-acac-3491c9721bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825145120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2825145120
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1092445102
Short name T764
Test name
Test status
Simulation time 6093466447 ps
CPU time 16.32 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 01:00:03 PM PDT 24
Peak memory 200188 kb
Host smart-954bd80a-83df-495a-9c4f-44653140f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092445102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1092445102
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2613492279
Short name T324
Test name
Test status
Simulation time 454544624252 ps
CPU time 312.97 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:05:05 PM PDT 24
Peak memory 217204 kb
Host smart-705e8be3-70c5-4c2f-aa61-f34f922267f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613492279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2613492279
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.407789892
Short name T1034
Test name
Test status
Simulation time 994199721 ps
CPU time 2.9 seconds
Started May 14 12:59:11 PM PDT 24
Finished May 14 12:59:53 PM PDT 24
Peak memory 199144 kb
Host smart-5a9c7269-a859-4a51-aa5e-485aeed0473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407789892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.407789892
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1887073282
Short name T396
Test name
Test status
Simulation time 64288905492 ps
CPU time 12.62 seconds
Started May 14 12:59:04 PM PDT 24
Finished May 14 12:59:59 PM PDT 24
Peak memory 199420 kb
Host smart-80637b74-e4a4-4141-8629-584c4c69affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887073282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1887073282
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.821325670
Short name T1054
Test name
Test status
Simulation time 28936642 ps
CPU time 0.54 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 12:59:55 PM PDT 24
Peak memory 196060 kb
Host smart-7df5e308-5f08-4bb6-af16-bdf9607f8197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821325670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.821325670
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.537175454
Short name T1160
Test name
Test status
Simulation time 62675554719 ps
CPU time 26.91 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:00:19 PM PDT 24
Peak memory 200188 kb
Host smart-6867aa35-b772-4371-8945-d8ebce7c33e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537175454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.537175454
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2160570340
Short name T429
Test name
Test status
Simulation time 97838416755 ps
CPU time 14.2 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:00:06 PM PDT 24
Peak memory 198840 kb
Host smart-3df68856-391a-4c51-8726-35106ee8617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160570340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2160570340
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.476324616
Short name T1178
Test name
Test status
Simulation time 18439971149 ps
CPU time 31.15 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:00:22 PM PDT 24
Peak memory 200452 kb
Host smart-73676390-4abb-4aef-be45-5bc0b593ef0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476324616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.476324616
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2522511241
Short name T774
Test name
Test status
Simulation time 56697060233 ps
CPU time 170.43 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:02:43 PM PDT 24
Peak memory 200408 kb
Host smart-1477074f-6a8d-459b-a627-91ab955cf0c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522511241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2522511241
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4021209232
Short name T107
Test name
Test status
Simulation time 90608556737 ps
CPU time 692.99 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:11:25 PM PDT 24
Peak memory 200484 kb
Host smart-59450543-07a5-4214-843f-dc6da88efd2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021209232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4021209232
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2512748154
Short name T630
Test name
Test status
Simulation time 8169817942 ps
CPU time 16.1 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 200108 kb
Host smart-3e542fbd-e678-4bf4-bfae-89576d8805d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512748154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2512748154
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1584163737
Short name T423
Test name
Test status
Simulation time 34242640472 ps
CPU time 61.51 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:00:53 PM PDT 24
Peak memory 199696 kb
Host smart-bcdcc367-60b4-4a14-b742-6c7ee56eeabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584163737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1584163737
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.487566940
Short name T261
Test name
Test status
Simulation time 19140381738 ps
CPU time 1099.03 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:18:10 PM PDT 24
Peak memory 200496 kb
Host smart-beb051a1-fc25-4f4d-a538-b92f813727cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487566940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.487566940
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4091453570
Short name T348
Test name
Test status
Simulation time 4043157630 ps
CPU time 8.1 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:00:00 PM PDT 24
Peak memory 199520 kb
Host smart-aabaccca-8411-4443-9436-f28c68742f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091453570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4091453570
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.801490086
Short name T838
Test name
Test status
Simulation time 20117216677 ps
CPU time 44.17 seconds
Started May 14 12:59:13 PM PDT 24
Finished May 14 01:00:36 PM PDT 24
Peak memory 200252 kb
Host smart-f4228cd3-a63b-4e84-a6d1-23177cb55d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801490086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.801490086
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2520562029
Short name T784
Test name
Test status
Simulation time 52167004062 ps
CPU time 6.28 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 12:59:58 PM PDT 24
Peak memory 196200 kb
Host smart-75355f13-5f34-4763-a051-cfbb1751f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520562029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2520562029
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3242322785
Short name T717
Test name
Test status
Simulation time 5379829419 ps
CPU time 14.29 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 01:00:06 PM PDT 24
Peak memory 199768 kb
Host smart-4d17a1ad-804b-41f0-b1d9-143a6c6e8fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242322785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3242322785
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1436381552
Short name T657
Test name
Test status
Simulation time 107373437764 ps
CPU time 1051.18 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 01:17:26 PM PDT 24
Peak memory 200484 kb
Host smart-e0041efe-c0c8-4281-a068-5f9da9df9286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436381552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1436381552
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.759670476
Short name T1151
Test name
Test status
Simulation time 22373258245 ps
CPU time 167.96 seconds
Started May 14 12:59:20 PM PDT 24
Finished May 14 01:02:43 PM PDT 24
Peak memory 216376 kb
Host smart-bbc91b10-d198-4357-9a78-614aa98c8f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759670476 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.759670476
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3313555492
Short name T1142
Test name
Test status
Simulation time 7819702898 ps
CPU time 6.28 seconds
Started May 14 12:59:12 PM PDT 24
Finished May 14 12:59:58 PM PDT 24
Peak memory 200480 kb
Host smart-11400fcb-953c-4c47-a6b6-df3307d865a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313555492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3313555492
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4054097862
Short name T875
Test name
Test status
Simulation time 23335187946 ps
CPU time 39.51 seconds
Started May 14 12:59:14 PM PDT 24
Finished May 14 01:00:32 PM PDT 24
Peak memory 200480 kb
Host smart-9374e926-117f-47a3-8c72-2c0dba682607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054097862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4054097862
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2807576052
Short name T353
Test name
Test status
Simulation time 12841583 ps
CPU time 0.59 seconds
Started May 14 12:57:04 PM PDT 24
Finished May 14 12:57:07 PM PDT 24
Peak memory 194752 kb
Host smart-aa7bc3f1-904f-4e73-8878-b413429f1c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807576052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2807576052
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1625765565
Short name T1132
Test name
Test status
Simulation time 72536541523 ps
CPU time 15.91 seconds
Started May 14 12:57:03 PM PDT 24
Finished May 14 12:57:21 PM PDT 24
Peak memory 200448 kb
Host smart-9f6503d1-3524-4a87-b9e1-6548d9551913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625765565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1625765565
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3957034949
Short name T1044
Test name
Test status
Simulation time 10065789799 ps
CPU time 16.44 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:21 PM PDT 24
Peak memory 199836 kb
Host smart-e9658ce3-b5c8-4786-900d-b24e7c376e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957034949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3957034949
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.142658080
Short name T6
Test name
Test status
Simulation time 41365437351 ps
CPU time 56.64 seconds
Started May 14 12:57:03 PM PDT 24
Finished May 14 12:58:02 PM PDT 24
Peak memory 200540 kb
Host smart-a32f2f2f-9f74-4535-999b-7c81fd451de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142658080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.142658080
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1811191871
Short name T118
Test name
Test status
Simulation time 40014485260 ps
CPU time 22.26 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:27 PM PDT 24
Peak memory 200308 kb
Host smart-7f9dbdf9-3bda-4c8d-b304-f1e4b81fb93a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811191871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1811191871
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3456953246
Short name T410
Test name
Test status
Simulation time 93733991145 ps
CPU time 714.2 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 01:08:59 PM PDT 24
Peak memory 200488 kb
Host smart-269bdb9a-813e-44bc-8c32-55dda87f4b3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456953246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3456953246
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.816504231
Short name T369
Test name
Test status
Simulation time 5111860966 ps
CPU time 11.98 seconds
Started May 14 12:57:06 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 199668 kb
Host smart-03fdf9b6-ee8b-4d7e-b3d8-c38bc6d66817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816504231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.816504231
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3067581465
Short name T951
Test name
Test status
Simulation time 63158179961 ps
CPU time 51.03 seconds
Started May 14 12:57:04 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 200688 kb
Host smart-f7d3ef68-45fd-4c17-ab8c-9945c825c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067581465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3067581465
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3549116878
Short name T820
Test name
Test status
Simulation time 15850860925 ps
CPU time 716.29 seconds
Started May 14 12:57:04 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 200392 kb
Host smart-497bd9fc-68ab-4291-9606-2fccb27c5f23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549116878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3549116878
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2573946
Short name T347
Test name
Test status
Simulation time 3169457908 ps
CPU time 5.26 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:10 PM PDT 24
Peak memory 198484 kb
Host smart-63f875b7-a3b1-434c-afe9-eb2589934dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2573946
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3345696675
Short name T562
Test name
Test status
Simulation time 36885082011 ps
CPU time 11.94 seconds
Started May 14 12:57:05 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 200428 kb
Host smart-4e659a96-0c37-40e8-9d48-8ae0af62627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345696675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3345696675
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1336217456
Short name T422
Test name
Test status
Simulation time 3072931209 ps
CPU time 5.83 seconds
Started May 14 12:57:01 PM PDT 24
Finished May 14 12:57:09 PM PDT 24
Peak memory 196212 kb
Host smart-b732852e-215a-40f9-9b22-5cd53ce34ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336217456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1336217456
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.254124003
Short name T25
Test name
Test status
Simulation time 116099412 ps
CPU time 0.84 seconds
Started May 14 12:57:01 PM PDT 24
Finished May 14 12:57:05 PM PDT 24
Peak memory 218928 kb
Host smart-2d00c7b6-9315-4e84-aff2-ec9d39ebe2f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254124003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.254124003
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1297643271
Short name T485
Test name
Test status
Simulation time 428966365 ps
CPU time 2.46 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:07 PM PDT 24
Peak memory 199296 kb
Host smart-d722618a-69a6-4244-a0bc-ea0fe52258de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297643271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1297643271
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2894702179
Short name T1021
Test name
Test status
Simulation time 359420212137 ps
CPU time 456.28 seconds
Started May 14 12:57:01 PM PDT 24
Finished May 14 01:04:39 PM PDT 24
Peak memory 208948 kb
Host smart-bfa95323-4e8a-4797-98b6-01f99f35ec43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894702179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2894702179
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2001142583
Short name T515
Test name
Test status
Simulation time 58061129105 ps
CPU time 781.02 seconds
Started May 14 12:57:06 PM PDT 24
Finished May 14 01:10:08 PM PDT 24
Peak memory 216904 kb
Host smart-692b6925-d76d-4859-a853-dc8594ba3da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001142583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2001142583
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.185336717
Short name T334
Test name
Test status
Simulation time 2024584010 ps
CPU time 2.41 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:07 PM PDT 24
Peak memory 199296 kb
Host smart-4bc25ffa-7b32-4b62-82b3-97e409999854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185336717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.185336717
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2394378222
Short name T715
Test name
Test status
Simulation time 34023418347 ps
CPU time 33.26 seconds
Started May 14 12:57:03 PM PDT 24
Finished May 14 12:57:38 PM PDT 24
Peak memory 200232 kb
Host smart-41d923ef-9c48-4e13-a23a-5b7feb6f9f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394378222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2394378222
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1324415395
Short name T356
Test name
Test status
Simulation time 27128208 ps
CPU time 0.55 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 12:59:55 PM PDT 24
Peak memory 195868 kb
Host smart-28b26c53-b952-4a68-b64a-f110787c9723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324415395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1324415395
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.723694703
Short name T483
Test name
Test status
Simulation time 41611987760 ps
CPU time 64.09 seconds
Started May 14 12:59:22 PM PDT 24
Finished May 14 01:01:00 PM PDT 24
Peak memory 200448 kb
Host smart-8d3b1c19-5381-4d1b-b159-d7f669b64478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723694703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.723694703
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.546460877
Short name T495
Test name
Test status
Simulation time 24669608327 ps
CPU time 45.99 seconds
Started May 14 12:59:23 PM PDT 24
Finished May 14 01:00:43 PM PDT 24
Peak memory 200408 kb
Host smart-9e43c5aa-b67e-405d-87d8-56927aa7b962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546460877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.546460877
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.2846715202
Short name T964
Test name
Test status
Simulation time 5572991626 ps
CPU time 2.76 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 12:59:57 PM PDT 24
Peak memory 197180 kb
Host smart-1498f374-fd6f-435b-9a62-d525a71e15bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846715202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2846715202
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2164898657
Short name T1046
Test name
Test status
Simulation time 45747385453 ps
CPU time 203.82 seconds
Started May 14 12:59:20 PM PDT 24
Finished May 14 01:03:19 PM PDT 24
Peak memory 200440 kb
Host smart-a91b0b85-f329-4890-8751-01b40f2b7b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164898657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2164898657
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.449499949
Short name T544
Test name
Test status
Simulation time 2963909346 ps
CPU time 2.51 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 12:59:57 PM PDT 24
Peak memory 198900 kb
Host smart-bb32be3d-db32-42bf-9b81-d782af12013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449499949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.449499949
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.643530616
Short name T933
Test name
Test status
Simulation time 156919206486 ps
CPU time 58.31 seconds
Started May 14 12:59:18 PM PDT 24
Finished May 14 01:00:53 PM PDT 24
Peak memory 200688 kb
Host smart-1fd1b927-08ec-4aaf-8573-e6daf3bee0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643530616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.643530616
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2009972648
Short name T711
Test name
Test status
Simulation time 16294795787 ps
CPU time 223.5 seconds
Started May 14 12:59:20 PM PDT 24
Finished May 14 01:03:38 PM PDT 24
Peak memory 200496 kb
Host smart-6e1fe7c3-bf11-4bec-9c36-ef00a3eab094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009972648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2009972648
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1168269467
Short name T1180
Test name
Test status
Simulation time 4075205295 ps
CPU time 17.43 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 01:00:12 PM PDT 24
Peak memory 198512 kb
Host smart-e1158224-f312-40e9-86aa-333ff82f8893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168269467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1168269467
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3257567250
Short name T739
Test name
Test status
Simulation time 127692798089 ps
CPU time 53.3 seconds
Started May 14 12:59:21 PM PDT 24
Finished May 14 01:00:48 PM PDT 24
Peak memory 200508 kb
Host smart-025892ad-7012-4fce-af83-ef4f890c1667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257567250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3257567250
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2616501554
Short name T251
Test name
Test status
Simulation time 2292515375 ps
CPU time 2.3 seconds
Started May 14 12:59:20 PM PDT 24
Finished May 14 12:59:57 PM PDT 24
Peak memory 195948 kb
Host smart-4acfa800-fb0d-4603-b90c-8bd145a67801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616501554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2616501554
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3773842645
Short name T478
Test name
Test status
Simulation time 647638562 ps
CPU time 2.48 seconds
Started May 14 12:59:23 PM PDT 24
Finished May 14 01:00:00 PM PDT 24
Peak memory 200348 kb
Host smart-8388f6ce-65d4-4ca6-8827-427c25cdc021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773842645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3773842645
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1709788396
Short name T494
Test name
Test status
Simulation time 192354282319 ps
CPU time 213 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 01:03:28 PM PDT 24
Peak memory 200492 kb
Host smart-fb38f263-637e-4ceb-bea3-6d07a3b48cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709788396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1709788396
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.122553886
Short name T693
Test name
Test status
Simulation time 360854751 ps
CPU time 1.3 seconds
Started May 14 12:59:20 PM PDT 24
Finished May 14 12:59:56 PM PDT 24
Peak memory 198712 kb
Host smart-420d0390-55a3-4b3d-884a-88514643cf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122553886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.122553886
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1119877888
Short name T263
Test name
Test status
Simulation time 39761383260 ps
CPU time 39.43 seconds
Started May 14 12:59:20 PM PDT 24
Finished May 14 01:00:34 PM PDT 24
Peak memory 200476 kb
Host smart-a169273f-5f46-4b4c-b9f1-f295720db12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119877888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1119877888
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4180351984
Short name T22
Test name
Test status
Simulation time 14913742 ps
CPU time 0.57 seconds
Started May 14 12:59:33 PM PDT 24
Finished May 14 01:00:01 PM PDT 24
Peak memory 195864 kb
Host smart-1d2150cd-3aa3-450b-85b8-17ac7966322f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180351984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4180351984
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.58810284
Short name T1031
Test name
Test status
Simulation time 87192608705 ps
CPU time 26.46 seconds
Started May 14 12:59:18 PM PDT 24
Finished May 14 01:00:21 PM PDT 24
Peak memory 200524 kb
Host smart-961e2fb0-0570-406d-9df8-428e7f89b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58810284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.58810284
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.336351425
Short name T737
Test name
Test status
Simulation time 37951869712 ps
CPU time 36.9 seconds
Started May 14 12:59:22 PM PDT 24
Finished May 14 01:00:33 PM PDT 24
Peak memory 200508 kb
Host smart-f9cc4a2b-c932-44f5-936f-e8d928e12a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336351425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.336351425
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.3671399770
Short name T623
Test name
Test status
Simulation time 30343831883 ps
CPU time 18 seconds
Started May 14 12:59:26 PM PDT 24
Finished May 14 01:00:16 PM PDT 24
Peak memory 199152 kb
Host smart-9397619d-cf12-403e-8a73-d1d9ae7a9393
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671399770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3671399770
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.175694431
Short name T436
Test name
Test status
Simulation time 129666918905 ps
CPU time 340.4 seconds
Started May 14 12:59:28 PM PDT 24
Finished May 14 01:05:39 PM PDT 24
Peak memory 200452 kb
Host smart-87d31024-bdff-4426-8b11-289b0062efe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175694431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.175694431
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.577375405
Short name T540
Test name
Test status
Simulation time 5667856143 ps
CPU time 1.86 seconds
Started May 14 12:59:28 PM PDT 24
Finished May 14 01:00:00 PM PDT 24
Peak memory 198836 kb
Host smart-3b6f836c-314f-4665-a595-070cb89fa676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577375405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.577375405
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.712351790
Short name T942
Test name
Test status
Simulation time 73502875357 ps
CPU time 167.41 seconds
Started May 14 12:59:32 PM PDT 24
Finished May 14 01:02:48 PM PDT 24
Peak memory 199488 kb
Host smart-093aa259-5674-4937-a82c-046f3b22b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712351790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.712351790
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3708173921
Short name T506
Test name
Test status
Simulation time 6564722337 ps
CPU time 135.49 seconds
Started May 14 12:59:26 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 200448 kb
Host smart-25703b91-967f-462e-9ff1-21259646ce89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708173921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3708173921
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3089483333
Short name T1038
Test name
Test status
Simulation time 2440819842 ps
CPU time 15.96 seconds
Started May 14 12:59:27 PM PDT 24
Finished May 14 01:00:14 PM PDT 24
Peak memory 198596 kb
Host smart-c2a14afc-bd2f-40ac-bac8-a8f5a546ea0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089483333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3089483333
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2919325499
Short name T686
Test name
Test status
Simulation time 105785756289 ps
CPU time 72.5 seconds
Started May 14 12:59:28 PM PDT 24
Finished May 14 01:01:11 PM PDT 24
Peak memory 200344 kb
Host smart-04f7c42e-b061-4de9-992d-3dfe227a436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919325499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2919325499
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3771029402
Short name T271
Test name
Test status
Simulation time 34771868975 ps
CPU time 51.78 seconds
Started May 14 12:59:33 PM PDT 24
Finished May 14 01:00:52 PM PDT 24
Peak memory 196200 kb
Host smart-8a0159f9-7bb2-4836-bc93-efbadae45844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771029402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3771029402
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3408477711
Short name T574
Test name
Test status
Simulation time 11055613831 ps
CPU time 21.16 seconds
Started May 14 12:59:19 PM PDT 24
Finished May 14 01:00:16 PM PDT 24
Peak memory 200068 kb
Host smart-318a9dc3-e3a4-4b02-ad42-a80ecd387151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408477711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3408477711
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.430706599
Short name T1060
Test name
Test status
Simulation time 23636963740 ps
CPU time 39.6 seconds
Started May 14 12:59:27 PM PDT 24
Finished May 14 01:00:38 PM PDT 24
Peak memory 200452 kb
Host smart-3e338817-c2bf-40c5-9b19-f7f7ed08d5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430706599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.430706599
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.95529935
Short name T932
Test name
Test status
Simulation time 32629048494 ps
CPU time 728.88 seconds
Started May 14 12:59:28 PM PDT 24
Finished May 14 01:12:08 PM PDT 24
Peak memory 217192 kb
Host smart-9ad88428-d329-4e58-8e12-8bbd9e5c133d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95529935 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.95529935
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3646774507
Short name T299
Test name
Test status
Simulation time 2668079883 ps
CPU time 2 seconds
Started May 14 12:59:29 PM PDT 24
Finished May 14 01:00:01 PM PDT 24
Peak memory 199292 kb
Host smart-05af6383-6498-4b4f-8d98-9f8c8f02fb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646774507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3646774507
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1117377524
Short name T338
Test name
Test status
Simulation time 9287975273 ps
CPU time 18.65 seconds
Started May 14 12:59:21 PM PDT 24
Finished May 14 01:00:14 PM PDT 24
Peak memory 200504 kb
Host smart-e956c4d2-4901-4edd-be5f-bb8c762b74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117377524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1117377524
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3931018580
Short name T617
Test name
Test status
Simulation time 15291119 ps
CPU time 0.57 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:02 PM PDT 24
Peak memory 195848 kb
Host smart-3eaddf0e-068a-4f1a-95e5-c3c0bdb455b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931018580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3931018580
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2007357893
Short name T326
Test name
Test status
Simulation time 28904581893 ps
CPU time 18.33 seconds
Started May 14 12:59:27 PM PDT 24
Finished May 14 01:00:17 PM PDT 24
Peak memory 200496 kb
Host smart-988a8d50-d27d-4a9d-9dff-eddf051a8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007357893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2007357893
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.306028986
Short name T1121
Test name
Test status
Simulation time 14820801756 ps
CPU time 12.25 seconds
Started May 14 12:59:27 PM PDT 24
Finished May 14 01:00:11 PM PDT 24
Peak memory 198920 kb
Host smart-ec7fcf47-7158-4a91-8e62-ab4028d71bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306028986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.306028986
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1559548232
Short name T1156
Test name
Test status
Simulation time 14419386132 ps
CPU time 22.06 seconds
Started May 14 12:59:28 PM PDT 24
Finished May 14 01:00:21 PM PDT 24
Peak memory 200480 kb
Host smart-3adaef14-7bfe-484a-ba9e-b74ef6a5cc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559548232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1559548232
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1798514586
Short name T852
Test name
Test status
Simulation time 24448740346 ps
CPU time 39.89 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:41 PM PDT 24
Peak memory 200140 kb
Host smart-6ef10c72-b709-4fba-93d9-baee4c9133be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798514586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1798514586
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.593727439
Short name T641
Test name
Test status
Simulation time 111348509957 ps
CPU time 866.36 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 200380 kb
Host smart-801c6673-365f-44f0-843d-dc26494b6b51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593727439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.593727439
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3349503111
Short name T1130
Test name
Test status
Simulation time 6585420743 ps
CPU time 11.63 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:13 PM PDT 24
Peak memory 199384 kb
Host smart-6fbfce25-f078-4850-b7fa-5cda1f2e03bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349503111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3349503111
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2462531516
Short name T981
Test name
Test status
Simulation time 75977750622 ps
CPU time 118.23 seconds
Started May 14 12:59:34 PM PDT 24
Finished May 14 01:01:59 PM PDT 24
Peak memory 200660 kb
Host smart-76fcd807-02ad-42b7-a3b7-05adfff8a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462531516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2462531516
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3837864105
Short name T34
Test name
Test status
Simulation time 14978004385 ps
CPU time 210.48 seconds
Started May 14 12:59:37 PM PDT 24
Finished May 14 01:03:32 PM PDT 24
Peak memory 200440 kb
Host smart-df16c12d-0962-4c1a-bce4-a90b124f76ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837864105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3837864105
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3656513133
Short name T865
Test name
Test status
Simulation time 2425887095 ps
CPU time 15.31 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:16 PM PDT 24
Peak memory 198652 kb
Host smart-c8821e43-d2b9-42ad-a85a-22b6404139b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656513133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3656513133
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2799609049
Short name T123
Test name
Test status
Simulation time 99322765116 ps
CPU time 176.22 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:02:57 PM PDT 24
Peak memory 200516 kb
Host smart-d1dab556-ab55-4535-82a1-630fc1e5b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799609049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2799609049
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2068204982
Short name T1042
Test name
Test status
Simulation time 5323889772 ps
CPU time 2.52 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:04 PM PDT 24
Peak memory 196456 kb
Host smart-ee43dc23-d67a-400e-ae67-8c866ffe5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068204982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2068204982
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2766461838
Short name T593
Test name
Test status
Simulation time 665394838 ps
CPU time 3.21 seconds
Started May 14 12:59:29 PM PDT 24
Finished May 14 01:00:02 PM PDT 24
Peak memory 200364 kb
Host smart-0f5579cf-0ac1-4a81-b257-73f313d89fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766461838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2766461838
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1649146362
Short name T896
Test name
Test status
Simulation time 405538144114 ps
CPU time 979.25 seconds
Started May 14 12:59:36 PM PDT 24
Finished May 14 01:16:20 PM PDT 24
Peak memory 208988 kb
Host smart-3ce3f242-606a-47c9-86e0-67deb1e0e416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649146362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1649146362
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2169309149
Short name T15
Test name
Test status
Simulation time 25490322057 ps
CPU time 273.02 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:04:34 PM PDT 24
Peak memory 216024 kb
Host smart-f69df023-540b-4017-97ad-44931dfc1590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169309149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2169309149
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3088714487
Short name T533
Test name
Test status
Simulation time 7166818692 ps
CPU time 25.31 seconds
Started May 14 12:59:39 PM PDT 24
Finished May 14 01:00:28 PM PDT 24
Peak memory 200448 kb
Host smart-e7a90b66-8fea-41ce-9927-6f0ab5c21d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088714487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3088714487
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.985279768
Short name T1148
Test name
Test status
Simulation time 60287041214 ps
CPU time 36.22 seconds
Started May 14 12:59:29 PM PDT 24
Finished May 14 01:00:35 PM PDT 24
Peak memory 200448 kb
Host smart-b888a39a-f7f3-4d44-ac83-0dd997adb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985279768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.985279768
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.4087895752
Short name T23
Test name
Test status
Simulation time 14174685 ps
CPU time 0.54 seconds
Started May 14 12:59:42 PM PDT 24
Finished May 14 01:00:04 PM PDT 24
Peak memory 195852 kb
Host smart-4ec93a15-e11f-4269-ba69-5fd082c5a3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087895752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.4087895752
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1273453403
Short name T915
Test name
Test status
Simulation time 119886991003 ps
CPU time 257.8 seconds
Started May 14 12:59:36 PM PDT 24
Finished May 14 01:04:19 PM PDT 24
Peak memory 200500 kb
Host smart-f473e642-0501-4e9d-a14f-645523c429da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273453403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1273453403
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1936860190
Short name T377
Test name
Test status
Simulation time 11842267121 ps
CPU time 17.63 seconds
Started May 14 12:59:34 PM PDT 24
Finished May 14 01:00:19 PM PDT 24
Peak memory 200180 kb
Host smart-154579d3-89fa-40dc-9ef8-56106642559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936860190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1936860190
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.829553574
Short name T223
Test name
Test status
Simulation time 70180343059 ps
CPU time 28.83 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:30 PM PDT 24
Peak memory 200532 kb
Host smart-dc4c9b36-a4e8-4740-b83c-d9b61643096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829553574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.829553574
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.648703804
Short name T636
Test name
Test status
Simulation time 9573175810 ps
CPU time 14.3 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:15 PM PDT 24
Peak memory 200440 kb
Host smart-665cc757-0f64-410d-9621-d1330798de62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648703804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.648703804
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1293372999
Short name T1149
Test name
Test status
Simulation time 54700087103 ps
CPU time 380.89 seconds
Started May 14 12:59:45 PM PDT 24
Finished May 14 01:06:26 PM PDT 24
Peak memory 200460 kb
Host smart-18252751-4f72-4f79-a7ee-4b2ff4c80902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293372999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1293372999
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3552038756
Short name T349
Test name
Test status
Simulation time 6969320555 ps
CPU time 3.6 seconds
Started May 14 12:59:42 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 200384 kb
Host smart-89dac77f-880b-4ede-981a-329c5d90a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552038756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3552038756
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.743003261
Short name T632
Test name
Test status
Simulation time 132269699332 ps
CPU time 200.07 seconds
Started May 14 12:59:36 PM PDT 24
Finished May 14 01:03:21 PM PDT 24
Peak memory 200384 kb
Host smart-06f857e4-0aa2-47c7-a038-5455cc8a6c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743003261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.743003261
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.648442097
Short name T616
Test name
Test status
Simulation time 13516737893 ps
CPU time 188.83 seconds
Started May 14 12:59:46 PM PDT 24
Finished May 14 01:03:14 PM PDT 24
Peak memory 200480 kb
Host smart-ac1b1e8b-25c4-438b-994a-5f446862baf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648442097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.648442097
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3395995854
Short name T1033
Test name
Test status
Simulation time 5600902621 ps
CPU time 11.51 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:13 PM PDT 24
Peak memory 200428 kb
Host smart-0c0eab23-1daa-4f20-8a0f-bfc8ff687f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395995854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3395995854
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.758120590
Short name T1158
Test name
Test status
Simulation time 49326026056 ps
CPU time 7.42 seconds
Started May 14 12:59:46 PM PDT 24
Finished May 14 01:00:12 PM PDT 24
Peak memory 200488 kb
Host smart-851ad181-8863-470b-99bc-fb3523a1790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758120590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.758120590
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1965533700
Short name T854
Test name
Test status
Simulation time 41134401147 ps
CPU time 72.17 seconds
Started May 14 12:59:36 PM PDT 24
Finished May 14 01:01:13 PM PDT 24
Peak memory 196460 kb
Host smart-39c30d8e-d350-4493-a3ce-2a283d2a1a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965533700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1965533700
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.939097565
Short name T644
Test name
Test status
Simulation time 1045893621 ps
CPU time 1.64 seconds
Started May 14 12:59:34 PM PDT 24
Finished May 14 01:00:03 PM PDT 24
Peak memory 198868 kb
Host smart-dc1602a2-99d4-442f-932c-df8931b81737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939097565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.939097565
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1502817993
Short name T153
Test name
Test status
Simulation time 61998058834 ps
CPU time 604.96 seconds
Started May 14 12:59:43 PM PDT 24
Finished May 14 01:10:09 PM PDT 24
Peak memory 217164 kb
Host smart-6d74d2d5-eee6-49e6-ad3c-8604cd1d32ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502817993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1502817993
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2123590972
Short name T1100
Test name
Test status
Simulation time 1481913869 ps
CPU time 1.74 seconds
Started May 14 12:59:43 PM PDT 24
Finished May 14 01:00:06 PM PDT 24
Peak memory 198912 kb
Host smart-8a678f03-7903-4d0a-9d94-636870a6f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123590972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2123590972
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1451478647
Short name T1032
Test name
Test status
Simulation time 12791457991 ps
CPU time 11.38 seconds
Started May 14 12:59:35 PM PDT 24
Finished May 14 01:00:13 PM PDT 24
Peak memory 200424 kb
Host smart-cd3eac74-69ff-4d6a-ac37-2ecc41d7ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451478647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1451478647
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1882805480
Short name T449
Test name
Test status
Simulation time 42110688 ps
CPU time 0.54 seconds
Started May 14 12:59:53 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 195832 kb
Host smart-528760e2-b31a-4699-a726-382c5be9f6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882805480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1882805480
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4160267657
Short name T727
Test name
Test status
Simulation time 45815173625 ps
CPU time 80.85 seconds
Started May 14 12:59:42 PM PDT 24
Finished May 14 01:01:25 PM PDT 24
Peak memory 200472 kb
Host smart-16ad59b6-8119-4d5c-bfa8-921d321383c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160267657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4160267657
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.835850402
Short name T1014
Test name
Test status
Simulation time 31624549292 ps
CPU time 29.24 seconds
Started May 14 12:59:44 PM PDT 24
Finished May 14 01:00:34 PM PDT 24
Peak memory 200236 kb
Host smart-02573a4c-ac9a-468b-b7aa-63478044043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835850402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.835850402
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2609817395
Short name T63
Test name
Test status
Simulation time 27411996442 ps
CPU time 16.19 seconds
Started May 14 12:59:42 PM PDT 24
Finished May 14 01:00:20 PM PDT 24
Peak memory 200344 kb
Host smart-d5a66b1c-2b80-4836-a643-9f51c70ba99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609817395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2609817395
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3833433620
Short name T925
Test name
Test status
Simulation time 18754205483 ps
CPU time 3.19 seconds
Started May 14 12:59:44 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 199924 kb
Host smart-590ae18f-b7d2-4540-88aa-18ec789a522d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833433620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3833433620
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1921224053
Short name T806
Test name
Test status
Simulation time 91211215650 ps
CPU time 631.67 seconds
Started May 14 12:59:53 PM PDT 24
Finished May 14 01:10:39 PM PDT 24
Peak memory 200476 kb
Host smart-94a7ead4-2550-413f-9024-2f93bcaf5774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921224053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1921224053
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3640702896
Short name T97
Test name
Test status
Simulation time 2287619914 ps
CPU time 1.71 seconds
Started May 14 12:59:50 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 196672 kb
Host smart-fa4767d4-6f83-4e35-a627-ab9f67dde1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640702896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3640702896
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1904036545
Short name T670
Test name
Test status
Simulation time 69722479702 ps
CPU time 76.1 seconds
Started May 14 12:59:44 PM PDT 24
Finished May 14 01:01:20 PM PDT 24
Peak memory 208712 kb
Host smart-87fcf006-3633-4e43-96c8-fe642120664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904036545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1904036545
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2387486946
Short name T1000
Test name
Test status
Simulation time 8458135640 ps
CPU time 104.78 seconds
Started May 14 12:59:53 PM PDT 24
Finished May 14 01:01:52 PM PDT 24
Peak memory 200512 kb
Host smart-b25d87ae-89be-48f6-87c5-85976685e7ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387486946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2387486946
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1672481411
Short name T893
Test name
Test status
Simulation time 5604579749 ps
CPU time 47.75 seconds
Started May 14 12:59:46 PM PDT 24
Finished May 14 01:00:53 PM PDT 24
Peak memory 199184 kb
Host smart-b9663f34-56a4-4c14-9cc5-35b5932a7b98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672481411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1672481411
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2022512568
Short name T310
Test name
Test status
Simulation time 92193274847 ps
CPU time 130.53 seconds
Started May 14 12:59:43 PM PDT 24
Finished May 14 01:02:15 PM PDT 24
Peak memory 200416 kb
Host smart-8e3c41da-e5ea-48d1-b465-1d0f44414014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022512568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2022512568
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2814022263
Short name T1020
Test name
Test status
Simulation time 4697527679 ps
CPU time 6.89 seconds
Started May 14 12:59:46 PM PDT 24
Finished May 14 01:00:12 PM PDT 24
Peak memory 196412 kb
Host smart-523f837a-b346-4173-ba68-8012775e9448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814022263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2814022263
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3575190296
Short name T666
Test name
Test status
Simulation time 891852782 ps
CPU time 3.67 seconds
Started May 14 12:59:44 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 200400 kb
Host smart-128b7cff-555b-49b7-b973-6706c8039573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575190296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3575190296
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3314267888
Short name T1133
Test name
Test status
Simulation time 137688042805 ps
CPU time 453.67 seconds
Started May 14 12:59:52 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 216964 kb
Host smart-91e5b440-0bdd-4377-a52a-877a1610a346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314267888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3314267888
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.213121149
Short name T758
Test name
Test status
Simulation time 7443371984 ps
CPU time 10.49 seconds
Started May 14 12:59:53 PM PDT 24
Finished May 14 01:00:18 PM PDT 24
Peak memory 200260 kb
Host smart-1c98a6a3-8a7e-40d5-be04-cb74cdff3a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213121149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.213121149
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3761003143
Short name T857
Test name
Test status
Simulation time 8130651579 ps
CPU time 12.55 seconds
Started May 14 12:59:43 PM PDT 24
Finished May 14 01:00:17 PM PDT 24
Peak memory 200220 kb
Host smart-50452873-ed48-4512-9a55-f4d2e801f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761003143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3761003143
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4079176478
Short name T802
Test name
Test status
Simulation time 14000178 ps
CPU time 0.59 seconds
Started May 14 01:00:01 PM PDT 24
Finished May 14 01:00:09 PM PDT 24
Peak memory 195860 kb
Host smart-72f31406-99c5-4a33-8543-c7e01a158a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079176478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4079176478
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.526191750
Short name T984
Test name
Test status
Simulation time 29181291092 ps
CPU time 41.26 seconds
Started May 14 12:59:53 PM PDT 24
Finished May 14 01:00:48 PM PDT 24
Peak memory 200280 kb
Host smart-942e052b-f19d-421b-8362-9c5db6d9dce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526191750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.526191750
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2716989584
Short name T832
Test name
Test status
Simulation time 155287975389 ps
CPU time 57.8 seconds
Started May 14 12:59:50 PM PDT 24
Finished May 14 01:01:04 PM PDT 24
Peak memory 200336 kb
Host smart-6b92c0b2-f358-4a3e-abc9-55c25bcfb37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716989584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2716989584
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2351802091
Short name T522
Test name
Test status
Simulation time 147480801655 ps
CPU time 62.23 seconds
Started May 14 12:59:52 PM PDT 24
Finished May 14 01:01:09 PM PDT 24
Peak memory 200488 kb
Host smart-11a0d326-7a73-4f0c-b857-c2a8a2d1632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351802091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2351802091
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.252264393
Short name T610
Test name
Test status
Simulation time 40352570769 ps
CPU time 19.09 seconds
Started May 14 12:59:54 PM PDT 24
Finished May 14 01:00:26 PM PDT 24
Peak memory 199900 kb
Host smart-ef41f163-42f0-45a2-acb7-00a6efa562c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252264393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.252264393
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3764678250
Short name T639
Test name
Test status
Simulation time 104775771879 ps
CPU time 394.5 seconds
Started May 14 12:59:51 PM PDT 24
Finished May 14 01:06:41 PM PDT 24
Peak memory 200504 kb
Host smart-3278be9b-4f7d-47c9-8ba1-022f771bd2cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764678250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3764678250
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3542730334
Short name T1091
Test name
Test status
Simulation time 7192918671 ps
CPU time 8.1 seconds
Started May 14 12:59:51 PM PDT 24
Finished May 14 01:00:15 PM PDT 24
Peak memory 200420 kb
Host smart-cb8c9236-a2a3-4bf2-8223-366cf406e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542730334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3542730334
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3431485504
Short name T827
Test name
Test status
Simulation time 98768853580 ps
CPU time 119.8 seconds
Started May 14 12:59:51 PM PDT 24
Finished May 14 01:02:06 PM PDT 24
Peak memory 201016 kb
Host smart-ccb32be4-23fa-499e-a73e-d598512e1481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431485504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3431485504
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3640160653
Short name T959
Test name
Test status
Simulation time 13647780158 ps
CPU time 172.04 seconds
Started May 14 12:59:52 PM PDT 24
Finished May 14 01:02:59 PM PDT 24
Peak memory 200428 kb
Host smart-64584362-8474-4c0c-88b1-7c20241355c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640160653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3640160653
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.962159277
Short name T837
Test name
Test status
Simulation time 3041494142 ps
CPU time 5.09 seconds
Started May 14 12:59:54 PM PDT 24
Finished May 14 01:00:12 PM PDT 24
Peak memory 199876 kb
Host smart-fde9c562-62d0-4d45-895a-e26dd0b3ef13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962159277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.962159277
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.70617031
Short name T863
Test name
Test status
Simulation time 64924141260 ps
CPU time 57.93 seconds
Started May 14 12:59:54 PM PDT 24
Finished May 14 01:01:05 PM PDT 24
Peak memory 200456 kb
Host smart-9ed16137-53d4-4c21-96dc-638d9645d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70617031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.70617031
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.651123352
Short name T284
Test name
Test status
Simulation time 25305838761 ps
CPU time 20.23 seconds
Started May 14 12:59:52 PM PDT 24
Finished May 14 01:00:27 PM PDT 24
Peak memory 196312 kb
Host smart-cffac3ad-24b5-40c4-9f0c-30711d824971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651123352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.651123352
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3042651049
Short name T889
Test name
Test status
Simulation time 6059622803 ps
CPU time 7.97 seconds
Started May 14 12:59:50 PM PDT 24
Finished May 14 01:00:14 PM PDT 24
Peak memory 200364 kb
Host smart-262062f5-79ed-4ab7-a8bc-a271100e0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042651049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3042651049
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3645955583
Short name T438
Test name
Test status
Simulation time 1970788372 ps
CPU time 1.56 seconds
Started May 14 12:59:51 PM PDT 24
Finished May 14 01:00:08 PM PDT 24
Peak memory 197704 kb
Host smart-d6820d9b-65b1-435d-932e-93fef8f7ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645955583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3645955583
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1375910772
Short name T432
Test name
Test status
Simulation time 32053790804 ps
CPU time 31.44 seconds
Started May 14 12:59:53 PM PDT 24
Finished May 14 01:00:39 PM PDT 24
Peak memory 200480 kb
Host smart-642b0027-abf4-4326-ad35-db24808cb7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375910772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1375910772
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4216789909
Short name T688
Test name
Test status
Simulation time 88072517 ps
CPU time 0.57 seconds
Started May 14 12:59:59 PM PDT 24
Finished May 14 01:00:09 PM PDT 24
Peak memory 195840 kb
Host smart-9e920534-3082-4fb5-8392-fc7275c934f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216789909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4216789909
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3273744206
Short name T395
Test name
Test status
Simulation time 152256884555 ps
CPU time 579.55 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:09:48 PM PDT 24
Peak memory 200548 kb
Host smart-f63c73dc-6535-4261-b2bb-accff7ace35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273744206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3273744206
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3100499702
Short name T1119
Test name
Test status
Simulation time 17232290212 ps
CPU time 28.12 seconds
Started May 14 12:59:59 PM PDT 24
Finished May 14 01:00:36 PM PDT 24
Peak memory 200408 kb
Host smart-9a28a98a-e840-4741-a15a-ed4d6ad0fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100499702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3100499702
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.4127502252
Short name T524
Test name
Test status
Simulation time 125219125431 ps
CPU time 27.41 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:00:36 PM PDT 24
Peak memory 200420 kb
Host smart-ae43bc31-2713-410e-91a9-45d33adcd8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127502252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4127502252
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2027921755
Short name T680
Test name
Test status
Simulation time 32393442194 ps
CPU time 59.7 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:01:08 PM PDT 24
Peak memory 200280 kb
Host smart-ceb5c92b-5cde-4e9c-82ff-f8d11a807f8d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027921755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2027921755
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2963795066
Short name T1036
Test name
Test status
Simulation time 86060546759 ps
CPU time 755.58 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:12:44 PM PDT 24
Peak memory 200472 kb
Host smart-74f1d9de-f656-44de-8faa-a56e415aaa11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963795066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2963795066
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2144142850
Short name T335
Test name
Test status
Simulation time 1177077032 ps
CPU time 1.18 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:00:10 PM PDT 24
Peak memory 197472 kb
Host smart-e50c26fd-0faf-4a11-b4ea-a4b4ef6548e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144142850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2144142850
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3793262538
Short name T659
Test name
Test status
Simulation time 94503053963 ps
CPU time 91.9 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:01:40 PM PDT 24
Peak memory 208816 kb
Host smart-6ee506eb-1e6d-49f4-87e7-4a2397fd08a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793262538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3793262538
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3001038136
Short name T888
Test name
Test status
Simulation time 16544441932 ps
CPU time 138.1 seconds
Started May 14 12:59:59 PM PDT 24
Finished May 14 01:02:26 PM PDT 24
Peak memory 200440 kb
Host smart-bf09e1db-e5f0-4792-848c-6c2c7a883ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001038136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3001038136
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2084350231
Short name T976
Test name
Test status
Simulation time 1587082676 ps
CPU time 5.9 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:00:14 PM PDT 24
Peak memory 198588 kb
Host smart-1ba00d97-d1d4-43fb-9893-541c2b088be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084350231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2084350231
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4205596443
Short name T733
Test name
Test status
Simulation time 374907620870 ps
CPU time 52.45 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:01:01 PM PDT 24
Peak memory 200436 kb
Host smart-6260587f-dd09-4cfe-9d7f-eaae6ae55162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205596443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4205596443
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1901434799
Short name T547
Test name
Test status
Simulation time 3914642415 ps
CPU time 2.37 seconds
Started May 14 01:00:00 PM PDT 24
Finished May 14 01:00:11 PM PDT 24
Peak memory 196736 kb
Host smart-a25ce6ed-ffa7-4f8b-8387-ebdf7692b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901434799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1901434799
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3538553131
Short name T859
Test name
Test status
Simulation time 11070145845 ps
CPU time 14.71 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:00:23 PM PDT 24
Peak memory 200064 kb
Host smart-59324963-fa12-472a-8c73-930e4b011d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538553131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3538553131
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.522136894
Short name T989
Test name
Test status
Simulation time 207621492245 ps
CPU time 507.4 seconds
Started May 14 12:59:59 PM PDT 24
Finished May 14 01:08:36 PM PDT 24
Peak memory 208984 kb
Host smart-a5a7bab9-b7ac-4655-9a02-c197a7528cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522136894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.522136894
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.442932434
Short name T16
Test name
Test status
Simulation time 7449718870 ps
CPU time 17.51 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:00:26 PM PDT 24
Peak memory 200244 kb
Host smart-039ddc05-3c6b-446f-ad6d-a9132a2cb1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442932434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.442932434
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1000885739
Short name T937
Test name
Test status
Simulation time 69872554810 ps
CPU time 57.08 seconds
Started May 14 12:59:59 PM PDT 24
Finished May 14 01:01:05 PM PDT 24
Peak memory 200440 kb
Host smart-1e1a1974-c355-4f50-a49d-91705fefe5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000885739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1000885739
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1094594118
Short name T1061
Test name
Test status
Simulation time 182520653 ps
CPU time 0.53 seconds
Started May 14 01:00:09 PM PDT 24
Finished May 14 01:00:12 PM PDT 24
Peak memory 195864 kb
Host smart-1c0555c0-b664-4ffb-9626-181ae3ec590d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094594118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1094594118
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2524249168
Short name T38
Test name
Test status
Simulation time 148602356849 ps
CPU time 128.59 seconds
Started May 14 01:00:11 PM PDT 24
Finished May 14 01:02:22 PM PDT 24
Peak memory 200452 kb
Host smart-02a3f64a-7b07-4966-9832-0b5e635a3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524249168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2524249168
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1805903013
Short name T594
Test name
Test status
Simulation time 72799217871 ps
CPU time 36.35 seconds
Started May 14 01:00:10 PM PDT 24
Finished May 14 01:00:49 PM PDT 24
Peak memory 200420 kb
Host smart-294dc33e-3ee3-412c-8fe0-cba1df21f439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805903013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1805903013
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.515475392
Short name T694
Test name
Test status
Simulation time 31042006638 ps
CPU time 71.53 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:01:22 PM PDT 24
Peak memory 200528 kb
Host smart-ab909a17-9756-464f-a52c-bb06678fc0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515475392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.515475392
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4001233076
Short name T1105
Test name
Test status
Simulation time 42420994203 ps
CPU time 36.92 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:00:47 PM PDT 24
Peak memory 200464 kb
Host smart-d18f2d97-9923-4312-be30-4f197dd04a6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001233076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4001233076
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.700216779
Short name T799
Test name
Test status
Simulation time 120625808152 ps
CPU time 147.02 seconds
Started May 14 01:00:10 PM PDT 24
Finished May 14 01:02:40 PM PDT 24
Peak memory 200476 kb
Host smart-570a9962-decb-426b-baff-13d48b618ee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700216779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.700216779
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3871407451
Short name T469
Test name
Test status
Simulation time 8192505516 ps
CPU time 2.87 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:00:14 PM PDT 24
Peak memory 200416 kb
Host smart-0c061473-4037-4a41-8f6b-95f5cc85978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871407451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3871407451
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.344971976
Short name T1008
Test name
Test status
Simulation time 25684909202 ps
CPU time 99.65 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:01:50 PM PDT 24
Peak memory 200220 kb
Host smart-03c0d383-deb4-420c-b77e-e82bc4017b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344971976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.344971976
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.177939687
Short name T887
Test name
Test status
Simulation time 18102279941 ps
CPU time 836.15 seconds
Started May 14 01:00:08 PM PDT 24
Finished May 14 01:14:07 PM PDT 24
Peak memory 200428 kb
Host smart-fa1f48df-c76f-4426-8f59-0d5e8d312904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177939687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.177939687
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2464699993
Short name T1125
Test name
Test status
Simulation time 5177588655 ps
CPU time 46.85 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:00:57 PM PDT 24
Peak memory 200420 kb
Host smart-b7ef074d-de72-41c8-aa47-ddb668543c0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464699993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2464699993
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.441689948
Short name T652
Test name
Test status
Simulation time 32026108974 ps
CPU time 49.84 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:01:00 PM PDT 24
Peak memory 200488 kb
Host smart-84702cdf-dea6-45e9-8c51-22239b3f12c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441689948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.441689948
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1337416654
Short name T479
Test name
Test status
Simulation time 2916934313 ps
CPU time 1.99 seconds
Started May 14 01:00:07 PM PDT 24
Finished May 14 01:00:13 PM PDT 24
Peak memory 196344 kb
Host smart-186fe5b8-4f62-47e5-9af1-65ada629b2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337416654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1337416654
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2932124513
Short name T992
Test name
Test status
Simulation time 563247376 ps
CPU time 2 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:00:10 PM PDT 24
Peak memory 199120 kb
Host smart-aeae39fc-4334-40db-863a-244f531e740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932124513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2932124513
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1014013998
Short name T818
Test name
Test status
Simulation time 102759030261 ps
CPU time 755.05 seconds
Started May 14 01:00:08 PM PDT 24
Finished May 14 01:12:46 PM PDT 24
Peak memory 214504 kb
Host smart-4bd76357-5a33-4625-8767-30d2ce0fcd9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014013998 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1014013998
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2344795116
Short name T697
Test name
Test status
Simulation time 1825868375 ps
CPU time 1.98 seconds
Started May 14 01:00:10 PM PDT 24
Finished May 14 01:00:15 PM PDT 24
Peak memory 199084 kb
Host smart-b98f6e87-25e8-47d5-a6c7-8e8dc1bc76b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344795116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2344795116
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2063488118
Short name T1063
Test name
Test status
Simulation time 70323766754 ps
CPU time 29.49 seconds
Started May 14 12:59:58 PM PDT 24
Finished May 14 01:00:38 PM PDT 24
Peak memory 199684 kb
Host smart-36ea4112-1a5f-472d-be35-b37ca1b4d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063488118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2063488118
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1919762976
Short name T1039
Test name
Test status
Simulation time 15282582 ps
CPU time 0.56 seconds
Started May 14 01:00:15 PM PDT 24
Finished May 14 01:00:19 PM PDT 24
Peak memory 195848 kb
Host smart-3abea140-fcd1-498a-aba7-8136283c2d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919762976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1919762976
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1862969320
Short name T109
Test name
Test status
Simulation time 98938602147 ps
CPU time 86.65 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:01:46 PM PDT 24
Peak memory 200464 kb
Host smart-85e087b7-4a63-4363-bdf0-86174be7ba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862969320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1862969320
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.780992208
Short name T337
Test name
Test status
Simulation time 39847189144 ps
CPU time 12.14 seconds
Started May 14 01:00:15 PM PDT 24
Finished May 14 01:00:31 PM PDT 24
Peak memory 200152 kb
Host smart-6451cd7c-c85e-4fdb-95e0-0422aadaba39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780992208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.780992208
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4090759264
Short name T277
Test name
Test status
Simulation time 156376123877 ps
CPU time 327.03 seconds
Started May 14 01:00:15 PM PDT 24
Finished May 14 01:05:46 PM PDT 24
Peak memory 200516 kb
Host smart-1ff4fb59-b42c-432a-ac41-6c724bc7bf80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090759264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4090759264
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.927076015
Short name T471
Test name
Test status
Simulation time 8107181801 ps
CPU time 8.28 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:00:28 PM PDT 24
Peak memory 200380 kb
Host smart-3eb44668-c2f5-4e18-82c5-20dabbaf9312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927076015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.927076015
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.107566579
Short name T94
Test name
Test status
Simulation time 54443662363 ps
CPU time 96.25 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:01:56 PM PDT 24
Peak memory 200688 kb
Host smart-5754cb28-9994-41f7-a20d-8a5890c1173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107566579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.107566579
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3377700368
Short name T252
Test name
Test status
Simulation time 11434125273 ps
CPU time 476.83 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 200412 kb
Host smart-c2fac87a-909d-4f5b-b3da-ee69ecb81a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377700368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3377700368
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3353733721
Short name T816
Test name
Test status
Simulation time 1615546221 ps
CPU time 2.66 seconds
Started May 14 01:00:15 PM PDT 24
Finished May 14 01:00:21 PM PDT 24
Peak memory 199480 kb
Host smart-26b3e390-09b1-428a-b110-aa22a17a16fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353733721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3353733721
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1763376959
Short name T135
Test name
Test status
Simulation time 10058734788 ps
CPU time 17.9 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:00:37 PM PDT 24
Peak memory 199832 kb
Host smart-50eb50a8-4dc1-441b-a741-9ce1b00645b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763376959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1763376959
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2514816829
Short name T1107
Test name
Test status
Simulation time 6511773475 ps
CPU time 3.2 seconds
Started May 14 01:00:14 PM PDT 24
Finished May 14 01:00:21 PM PDT 24
Peak memory 196480 kb
Host smart-74755560-0455-4f65-b214-c8f733160d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514816829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2514816829
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.739283506
Short name T424
Test name
Test status
Simulation time 467195932 ps
CPU time 1.51 seconds
Started May 14 01:00:11 PM PDT 24
Finished May 14 01:00:15 PM PDT 24
Peak memory 198796 kb
Host smart-98f91623-f1f6-469e-a378-26f1f21c7e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739283506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.739283506
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3801241545
Short name T808
Test name
Test status
Simulation time 188478773127 ps
CPU time 874.96 seconds
Started May 14 01:00:17 PM PDT 24
Finished May 14 01:14:55 PM PDT 24
Peak memory 200452 kb
Host smart-945256cd-6f7f-480a-b7ae-11f3ea84c743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801241545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3801241545
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.146765638
Short name T878
Test name
Test status
Simulation time 297132554179 ps
CPU time 850.52 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 225612 kb
Host smart-00f5b586-a2ad-4505-a557-25ba7c75954e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146765638 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.146765638
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.428559921
Short name T982
Test name
Test status
Simulation time 1679409931 ps
CPU time 2.39 seconds
Started May 14 01:00:18 PM PDT 24
Finished May 14 01:00:23 PM PDT 24
Peak memory 199352 kb
Host smart-8d43bc23-49d2-4c17-b2e2-063408945e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428559921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.428559921
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3689179791
Short name T514
Test name
Test status
Simulation time 115398872192 ps
CPU time 189.03 seconds
Started May 14 01:00:08 PM PDT 24
Finished May 14 01:03:20 PM PDT 24
Peak memory 200460 kb
Host smart-51546fdf-f7d6-4a7a-af90-e5fbdfd4c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689179791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3689179791
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1458877922
Short name T667
Test name
Test status
Simulation time 47635495 ps
CPU time 0.56 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:00:29 PM PDT 24
Peak memory 195852 kb
Host smart-b4713d30-97ba-4d34-b0ff-b7007d9e7f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458877922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1458877922
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1785937211
Short name T812
Test name
Test status
Simulation time 11837513667 ps
CPU time 23.81 seconds
Started May 14 01:00:16 PM PDT 24
Finished May 14 01:00:43 PM PDT 24
Peak memory 200456 kb
Host smart-2aab1050-a8f6-47f8-a630-992e398ce639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785937211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1785937211
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.733951161
Short name T493
Test name
Test status
Simulation time 72734921674 ps
CPU time 32.83 seconds
Started May 14 01:00:14 PM PDT 24
Finished May 14 01:00:51 PM PDT 24
Peak memory 200412 kb
Host smart-7db2cb23-22db-4be3-91bb-4810a0fce9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733951161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.733951161
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2244171682
Short name T803
Test name
Test status
Simulation time 90973151663 ps
CPU time 118.78 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:02:26 PM PDT 24
Peak memory 200504 kb
Host smart-bf1a7a23-108c-4930-8efc-fddc543a795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244171682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2244171682
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3881827161
Short name T446
Test name
Test status
Simulation time 32611006476 ps
CPU time 42.98 seconds
Started May 14 01:00:29 PM PDT 24
Finished May 14 01:01:14 PM PDT 24
Peak memory 200376 kb
Host smart-5c0e8f59-8054-40d3-a8e0-c48b2f251e16
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881827161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3881827161
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2675990441
Short name T1110
Test name
Test status
Simulation time 63304432918 ps
CPU time 171.12 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:03:18 PM PDT 24
Peak memory 200468 kb
Host smart-ea03b39c-8631-49a7-9d5c-2b542c6c8099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675990441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2675990441
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2782462419
Short name T569
Test name
Test status
Simulation time 6744644368 ps
CPU time 6.32 seconds
Started May 14 01:00:29 PM PDT 24
Finished May 14 01:00:38 PM PDT 24
Peak memory 200160 kb
Host smart-d47caa7c-7be5-4858-83e4-df4bcabff921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782462419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2782462419
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.4231743383
Short name T475
Test name
Test status
Simulation time 142017655674 ps
CPU time 102.01 seconds
Started May 14 01:00:30 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 200684 kb
Host smart-9625a297-94eb-4262-a153-99b4c2e0b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231743383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4231743383
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2660315411
Short name T558
Test name
Test status
Simulation time 18130019278 ps
CPU time 211.35 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:03:57 PM PDT 24
Peak memory 200436 kb
Host smart-586be356-016f-48e5-8c91-850544003dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660315411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2660315411
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2559269265
Short name T1167
Test name
Test status
Simulation time 4303014157 ps
CPU time 35.84 seconds
Started May 14 01:00:30 PM PDT 24
Finished May 14 01:01:08 PM PDT 24
Peak memory 198644 kb
Host smart-aad084c7-6afb-4365-9dfd-ab10fbf8c021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559269265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2559269265
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1985208156
Short name T1135
Test name
Test status
Simulation time 9695912113 ps
CPU time 14.66 seconds
Started May 14 01:00:29 PM PDT 24
Finished May 14 01:00:45 PM PDT 24
Peak memory 200468 kb
Host smart-0c63e0a7-71e4-4a79-83f0-5c354adf162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985208156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1985208156
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3742287985
Short name T698
Test name
Test status
Simulation time 40992174282 ps
CPU time 16.75 seconds
Started May 14 01:00:30 PM PDT 24
Finished May 14 01:00:48 PM PDT 24
Peak memory 196428 kb
Host smart-5770218c-0a6b-498e-a347-6e0f065ea06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742287985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3742287985
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1214861863
Short name T855
Test name
Test status
Simulation time 131936404 ps
CPU time 0.79 seconds
Started May 14 01:00:15 PM PDT 24
Finished May 14 01:00:20 PM PDT 24
Peak memory 197764 kb
Host smart-6d8fa1f5-075b-4157-a9b3-4e84150ecea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214861863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1214861863
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.199482821
Short name T295
Test name
Test status
Simulation time 33221564546 ps
CPU time 1322.97 seconds
Started May 14 01:00:29 PM PDT 24
Finished May 14 01:22:34 PM PDT 24
Peak memory 200420 kb
Host smart-8a79f324-f851-43e9-ba4d-04a40a084ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199482821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.199482821
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.91243584
Short name T943
Test name
Test status
Simulation time 52546642404 ps
CPU time 619.22 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:10:45 PM PDT 24
Peak memory 216888 kb
Host smart-b13c9060-b26e-468b-969d-ac111cd7a2fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91243584 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.91243584
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4050003925
Short name T555
Test name
Test status
Simulation time 7303647002 ps
CPU time 7.88 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:00:35 PM PDT 24
Peak memory 200352 kb
Host smart-add88ed3-c48a-4cf0-8b52-58c0d8853b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050003925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4050003925
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.107933546
Short name T934
Test name
Test status
Simulation time 60829347931 ps
CPU time 167.06 seconds
Started May 14 01:00:15 PM PDT 24
Finished May 14 01:03:05 PM PDT 24
Peak memory 200476 kb
Host smart-a6dffe71-a742-4818-a2dd-cd2b7c90b33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107933546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.107933546
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.189340877
Short name T609
Test name
Test status
Simulation time 14970282 ps
CPU time 0.55 seconds
Started May 14 12:57:15 PM PDT 24
Finished May 14 12:57:18 PM PDT 24
Peak memory 195832 kb
Host smart-1c5da170-2bfa-4f5d-93b8-4ad6c85211a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189340877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.189340877
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1983765091
Short name T408
Test name
Test status
Simulation time 173512674797 ps
CPU time 317.07 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 01:02:21 PM PDT 24
Peak memory 200460 kb
Host smart-61749977-6b92-498e-8a21-55ffbff50d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983765091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1983765091
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3267012684
Short name T1040
Test name
Test status
Simulation time 7331000427 ps
CPU time 12.52 seconds
Started May 14 12:57:01 PM PDT 24
Finished May 14 12:57:16 PM PDT 24
Peak memory 200056 kb
Host smart-662fe2b0-8534-4a33-9a14-660ba1fd0979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267012684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3267012684
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2021696240
Short name T152
Test name
Test status
Simulation time 27424650790 ps
CPU time 17.06 seconds
Started May 14 12:57:02 PM PDT 24
Finished May 14 12:57:22 PM PDT 24
Peak memory 200496 kb
Host smart-40063292-e2f5-45fc-aa03-331cb47aa9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021696240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2021696240
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.91089360
Short name T1141
Test name
Test status
Simulation time 65242350508 ps
CPU time 44.27 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 200036 kb
Host smart-fccf4711-b7a7-40a1-b49d-bd5096e94cab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91089360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.91089360
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1455393992
Short name T248
Test name
Test status
Simulation time 49703650228 ps
CPU time 252.04 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 01:01:28 PM PDT 24
Peak memory 200368 kb
Host smart-3ccc8015-a21b-4593-8a4f-793894593244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455393992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1455393992
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2472002124
Short name T414
Test name
Test status
Simulation time 9814664793 ps
CPU time 18.08 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:33 PM PDT 24
Peak memory 200260 kb
Host smart-125f043a-68f4-437f-8c85-8ec3606fbed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472002124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2472002124
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.268314034
Short name T244
Test name
Test status
Simulation time 23164646523 ps
CPU time 41.3 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:56 PM PDT 24
Peak memory 198736 kb
Host smart-8911022d-e63f-42b5-9aaa-94db74175b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268314034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.268314034
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1566545628
Short name T1078
Test name
Test status
Simulation time 27429060183 ps
CPU time 1254.32 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 01:18:08 PM PDT 24
Peak memory 200468 kb
Host smart-c1709e5e-6b07-40a8-adea-61139fa0045f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566545628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1566545628
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3595727665
Short name T354
Test name
Test status
Simulation time 1287154802 ps
CPU time 1.12 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:16 PM PDT 24
Peak memory 195964 kb
Host smart-6d40ace7-8693-49b2-a457-d8d7ff391324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595727665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3595727665
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1438607956
Short name T833
Test name
Test status
Simulation time 119916641558 ps
CPU time 136.57 seconds
Started May 14 12:57:11 PM PDT 24
Finished May 14 12:59:28 PM PDT 24
Peak memory 200412 kb
Host smart-0a9c0964-c112-4f49-acc6-917bf0c22e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438607956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1438607956
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3944894004
Short name T592
Test name
Test status
Simulation time 34089770641 ps
CPU time 59.4 seconds
Started May 14 12:57:15 PM PDT 24
Finished May 14 12:58:17 PM PDT 24
Peak memory 196484 kb
Host smart-4e097d0e-bf5a-40c1-90de-ccfb6141474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944894004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3944894004
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1322680496
Short name T823
Test name
Test status
Simulation time 5383828421 ps
CPU time 8.88 seconds
Started May 14 12:57:03 PM PDT 24
Finished May 14 12:57:14 PM PDT 24
Peak memory 199736 kb
Host smart-381ae192-f001-47b4-ad84-8b6cb0311d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322680496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1322680496
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3607597704
Short name T828
Test name
Test status
Simulation time 68400949874 ps
CPU time 341.95 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 01:02:55 PM PDT 24
Peak memory 200336 kb
Host smart-ef84d5a9-74b5-4e57-851e-30227e1f2415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607597704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3607597704
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1791179704
Short name T415
Test name
Test status
Simulation time 2724832279 ps
CPU time 2.06 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:57:18 PM PDT 24
Peak memory 199244 kb
Host smart-87301bc1-cc0f-490c-baa7-9d41123cacd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791179704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1791179704
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3873634070
Short name T59
Test name
Test status
Simulation time 47184496136 ps
CPU time 100.76 seconds
Started May 14 12:57:03 PM PDT 24
Finished May 14 12:58:46 PM PDT 24
Peak memory 200508 kb
Host smart-ffa37aff-0176-4d30-9b3c-7f13925a687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873634070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3873634070
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.401474883
Short name T1080
Test name
Test status
Simulation time 163281966919 ps
CPU time 281.7 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:05:08 PM PDT 24
Peak memory 200440 kb
Host smart-bef3e591-f019-4716-8225-b4ee2e316821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401474883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.401474883
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3726401259
Short name T528
Test name
Test status
Simulation time 767868811749 ps
CPU time 516.29 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:09:04 PM PDT 24
Peak memory 217300 kb
Host smart-1f6653b8-625c-403c-862f-d8bb15418ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726401259 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3726401259
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4232694667
Short name T729
Test name
Test status
Simulation time 171635730521 ps
CPU time 292.13 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:05:18 PM PDT 24
Peak memory 200720 kb
Host smart-ddbb9f14-3d68-408d-aca1-584fd0138356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232694667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4232694667
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2970648516
Short name T192
Test name
Test status
Simulation time 92245122599 ps
CPU time 495.88 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:08:43 PM PDT 24
Peak memory 227168 kb
Host smart-ba3f0fb2-f4b0-433c-a128-5eb4fef24a34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970648516 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2970648516
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3876655275
Short name T93
Test name
Test status
Simulation time 136306039313 ps
CPU time 54.31 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:01:21 PM PDT 24
Peak memory 200488 kb
Host smart-23cfb261-d5bb-4da2-a8f4-1de95379ae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876655275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3876655275
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3253608577
Short name T167
Test name
Test status
Simulation time 18910412400 ps
CPU time 44.67 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:01:11 PM PDT 24
Peak memory 200492 kb
Host smart-9a91ccfd-29af-42a1-a7dc-c336419946a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253608577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3253608577
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1050588480
Short name T1075
Test name
Test status
Simulation time 159012009912 ps
CPU time 447.17 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 216912 kb
Host smart-50576f7d-4679-483b-915f-f656227526b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050588480 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1050588480
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2465995126
Short name T728
Test name
Test status
Simulation time 139327080746 ps
CPU time 171.2 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:03:19 PM PDT 24
Peak memory 200472 kb
Host smart-12374549-8c59-4aa9-9b86-a715db8a38a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465995126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2465995126
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2614966675
Short name T713
Test name
Test status
Simulation time 261945091780 ps
CPU time 924.28 seconds
Started May 14 01:00:25 PM PDT 24
Finished May 14 01:15:52 PM PDT 24
Peak memory 225340 kb
Host smart-00a47511-5b86-41a9-a14f-5d8eb201a5ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614966675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2614966675
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.4086753583
Short name T321
Test name
Test status
Simulation time 66102846854 ps
CPU time 108.77 seconds
Started May 14 01:00:24 PM PDT 24
Finished May 14 01:02:15 PM PDT 24
Peak memory 200288 kb
Host smart-96de9fe5-0c80-495a-b5b7-9db29a6ee479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086753583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.4086753583
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1766341305
Short name T578
Test name
Test status
Simulation time 137001022264 ps
CPU time 2222.97 seconds
Started May 14 01:00:29 PM PDT 24
Finished May 14 01:37:34 PM PDT 24
Peak memory 216992 kb
Host smart-fc952dec-07d9-411c-8cda-30ac32766fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766341305 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1766341305
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4182296116
Short name T947
Test name
Test status
Simulation time 60673999407 ps
CPU time 28.87 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:01:06 PM PDT 24
Peak memory 200456 kb
Host smart-7a15bfc7-107f-4c2a-8d1c-bf8b1b8980c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182296116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4182296116
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3451428427
Short name T45
Test name
Test status
Simulation time 125375419003 ps
CPU time 715.74 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:12:32 PM PDT 24
Peak memory 216880 kb
Host smart-87f177de-031c-4605-8582-a686748f9e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451428427 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3451428427
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.481414371
Short name T477
Test name
Test status
Simulation time 17994618980 ps
CPU time 30.82 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:01:08 PM PDT 24
Peak memory 200468 kb
Host smart-5648a05b-6a2c-4812-872e-51770d347eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481414371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.481414371
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2989023233
Short name T1090
Test name
Test status
Simulation time 7731234750 ps
CPU time 76.07 seconds
Started May 14 01:00:35 PM PDT 24
Finished May 14 01:01:55 PM PDT 24
Peak memory 217252 kb
Host smart-4736308a-18b6-4c17-87a3-663edcc689dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989023233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2989023233
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3329801062
Short name T633
Test name
Test status
Simulation time 64234778630 ps
CPU time 32.11 seconds
Started May 14 01:00:35 PM PDT 24
Finished May 14 01:01:10 PM PDT 24
Peak memory 200536 kb
Host smart-bd15732d-8f84-4e1a-bb80-17160198eac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329801062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3329801062
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1883312109
Short name T42
Test name
Test status
Simulation time 80422996872 ps
CPU time 831.01 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 225452 kb
Host smart-536ed598-584f-4c59-9045-18e02a265272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883312109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1883312109
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2495910029
Short name T265
Test name
Test status
Simulation time 133950584884 ps
CPU time 60.5 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:01:38 PM PDT 24
Peak memory 200428 kb
Host smart-4cb39c53-9e9a-48ca-87da-17ed6a790d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495910029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2495910029
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2655942116
Short name T330
Test name
Test status
Simulation time 11230985356 ps
CPU time 128.95 seconds
Started May 14 01:00:32 PM PDT 24
Finished May 14 01:02:44 PM PDT 24
Peak memory 216780 kb
Host smart-9d45619c-a42d-4c3b-ab15-f0f35a5e9ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655942116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2655942116
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2009837751
Short name T368
Test name
Test status
Simulation time 12741742 ps
CPU time 0.58 seconds
Started May 14 12:57:15 PM PDT 24
Finished May 14 12:57:18 PM PDT 24
Peak memory 195844 kb
Host smart-ec9336bd-fee8-44af-bcae-61cc48dc9e16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009837751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2009837751
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4278405324
Short name T456
Test name
Test status
Simulation time 43265824187 ps
CPU time 33.34 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:57:47 PM PDT 24
Peak memory 200468 kb
Host smart-0b26e5d2-bd99-4847-aa8d-4cc6ff7125a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278405324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4278405324
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3681696860
Short name T969
Test name
Test status
Simulation time 49797037221 ps
CPU time 91.3 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:58:45 PM PDT 24
Peak memory 200116 kb
Host smart-321a9618-3cb3-4e62-bc69-f6d726dc4cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681696860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3681696860
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2542478126
Short name T106
Test name
Test status
Simulation time 38135620939 ps
CPU time 18.76 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:57:35 PM PDT 24
Peak memory 200380 kb
Host smart-b24ea39e-9cc1-4b5e-bd96-eae813dd2b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542478126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2542478126
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4209137809
Short name T380
Test name
Test status
Simulation time 221015974046 ps
CPU time 142.71 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:59:35 PM PDT 24
Peak memory 200284 kb
Host smart-a8f12601-fe2b-4126-87e8-c622379ae3d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209137809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4209137809
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2002049293
Short name T881
Test name
Test status
Simulation time 149816290749 ps
CPU time 921.6 seconds
Started May 14 12:57:11 PM PDT 24
Finished May 14 01:12:34 PM PDT 24
Peak memory 200492 kb
Host smart-c21f03c6-a75e-42d8-8ed9-5278c35b3c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002049293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2002049293
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1710202719
Short name T627
Test name
Test status
Simulation time 5172929476 ps
CPU time 4.93 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:20 PM PDT 24
Peak memory 200400 kb
Host smart-da8996de-af32-4d72-887c-b3e58b7ca059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710202719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1710202719
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4024161490
Short name T470
Test name
Test status
Simulation time 269026612793 ps
CPU time 84.87 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:58:38 PM PDT 24
Peak memory 200748 kb
Host smart-15948f68-0dc8-43b5-be66-18a481b85c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024161490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4024161490
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2282055245
Short name T948
Test name
Test status
Simulation time 13907678367 ps
CPU time 360.14 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 01:03:13 PM PDT 24
Peak memory 200404 kb
Host smart-27bdd368-1265-4068-ac59-10ff7f834985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282055245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2282055245
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.158873905
Short name T626
Test name
Test status
Simulation time 1273452905 ps
CPU time 2.7 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 12:57:21 PM PDT 24
Peak memory 198268 kb
Host smart-9069884e-9550-4740-9f19-59b77597f6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158873905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.158873905
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1506957786
Short name T868
Test name
Test status
Simulation time 26383886597 ps
CPU time 46.96 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 200388 kb
Host smart-cc82194d-8543-4ddf-b30f-01fba692a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506957786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1506957786
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.147779694
Short name T500
Test name
Test status
Simulation time 6673313585 ps
CPU time 2.55 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 196536 kb
Host smart-8e8f25e4-765a-4ff9-9dfb-58affe61966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147779694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.147779694
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4096916236
Short name T274
Test name
Test status
Simulation time 622023829 ps
CPU time 3.13 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:18 PM PDT 24
Peak memory 200228 kb
Host smart-9176799b-6d1f-4f39-8cdd-ef560889164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096916236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4096916236
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3580126118
Short name T566
Test name
Test status
Simulation time 18289287411 ps
CPU time 23.36 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:57:39 PM PDT 24
Peak memory 200884 kb
Host smart-ee5a2be2-6199-47c2-ba0a-8ce7ea6a0aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580126118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3580126118
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2656915959
Short name T32
Test name
Test status
Simulation time 34940678500 ps
CPU time 347.08 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 01:03:07 PM PDT 24
Peak memory 216924 kb
Host smart-499299ed-22f1-4b6e-bd22-b576960b50ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656915959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2656915959
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2891002319
Short name T792
Test name
Test status
Simulation time 7335844249 ps
CPU time 16.62 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:57:30 PM PDT 24
Peak memory 200216 kb
Host smart-eeacda37-4e21-4d3a-bd41-6c5cf3c06951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891002319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2891002319
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4150248779
Short name T876
Test name
Test status
Simulation time 11472138809 ps
CPU time 19.81 seconds
Started May 14 12:57:15 PM PDT 24
Finished May 14 12:57:38 PM PDT 24
Peak memory 200420 kb
Host smart-5faa2d0e-5294-4ff2-901b-6e2769ab07c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150248779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4150248779
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1528600567
Short name T214
Test name
Test status
Simulation time 35618791746 ps
CPU time 22.53 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:00:58 PM PDT 24
Peak memory 200400 kb
Host smart-a4e32408-3a90-455c-9894-69e9223e9c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528600567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1528600567
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2576403443
Short name T205
Test name
Test status
Simulation time 24480775885 ps
CPU time 40.09 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:01:17 PM PDT 24
Peak memory 200436 kb
Host smart-882212af-8c92-4876-9e31-d848506bd349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576403443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2576403443
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2581993839
Short name T66
Test name
Test status
Simulation time 65051787548 ps
CPU time 480.64 seconds
Started May 14 01:00:35 PM PDT 24
Finished May 14 01:08:39 PM PDT 24
Peak memory 216992 kb
Host smart-319276b7-b5bc-4668-9aac-af217ed388e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581993839 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2581993839
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4008323374
Short name T1166
Test name
Test status
Simulation time 142554574794 ps
CPU time 60.38 seconds
Started May 14 01:00:35 PM PDT 24
Finished May 14 01:01:38 PM PDT 24
Peak memory 200420 kb
Host smart-004cb3b5-25c7-4bff-ab64-8ff7ffa9d94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008323374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4008323374
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3786129923
Short name T46
Test name
Test status
Simulation time 100219743911 ps
CPU time 801.1 seconds
Started May 14 01:00:35 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 216916 kb
Host smart-da229763-9b0b-4686-8e79-d47c9647cf78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786129923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3786129923
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1042691407
Short name T824
Test name
Test status
Simulation time 43638978889 ps
CPU time 29.79 seconds
Started May 14 01:00:34 PM PDT 24
Finished May 14 01:01:07 PM PDT 24
Peak memory 200496 kb
Host smart-41199f7c-28e7-4e99-b3b1-9e0c68ab72f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042691407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1042691407
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2381674916
Short name T1129
Test name
Test status
Simulation time 51576212548 ps
CPU time 644.36 seconds
Started May 14 01:00:32 PM PDT 24
Finished May 14 01:11:19 PM PDT 24
Peak memory 217148 kb
Host smart-6a436162-f2fe-4f70-af6e-8c2ae41b5643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381674916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2381674916
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.65076072
Short name T862
Test name
Test status
Simulation time 120991400207 ps
CPU time 178.09 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:03:34 PM PDT 24
Peak memory 200400 kb
Host smart-7ed67c91-f591-4165-8878-1c94471f2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65076072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.65076072
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3103579832
Short name T95
Test name
Test status
Simulation time 106792762903 ps
CPU time 944.32 seconds
Started May 14 01:00:37 PM PDT 24
Finished May 14 01:16:24 PM PDT 24
Peak memory 217208 kb
Host smart-6c689e48-ded5-46f1-a64c-6da18a69dfab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103579832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3103579832
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1548439909
Short name T49
Test name
Test status
Simulation time 251656165258 ps
CPU time 561.38 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:09:57 PM PDT 24
Peak memory 227948 kb
Host smart-e3972303-a540-48dc-a656-1760d725ed6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548439909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1548439909
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3294770605
Short name T960
Test name
Test status
Simulation time 83579625127 ps
CPU time 34.04 seconds
Started May 14 01:00:37 PM PDT 24
Finished May 14 01:01:13 PM PDT 24
Peak memory 200476 kb
Host smart-81135469-92ca-4f25-909e-80dc93c3ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294770605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3294770605
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.4072236864
Short name T829
Test name
Test status
Simulation time 60153742793 ps
CPU time 549.68 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:09:45 PM PDT 24
Peak memory 217152 kb
Host smart-944a4c97-328f-44d8-9936-2ef07aa5bd8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072236864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4072236864
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.943136274
Short name T1093
Test name
Test status
Simulation time 93476760729 ps
CPU time 344.91 seconds
Started May 14 01:00:35 PM PDT 24
Finished May 14 01:06:23 PM PDT 24
Peak memory 200460 kb
Host smart-f072d087-45bc-4076-893b-df80cbc25bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943136274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.943136274
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1263341298
Short name T103
Test name
Test status
Simulation time 89130658916 ps
CPU time 395.6 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 216948 kb
Host smart-9fd54dc9-bf68-434d-b9f2-c9868ef01f32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263341298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1263341298
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2061872315
Short name T112
Test name
Test status
Simulation time 32232173816 ps
CPU time 29.77 seconds
Started May 14 01:00:38 PM PDT 24
Finished May 14 01:01:10 PM PDT 24
Peak memory 200376 kb
Host smart-94cfd16b-79b8-4b6c-8329-4a0b85653aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061872315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2061872315
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.739607663
Short name T327
Test name
Test status
Simulation time 120280366817 ps
CPU time 375.05 seconds
Started May 14 01:00:32 PM PDT 24
Finished May 14 01:06:49 PM PDT 24
Peak memory 211184 kb
Host smart-1f22f087-7c9b-48f1-b32e-a4a97dd17cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739607663 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.739607663
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.490887578
Short name T220
Test name
Test status
Simulation time 95733598340 ps
CPU time 77.93 seconds
Started May 14 01:00:33 PM PDT 24
Finished May 14 01:01:54 PM PDT 24
Peak memory 200500 kb
Host smart-e0b361e2-6836-401f-9eec-dfd3b1a85858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490887578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.490887578
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.380059666
Short name T681
Test name
Test status
Simulation time 158404079077 ps
CPU time 571.07 seconds
Started May 14 01:00:42 PM PDT 24
Finished May 14 01:10:15 PM PDT 24
Peak memory 225412 kb
Host smart-cf5e17af-e333-4ddd-a3eb-fa23c2292f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380059666 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.380059666
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.230546689
Short name T997
Test name
Test status
Simulation time 14267541 ps
CPU time 0.56 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:22 PM PDT 24
Peak memory 195828 kb
Host smart-e684f9fd-2a96-4931-b86b-e06f83711e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230546689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.230546689
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.868442771
Short name T1065
Test name
Test status
Simulation time 82096833851 ps
CPU time 41.42 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:57:58 PM PDT 24
Peak memory 200428 kb
Host smart-86c4d2c3-5c68-4444-a9ab-49c03c6405f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868442771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.868442771
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.348712670
Short name T417
Test name
Test status
Simulation time 51630958316 ps
CPU time 69.42 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:58:26 PM PDT 24
Peak memory 200236 kb
Host smart-19be2792-2644-4517-bce0-59038acca70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348712670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.348712670
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4007457730
Short name T572
Test name
Test status
Simulation time 74578085867 ps
CPU time 48.16 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 12:58:06 PM PDT 24
Peak memory 200496 kb
Host smart-6b0f0e16-cb36-47f2-8ead-10b25b4cb753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007457730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4007457730
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.954238257
Short name T1165
Test name
Test status
Simulation time 35687224045 ps
CPU time 14.83 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:29 PM PDT 24
Peak memory 200440 kb
Host smart-d256c197-0fa5-4e5a-93bb-b079afb1b37a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954238257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.954238257
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2136679784
Short name T428
Test name
Test status
Simulation time 51410551411 ps
CPU time 299.27 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 01:02:18 PM PDT 24
Peak memory 200428 kb
Host smart-355fd180-dffb-43fe-8555-a62a273f9ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136679784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2136679784
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.518634965
Short name T1117
Test name
Test status
Simulation time 2856886444 ps
CPU time 2.43 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:23 PM PDT 24
Peak memory 199256 kb
Host smart-55fa9dcb-406d-402c-95e8-7df3cd8e57e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518634965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.518634965
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.560226810
Short name T809
Test name
Test status
Simulation time 16114308953 ps
CPU time 15.04 seconds
Started May 14 12:57:12 PM PDT 24
Finished May 14 12:57:28 PM PDT 24
Peak memory 200700 kb
Host smart-b59ffaf2-4336-4c70-bd82-d558d85d9cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560226810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.560226810
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.430985402
Short name T620
Test name
Test status
Simulation time 12264364088 ps
CPU time 334.23 seconds
Started May 14 12:57:20 PM PDT 24
Finished May 14 01:02:56 PM PDT 24
Peak memory 200460 kb
Host smart-ebf5aadb-ed6d-42fc-a67e-a59afed0d2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430985402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.430985402
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1164575206
Short name T350
Test name
Test status
Simulation time 4573906519 ps
CPU time 6.62 seconds
Started May 14 12:57:13 PM PDT 24
Finished May 14 12:57:22 PM PDT 24
Peak memory 198520 kb
Host smart-9b062653-005a-4ad2-a919-340046e87421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164575206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1164575206
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1816882647
Short name T126
Test name
Test status
Simulation time 48829142569 ps
CPU time 27.88 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 12:57:47 PM PDT 24
Peak memory 200460 kb
Host smart-9583eb03-b890-4c04-80c7-e5319bb38678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816882647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1816882647
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2154133607
Short name T323
Test name
Test status
Simulation time 46554527387 ps
CPU time 17.95 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:57:35 PM PDT 24
Peak memory 196496 kb
Host smart-3967f85b-500d-45a2-9c8b-2d5fefe3b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154133607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2154133607
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3154422622
Short name T381
Test name
Test status
Simulation time 710038411 ps
CPU time 1.8 seconds
Started May 14 12:57:15 PM PDT 24
Finished May 14 12:57:20 PM PDT 24
Peak memory 199140 kb
Host smart-e47aa065-4a1b-4310-9e8f-b8ac292185bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154422622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3154422622
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1992502204
Short name T716
Test name
Test status
Simulation time 162839885712 ps
CPU time 559.67 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 01:06:39 PM PDT 24
Peak memory 200380 kb
Host smart-7bd62922-bbf1-4403-969f-6556b625918e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992502204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1992502204
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3863440038
Short name T668
Test name
Test status
Simulation time 739516514121 ps
CPU time 729.84 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 01:09:30 PM PDT 24
Peak memory 213980 kb
Host smart-a2df29cf-5dd8-4494-8aa7-07dcf184c754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863440038 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3863440038
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1804371192
Short name T775
Test name
Test status
Simulation time 1059340635 ps
CPU time 4.96 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 12:57:24 PM PDT 24
Peak memory 200336 kb
Host smart-4a2c0503-f137-4559-a248-05d4b08c6f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804371192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1804371192
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1942975534
Short name T795
Test name
Test status
Simulation time 30425217063 ps
CPU time 115.97 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 12:59:13 PM PDT 24
Peak memory 200532 kb
Host smart-649d82df-f6da-435e-bcfd-682ef5dd3ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942975534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1942975534
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3462066065
Short name T204
Test name
Test status
Simulation time 19498714006 ps
CPU time 33.01 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:01:20 PM PDT 24
Peak memory 200392 kb
Host smart-8da8e8dc-b83e-4922-b4a5-37075e7dbfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462066065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3462066065
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.34069513
Short name T224
Test name
Test status
Simulation time 452568037007 ps
CPU time 545.83 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:09:53 PM PDT 24
Peak memory 216928 kb
Host smart-cb745241-2db1-429c-a5ae-e8c524720295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069513 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.34069513
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2780919212
Short name T36
Test name
Test status
Simulation time 110054158957 ps
CPU time 51.86 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:01:47 PM PDT 24
Peak memory 200432 kb
Host smart-05c470bc-c63f-4575-b96f-c74b695c0e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780919212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2780919212
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.552812284
Short name T955
Test name
Test status
Simulation time 96500509978 ps
CPU time 885.14 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 216948 kb
Host smart-e5b4a67f-0c84-4ac8-bb4e-98830a927f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552812284 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.552812284
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2530026376
Short name T793
Test name
Test status
Simulation time 32794375287 ps
CPU time 16.45 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:11 PM PDT 24
Peak memory 200412 kb
Host smart-30d2356d-bccf-4fe8-87c3-5f8d827040cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530026376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2530026376
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2321080276
Short name T230
Test name
Test status
Simulation time 18970070432 ps
CPU time 49.31 seconds
Started May 14 01:00:47 PM PDT 24
Finished May 14 01:01:38 PM PDT 24
Peak memory 200472 kb
Host smart-421c0c4b-c71e-4c51-a14f-4212f7ca7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321080276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2321080276
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1907283351
Short name T730
Test name
Test status
Simulation time 41320750469 ps
CPU time 458.73 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:08:34 PM PDT 24
Peak memory 216292 kb
Host smart-02a86840-f28e-4782-befb-f61afd1adfd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907283351 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1907283351
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.216071274
Short name T1051
Test name
Test status
Simulation time 9238222648 ps
CPU time 15.4 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:10 PM PDT 24
Peak memory 200456 kb
Host smart-9e6638ec-fcdb-4e5e-b378-73c98f6ee8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216071274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.216071274
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3083098498
Short name T33
Test name
Test status
Simulation time 355111523784 ps
CPU time 985.22 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:17:13 PM PDT 24
Peak memory 226008 kb
Host smart-35181977-9476-4410-878f-9a636a67b606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083098498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3083098498
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1777757732
Short name T658
Test name
Test status
Simulation time 32887219470 ps
CPU time 16.57 seconds
Started May 14 01:00:46 PM PDT 24
Finished May 14 01:01:06 PM PDT 24
Peak memory 200416 kb
Host smart-244415eb-1755-41f8-a783-ec321e9d9f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777757732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1777757732
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.619608860
Short name T57
Test name
Test status
Simulation time 32921534631 ps
CPU time 572.86 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:10:19 PM PDT 24
Peak memory 216008 kb
Host smart-83f6b79d-eeb8-4538-a2af-37d0efc90ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619608860 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.619608860
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1737234258
Short name T542
Test name
Test status
Simulation time 49924087377 ps
CPU time 42.27 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:01:29 PM PDT 24
Peak memory 200532 kb
Host smart-384ebc6e-0c61-469b-8669-76fbc8ec9add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737234258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1737234258
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.846841739
Short name T458
Test name
Test status
Simulation time 238860174570 ps
CPU time 563.21 seconds
Started May 14 01:00:45 PM PDT 24
Finished May 14 01:10:11 PM PDT 24
Peak memory 228260 kb
Host smart-77753801-a353-4d12-9a4c-0f085df09a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846841739 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.846841739
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3747127946
Short name T132
Test name
Test status
Simulation time 47414994307 ps
CPU time 67.9 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:01:54 PM PDT 24
Peak memory 200460 kb
Host smart-94f255ca-ce54-4419-bc75-eef5617c659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747127946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3747127946
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2075957909
Short name T47
Test name
Test status
Simulation time 136005973076 ps
CPU time 3472.81 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:58:41 PM PDT 24
Peak memory 226204 kb
Host smart-f7554cc2-956b-473d-8606-df4565a857d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075957909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2075957909
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.4237751901
Short name T1139
Test name
Test status
Simulation time 135437530362 ps
CPU time 220.86 seconds
Started May 14 01:00:46 PM PDT 24
Finished May 14 01:04:30 PM PDT 24
Peak memory 200684 kb
Host smart-7f6df887-a48f-49f6-9dc9-618435e8757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237751901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.4237751901
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3157685157
Short name T941
Test name
Test status
Simulation time 82351374359 ps
CPU time 254.28 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:05:00 PM PDT 24
Peak memory 209792 kb
Host smart-a1c7760b-1db3-40be-af57-bb0744295a8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157685157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3157685157
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2023866752
Short name T949
Test name
Test status
Simulation time 36520633406 ps
CPU time 13.96 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:00:58 PM PDT 24
Peak memory 200364 kb
Host smart-6d1b4e68-c91b-4954-86b7-4450dfd85aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023866752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2023866752
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.774040957
Short name T973
Test name
Test status
Simulation time 174692477803 ps
CPU time 1662.39 seconds
Started May 14 01:00:46 PM PDT 24
Finished May 14 01:28:31 PM PDT 24
Peak memory 227304 kb
Host smart-bfbf6991-a9c2-47d7-bf0f-7e62ee1037ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774040957 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.774040957
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2257902823
Short name T998
Test name
Test status
Simulation time 13105896 ps
CPU time 0.61 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 12:57:28 PM PDT 24
Peak memory 195780 kb
Host smart-f4b8c512-57b0-47d6-a342-0213b4501e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257902823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2257902823
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.4270008429
Short name T725
Test name
Test status
Simulation time 55489668716 ps
CPU time 26.13 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:48 PM PDT 24
Peak memory 200420 kb
Host smart-3721d08e-72a4-4212-8772-1f3efc6c93ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270008429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4270008429
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3546960932
Short name T518
Test name
Test status
Simulation time 114731556028 ps
CPU time 202.09 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 01:00:40 PM PDT 24
Peak memory 200396 kb
Host smart-d8f604f5-2a31-4154-b23e-bcc394551eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546960932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3546960932
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2404787257
Short name T965
Test name
Test status
Simulation time 86345043467 ps
CPU time 59.89 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 12:58:27 PM PDT 24
Peak memory 200352 kb
Host smart-65109ee0-f04a-4432-bf42-bb8897c15996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404787257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2404787257
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2010405398
Short name T1058
Test name
Test status
Simulation time 20620328104 ps
CPU time 8.07 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 12:57:28 PM PDT 24
Peak memory 198700 kb
Host smart-255499b4-6ea6-4057-a2b0-5e29addb2418
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010405398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2010405398
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1447332519
Short name T403
Test name
Test status
Simulation time 150014122209 ps
CPU time 190.6 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 01:00:32 PM PDT 24
Peak memory 200432 kb
Host smart-7db0fffb-d887-4622-8f97-93dfc22f9adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447332519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1447332519
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1839055008
Short name T1170
Test name
Test status
Simulation time 6585051903 ps
CPU time 13.41 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 12:57:38 PM PDT 24
Peak memory 200348 kb
Host smart-c4eb680d-3d4b-47d6-bcef-8247936581c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839055008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1839055008
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.13300257
Short name T557
Test name
Test status
Simulation time 10099009885 ps
CPU time 17.13 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:39 PM PDT 24
Peak memory 198276 kb
Host smart-7366abcc-993b-4fa8-9e9d-d832b499ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13300257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.13300257
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1177802671
Short name T791
Test name
Test status
Simulation time 11005396938 ps
CPU time 528.5 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 01:06:09 PM PDT 24
Peak memory 200484 kb
Host smart-08212104-87de-4f3a-b725-88df1efcadbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177802671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1177802671
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2051465080
Short name T331
Test name
Test status
Simulation time 1282260849 ps
CPU time 1.66 seconds
Started May 14 12:57:20 PM PDT 24
Finished May 14 12:57:23 PM PDT 24
Peak memory 196852 kb
Host smart-4340b4f5-5cc4-4aff-b7d8-f6d728784b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051465080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2051465080
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2873103549
Short name T391
Test name
Test status
Simulation time 62667703613 ps
CPU time 91.7 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 12:58:50 PM PDT 24
Peak memory 200396 kb
Host smart-307cd4dc-c399-4763-8ee5-660344ae6a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873103549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2873103549
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3893288149
Short name T790
Test name
Test status
Simulation time 1611730910 ps
CPU time 1.9 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 12:57:21 PM PDT 24
Peak memory 195908 kb
Host smart-913334a7-d031-4764-95ee-a0dabd9312da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893288149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3893288149
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3996202980
Short name T918
Test name
Test status
Simulation time 498026957 ps
CPU time 1.56 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 12:57:20 PM PDT 24
Peak memory 199124 kb
Host smart-39b69206-c163-47eb-8763-983fe2f51483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996202980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3996202980
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.303768639
Short name T172
Test name
Test status
Simulation time 66363142571 ps
CPU time 108.09 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 12:59:09 PM PDT 24
Peak memory 208900 kb
Host smart-b801846c-a467-41c1-861a-224a7e74e511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303768639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.303768639
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.856840390
Short name T961
Test name
Test status
Simulation time 156565062707 ps
CPU time 899.63 seconds
Started May 14 12:57:25 PM PDT 24
Finished May 14 01:12:27 PM PDT 24
Peak memory 225388 kb
Host smart-2066d003-e79c-492e-8819-5244b063a9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856840390 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.856840390
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3384029163
Short name T545
Test name
Test status
Simulation time 1658954736 ps
CPU time 1.85 seconds
Started May 14 12:57:15 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 198940 kb
Host smart-4bfa48ae-d3ac-4a63-bc51-8d2d91fa2b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384029163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3384029163
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2665659926
Short name T502
Test name
Test status
Simulation time 45093646677 ps
CPU time 12.39 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 200160 kb
Host smart-40021e4f-0e72-48e0-b04c-a97f714c7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665659926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2665659926
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.106487398
Short name T1076
Test name
Test status
Simulation time 114590300845 ps
CPU time 45.33 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:39 PM PDT 24
Peak memory 199412 kb
Host smart-1890410e-69ef-4e81-b7e2-5c64b3854b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106487398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.106487398
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.463744348
Short name T835
Test name
Test status
Simulation time 50167018116 ps
CPU time 698.23 seconds
Started May 14 01:00:49 PM PDT 24
Finished May 14 01:12:29 PM PDT 24
Peak memory 212876 kb
Host smart-a698a57b-fbec-4727-8c82-72d62800d42a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463744348 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.463744348
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1148547361
Short name T203
Test name
Test status
Simulation time 136544599596 ps
CPU time 62.08 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:01:49 PM PDT 24
Peak memory 200488 kb
Host smart-3ec1deb7-442d-444e-93ac-ee1d28b02d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148547361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1148547361
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1409363422
Short name T297
Test name
Test status
Simulation time 17405400458 ps
CPU time 31.03 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:01:17 PM PDT 24
Peak memory 200404 kb
Host smart-670d65f4-fdf4-48f9-b54f-b74d6aa4b7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409363422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1409363422
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1806280433
Short name T1176
Test name
Test status
Simulation time 333577237959 ps
CPU time 1365.9 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 225472 kb
Host smart-88a8b621-16b5-43d6-91ea-38bcb868c3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806280433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1806280433
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1685043880
Short name T8
Test name
Test status
Simulation time 140412625470 ps
CPU time 86.32 seconds
Started May 14 01:00:42 PM PDT 24
Finished May 14 01:02:11 PM PDT 24
Peak memory 200228 kb
Host smart-bc7121bb-68d8-4029-b6ed-72929220884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685043880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1685043880
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.287638689
Short name T215
Test name
Test status
Simulation time 78129938829 ps
CPU time 848.78 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 216964 kb
Host smart-79515090-c9ed-426d-bfca-1ff59a60e43a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287638689 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.287638689
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1620245830
Short name T690
Test name
Test status
Simulation time 63564683113 ps
CPU time 92.08 seconds
Started May 14 01:00:42 PM PDT 24
Finished May 14 01:02:16 PM PDT 24
Peak memory 200512 kb
Host smart-81c11e75-b331-49d3-84d4-0e20fe11230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620245830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1620245830
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3852077081
Short name T240
Test name
Test status
Simulation time 117879751362 ps
CPU time 288.24 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:05:33 PM PDT 24
Peak memory 209956 kb
Host smart-84bb5de0-1b76-441d-afa9-edffa0c6619c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852077081 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3852077081
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4036640127
Short name T29
Test name
Test status
Simulation time 46175423986 ps
CPU time 1589.19 seconds
Started May 14 01:00:46 PM PDT 24
Finished May 14 01:27:18 PM PDT 24
Peak memory 217144 kb
Host smart-4d9d8d80-4ea0-43eb-ae4a-0fed0efcc838
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036640127 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4036640127
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1284862035
Short name T1005
Test name
Test status
Simulation time 28674164006 ps
CPU time 48.13 seconds
Started May 14 01:00:45 PM PDT 24
Finished May 14 01:01:36 PM PDT 24
Peak memory 200444 kb
Host smart-f3159599-1b87-4ff2-9cc5-796a9b9dcdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284862035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1284862035
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3227436829
Short name T43
Test name
Test status
Simulation time 398733648724 ps
CPU time 931.77 seconds
Started May 14 01:00:42 PM PDT 24
Finished May 14 01:16:15 PM PDT 24
Peak memory 217200 kb
Host smart-75da5d13-b8a0-4106-b759-8b2b05db23fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227436829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3227436829
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.832096193
Short name T536
Test name
Test status
Simulation time 98712071828 ps
CPU time 19.26 seconds
Started May 14 01:00:47 PM PDT 24
Finished May 14 01:01:08 PM PDT 24
Peak memory 199220 kb
Host smart-f794931d-f62a-4fb8-af31-6d5daa355c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832096193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.832096193
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.34445484
Short name T841
Test name
Test status
Simulation time 84321332582 ps
CPU time 778.04 seconds
Started May 14 01:00:45 PM PDT 24
Finished May 14 01:13:46 PM PDT 24
Peak memory 216952 kb
Host smart-0ff27763-80e7-4f91-a592-2d4d11df6591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34445484 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.34445484
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2150532288
Short name T612
Test name
Test status
Simulation time 121413971470 ps
CPU time 47.82 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:01:35 PM PDT 24
Peak memory 200416 kb
Host smart-87a6a355-9bbf-4f1f-8aab-a860960819ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150532288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2150532288
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.665106720
Short name T484
Test name
Test status
Simulation time 45810942651 ps
CPU time 845.8 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 217208 kb
Host smart-c79b9bcf-335e-4516-bc6d-a15bcb1c9d1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665106720 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.665106720
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2707669217
Short name T100
Test name
Test status
Simulation time 28447201196 ps
CPU time 48.83 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:01:35 PM PDT 24
Peak memory 200368 kb
Host smart-f260a738-b4b3-4d07-9323-a5ae0fd107fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707669217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2707669217
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2341272821
Short name T101
Test name
Test status
Simulation time 30203764625 ps
CPU time 189.39 seconds
Started May 14 01:00:44 PM PDT 24
Finished May 14 01:03:57 PM PDT 24
Peak memory 212784 kb
Host smart-3b5ed1af-b2f3-4c96-97a0-3b5c461ac842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341272821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2341272821
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1038653588
Short name T830
Test name
Test status
Simulation time 31404796 ps
CPU time 0.57 seconds
Started May 14 12:57:20 PM PDT 24
Finished May 14 12:57:23 PM PDT 24
Peak memory 195848 kb
Host smart-8a55f726-b783-4d9e-8613-a12f72c62c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038653588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1038653588
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.191733017
Short name T842
Test name
Test status
Simulation time 12794741387 ps
CPU time 11.79 seconds
Started May 14 12:57:26 PM PDT 24
Finished May 14 12:57:40 PM PDT 24
Peak memory 200340 kb
Host smart-48f29958-3e25-4ace-b210-aa45835b2a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191733017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.191733017
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1743636783
Short name T768
Test name
Test status
Simulation time 41706965204 ps
CPU time 34.63 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 12:57:55 PM PDT 24
Peak memory 200428 kb
Host smart-9a31e40f-3ec8-48be-b115-fdc1b06d55ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743636783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1743636783
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3703872260
Short name T712
Test name
Test status
Simulation time 116477227878 ps
CPU time 415.43 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 01:04:16 PM PDT 24
Peak memory 200484 kb
Host smart-50d9de92-cf78-4519-b152-195642a4b520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703872260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3703872260
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1630999862
Short name T1068
Test name
Test status
Simulation time 8663056859 ps
CPU time 5.53 seconds
Started May 14 12:57:23 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 200476 kb
Host smart-de7105fd-b818-463f-8ed0-1d5a6aeed325
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630999862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1630999862
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2709708579
Short name T671
Test name
Test status
Simulation time 133283948998 ps
CPU time 1051 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 01:14:51 PM PDT 24
Peak memory 200512 kb
Host smart-843ebd71-4610-424d-af87-05b1356f2f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709708579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2709708579
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2548214394
Short name T4
Test name
Test status
Simulation time 5771111830 ps
CPU time 12.68 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:34 PM PDT 24
Peak memory 200072 kb
Host smart-7d33bec0-bbb0-4140-9d08-4575fcb50e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548214394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2548214394
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.374220526
Short name T721
Test name
Test status
Simulation time 24521937265 ps
CPU time 42.15 seconds
Started May 14 12:57:16 PM PDT 24
Finished May 14 12:58:00 PM PDT 24
Peak memory 200684 kb
Host smart-6ad97827-94a3-4167-a69b-39743f96367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374220526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.374220526
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3786208896
Short name T291
Test name
Test status
Simulation time 13517934776 ps
CPU time 59.83 seconds
Started May 14 12:57:20 PM PDT 24
Finished May 14 12:58:22 PM PDT 24
Peak memory 200472 kb
Host smart-a6f1e9fd-99ab-4466-be06-03505e8ff0ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786208896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3786208896
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1560038260
Short name T726
Test name
Test status
Simulation time 2647112398 ps
CPU time 20.03 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 199740 kb
Host smart-ec54bf55-504c-4da6-a77d-1c0a9a8d7ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560038260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1560038260
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1368723196
Short name T1109
Test name
Test status
Simulation time 12057358911 ps
CPU time 5.91 seconds
Started May 14 12:57:19 PM PDT 24
Finished May 14 12:57:27 PM PDT 24
Peak memory 200272 kb
Host smart-6652b9a7-defe-4e87-9c2a-136cc14b1369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368723196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1368723196
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2545326854
Short name T292
Test name
Test status
Simulation time 5013670152 ps
CPU time 2.89 seconds
Started May 14 12:57:18 PM PDT 24
Finished May 14 12:57:23 PM PDT 24
Peak memory 196772 kb
Host smart-db35cbfe-7dfc-4739-9d84-b18e0e3be1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545326854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2545326854
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3093020362
Short name T273
Test name
Test status
Simulation time 6324314405 ps
CPU time 20.94 seconds
Started May 14 12:57:17 PM PDT 24
Finished May 14 12:57:40 PM PDT 24
Peak memory 199844 kb
Host smart-c5dd6533-c2e2-4297-9c38-18cc938ab6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093020362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3093020362
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2899251630
Short name T760
Test name
Test status
Simulation time 29135716112 ps
CPU time 46.99 seconds
Started May 14 12:57:20 PM PDT 24
Finished May 14 12:58:09 PM PDT 24
Peak memory 200472 kb
Host smart-50f6879b-178d-4e1e-b32b-2fa293d540fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899251630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2899251630
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1746036753
Short name T55
Test name
Test status
Simulation time 91645458614 ps
CPU time 1093.54 seconds
Started May 14 12:57:14 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 225900 kb
Host smart-6bd50a22-c19d-447e-bf18-00d375c23b41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746036753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1746036753
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4123705484
Short name T614
Test name
Test status
Simulation time 6646333935 ps
CPU time 16.8 seconds
Started May 14 12:57:22 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 199932 kb
Host smart-44643d27-8fd6-48a3-9ef2-93b10ac8dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123705484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4123705484
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3073086618
Short name T622
Test name
Test status
Simulation time 38875123107 ps
CPU time 17.58 seconds
Started May 14 12:57:20 PM PDT 24
Finished May 14 12:57:40 PM PDT 24
Peak memory 200484 kb
Host smart-22751cd9-047d-4267-a450-9f399981806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073086618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3073086618
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.646344055
Short name T212
Test name
Test status
Simulation time 18806950085 ps
CPU time 56.08 seconds
Started May 14 01:00:43 PM PDT 24
Finished May 14 01:01:42 PM PDT 24
Peak memory 200364 kb
Host smart-7f268a38-7042-4403-81e4-c72f0923576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646344055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.646344055
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.553762499
Short name T1161
Test name
Test status
Simulation time 57452180283 ps
CPU time 98.88 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:02:34 PM PDT 24
Peak memory 200452 kb
Host smart-590b57a6-9e91-486a-a4aa-d83a83ff69de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553762499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.553762499
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1866516786
Short name T54
Test name
Test status
Simulation time 70661908557 ps
CPU time 416.51 seconds
Started May 14 01:00:55 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 214448 kb
Host smart-bd0eb370-1aa9-4fe8-a6ec-6272b31b324e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866516786 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1866516786
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1521388220
Short name T746
Test name
Test status
Simulation time 170538967091 ps
CPU time 178.69 seconds
Started May 14 01:00:50 PM PDT 24
Finished May 14 01:03:50 PM PDT 24
Peak memory 200408 kb
Host smart-1f5bcf13-2f08-41fd-b367-5110aeb702ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521388220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1521388220
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3924271355
Short name T864
Test name
Test status
Simulation time 70146357327 ps
CPU time 473.28 seconds
Started May 14 01:00:53 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 217196 kb
Host smart-17847bc0-c1b3-4a86-912f-fc27b7f08a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924271355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3924271355
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2409703661
Short name T895
Test name
Test status
Simulation time 105448759796 ps
CPU time 102.85 seconds
Started May 14 01:00:54 PM PDT 24
Finished May 14 01:02:41 PM PDT 24
Peak memory 200468 kb
Host smart-f89b264f-afaa-4853-a230-ee372119b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409703661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2409703661
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2963794638
Short name T565
Test name
Test status
Simulation time 75237666808 ps
CPU time 226.54 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:04:43 PM PDT 24
Peak memory 216848 kb
Host smart-fff6812d-a086-414b-84a3-0bcbe419a0bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963794638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2963794638
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3623433197
Short name T794
Test name
Test status
Simulation time 32816559749 ps
CPU time 58.36 seconds
Started May 14 01:00:55 PM PDT 24
Finished May 14 01:01:57 PM PDT 24
Peak memory 200472 kb
Host smart-b42bf2f0-31d8-46b3-93bf-b91fc47cfa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623433197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3623433197
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3249471653
Short name T800
Test name
Test status
Simulation time 159589793748 ps
CPU time 956.29 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:16:51 PM PDT 24
Peak memory 232172 kb
Host smart-be73d901-6015-44ca-b196-4de1f5baf547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249471653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3249471653
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.932311646
Short name T393
Test name
Test status
Simulation time 94462391852 ps
CPU time 39.01 seconds
Started May 14 01:00:54 PM PDT 24
Finished May 14 01:01:38 PM PDT 24
Peak memory 200256 kb
Host smart-d27bd36a-fd93-42d4-8128-f3af9cfa1836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932311646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.932311646
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3990250134
Short name T435
Test name
Test status
Simulation time 33061857479 ps
CPU time 362.2 seconds
Started May 14 01:00:52 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 217076 kb
Host smart-b7fbb533-70f9-4503-9d6d-0ca6c3ae139b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990250134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3990250134
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2272967313
Short name T238
Test name
Test status
Simulation time 18828946707 ps
CPU time 9.37 seconds
Started May 14 01:00:50 PM PDT 24
Finished May 14 01:01:03 PM PDT 24
Peak memory 200528 kb
Host smart-1ae634e0-ad9c-4fda-9c64-05072b6a130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272967313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2272967313
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2620425656
Short name T684
Test name
Test status
Simulation time 74571467319 ps
CPU time 164.72 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:03:47 PM PDT 24
Peak memory 200048 kb
Host smart-35721511-db67-4aa4-a024-cf5df7716b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620425656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2620425656
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.751409716
Short name T194
Test name
Test status
Simulation time 31513658655 ps
CPU time 49.83 seconds
Started May 14 01:00:58 PM PDT 24
Finished May 14 01:01:52 PM PDT 24
Peak memory 200432 kb
Host smart-f06c6d76-964f-4a2d-b965-7ab760fae61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751409716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.751409716
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3629570908
Short name T1145
Test name
Test status
Simulation time 23685235969 ps
CPU time 29.6 seconds
Started May 14 01:00:51 PM PDT 24
Finished May 14 01:01:24 PM PDT 24
Peak memory 200448 kb
Host smart-89b2244d-ed74-4355-afe5-74daedb47f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629570908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3629570908
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1898569057
Short name T64
Test name
Test status
Simulation time 282147203031 ps
CPU time 1297.72 seconds
Started May 14 01:00:49 PM PDT 24
Finished May 14 01:22:28 PM PDT 24
Peak memory 226364 kb
Host smart-c8a62395-eef9-45b9-b0e9-63889be8d8c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898569057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1898569057
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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