Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108833	1			T1	1		T2	25		T3	325
all_values[1]	108833	1			T1	1		T2	25		T3	325
all_values[2]	108833	1			T1	1		T2	25		T3	325
all_values[3]	108833	1			T1	1		T2	25		T3	325
all_values[4]	108833	1			T1	1		T2	25		T3	325
all_values[5]	108833	1			T1	1		T2	25		T3	325
all_values[6]	108833	1			T1	1		T2	25		T3	325
all_values[7]	108833	1			T1	1		T2	25		T3	325

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439264

1

T1

2

T2

126

T3

1161

auto[1]

431400

1

T1

6

T2

74

T3

1439

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814383

1

T1

7

T2

175

T3

2491

auto[1]

56281

1

T1

1

T2

25

T3

109

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33198	1			T3	225		T4	26		T6	15
all_values[0]	auto[0]	auto[1]	22092	1			T3	93		T4	3		T5	3
all_values[0]	auto[1]	auto[0]	31970	1			T2	7		T5	20		T6	63
all_values[0]	auto[1]	auto[1]	21573	1			T1	1		T2	18		T3	7
all_values[1]	auto[0]	auto[0]	54112	1			T2	3		T3	1		T5	1
all_values[1]	auto[0]	auto[1]	1470	1			T7	1		T35	1		T112	20
all_values[1]	auto[1]	auto[0]	51113	1			T1	1		T2	21		T3	316
all_values[1]	auto[1]	auto[1]	2138	1			T2	1		T3	8		T4	10
all_values[2]	auto[0]	auto[0]	54866	1			T1	1		T2	18		T3	324
all_values[2]	auto[0]	auto[1]	2805	1			T2	4		T3	1		T5	1
all_values[2]	auto[1]	auto[0]	48541	1			T2	1		T4	1		T5	14
all_values[2]	auto[1]	auto[1]	2621	1			T2	2		T4	2		T5	5
all_values[3]	auto[0]	auto[0]	50612	1			T2	25		T3	167		T4	3
all_values[3]	auto[0]	auto[1]	354	1			T15	2		T13	2		T22	2
all_values[3]	auto[1]	auto[0]	57499	1			T1	1		T3	158		T4	26
all_values[3]	auto[1]	auto[1]	368	1			T12	2		T15	4		T16	3
all_values[4]	auto[0]	auto[0]	52249	1			T2	18		T3	8		T4	29
all_values[4]	auto[0]	auto[1]	493	1			T15	3		T16	4		T14	8
all_values[4]	auto[1]	auto[0]	55459	1			T1	1		T2	7		T3	317
all_values[4]	auto[1]	auto[1]	632	1			T15	8		T13	10		T16	3
all_values[5]	auto[0]	auto[0]	56673	1			T1	1		T2	15		T3	1
all_values[5]	auto[0]	auto[1]	192	1			T15	6		T16	1		T19	1
all_values[5]	auto[1]	auto[0]	51734	1			T2	10		T3	324		T5	11
all_values[5]	auto[1]	auto[1]	234	1			T15	1		T16	2		T22	3
all_values[6]	auto[0]	auto[0]	56142	1			T2	18		T3	167		T4	3
all_values[6]	auto[0]	auto[1]	227	1			T15	2		T16	2		T19	2
all_values[6]	auto[1]	auto[0]	52247	1			T1	1		T2	7		T3	158
all_values[6]	auto[1]	auto[1]	217	1			T15	1		T16	4		T22	2
all_values[7]	auto[0]	auto[0]	53302	1			T2	25		T3	174		T4	29
all_values[7]	auto[0]	auto[1]	477	1			T15	2		T16	1		T22	4
all_values[7]	auto[1]	auto[0]	54666	1			T1	1		T3	151		T5	9
all_values[7]	auto[1]	auto[1]	388	1			T15	4		T16	1		T14	4