Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2605

1

T1

1

T2

1

T3

6

auto[UartRx]

2605

1

T1

1

T2

1

T3

6

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4607	1			T1	2		T2	2		T3	8
values[1]	45	1			T3	1		T15	1		T22	1
values[2]	44	1			T15	1		T22	1		T19	1
values[3]	59	1			T15	1		T19	1		T20	1
values[4]	50	1			T6	1		T15	1		T19	1
values[5]	64	1			T15	2		T19	2		T31	1
values[6]	70	1			T3	2		T15	1		T22	1
values[7]	57	1			T6	3		T22	1		T19	1
values[8]	47	1			T6	2		T22	2		T19	1
values[9]	74	1			T3	1		T6	2		T15	1
values[10]	55	1			T15	2		T22	1		T31	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2397	1			T1	1		T2	1		T3	5
auto[UartTx]	values[1]	19	1			T33	1		T41	1		T42	1
auto[UartTx]	values[2]	18	1			T15	1		T20	1		T34	1
auto[UartTx]	values[3]	22	1			T19	1		T123	2		T306	1
auto[UartTx]	values[4]	16	1			T15	1		T20	3		T32	1
auto[UartTx]	values[5]	23	1			T19	1		T31	1		T33	2
auto[UartTx]	values[6]	23	1			T3	1		T19	1		T99	1
auto[UartTx]	values[7]	15	1			T6	1		T33	1		T197	1
auto[UartTx]	values[8]	21	1			T22	1		T156	2		T41	1
auto[UartTx]	values[9]	23	1			T6	2		T19	1		T123	1
auto[UartTx]	values[10]	18	1			T123	1		T197	1		T40	2
auto[UartRx]	values[0]	2210	1			T1	1		T2	1		T3	3
auto[UartRx]	values[1]	26	1			T3	1		T15	1		T22	1
auto[UartRx]	values[2]	26	1			T22	1		T19	1		T31	1
auto[UartRx]	values[3]	37	1			T15	1		T20	1		T32	1
auto[UartRx]	values[4]	34	1			T6	1		T19	1		T31	1
auto[UartRx]	values[5]	41	1			T15	2		T19	1		T123	1
auto[UartRx]	values[6]	47	1			T3	1		T15	1		T22	1
auto[UartRx]	values[7]	42	1			T6	2		T22	1		T19	1
auto[UartRx]	values[8]	26	1			T6	2		T22	1		T19	1
auto[UartRx]	values[9]	51	1			T3	1		T15	1		T22	1
auto[UartRx]	values[10]	37	1			T15	2		T22	1		T31	1