Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2301	1			T1	4		T2	2		T3	2
auto[BaudRate115200]	2093	1			T2	1		T3	2		T4	1
auto[BaudRate230400]	2115	1			T3	2		T5	3		T6	6
auto[BaudRate128Kbps]	2045	1			T4	2		T5	2		T6	3
auto[BaudRate256Kbps]	2261	1			T2	2		T3	1		T4	1
auto[BaudRate1Mbps]	2009	1			T2	1		T4	1		T5	3
auto[BaudRate1p5Mbps]	1273	1			T6	7		T8	4		T9	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1646	1			T2	6		T4	6		T10	2
freqs[25]	1097	1			T14	4		T115	7		T129	8
freqs[48]	600	1			T12	5		T18	2		T113	6
freqs[50]	624	1			T275	5		T126	5		T118	4
freqs[100]	1154	1			T17	15		T195	5		T102	60

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	264	1			T2	2		T4	1		T257	2
auto[BaudRate9600]	freqs[25]	143	1			T129	1		T254	1		T33	13
auto[BaudRate9600]	freqs[48]	113	1			T12	1		T153	2		T293	1
auto[BaudRate9600]	freqs[50]	75	1			T137	2		T276	2		T154	4
auto[BaudRate9600]	freqs[100]	183	1			T17	15		T102	9		T105	3
auto[BaudRate115200]	freqs[24]	268	1			T2	1		T4	1		T10	1
auto[BaudRate115200]	freqs[25]	150	1			T129	2		T254	1		T33	15
auto[BaudRate115200]	freqs[48]	74	1			T12	2		T153	1		T313	1
auto[BaudRate115200]	freqs[50]	94	1			T275	1		T126	1		T118	1
auto[BaudRate115200]	freqs[100]	185	1			T102	6		T105	2		T127	5
auto[BaudRate230400]	freqs[24]	235	1			T257	3		T101	1		T141	2
auto[BaudRate230400]	freqs[25]	178	1			T14	1		T115	2		T129	1
auto[BaudRate230400]	freqs[48]	75	1			T12	1		T153	2		T313	1
auto[BaudRate230400]	freqs[50]	84	1			T275	1		T126	2		T118	1
auto[BaudRate230400]	freqs[100]	139	1			T195	1		T102	6		T127	2
auto[BaudRate128Kbps]	freqs[24]	233	1			T4	2		T10	1		T257	3
auto[BaudRate128Kbps]	freqs[25]	177	1			T14	3		T129	3		T254	1
auto[BaudRate128Kbps]	freqs[48]	85	1			T113	4		T153	1		T293	1
auto[BaudRate128Kbps]	freqs[50]	87	1			T118	2		T276	1		T154	2
auto[BaudRate128Kbps]	freqs[100]	142	1			T195	1		T102	9		T105	1
auto[BaudRate256Kbps]	freqs[24]	263	1			T2	2		T4	1		T257	5
auto[BaudRate256Kbps]	freqs[25]	163	1			T115	1		T33	21		T318	4
auto[BaudRate256Kbps]	freqs[48]	101	1			T18	1		T113	1		T153	2
auto[BaudRate256Kbps]	freqs[50]	91	1			T126	1		T137	1		T134	1
auto[BaudRate256Kbps]	freqs[100]	180	1			T195	2		T102	9		T127	6
auto[BaudRate1Mbps]	freqs[24]	274	1			T2	1		T4	1		T101	1
auto[BaudRate1Mbps]	freqs[25]	178	1			T115	3		T254	1		T33	17
auto[BaudRate1Mbps]	freqs[48]	78	1			T18	1		T153	1		T293	4
auto[BaudRate1Mbps]	freqs[50]	103	1			T275	1		T126	1		T137	3
auto[BaudRate1Mbps]	freqs[100]	170	1			T195	1		T102	15		T105	1
auto[BaudRate1p5Mbps]	freqs[25]	108	1			T115	1		T129	1		T33	14
auto[BaudRate1p5Mbps]	freqs[48]	74	1			T12	1		T113	1		T319	1
auto[BaudRate1p5Mbps]	freqs[50]	90	1			T275	2		T137	1		T134	1
auto[BaudRate1p5Mbps]	freqs[100]	155	1			T102	6		T127	2		T130	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded