Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29065154	1			T1	1		T2	87		T3	168066
all_levels[1]	202395	1			T2	4		T3	59		T4	9
all_levels[2]	2596	1			T2	3		T4	8		T5	2
all_levels[3]	1106	1			T2	2		T4	6		T5	3
all_levels[4]	760	1			T2	1		T4	6		T5	2
all_levels[5]	573	1			T4	7		T6	1		T7	1
all_levels[6]	442	1			T2	1		T4	1		T5	3
all_levels[7]	377	1			T4	2		T8	1		T112	1
all_levels[8]	270	1			T4	1		T7	2		T8	2
all_levels[9]	245	1			T4	1		T7	1		T8	2
all_levels[10]	207	1			T5	1		T6	1		T8	1
all_levels[11]	178	1			T2	1		T4	3		T7	1
all_levels[12]	187	1			T7	2		T124	2		T16	1
all_levels[13]	138	1			T39	3		T112	1		T114	2
all_levels[14]	126	1			T35	3		T39	1		T114	1
all_levels[15]	116	1			T4	1		T6	1		T19	1
all_levels[16]	102	1			T4	1		T112	1		T19	1
all_levels[17]	91	1			T112	1		T114	1		T125	1
all_levels[18]	89	1			T39	1		T126	1		T127	1
all_levels[19]	57	1			T114	1		T126	1		T19	1
all_levels[20]	78	1			T7	1		T128	1		T19	1
all_levels[21]	83	1			T124	1		T128	2		T129	1
all_levels[22]	60	1			T39	1		T125	1		T19	1
all_levels[23]	49	1			T4	4		T130	1		T33	1
all_levels[24]	44	1			T114	1		T116	1		T131	1
all_levels[25]	38	1			T2	1		T35	1		T132	1
all_levels[26]	50	1			T7	2		T61	1		T42	1
all_levels[27]	48	1			T7	1		T127	2		T133	3
all_levels[28]	46	1			T128	1		T127	2		T134	1
all_levels[29]	49	1			T132	1		T19	1		T135	1
all_levels[30]	27	1			T114	1		T136	1		T123	1
all_levels[31]	34	1			T22	1		T137	1		T40	1
all_levels[32]	31	1			T117	2		T20	1		T137	1
all_levels[33]	19	1			T128	1		T101	1		T134	1
all_levels[34]	20	1			T137	2		T33	2		T63	1
all_levels[35]	30	1			T7	1		T125	1		T127	1
all_levels[36]	28	1			T114	1		T138	1		T61	1
all_levels[37]	20	1			T33	1		T139	2		T89	1
all_levels[38]	21	1			T113	1		T140	1		T141	2
all_levels[39]	13	1			T2	1		T12	1		T142	1
all_levels[40]	14	1			T94	1		T98	1		T143	1
all_levels[41]	21	1			T33	1		T144	1		T145	1
all_levels[42]	22	1			T142	3		T93	1		T146	1
all_levels[43]	16	1			T147	1		T148	2		T149	1
all_levels[44]	27	1			T20	1		T135	1		T87	3
all_levels[45]	19	1			T147	1		T150	1		T151	1
all_levels[46]	20	1			T126	3		T136	1		T152	1
all_levels[47]	13	1			T153	1		T154	1		T155	1
all_levels[48]	13	1			T156	1		T148	1		T157	1
all_levels[49]	7	1			T148	1		T158	1		T159	1
all_levels[50]	5	1			T160	1		T161	1		T162	1
all_levels[51]	7	1			T12	1		T139	1		T163	1
all_levels[52]	12	1			T116	1		T164	1		T165	1
all_levels[53]	4	1			T166	1		T167	1		T168	1
all_levels[54]	11	1			T137	1		T169	3		T170	1
all_levels[55]	7	1			T171	2		T164	1		T145	1
all_levels[56]	7	1			T12	1		T135	1		T33	1
all_levels[57]	8	1			T137	1		T172	1		T173	1
all_levels[58]	8	1			T137	1		T156	1		T174	1
all_levels[59]	8	1			T175	1		T176	1		T177	1
all_levels[60]	13	1			T175	2		T176	1		T178	1
all_levels[61]	5	1			T179	1		T180	1		T181	1
all_levels[62]	4	1			T182	1		T163	1		T47	1
all_levels[63]	8	1			T175	2		T183	1		T184	1
all_levels[64]	100	1			T12	1		T22	1		T113	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29271517

1

T2

101

T3

168124

T4

66

auto[1]

4859

1

T1

1

T3

1

T4

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[19]]	[auto[1]]	0	1	1
[all_levels[24]]	[auto[1]]	0	1	1
[all_levels[31]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53]]	[auto[1]]	--	--	4
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29060721	1			T2	87		T3	168065		T4	19
all_levels[0]	auto[1]	4433	1			T1	1		T3	1		T4	1
all_levels[1]	auto[0]	202314	1			T2	4		T3	59		T4	9
all_levels[1]	auto[1]	81	1			T35	1		T185	1		T16	1
all_levels[2]	auto[0]	2562	1			T2	3		T4	8		T5	2
all_levels[2]	auto[1]	34	1			T36	3		T12	1		T155	3
all_levels[3]	auto[0]	1083	1			T2	2		T4	6		T5	3
all_levels[3]	auto[1]	23	1			T186	2		T187	1		T188	1
all_levels[4]	auto[0]	749	1			T2	1		T4	6		T5	2
all_levels[4]	auto[1]	11	1			T151	1		T189	3		T190	3
all_levels[5]	auto[0]	555	1			T4	7		T6	1		T7	1
all_levels[5]	auto[1]	18	1			T191	1		T192	1		T193	2
all_levels[6]	auto[0]	422	1			T2	1		T4	1		T5	3
all_levels[6]	auto[1]	20	1			T194	2		T195	4		T196	1
all_levels[7]	auto[0]	363	1			T4	2		T8	1		T112	1
all_levels[7]	auto[1]	14	1			T195	1		T197	1		T95	1
all_levels[8]	auto[0]	263	1			T4	1		T7	1		T8	2
all_levels[8]	auto[1]	7	1			T7	1		T198	3		T199	2
all_levels[9]	auto[0]	234	1			T4	1		T7	1		T8	2
all_levels[9]	auto[1]	11	1			T15	1		T157	2		T111	1
all_levels[10]	auto[0]	199	1			T5	1		T6	1		T8	1
all_levels[10]	auto[1]	8	1			T200	1		T201	2		T202	3
all_levels[11]	auto[0]	169	1			T2	1		T4	3		T7	1
all_levels[11]	auto[1]	9	1			T132	1		T150	2		T203	1
all_levels[12]	auto[0]	166	1			T7	1		T124	2		T16	1
all_levels[12]	auto[1]	21	1			T7	1		T134	1		T141	1
all_levels[13]	auto[0]	128	1			T39	3		T112	1		T114	2
all_levels[13]	auto[1]	10	1			T148	1		T204	1		T205	2
all_levels[14]	auto[0]	117	1			T35	1		T39	1		T114	1
all_levels[14]	auto[1]	9	1			T35	2		T129	1		T206	1
all_levels[15]	auto[0]	104	1			T4	1		T6	1		T19	1
all_levels[15]	auto[1]	12	1			T207	1		T208	1		T209	1
all_levels[16]	auto[0]	93	1			T4	1		T112	1		T19	1
all_levels[16]	auto[1]	9	1			T210	1		T87	1		T211	1
all_levels[17]	auto[0]	82	1			T112	1		T114	1		T125	1
all_levels[17]	auto[1]	9	1			T212	1		T213	3		T214	1
all_levels[18]	auto[0]	80	1			T39	1		T126	1		T127	1
all_levels[18]	auto[1]	9	1			T176	1		T98	2		T215	2
all_levels[19]	auto[0]	57	1			T114	1		T126	1		T19	1
all_levels[20]	auto[0]	73	1			T7	1		T128	1		T19	1
all_levels[20]	auto[1]	5	1			T216	1		T217	1		T218	1
all_levels[21]	auto[0]	77	1			T124	1		T128	1		T129	1
all_levels[21]	auto[1]	6	1			T128	1		T134	1		T219	2
all_levels[22]	auto[0]	56	1			T39	1		T125	1		T19	1
all_levels[22]	auto[1]	4	1			T220	1		T163	1		T143	2
all_levels[23]	auto[0]	44	1			T4	1		T130	1		T33	1
all_levels[23]	auto[1]	5	1			T4	3		T221	1		T222	1
all_levels[24]	auto[0]	44	1			T114	1		T116	1		T131	1
all_levels[25]	auto[0]	35	1			T2	1		T35	1		T132	1
all_levels[25]	auto[1]	3	1			T112	1		T223	2		-	-
all_levels[26]	auto[0]	45	1			T7	2		T61	1		T42	1
all_levels[26]	auto[1]	5	1			T224	1		T225	2		T226	1
all_levels[27]	auto[0]	42	1			T7	1		T127	2		T133	1
all_levels[27]	auto[1]	6	1			T133	2		T227	4		-	-
all_levels[28]	auto[0]	43	1			T128	1		T127	2		T134	1
all_levels[28]	auto[1]	3	1			T174	1		T228	1		T229	1
all_levels[29]	auto[0]	43	1			T132	1		T19	1		T135	1
all_levels[29]	auto[1]	6	1			T149	3		T43	2		T44	1
all_levels[30]	auto[0]	25	1			T114	1		T136	1		T123	1
all_levels[30]	auto[1]	2	1			T230	1		T170	1		-	-
all_levels[31]	auto[0]	34	1			T22	1		T137	1		T40	1
all_levels[32]	auto[0]	30	1			T117	1		T20	1		T137	1
all_levels[32]	auto[1]	1	1			T117	1		-	-		-	-
all_levels[33]	auto[0]	18	1			T128	1		T101	1		T134	1
all_levels[33]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[34]	auto[0]	19	1			T137	2		T33	2		T63	1
all_levels[34]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[35]	auto[0]	28	1			T7	1		T125	1		T127	1
all_levels[35]	auto[1]	2	1			T233	2		-	-		-	-
all_levels[36]	auto[0]	23	1			T114	1		T138	1		T61	1
all_levels[36]	auto[1]	5	1			T182	1		T234	2		T235	1
all_levels[37]	auto[0]	19	1			T33	1		T139	2		T89	1
all_levels[37]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[38]	auto[0]	15	1			T113	1		T140	1		T141	1
all_levels[38]	auto[1]	6	1			T141	1		T236	4		T237	1
all_levels[39]	auto[0]	13	1			T2	1		T12	1		T142	1
all_levels[40]	auto[0]	12	1			T94	1		T98	1		T143	1
all_levels[40]	auto[1]	2	1			T238	2		-	-		-	-
all_levels[41]	auto[0]	19	1			T33	1		T144	1		T145	1
all_levels[41]	auto[1]	2	1			T239	1		T240	1		-	-
all_levels[42]	auto[0]	17	1			T142	1		T93	1		T146	1
all_levels[42]	auto[1]	5	1			T142	2		T241	1		T242	1
all_levels[43]	auto[0]	15	1			T147	1		T148	2		T149	1
all_levels[43]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[44]	auto[0]	20	1			T20	1		T135	1		T87	1
all_levels[44]	auto[1]	7	1			T87	2		T244	1		T218	1
all_levels[45]	auto[0]	18	1			T147	1		T150	1		T151	1
all_levels[45]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[46]	auto[0]	14	1			T126	2		T136	1		T152	1
all_levels[46]	auto[1]	6	1			T126	1		T246	1		T218	2
all_levels[47]	auto[0]	10	1			T153	1		T154	1		T155	1
all_levels[47]	auto[1]	3	1			T247	3		-	-		-	-
all_levels[48]	auto[0]	11	1			T156	1		T148	1		T157	1
all_levels[48]	auto[1]	2	1			T164	1		T248	1		-	-
all_levels[49]	auto[0]	6	1			T148	1		T158	1		T159	1
all_levels[49]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[50]	auto[0]	5	1			T160	1		T161	1		T162	1
all_levels[51]	auto[0]	7	1			T12	1		T139	1		T163	1
all_levels[52]	auto[0]	12	1			T116	1		T164	1		T165	1
all_levels[53]	auto[0]	4	1			T166	1		T167	1		T168	1
all_levels[54]	auto[0]	9	1			T137	1		T169	2		T170	1
all_levels[54]	auto[1]	2	1			T169	1		T250	1		-	-
all_levels[55]	auto[0]	6	1			T171	1		T164	1		T145	1
all_levels[55]	auto[1]	1	1			T171	1		-	-		-	-
all_levels[56]	auto[0]	7	1			T12	1		T135	1		T33	1
all_levels[57]	auto[0]	7	1			T137	1		T172	1		T173	1
all_levels[57]	auto[1]	1	1			T181	1		-	-		-	-
all_levels[58]	auto[0]	8	1			T137	1		T156	1		T174	1
all_levels[59]	auto[0]	6	1			T175	1		T176	1		T177	1
all_levels[59]	auto[1]	2	1			T230	1		T251	1		-	-
all_levels[60]	auto[0]	11	1			T175	1		T176	1		T178	1
all_levels[60]	auto[1]	2	1			T175	1		T252	1		-	-
all_levels[61]	auto[0]	5	1			T179	1		T180	1		T181	1
all_levels[62]	auto[0]	4	1			T182	1		T163	1		T47	1
all_levels[63]	auto[0]	7	1			T175	1		T183	1		T184	1
all_levels[63]	auto[1]	1	1			T175	1		-	-		-	-
all_levels[64]	auto[0]	90	1			T12	1		T22	1		T113	1
all_levels[64]	auto[1]	10	1			T142	1		T98	2		T253	1