Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1570 1 T3 5 T35 1 T112 17
all_levels[1] 668 1 T2 1 T3 3 T7 1
all_levels[2] 507 1 T4 10 T6 2 T35 4
all_levels[3] 389 1 T13 13 T14 11 T113 8
all_levels[4] 219 1 T114 1 T115 2 T116 7
all_levels[5] 143 1 T117 19 T21 8 T32 6
all_levels[6] 92 1 T13 2 T118 4 T119 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%