Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	108833	1			T1	1		T2	25		T3	325
all_pins[1]	108833	1			T1	1		T2	25		T3	325
all_pins[2]	108833	1			T1	1		T2	25		T3	325
all_pins[3]	108833	1			T1	1		T2	25		T3	325
all_pins[4]	108833	1			T1	1		T2	25		T3	325
all_pins[5]	108833	1			T1	1		T2	25		T3	325
all_pins[6]	108833	1			T1	1		T2	25		T3	325
all_pins[7]	108833	1			T1	1		T2	25		T3	325

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	841646	1			T1	7		T2	179		T3	2583
values[0x1]	29018	1			T1	1		T2	21		T3	17
transitions[0x0=>0x1]	27612	1			T1	1		T2	21		T3	14
transitions[0x1=>0x0]	27188	1			T2	20		T3	14		T4	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87190	1			T2	7		T3	318		T4	29
all_pins[0]	values[0x1]	21643	1			T1	1		T2	18		T3	7
all_pins[0]	transitions[0x0=>0x1]	20963	1			T1	1		T2	18		T3	4
all_pins[0]	transitions[0x1=>0x0]	1451	1			T2	1		T3	5		T4	10
all_pins[1]	values[0x0]	106702	1			T1	1		T2	24		T3	317
all_pins[1]	values[0x1]	2131	1			T2	1		T3	8		T4	10
all_pins[1]	transitions[0x0=>0x1]	1995	1			T2	1		T3	8		T4	10
all_pins[1]	transitions[0x1=>0x0]	2556	1			T2	2		T4	2		T5	5
all_pins[2]	values[0x0]	106141	1			T1	1		T2	23		T3	325
all_pins[2]	values[0x1]	2692	1			T2	2		T4	2		T5	5
all_pins[2]	transitions[0x0=>0x1]	2598	1			T2	2		T4	2		T5	5
all_pins[2]	transitions[0x1=>0x0]	273	1			T12	2		T15	1		T16	2
all_pins[3]	values[0x0]	108466	1			T1	1		T2	25		T3	325
all_pins[3]	values[0x1]	367	1			T12	2		T15	4		T16	3
all_pins[3]	transitions[0x0=>0x1]	294	1			T12	2		T15	1		T16	2
all_pins[3]	transitions[0x1=>0x0]	559	1			T15	5		T13	10		T16	2
all_pins[4]	values[0x0]	108201	1			T1	1		T2	25		T3	325
all_pins[4]	values[0x1]	632	1			T15	8		T13	10		T16	3
all_pins[4]	transitions[0x0=>0x1]	526	1			T15	8		T13	8		T16	2
all_pins[4]	transitions[0x1=>0x0]	199	1			T15	1		T16	1		T14	2
all_pins[5]	values[0x0]	108528	1			T1	1		T2	25		T3	325
all_pins[5]	values[0x1]	305	1			T15	1		T13	2		T16	2
all_pins[5]	transitions[0x0=>0x1]	241	1			T15	1		T13	2		T16	2
all_pins[5]	transitions[0x1=>0x0]	796	1			T3	2		T9	1		T11	1
all_pins[6]	values[0x0]	107973	1			T1	1		T2	25		T3	323
all_pins[6]	values[0x1]	860	1			T3	2		T9	1		T11	1
all_pins[6]	transitions[0x0=>0x1]	794	1			T3	2		T9	1		T11	1
all_pins[6]	transitions[0x1=>0x0]	322	1			T15	3		T16	1		T14	4
all_pins[7]	values[0x0]	108445	1			T1	1		T2	25		T3	325
all_pins[7]	values[0x1]	388	1			T15	4		T16	1		T14	4
all_pins[7]	transitions[0x0=>0x1]	201	1			T15	2		T14	3		T31	1
all_pins[7]	transitions[0x1=>0x0]	21032	1			T2	17		T3	7		T5	6