Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6678941	1			T1	1		T2	36		T3	41043
all_levels[1]	1607016	1			T2	2		T3	2085		T5	3
all_levels[2]	302750	1			T3	1425		T5	2		T6	1092
all_levels[3]	308356	1			T3	2081		T5	2		T6	717
all_levels[4]	368640	1			T3	2085		T5	3		T6	523
all_levels[5]	211546	1			T3	1549		T5	67		T6	800
all_levels[6]	266138	1			T2	3		T3	2086		T5	6
all_levels[7]	290459	1			T3	1781		T4	3		T5	11
all_levels[8]	203441	1			T2	1		T3	1587		T5	3
all_levels[9]	270062	1			T2	2		T3	1849		T5	6
all_levels[10]	359301	1			T2	13		T3	1665		T4	4
all_levels[11]	476106	1			T2	1		T3	2085		T5	7
all_levels[12]	369677	1			T2	1		T3	1487		T5	6
all_levels[13]	170338	1			T2	4		T3	2006		T5	42
all_levels[14]	159393	1			T3	1428		T6	1045		T8	22
all_levels[15]	179521	1			T2	1		T3	1881		T6	685
all_levels[16]	174764	1			T3	1573		T5	3		T6	645
all_levels[17]	217909	1			T2	2		T3	1943		T6	1068
all_levels[18]	186922	1			T2	1		T3	1850		T4	1
all_levels[19]	169614	1			T2	2		T3	2083		T6	547
all_levels[20]	564919	1			T2	3		T3	1301		T6	1068
all_levels[21]	196526	1			T2	3		T3	2080		T6	1069
all_levels[22]	157075	1			T2	4		T3	2083		T6	1064
all_levels[23]	289728	1			T2	2		T3	1648		T6	710
all_levels[24]	144139	1			T2	2		T3	1386		T6	772
all_levels[25]	276094	1			T2	1		T3	2084		T6	1063
all_levels[26]	163272	1			T2	3		T3	1974		T6	1490
all_levels[27]	193665	1			T2	2		T3	1409		T5	3
all_levels[28]	342694	1			T2	4		T3	78588		T5	21
all_levels[29]	283228	1			T2	2		T6	7038		T7	1
all_levels[30]	141931	1			T2	2		T7	8		T11	2
all_levels[31]	695281	1			T2	1		T7	1		T9	1
all_levels[32]	12856488	1			T2	3		T4	61		T6	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29271517

1

T2

101

T3

168124

T4

66

auto[1]

4417

1

T1

1

T3

1

T4

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6676476	1			T2	36		T3	41042		T4	2
all_levels[0]	auto[1]	2465	1			T1	1		T3	1		T4	2
all_levels[1]	auto[0]	1606664	1			T2	2		T3	2085		T5	3
all_levels[1]	auto[1]	352	1			T112	1		T12	1		T101	1
all_levels[2]	auto[0]	302717	1			T3	1425		T5	2		T6	1092
all_levels[2]	auto[1]	33	1			T35	2		T318	1		T151	1
all_levels[3]	auto[0]	308169	1			T3	2081		T5	2		T6	717
all_levels[3]	auto[1]	187	1			T117	1		T13	22		T118	11
all_levels[4]	auto[0]	368612	1			T3	2085		T5	3		T6	523
all_levels[4]	auto[1]	28	1			T101	2		T276	2		T95	1
all_levels[5]	auto[0]	211528	1			T3	1549		T5	67		T6	800
all_levels[5]	auto[1]	18	1			T294	4		T321	1		T221	3
all_levels[6]	auto[0]	266117	1			T2	3		T3	2086		T5	6
all_levels[6]	auto[1]	21	1			T7	1		T195	2		T104	1
all_levels[7]	auto[0]	290347	1			T3	1781		T4	2		T5	11
all_levels[7]	auto[1]	112	1			T4	1		T22	4		T262	8
all_levels[8]	auto[0]	203406	1			T2	1		T3	1587		T5	3
all_levels[8]	auto[1]	35	1			T126	1		T107	2		T191	1
all_levels[9]	auto[0]	270034	1			T2	2		T3	1849		T5	6
all_levels[9]	auto[1]	28	1			T194	3		T128	1		T276	2
all_levels[10]	auto[0]	359270	1			T2	13		T3	1665		T4	1
all_levels[10]	auto[1]	31	1			T4	3		T5	1		T35	3
all_levels[11]	auto[0]	476074	1			T2	1		T3	2085		T5	7
all_levels[11]	auto[1]	32	1			T153	1		T116	1		T186	1
all_levels[12]	auto[0]	369652	1			T2	1		T3	1487		T5	6
all_levels[12]	auto[1]	25	1			T36	2		T257	1		T33	1
all_levels[13]	auto[0]	170325	1			T2	4		T3	2006		T5	42
all_levels[13]	auto[1]	13	1			T134	1		T322	2		T151	1
all_levels[14]	auto[0]	159366	1			T3	1428		T6	1045		T8	22
all_levels[14]	auto[1]	27	1			T282	1		T323	1		T155	1
all_levels[15]	auto[0]	179437	1			T2	1		T3	1881		T6	685
all_levels[15]	auto[1]	84	1			T14	12		T100	4		T262	6
all_levels[16]	auto[0]	174744	1			T3	1573		T5	3		T6	645
all_levels[16]	auto[1]	20	1			T7	2		T112	1		T324	1
all_levels[17]	auto[0]	217879	1			T2	2		T3	1943		T6	1068
all_levels[17]	auto[1]	30	1			T115	1		T126	2		T130	1
all_levels[18]	auto[0]	186889	1			T2	1		T3	1850		T4	1
all_levels[18]	auto[1]	33	1			T6	1		T101	2		T103	1
all_levels[19]	auto[0]	169589	1			T2	2		T3	2083		T6	547
all_levels[19]	auto[1]	25	1			T141	1		T197	1		T87	2
all_levels[20]	auto[0]	564901	1			T2	3		T3	1301		T6	1068
all_levels[20]	auto[1]	18	1			T100	1		T134	1		T59	2
all_levels[21]	auto[0]	196495	1			T2	3		T3	2080		T6	1069
all_levels[21]	auto[1]	31	1			T145	2		T163	5		T325	2
all_levels[22]	auto[0]	157058	1			T2	4		T3	2083		T6	1064
all_levels[22]	auto[1]	17	1			T192	2		T220	1		T326	4
all_levels[23]	auto[0]	289706	1			T2	2		T3	1648		T6	710
all_levels[23]	auto[1]	22	1			T128	2		T87	1		T327	1
all_levels[24]	auto[0]	144114	1			T2	2		T3	1386		T6	772
all_levels[24]	auto[1]	25	1			T129	1		T276	1		T141	2
all_levels[25]	auto[0]	276078	1			T2	1		T3	2084		T6	1063
all_levels[25]	auto[1]	16	1			T185	4		T61	1		T87	1
all_levels[26]	auto[0]	163255	1			T2	3		T3	1974		T6	1490
all_levels[26]	auto[1]	17	1			T112	1		T150	2		T111	1
all_levels[27]	auto[0]	193632	1			T2	2		T3	1409		T5	3
all_levels[27]	auto[1]	33	1			T35	2		T131	1		T216	4
all_levels[28]	auto[0]	342679	1			T2	4		T3	78588		T5	21
all_levels[28]	auto[1]	15	1			T7	1		T129	2		T296	1
all_levels[29]	auto[0]	283202	1			T2	2		T6	7038		T7	1
all_levels[29]	auto[1]	26	1			T153	3		T188	1		T221	2
all_levels[30]	auto[0]	141908	1			T2	2		T7	7		T11	2
all_levels[30]	auto[1]	23	1			T7	1		T128	1		T282	2
all_levels[31]	auto[0]	695248	1			T2	1		T7	1		T9	1
all_levels[31]	auto[1]	33	1			T12	1		T117	1		T16	1
all_levels[32]	auto[0]	12855946	1			T2	3		T4	60		T6	1
all_levels[32]	auto[1]	542	1			T4	1		T7	3		T8	1