Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	908	1			T15	11		T16	7		T22	7
all_values[1]	908	1			T15	11		T16	7		T22	7
all_values[2]	908	1			T15	11		T16	7		T22	7
all_values[3]	908	1			T15	11		T16	7		T22	7
all_values[4]	908	1			T15	11		T16	7		T22	7
all_values[5]	908	1			T15	11		T16	7		T22	7
all_values[6]	908	1			T15	11		T16	7		T22	7
all_values[7]	908	1			T15	11		T16	7		T22	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3846

1

T15

48

T16

31

T22

33

auto[1]

3418

1

T15

40

T16

25

T22

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2635

1

T15

28

T16

18

T22

23

auto[1]

4629

1

T15

60

T16

38

T22

33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4332

1

T15

49

T16

34

T22

33

auto[1]

2932

1

T15

39

T16

22

T22

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	303	1			T15	7		T16	6		T22	3
all_values[0]	auto[0]	auto[1]	auto[1]	269	1			T15	2		T19	4		T31	3
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T15	1		T22	3		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T15	1		T16	1		T22	1
all_values[1]	auto[0]	auto[0]	auto[0]	284	1			T15	5		T16	1		T22	3
all_values[1]	auto[0]	auto[1]	auto[0]	248	1			T15	3		T22	2		T19	3
all_values[1]	auto[1]	auto[0]	auto[1]	211	1			T15	2		T16	3		T22	2
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T15	1		T16	3		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	191	1			T15	2		T16	5		T22	3
all_values[2]	auto[0]	auto[0]	auto[1]	91	1			T19	1		T20	2		T123	3
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T15	3		T22	1		T19	1
all_values[2]	auto[0]	auto[1]	auto[1]	106	1			T15	1		T22	1		T31	1
all_values[2]	auto[1]	auto[0]	auto[1]	208	1			T15	3		T16	1		T22	2
all_values[2]	auto[1]	auto[1]	auto[1]	169	1			T15	2		T16	1		T31	1
all_values[3]	auto[0]	auto[0]	auto[0]	196	1			T15	1		T19	2		T20	3
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T15	2		T22	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T15	1		T16	4		T19	2
all_values[3]	auto[0]	auto[1]	auto[1]	117	1			T15	2		T16	1		T22	2
all_values[3]	auto[1]	auto[0]	auto[1]	188	1			T15	3		T22	2		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	191	1			T15	2		T16	2		T22	2
all_values[4]	auto[0]	auto[0]	auto[0]	215	1			T22	2		T19	1		T31	2
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T16	1		T31	2		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	167	1			T22	2		T33	1		T34	2
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T15	2		T16	2		T22	1
all_values[4]	auto[1]	auto[0]	auto[1]	170	1			T15	3		T16	2		T22	1
all_values[4]	auto[1]	auto[1]	auto[1]	183	1			T15	6		T16	2		T22	1
all_values[5]	auto[0]	auto[0]	auto[0]	202	1			T15	1		T16	3		T22	1
all_values[5]	auto[0]	auto[0]	auto[1]	91	1			T15	3		T16	2		T33	2
all_values[5]	auto[0]	auto[1]	auto[0]	158	1			T15	1		T22	1		T19	2
all_values[5]	auto[0]	auto[1]	auto[1]	92	1			T22	1		T31	4		T20	2
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T15	5		T16	1		T22	1
all_values[5]	auto[1]	auto[1]	auto[1]	190	1			T15	1		T16	1		T22	3
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T15	4		T22	2		T31	2
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T20	1		T33	1		T34	1
all_values[6]	auto[0]	auto[1]	auto[0]	166	1			T15	3		T16	1		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	95	1			T16	3		T22	1		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	211	1			T15	1		T16	2		T22	2
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T15	3		T16	1		T22	2
all_values[7]	auto[0]	auto[0]	auto[0]	174	1			T15	1		T16	2		T22	4
all_values[7]	auto[0]	auto[0]	auto[1]	105	1			T15	1		T31	1		T20	1
all_values[7]	auto[0]	auto[1]	auto[0]	172	1			T15	3		T16	2		T22	2
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T15	1		T16	1		T31	3
all_values[7]	auto[1]	auto[0]	auto[1]	213	1			T15	3		T16	2		T22	1
all_values[7]	auto[1]	auto[1]	auto[1]	157	1			T15	2		T19	1		T20	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal