Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.27 97.95 100.00 98.80 100.00 99.55


Total test records in report: 1316
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T1254 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1915007761 May 16 12:58:38 PM PDT 24 May 16 12:59:12 PM PDT 24 194626905 ps
T1255 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1859649901 May 16 12:58:52 PM PDT 24 May 16 12:59:25 PM PDT 24 60945425 ps
T1256 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4265703346 May 16 12:58:44 PM PDT 24 May 16 12:59:17 PM PDT 24 140441844 ps
T1257 /workspace/coverage/cover_reg_top/39.uart_intr_test.3819054449 May 16 12:59:08 PM PDT 24 May 16 12:59:44 PM PDT 24 18024544 ps
T1258 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2065679703 May 16 12:58:56 PM PDT 24 May 16 12:59:32 PM PDT 24 34048763 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2269034337 May 16 12:58:39 PM PDT 24 May 16 12:59:13 PM PDT 24 465038384 ps
T1260 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2733219058 May 16 12:58:41 PM PDT 24 May 16 12:59:13 PM PDT 24 37822996 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3433700709 May 16 12:58:59 PM PDT 24 May 16 12:59:34 PM PDT 24 138563859 ps
T1262 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1321507750 May 16 12:58:58 PM PDT 24 May 16 12:59:34 PM PDT 24 15928863 ps
T1263 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1894860731 May 16 12:58:59 PM PDT 24 May 16 12:59:35 PM PDT 24 12139475 ps
T1264 /workspace/coverage/cover_reg_top/15.uart_intr_test.998828300 May 16 12:58:55 PM PDT 24 May 16 12:59:30 PM PDT 24 13972649 ps
T1265 /workspace/coverage/cover_reg_top/1.uart_intr_test.865388024 May 16 12:58:38 PM PDT 24 May 16 12:59:11 PM PDT 24 21277486 ps
T1266 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1527480953 May 16 12:58:59 PM PDT 24 May 16 12:59:34 PM PDT 24 20122389 ps
T1267 /workspace/coverage/cover_reg_top/21.uart_intr_test.3331347141 May 16 12:58:59 PM PDT 24 May 16 12:59:34 PM PDT 24 51204898 ps
T56 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3237219751 May 16 12:58:58 PM PDT 24 May 16 12:59:34 PM PDT 24 25056908 ps
T1268 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2470978488 May 16 12:58:58 PM PDT 24 May 16 12:59:34 PM PDT 24 46723989 ps
T1269 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2937982023 May 16 12:58:49 PM PDT 24 May 16 12:59:23 PM PDT 24 181465838 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1776215349 May 16 12:58:52 PM PDT 24 May 16 12:59:25 PM PDT 24 42311462 ps
T1271 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.493993592 May 16 12:58:39 PM PDT 24 May 16 12:59:12 PM PDT 24 26865793 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3077046985 May 16 12:58:39 PM PDT 24 May 16 12:59:12 PM PDT 24 113610959 ps
T1273 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3722982748 May 16 12:59:00 PM PDT 24 May 16 12:59:35 PM PDT 24 174545587 ps
T1274 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4223917440 May 16 12:58:57 PM PDT 24 May 16 12:59:33 PM PDT 24 32645197 ps
T1275 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2900052555 May 16 12:58:40 PM PDT 24 May 16 12:59:13 PM PDT 24 40176094 ps
T83 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.393047429 May 16 12:58:48 PM PDT 24 May 16 12:59:22 PM PDT 24 183205865 ps
T1276 /workspace/coverage/cover_reg_top/20.uart_intr_test.3527192106 May 16 12:58:58 PM PDT 24 May 16 12:59:33 PM PDT 24 103653376 ps
T1277 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3063696091 May 16 12:58:59 PM PDT 24 May 16 12:59:34 PM PDT 24 111509684 ps
T1278 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.593293665 May 16 12:58:58 PM PDT 24 May 16 12:59:34 PM PDT 24 87421235 ps
T1279 /workspace/coverage/cover_reg_top/37.uart_intr_test.4075512722 May 16 12:59:08 PM PDT 24 May 16 12:59:44 PM PDT 24 28656943 ps
T1280 /workspace/coverage/cover_reg_top/38.uart_intr_test.1268654907 May 16 12:59:10 PM PDT 24 May 16 12:59:45 PM PDT 24 13459297 ps
T1281 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.267770522 May 16 12:58:38 PM PDT 24 May 16 12:59:12 PM PDT 24 88405775 ps
T1282 /workspace/coverage/cover_reg_top/35.uart_intr_test.4136538513 May 16 12:59:10 PM PDT 24 May 16 12:59:45 PM PDT 24 47599613 ps
T1283 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2950174976 May 16 12:58:42 PM PDT 24 May 16 12:59:15 PM PDT 24 136807572 ps
T1284 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3314204324 May 16 12:58:51 PM PDT 24 May 16 12:59:24 PM PDT 24 29376171 ps
T1285 /workspace/coverage/cover_reg_top/47.uart_intr_test.2476850327 May 16 12:59:07 PM PDT 24 May 16 12:59:43 PM PDT 24 10640319 ps
T1286 /workspace/coverage/cover_reg_top/46.uart_intr_test.3703081905 May 16 12:59:08 PM PDT 24 May 16 12:59:44 PM PDT 24 33417483 ps
T1287 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2195457619 May 16 12:58:44 PM PDT 24 May 16 12:59:17 PM PDT 24 21717792 ps
T1288 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3158276012 May 16 12:58:52 PM PDT 24 May 16 12:59:25 PM PDT 24 27931274 ps
T1289 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.169167113 May 16 12:58:38 PM PDT 24 May 16 12:59:12 PM PDT 24 31207327 ps
T1290 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3713281808 May 16 12:58:47 PM PDT 24 May 16 12:59:21 PM PDT 24 16204709 ps
T1291 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3622672066 May 16 12:58:39 PM PDT 24 May 16 12:59:12 PM PDT 24 36324307 ps
T1292 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2540562209 May 16 12:58:39 PM PDT 24 May 16 12:59:12 PM PDT 24 21181579 ps
T1293 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3139948743 May 16 12:58:50 PM PDT 24 May 16 12:59:23 PM PDT 24 50402541 ps
T1294 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3367101866 May 16 12:58:39 PM PDT 24 May 16 12:59:12 PM PDT 24 37625669 ps
T1295 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4166346071 May 16 12:58:47 PM PDT 24 May 16 12:59:22 PM PDT 24 204546254 ps
T1296 /workspace/coverage/cover_reg_top/49.uart_intr_test.3055191987 May 16 12:59:10 PM PDT 24 May 16 12:59:45 PM PDT 24 14129250 ps
T1297 /workspace/coverage/cover_reg_top/43.uart_intr_test.2194536706 May 16 12:59:08 PM PDT 24 May 16 12:59:44 PM PDT 24 40570324 ps
T1298 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.543408471 May 16 12:58:51 PM PDT 24 May 16 12:59:24 PM PDT 24 131805914 ps
T1299 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2618538292 May 16 12:58:58 PM PDT 24 May 16 12:59:35 PM PDT 24 428954440 ps
T1300 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3779978354 May 16 12:58:47 PM PDT 24 May 16 12:59:21 PM PDT 24 18462177 ps
T1301 /workspace/coverage/cover_reg_top/18.uart_intr_test.3624117434 May 16 12:58:57 PM PDT 24 May 16 12:59:33 PM PDT 24 31122597 ps
T1302 /workspace/coverage/cover_reg_top/16.uart_intr_test.946085714 May 16 12:58:57 PM PDT 24 May 16 12:59:33 PM PDT 24 16683496 ps
T1303 /workspace/coverage/cover_reg_top/24.uart_intr_test.4133025273 May 16 12:59:12 PM PDT 24 May 16 12:59:47 PM PDT 24 12611703 ps
T1304 /workspace/coverage/cover_reg_top/34.uart_intr_test.3289343290 May 16 12:59:09 PM PDT 24 May 16 12:59:44 PM PDT 24 13547710 ps
T1305 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3793083348 May 16 12:58:42 PM PDT 24 May 16 12:59:16 PM PDT 24 147877114 ps
T1306 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1162700342 May 16 12:58:48 PM PDT 24 May 16 12:59:23 PM PDT 24 127284372 ps
T1307 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1088006888 May 16 12:58:39 PM PDT 24 May 16 12:59:13 PM PDT 24 253838885 ps
T1308 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1208053518 May 16 12:58:52 PM PDT 24 May 16 12:59:25 PM PDT 24 42729015 ps
T1309 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2429853697 May 16 12:58:40 PM PDT 24 May 16 12:59:13 PM PDT 24 16135265 ps
T1310 /workspace/coverage/cover_reg_top/0.uart_intr_test.3910520116 May 16 12:58:40 PM PDT 24 May 16 12:59:13 PM PDT 24 33492183 ps
T1311 /workspace/coverage/cover_reg_top/31.uart_intr_test.315364900 May 16 12:59:12 PM PDT 24 May 16 12:59:47 PM PDT 24 38343050 ps
T1312 /workspace/coverage/cover_reg_top/3.uart_tl_errors.285060732 May 16 12:58:53 PM PDT 24 May 16 12:59:26 PM PDT 24 35206114 ps
T1313 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1997632126 May 16 12:58:45 PM PDT 24 May 16 12:59:20 PM PDT 24 89363232 ps
T1314 /workspace/coverage/cover_reg_top/11.uart_intr_test.1095712019 May 16 12:58:47 PM PDT 24 May 16 12:59:21 PM PDT 24 13265091 ps
T1315 /workspace/coverage/cover_reg_top/28.uart_intr_test.346612357 May 16 12:59:06 PM PDT 24 May 16 12:59:42 PM PDT 24 113442632 ps
T57 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2052363217 May 16 12:58:40 PM PDT 24 May 16 12:59:13 PM PDT 24 116659447 ps
T1316 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.862023312 May 16 12:58:42 PM PDT 24 May 16 12:59:15 PM PDT 24 53014357 ps

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1672057559
Short name T6
Test name
Test status
Simulation time 90952465416 ps
CPU time 838.13 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 217196 kb
Host smart-9868f73a-f8c7-45e7-97dd-d3f71a9b409d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672057559 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1672057559
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1513353492
Short name T19
Test name
Test status
Simulation time 61278237506 ps
CPU time 602.9 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:13:35 PM PDT 24
Peak memory 216988 kb
Host smart-3386dfec-3329-41d6-82f8-d9f0a70c0c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513353492 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1513353492
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1534591726
Short name T197
Test name
Test status
Simulation time 251259152987 ps
CPU time 1195.13 seconds
Started May 16 01:03:28 PM PDT 24
Finished May 16 01:23:33 PM PDT 24
Peak memory 217140 kb
Host smart-48ac9ce2-59c6-4124-a21f-3b9a8547f514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534591726 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1534591726
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2849299757
Short name T114
Test name
Test status
Simulation time 272913431910 ps
CPU time 86.9 seconds
Started May 16 01:01:45 PM PDT 24
Finished May 16 01:03:38 PM PDT 24
Peak memory 200448 kb
Host smart-0819020a-d0ba-4b95-b70b-5eb369e0e962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849299757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2849299757
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_stress_all.646348991
Short name T262
Test name
Test status
Simulation time 174225935603 ps
CPU time 615.6 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:11:04 PM PDT 24
Peak memory 200432 kb
Host smart-b9562707-10b6-4007-9646-50a348015e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646348991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.646348991
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all.986144034
Short name T108
Test name
Test status
Simulation time 342227916097 ps
CPU time 544.34 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:12:18 PM PDT 24
Peak memory 208888 kb
Host smart-d7528f0a-f724-41dd-84bd-7862b6b3a4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986144034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.986144034
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.661730295
Short name T20
Test name
Test status
Simulation time 68087401456 ps
CPU time 329.55 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:09:17 PM PDT 24
Peak memory 210800 kb
Host smart-144d9368-4655-47dd-bd9a-22a6a5ac7037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661730295 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.661730295
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.2397942650
Short name T127
Test name
Test status
Simulation time 207023553054 ps
CPU time 888.95 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:17:01 PM PDT 24
Peak memory 200708 kb
Host smart-927fed04-56d8-46f3-8502-623e137d584b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397942650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2397942650
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4236412153
Short name T28
Test name
Test status
Simulation time 32826427 ps
CPU time 0.75 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:00:49 PM PDT 24
Peak memory 218720 kb
Host smart-b85aa37a-d40c-4c21-9bf4-975e4c51a8be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236412153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4236412153
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_stress_all.1966702370
Short name T16
Test name
Test status
Simulation time 344666398159 ps
CPU time 763.24 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:13:36 PM PDT 24
Peak memory 208940 kb
Host smart-4c4f7a89-a82a-45e5-8650-33e0de3773e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966702370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1966702370
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.496586399
Short name T33
Test name
Test status
Simulation time 239517421406 ps
CPU time 795.14 seconds
Started May 16 01:03:38 PM PDT 24
Finished May 16 01:17:01 PM PDT 24
Peak memory 215296 kb
Host smart-6b430c47-7fc7-4bff-839e-cd2d913c03f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496586399 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.496586399
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1037816747
Short name T40
Test name
Test status
Simulation time 72718658753 ps
CPU time 437.31 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:08:32 PM PDT 24
Peak memory 216928 kb
Host smart-79044b41-56ae-46d4-a48f-925b69976dd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037816747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1037816747
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3397332228
Short name T128
Test name
Test status
Simulation time 354180392366 ps
CPU time 213.96 seconds
Started May 16 01:05:22 PM PDT 24
Finished May 16 01:09:04 PM PDT 24
Peak memory 200488 kb
Host smart-6d9464a5-5fdf-42ef-a273-b450c0443046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397332228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3397332228
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4251976789
Short name T2
Test name
Test status
Simulation time 146047605688 ps
CPU time 130.42 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:03:26 PM PDT 24
Peak memory 199756 kb
Host smart-66d765fe-ffe8-42c7-905e-3e75d8555797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251976789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4251976789
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.589467038
Short name T7
Test name
Test status
Simulation time 81064253567 ps
CPU time 148.3 seconds
Started May 16 01:03:38 PM PDT 24
Finished May 16 01:06:15 PM PDT 24
Peak memory 200492 kb
Host smart-e7a25006-c8e4-4be6-9e15-f47937a799ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589467038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.589467038
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1233625025
Short name T182
Test name
Test status
Simulation time 476939586090 ps
CPU time 949.1 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:19:29 PM PDT 24
Peak memory 225740 kb
Host smart-563af98f-4d73-4873-b7b0-08b9ed356d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233625025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1233625025
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1035669859
Short name T79
Test name
Test status
Simulation time 265251199 ps
CPU time 1.19 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 198992 kb
Host smart-c4b21e3e-bdba-453d-a60a-d49a58bdfd4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035669859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1035669859
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/16.uart_alert_test.1556881648
Short name T91
Test name
Test status
Simulation time 41440230 ps
CPU time 0.54 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:01:32 PM PDT 24
Peak memory 195864 kb
Host smart-9ebfdc92-1761-4f66-8312-5292bbc8aeac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556881648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1556881648
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_stress_all.1154744751
Short name T131
Test name
Test status
Simulation time 200392346984 ps
CPU time 312.22 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:06:12 PM PDT 24
Peak memory 200496 kb
Host smart-1df4be1f-d938-4c04-bf09-f8f447e7e21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154744751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1154744751
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3867068148
Short name T51
Test name
Test status
Simulation time 25808299 ps
CPU time 0.61 seconds
Started May 16 12:58:50 PM PDT 24
Finished May 16 12:59:24 PM PDT 24
Peak memory 195224 kb
Host smart-0d1022c6-61bc-41b5-98f8-7af844d818b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867068148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3867068148
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1462584168
Short name T113
Test name
Test status
Simulation time 47973912467 ps
CPU time 49.18 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:03:06 PM PDT 24
Peak memory 200476 kb
Host smart-f40da67e-4ec4-437b-aa26-e9a54e4f88d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462584168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1462584168
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1728336910
Short name T306
Test name
Test status
Simulation time 322883177888 ps
CPU time 1252.77 seconds
Started May 16 01:00:27 PM PDT 24
Finished May 16 01:21:57 PM PDT 24
Peak memory 225516 kb
Host smart-8d58df20-b1d6-436c-ba13-2cdeac56d08a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728336910 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1728336910
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3120684824
Short name T87
Test name
Test status
Simulation time 141976500905 ps
CPU time 168.51 seconds
Started May 16 01:03:47 PM PDT 24
Finished May 16 01:06:42 PM PDT 24
Peak memory 200436 kb
Host smart-55e3efe5-750f-4231-b60a-ba072c11f561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120684824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3120684824
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.374394581
Short name T137
Test name
Test status
Simulation time 116138174624 ps
CPU time 129.62 seconds
Started May 16 01:01:13 PM PDT 24
Finished May 16 01:03:53 PM PDT 24
Peak memory 200396 kb
Host smart-1145bec9-d81e-49bb-9604-a7a562f05bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374394581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.374394581
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.61275414
Short name T192
Test name
Test status
Simulation time 178772672026 ps
CPU time 31.45 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:10:34 PM PDT 24
Peak memory 200460 kb
Host smart-e8330bf5-a468-4187-8cd2-a9801201ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61275414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.61275414
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2492595980
Short name T175
Test name
Test status
Simulation time 189983902246 ps
CPU time 74.38 seconds
Started May 16 01:02:15 PM PDT 24
Finished May 16 01:03:48 PM PDT 24
Peak memory 200500 kb
Host smart-dc81a1df-5725-49c3-91fd-e74df748f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492595980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2492595980
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2096679759
Short name T153
Test name
Test status
Simulation time 89525170255 ps
CPU time 117.96 seconds
Started May 16 01:04:01 PM PDT 24
Finished May 16 01:06:06 PM PDT 24
Peak memory 200432 kb
Host smart-6b1b9814-4ce4-4388-a60a-14127b6bfcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096679759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2096679759
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.2555612652
Short name T157
Test name
Test status
Simulation time 220072484962 ps
CPU time 753.24 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:16:01 PM PDT 24
Peak memory 208980 kb
Host smart-fecd8f9d-b0bd-4c80-9d88-3222b6146689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555612652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2555612652
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1926092263
Short name T101
Test name
Test status
Simulation time 162327119170 ps
CPU time 76.96 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 200508 kb
Host smart-ee575d70-9507-4e40-8eb2-809eda68d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926092263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1926092263
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2176020020
Short name T152
Test name
Test status
Simulation time 169914361338 ps
CPU time 538.2 seconds
Started May 16 01:00:47 PM PDT 24
Finished May 16 01:10:19 PM PDT 24
Peak memory 225388 kb
Host smart-071f7578-abf8-460f-ad71-453b0732e148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176020020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2176020020
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3561735514
Short name T151
Test name
Test status
Simulation time 18204263683 ps
CPU time 33.23 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:02:14 PM PDT 24
Peak memory 200400 kb
Host smart-729139b9-d738-4aaa-8a44-ebde67ab2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561735514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3561735514
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.393047429
Short name T83
Test name
Test status
Simulation time 183205865 ps
CPU time 0.93 seconds
Started May 16 12:58:48 PM PDT 24
Finished May 16 12:59:22 PM PDT 24
Peak memory 199012 kb
Host smart-566bc7a3-aa18-49ec-8710-6bd099ccb59a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393047429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.393047429
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/27.uart_intr.413277794
Short name T285
Test name
Test status
Simulation time 38618518308 ps
CPU time 44.36 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 200448 kb
Host smart-fafbfb48-0c89-4626-9089-b7ee0dd427c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413277794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.413277794
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/34.uart_stress_all.197504789
Short name T282
Test name
Test status
Simulation time 125066777292 ps
CPU time 310.21 seconds
Started May 16 01:02:12 PM PDT 24
Finished May 16 01:07:41 PM PDT 24
Peak memory 200496 kb
Host smart-5d8afe00-7c4e-4e69-8ccf-935476eb4cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197504789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.197504789
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.836694631
Short name T225
Test name
Test status
Simulation time 71028498623 ps
CPU time 37.87 seconds
Started May 16 01:09:45 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 200512 kb
Host smart-29680aa7-f4c5-4315-ad7a-aa1287f214e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836694631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.836694631
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1221533222
Short name T63
Test name
Test status
Simulation time 15372405909 ps
CPU time 26.43 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:01:37 PM PDT 24
Peak memory 200468 kb
Host smart-0932ce8a-107b-4030-a6c3-ab6c5f679c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221533222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1221533222
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1283069890
Short name T1179
Test name
Test status
Simulation time 19352428670 ps
CPU time 31.33 seconds
Started May 16 01:03:52 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200472 kb
Host smart-9fdaa294-e444-4849-bb6b-5ed306d94928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283069890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1283069890
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2850243133
Short name T249
Test name
Test status
Simulation time 109895459959 ps
CPU time 39.72 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:04:35 PM PDT 24
Peak memory 200464 kb
Host smart-0541397e-0efa-4dac-bf51-08dd64249c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850243133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2850243133
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.4182194149
Short name T460
Test name
Test status
Simulation time 52184648334 ps
CPU time 77.92 seconds
Started May 16 01:05:21 PM PDT 24
Finished May 16 01:06:47 PM PDT 24
Peak memory 200424 kb
Host smart-711240ab-52fe-4aba-8de6-ce500a715c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182194149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.4182194149
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.1169101813
Short name T166
Test name
Test status
Simulation time 94706850595 ps
CPU time 98.48 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:03:36 PM PDT 24
Peak memory 208880 kb
Host smart-82f19226-d5a6-4cc6-bdb6-33bfd7482f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169101813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1169101813
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.402351357
Short name T163
Test name
Test status
Simulation time 1280887842932 ps
CPU time 829.31 seconds
Started May 16 01:03:37 PM PDT 24
Finished May 16 01:17:35 PM PDT 24
Peak memory 216984 kb
Host smart-676b6351-4571-40f2-9ff1-af55968a1cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402351357 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.402351357
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3594715115
Short name T221
Test name
Test status
Simulation time 154175827565 ps
CPU time 190.01 seconds
Started May 16 01:03:50 PM PDT 24
Finished May 16 01:07:06 PM PDT 24
Peak memory 200416 kb
Host smart-41fef9fb-758c-42bf-8a4c-51a7af26f960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594715115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3594715115
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.3997143522
Short name T164
Test name
Test status
Simulation time 386440908024 ps
CPU time 449.98 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:09:17 PM PDT 24
Peak memory 200488 kb
Host smart-838865af-8af1-4353-b042-f2500fa159fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997143522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3997143522
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.331604045
Short name T181
Test name
Test status
Simulation time 122683185047 ps
CPU time 58.79 seconds
Started May 16 01:09:45 PM PDT 24
Finished May 16 01:10:56 PM PDT 24
Peak memory 200448 kb
Host smart-4bf36240-7e94-4c60-bcb9-b7c85b0fd4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331604045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.331604045
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1331817187
Short name T228
Test name
Test status
Simulation time 166893138597 ps
CPU time 92.39 seconds
Started May 16 01:09:56 PM PDT 24
Finished May 16 01:11:42 PM PDT 24
Peak memory 200404 kb
Host smart-1a787982-3205-4d9b-8286-f80b5b1ae424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331817187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1331817187
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1100709915
Short name T170
Test name
Test status
Simulation time 114253622501 ps
CPU time 101.97 seconds
Started May 16 01:02:46 PM PDT 24
Finished May 16 01:04:38 PM PDT 24
Peak memory 200424 kb
Host smart-03484284-8a55-448b-8821-67a9c025b11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100709915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1100709915
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3591706731
Short name T84
Test name
Test status
Simulation time 283515382 ps
CPU time 1.31 seconds
Started May 16 12:58:43 PM PDT 24
Finished May 16 12:59:16 PM PDT 24
Peak memory 199148 kb
Host smart-d879dc19-1002-43ca-8387-c9271c9be6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591706731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3591706731
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/12.uart_stress_all.2992047175
Short name T311
Test name
Test status
Simulation time 68282505951 ps
CPU time 954.02 seconds
Started May 16 01:00:55 PM PDT 24
Finished May 16 01:17:22 PM PDT 24
Peak memory 199404 kb
Host smart-ec25a13b-ff95-4fc0-abfa-3de205c3f88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992047175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2992047175
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3483288035
Short name T1093
Test name
Test status
Simulation time 41928031847 ps
CPU time 38.15 seconds
Started May 16 01:03:53 PM PDT 24
Finished May 16 01:04:36 PM PDT 24
Peak memory 200436 kb
Host smart-dd2e8a00-fd5e-49eb-ab06-a301c2a76081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483288035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3483288035
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1932554519
Short name T461
Test name
Test status
Simulation time 135985211565 ps
CPU time 391.39 seconds
Started May 16 01:00:49 PM PDT 24
Finished May 16 01:07:53 PM PDT 24
Peak memory 200408 kb
Host smart-1065204c-8316-4e2e-9e80-bd05f17d7480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932554519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1932554519
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2704741135
Short name T134
Test name
Test status
Simulation time 15923228602 ps
CPU time 16.71 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:04:26 PM PDT 24
Peak memory 200492 kb
Host smart-6b298118-64f0-403c-959c-72304c55187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704741135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2704741135
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3766920325
Short name T117
Test name
Test status
Simulation time 235817510286 ps
CPU time 83.7 seconds
Started May 16 01:05:20 PM PDT 24
Finished May 16 01:06:53 PM PDT 24
Peak memory 200456 kb
Host smart-83c9721c-8350-4cbb-b31c-1f3db814b154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766920325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3766920325
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1284179462
Short name T273
Test name
Test status
Simulation time 49231683458 ps
CPU time 93.85 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:03:22 PM PDT 24
Peak memory 200460 kb
Host smart-987e9abf-e89e-4936-8c02-9bbfbfa2be87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284179462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1284179462
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.251980061
Short name T132
Test name
Test status
Simulation time 133459631979 ps
CPU time 104.87 seconds
Started May 16 01:10:01 PM PDT 24
Finished May 16 01:11:57 PM PDT 24
Peak memory 200508 kb
Host smart-45fc59a0-f9b5-4f62-a569-22bdc6e2afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251980061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.251980061
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.687137028
Short name T112
Test name
Test status
Simulation time 93985894640 ps
CPU time 76.3 seconds
Started May 16 01:10:05 PM PDT 24
Finished May 16 01:11:30 PM PDT 24
Peak memory 200396 kb
Host smart-1d3fb2ca-d68f-420d-9bc0-87bc27330be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687137028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.687137028
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.399130073
Short name T231
Test name
Test status
Simulation time 82953097989 ps
CPU time 39.67 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:04:05 PM PDT 24
Peak memory 200444 kb
Host smart-7aa0328f-8052-4742-ade0-02183a386da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399130073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.399130073
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.4277732989
Short name T807
Test name
Test status
Simulation time 113933781972 ps
CPU time 220.86 seconds
Started May 16 01:00:03 PM PDT 24
Finished May 16 01:04:25 PM PDT 24
Peak memory 200440 kb
Host smart-c1247215-934d-4f6a-8b50-329023ddfabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277732989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4277732989
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3667563580
Short name T233
Test name
Test status
Simulation time 46848231619 ps
CPU time 95.64 seconds
Started May 16 01:03:42 PM PDT 24
Finished May 16 01:05:25 PM PDT 24
Peak memory 200524 kb
Host smart-368d41c9-4959-427e-a491-09f2d8febcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667563580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3667563580
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1478604121
Short name T250
Test name
Test status
Simulation time 126632252740 ps
CPU time 184.79 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:06:52 PM PDT 24
Peak memory 200476 kb
Host smart-048f9844-daec-4279-896a-f632e75ac99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478604121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1478604121
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2272672931
Short name T236
Test name
Test status
Simulation time 19524392306 ps
CPU time 12.19 seconds
Started May 16 01:00:39 PM PDT 24
Finished May 16 01:01:27 PM PDT 24
Peak memory 200452 kb
Host smart-cc9a15e1-2f54-4618-bc2a-97d39cfecd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272672931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2272672931
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1512752031
Short name T44
Test name
Test status
Simulation time 171086457106 ps
CPU time 542.98 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 216940 kb
Host smart-1c909aae-d6e9-444e-b76f-e438653b41c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512752031 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1512752031
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4274756363
Short name T775
Test name
Test status
Simulation time 121461632802 ps
CPU time 51.46 seconds
Started May 16 01:05:10 PM PDT 24
Finished May 16 01:06:11 PM PDT 24
Peak memory 200396 kb
Host smart-38e27ef8-dc34-4557-8273-3911abd1c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274756363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4274756363
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1428932072
Short name T245
Test name
Test status
Simulation time 123584138143 ps
CPU time 50.85 seconds
Started May 16 01:05:09 PM PDT 24
Finished May 16 01:06:09 PM PDT 24
Peak memory 200472 kb
Host smart-cafd3050-abf2-4920-81aa-cbd50e3778dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428932072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1428932072
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2347062876
Short name T227
Test name
Test status
Simulation time 204637351823 ps
CPU time 37.76 seconds
Started May 16 01:00:11 PM PDT 24
Finished May 16 01:01:28 PM PDT 24
Peak memory 200480 kb
Host smart-d7c70de2-f30c-4f3f-9329-db0f5f3d516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347062876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2347062876
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1309049809
Short name T238
Test name
Test status
Simulation time 166613211232 ps
CPU time 49.22 seconds
Started May 16 01:09:48 PM PDT 24
Finished May 16 01:10:53 PM PDT 24
Peak memory 200428 kb
Host smart-ed017051-f948-4f85-8b86-6cd7594c97bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309049809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1309049809
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2524784178
Short name T239
Test name
Test status
Simulation time 76483222877 ps
CPU time 43.88 seconds
Started May 16 01:09:55 PM PDT 24
Finished May 16 01:10:53 PM PDT 24
Peak memory 200508 kb
Host smart-0544724b-f05a-47df-b56d-9ce06c6520ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524784178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2524784178
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1468619493
Short name T243
Test name
Test status
Simulation time 50794822717 ps
CPU time 37.03 seconds
Started May 16 01:10:03 PM PDT 24
Finished May 16 01:10:50 PM PDT 24
Peak memory 200460 kb
Host smart-b565e0a5-4261-4665-913e-ff6c6df287fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468619493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1468619493
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1693582080
Short name T258
Test name
Test status
Simulation time 215307453245 ps
CPU time 520.53 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:10:51 PM PDT 24
Peak memory 200520 kb
Host smart-40e2e77b-146c-4ac1-982f-c5595ade0b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693582080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1693582080
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2700552885
Short name T171
Test name
Test status
Simulation time 22529764582 ps
CPU time 47.47 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:03:17 PM PDT 24
Peak memory 200492 kb
Host smart-d1a28142-3fed-4c07-b85c-0b26fa46c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700552885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2700552885
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2207903411
Short name T251
Test name
Test status
Simulation time 109940841483 ps
CPU time 473.3 seconds
Started May 16 01:03:21 PM PDT 24
Finished May 16 01:11:22 PM PDT 24
Peak memory 225444 kb
Host smart-2021c081-6b76-4e36-8f18-41fcecc47be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207903411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2207903411
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3661840373
Short name T247
Test name
Test status
Simulation time 78075196605 ps
CPU time 290.28 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:08:32 PM PDT 24
Peak memory 217200 kb
Host smart-111f3b41-6fa0-408a-9472-0f1c4a6fc48f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661840373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3661840373
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3432178555
Short name T232
Test name
Test status
Simulation time 179418716310 ps
CPU time 146.6 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:06:09 PM PDT 24
Peak memory 200124 kb
Host smart-5210c8ab-ca0d-4c96-af80-74af4881623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432178555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3432178555
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1915007761
Short name T1254
Test name
Test status
Simulation time 194626905 ps
CPU time 0.68 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 194792 kb
Host smart-54ce93eb-99b6-4bbe-9bd0-397e308ece5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915007761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1915007761
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3998853639
Short name T1222
Test name
Test status
Simulation time 49966048 ps
CPU time 1.39 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 197452 kb
Host smart-98a97684-ccc7-4d77-84e1-28c139a98886
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998853639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3998853639
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1208053518
Short name T1308
Test name
Test status
Simulation time 42729015 ps
CPU time 0.58 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 195232 kb
Host smart-10c7a0c6-0a9e-4420-813b-44425509dbaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208053518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1208053518
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2297849707
Short name T1224
Test name
Test status
Simulation time 30517600 ps
CPU time 1.4 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:14 PM PDT 24
Peak memory 199904 kb
Host smart-d2505b0e-574b-42cc-bd22-897fffa63094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297849707 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2297849707
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2195457619
Short name T1287
Test name
Test status
Simulation time 21717792 ps
CPU time 0.57 seconds
Started May 16 12:58:44 PM PDT 24
Finished May 16 12:59:17 PM PDT 24
Peak memory 195296 kb
Host smart-d5ffa0df-f09a-44ad-9389-4758d3e9e877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195457619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2195457619
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3910520116
Short name T1310
Test name
Test status
Simulation time 33492183 ps
CPU time 0.6 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 194204 kb
Host smart-79d23fd5-bb19-4d94-86b0-01a22d55bb2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910520116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3910520116
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3788585646
Short name T1250
Test name
Test status
Simulation time 98915923 ps
CPU time 0.73 seconds
Started May 16 12:58:37 PM PDT 24
Finished May 16 12:59:10 PM PDT 24
Peak memory 196988 kb
Host smart-f92c8787-a532-467e-988d-dfa142f773f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788585646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3788585646
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2950174976
Short name T1283
Test name
Test status
Simulation time 136807572 ps
CPU time 1.09 seconds
Started May 16 12:58:42 PM PDT 24
Finished May 16 12:59:15 PM PDT 24
Peak memory 199604 kb
Host smart-1bcd2393-2392-49af-9ca3-9a211ec1d0e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950174976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2950174976
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.680748100
Short name T1252
Test name
Test status
Simulation time 132608336 ps
CPU time 1.29 seconds
Started May 16 12:58:42 PM PDT 24
Finished May 16 12:59:15 PM PDT 24
Peak memory 199336 kb
Host smart-66d1a648-a507-434f-8b49-6349852e3a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680748100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.680748100
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.4158792297
Short name T52
Test name
Test status
Simulation time 21592303 ps
CPU time 0.65 seconds
Started May 16 12:58:43 PM PDT 24
Finished May 16 12:59:15 PM PDT 24
Peak memory 194700 kb
Host smart-51aba2e2-a92b-4b53-a7df-718740e423aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158792297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.4158792297
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3119564833
Short name T1182
Test name
Test status
Simulation time 267537624 ps
CPU time 2.53 seconds
Started May 16 12:58:43 PM PDT 24
Finished May 16 12:59:17 PM PDT 24
Peak memory 197648 kb
Host smart-776f9715-ac7d-4113-82aa-f86e69acc128
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119564833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3119564833
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2900052555
Short name T1275
Test name
Test status
Simulation time 40176094 ps
CPU time 0.57 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 195232 kb
Host smart-a2e562b3-ce6f-4b20-91c0-9d15ba1d1c1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900052555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2900052555
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.862023312
Short name T1316
Test name
Test status
Simulation time 53014357 ps
CPU time 1.28 seconds
Started May 16 12:58:42 PM PDT 24
Finished May 16 12:59:15 PM PDT 24
Peak memory 200004 kb
Host smart-41f78f2f-7eff-4317-8628-1e45e3c92633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862023312 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.862023312
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1063068926
Short name T68
Test name
Test status
Simulation time 14403790 ps
CPU time 0.58 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 194996 kb
Host smart-e0920c0a-05eb-4415-9d66-f83a514c0670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063068926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1063068926
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.865388024
Short name T1265
Test name
Test status
Simulation time 21277486 ps
CPU time 0.56 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:11 PM PDT 24
Peak memory 194272 kb
Host smart-fb95f10b-5327-43cc-b9a7-79afe28e5b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865388024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.865388024
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1899570085
Short name T71
Test name
Test status
Simulation time 21466709 ps
CPU time 0.7 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 195544 kb
Host smart-b27133cc-d696-460b-b601-296fab4fc8c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899570085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1899570085
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3793083348
Short name T1305
Test name
Test status
Simulation time 147877114 ps
CPU time 1.87 seconds
Started May 16 12:58:42 PM PDT 24
Finished May 16 12:59:16 PM PDT 24
Peak memory 199980 kb
Host smart-9cdc70e2-0f78-48f8-b47b-81e630f47e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793083348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3793083348
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3342299999
Short name T1217
Test name
Test status
Simulation time 85161606 ps
CPU time 0.9 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 198852 kb
Host smart-46e8715d-b161-46c5-bc8a-5e12d272a2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342299999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3342299999
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.593293665
Short name T1278
Test name
Test status
Simulation time 87421235 ps
CPU time 0.71 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 198564 kb
Host smart-19f026ad-a34f-4080-9c04-f2d73611a051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593293665 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.593293665
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1587814927
Short name T1188
Test name
Test status
Simulation time 24107449 ps
CPU time 0.58 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:22 PM PDT 24
Peak memory 194132 kb
Host smart-ab018ee4-b961-4f3d-9dca-089680ed27fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587814927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1587814927
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2065679703
Short name T1258
Test name
Test status
Simulation time 34048763 ps
CPU time 0.73 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:32 PM PDT 24
Peak memory 197620 kb
Host smart-e2c816e2-b242-4c74-95e9-dc11b494feb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065679703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2065679703
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4004686097
Short name T1197
Test name
Test status
Simulation time 626664934 ps
CPU time 1.26 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199924 kb
Host smart-ac17712a-7aa1-41db-a48d-ead5d394bb07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004686097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4004686097
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2937982023
Short name T1269
Test name
Test status
Simulation time 181465838 ps
CPU time 0.95 seconds
Started May 16 12:58:49 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 198824 kb
Host smart-d6e51240-b1a8-4e47-b78c-6e2869a3080f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937982023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2937982023
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2705872174
Short name T1198
Test name
Test status
Simulation time 58706925 ps
CPU time 0.71 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 198436 kb
Host smart-35b24f08-efbe-47aa-8546-6e498f7d23de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705872174 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2705872174
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.4054776808
Short name T1221
Test name
Test status
Simulation time 26207278 ps
CPU time 0.56 seconds
Started May 16 12:58:50 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 195252 kb
Host smart-8a625158-f85e-43a9-ba63-b3f082e288c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054776808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.4054776808
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1095712019
Short name T1314
Test name
Test status
Simulation time 13265091 ps
CPU time 0.56 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 194156 kb
Host smart-f48841c7-d2af-4dbd-9cc1-b0dc33c9ebfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095712019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1095712019
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4084322219
Short name T1232
Test name
Test status
Simulation time 52994288 ps
CPU time 0.72 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 196936 kb
Host smart-da856b8b-c1e1-47ce-b0c5-3c3ca8079e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084322219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.4084322219
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1007732667
Short name T1244
Test name
Test status
Simulation time 139555830 ps
CPU time 0.99 seconds
Started May 16 12:58:49 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 199712 kb
Host smart-d04f3481-aad4-4a9f-b0b9-3e2f4e5e7286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007732667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1007732667
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1997632126
Short name T1313
Test name
Test status
Simulation time 89363232 ps
CPU time 1.33 seconds
Started May 16 12:58:45 PM PDT 24
Finished May 16 12:59:20 PM PDT 24
Peak memory 199212 kb
Host smart-06c18575-0caf-4717-bda3-818c530a926b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997632126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1997632126
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2726755026
Short name T1205
Test name
Test status
Simulation time 81364624 ps
CPU time 0.74 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 198364 kb
Host smart-e1c1dad2-74e7-4880-9a16-027154a6f6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726755026 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2726755026
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1602853971
Short name T1210
Test name
Test status
Simulation time 17784201 ps
CPU time 0.62 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 195176 kb
Host smart-ad47e968-7af0-4b69-b887-71f456350ace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602853971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1602853971
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4162365063
Short name T1238
Test name
Test status
Simulation time 32448411 ps
CPU time 0.55 seconds
Started May 16 12:59:00 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 194208 kb
Host smart-1dd6259d-2c39-4f61-aab6-20522d07a565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162365063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4162365063
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1527480953
Short name T1266
Test name
Test status
Simulation time 20122389 ps
CPU time 0.82 seconds
Started May 16 12:58:59 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 196812 kb
Host smart-ebc720ac-8af5-4e34-805f-3dcb1b5f92a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527480953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1527480953
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2988827092
Short name T1240
Test name
Test status
Simulation time 229013432 ps
CPU time 1.25 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 199932 kb
Host smart-7528b0c4-da48-45f2-83c9-480bac67c412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988827092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2988827092
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1406341078
Short name T1204
Test name
Test status
Simulation time 23926879 ps
CPU time 0.64 seconds
Started May 16 12:58:59 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 197600 kb
Host smart-7b500545-5ff6-4ae9-ab25-5a733daf80ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406341078 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1406341078
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3439499781
Short name T66
Test name
Test status
Simulation time 13562580 ps
CPU time 0.62 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 195252 kb
Host smart-d40c2ba9-3e06-4279-9d52-1b7908777868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439499781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3439499781
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3417956595
Short name T1191
Test name
Test status
Simulation time 23776471 ps
CPU time 0.58 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:30 PM PDT 24
Peak memory 194204 kb
Host smart-d35c2b97-d192-4c5b-9bae-6f345b3593aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417956595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3417956595
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1999639364
Short name T1215
Test name
Test status
Simulation time 23091890 ps
CPU time 0.67 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:30 PM PDT 24
Peak memory 195784 kb
Host smart-6fbbdd56-1560-4db2-a5e4-577e588b7feb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999639364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1999639364
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.629895889
Short name T1184
Test name
Test status
Simulation time 25555321 ps
CPU time 1.33 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199780 kb
Host smart-dfbc9c85-10dd-47bd-a8f7-9d0d8b7a1a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629895889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.629895889
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2573749086
Short name T80
Test name
Test status
Simulation time 124819743 ps
CPU time 1.32 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 199156 kb
Host smart-e777a2e8-202e-42a6-90c8-ccdfb0ce9cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573749086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2573749086
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1588776075
Short name T1194
Test name
Test status
Simulation time 25578120 ps
CPU time 1.14 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 199936 kb
Host smart-1fc8ea15-30dc-499b-b659-c37a6f936c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588776075 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1588776075
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3237219751
Short name T56
Test name
Test status
Simulation time 25056908 ps
CPU time 0.6 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 195260 kb
Host smart-a322e110-5d5d-4e5b-bef5-7a6a952e4ed1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237219751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3237219751
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1739068346
Short name T1242
Test name
Test status
Simulation time 17308221 ps
CPU time 0.63 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 194228 kb
Host smart-d27e9729-a508-459e-b8bd-4f37fba3117c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739068346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1739068346
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4223917440
Short name T1274
Test name
Test status
Simulation time 32645197 ps
CPU time 0.76 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 195972 kb
Host smart-4511a345-66f0-4a54-8900-4bcff4e37c9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223917440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4223917440
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2391195224
Short name T1213
Test name
Test status
Simulation time 44677631 ps
CPU time 1.18 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199888 kb
Host smart-4cd65b0f-e72c-418a-94bc-a83aaaf46c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391195224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2391195224
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1668414278
Short name T1207
Test name
Test status
Simulation time 205971453 ps
CPU time 1.05 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 198816 kb
Host smart-65e93054-1525-4140-8fd6-b8280eefdc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668414278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1668414278
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3063696091
Short name T1277
Test name
Test status
Simulation time 111509684 ps
CPU time 0.82 seconds
Started May 16 12:58:59 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199692 kb
Host smart-ec5a3c9d-b1fd-4bf7-b36b-5102c97779e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063696091 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3063696091
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3181225721
Short name T69
Test name
Test status
Simulation time 46527086 ps
CPU time 0.59 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 195252 kb
Host smart-1e81d4c0-6d48-4f2f-a8e4-3a911890583c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181225721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3181225721
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.998828300
Short name T1264
Test name
Test status
Simulation time 13972649 ps
CPU time 0.57 seconds
Started May 16 12:58:55 PM PDT 24
Finished May 16 12:59:30 PM PDT 24
Peak memory 194228 kb
Host smart-0f930e5a-aa28-4626-a250-d3a571e10ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998828300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.998828300
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1625132636
Short name T1231
Test name
Test status
Simulation time 79175675 ps
CPU time 0.72 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:32 PM PDT 24
Peak memory 195876 kb
Host smart-8ec34b99-754e-47ec-a983-3c7234ec5cc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625132636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1625132636
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3722982748
Short name T1273
Test name
Test status
Simulation time 174545587 ps
CPU time 1.11 seconds
Started May 16 12:59:00 PM PDT 24
Finished May 16 12:59:35 PM PDT 24
Peak memory 199696 kb
Host smart-1b31b211-27d7-4cb4-9174-a18ec49d7e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722982748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3722982748
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.922023483
Short name T81
Test name
Test status
Simulation time 326456554 ps
CPU time 1.52 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199168 kb
Host smart-c8a2e963-ca05-4923-b1fe-b5848a86ccdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922023483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.922023483
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3433700709
Short name T1261
Test name
Test status
Simulation time 138563859 ps
CPU time 0.87 seconds
Started May 16 12:58:59 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199724 kb
Host smart-421382c1-15b9-4129-8670-b64e331ab506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433700709 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3433700709
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1864660621
Short name T50
Test name
Test status
Simulation time 15906223 ps
CPU time 0.62 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:32 PM PDT 24
Peak memory 195492 kb
Host smart-85698b9e-b135-44e9-898c-038f800241db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864660621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1864660621
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.946085714
Short name T1302
Test name
Test status
Simulation time 16683496 ps
CPU time 0.58 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 194164 kb
Host smart-5ddb20ad-1e8d-4c84-a449-b2d66df42dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946085714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.946085714
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3498978479
Short name T1245
Test name
Test status
Simulation time 99063469 ps
CPU time 0.74 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 195596 kb
Host smart-a7cee904-9c81-4b07-87f0-c1da7a66e74d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498978479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3498978479
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1978151512
Short name T1200
Test name
Test status
Simulation time 632117130 ps
CPU time 2.1 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:35 PM PDT 24
Peak memory 199928 kb
Host smart-944154e4-7b5f-45ce-acbd-f1f967d43d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978151512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1978151512
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1394152900
Short name T120
Test name
Test status
Simulation time 330767585 ps
CPU time 1.29 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 199340 kb
Host smart-d9c4b0f5-f55c-4959-8c81-f3d044203dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394152900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1394152900
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3986037626
Short name T1187
Test name
Test status
Simulation time 20725072 ps
CPU time 0.66 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 197756 kb
Host smart-9e99c809-3936-4186-89e5-e3502d3747ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986037626 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3986037626
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2088475903
Short name T1243
Test name
Test status
Simulation time 11063362 ps
CPU time 0.56 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 195204 kb
Host smart-fec63d7f-37cd-4986-9444-2188afe746ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088475903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2088475903
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3440032523
Short name T1247
Test name
Test status
Simulation time 13590723 ps
CPU time 0.58 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:32 PM PDT 24
Peak memory 194212 kb
Host smart-010fd9a3-ad8c-4ad2-b34d-c1d269dd584f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440032523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3440032523
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.639056532
Short name T1225
Test name
Test status
Simulation time 111940001 ps
CPU time 0.77 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:31 PM PDT 24
Peak memory 197540 kb
Host smart-b8cb8208-7573-4ac7-81ca-8e86c05b7304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639056532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.639056532
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4052122820
Short name T1241
Test name
Test status
Simulation time 208921758 ps
CPU time 1.51 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199816 kb
Host smart-ee2d9494-fca2-42f7-9e0a-4c24eb8cd30b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052122820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4052122820
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4096756231
Short name T121
Test name
Test status
Simulation time 167138065 ps
CPU time 0.94 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 198768 kb
Host smart-aa06f47e-ff6c-4bf3-b48a-1eedd60a04a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096756231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4096756231
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.108302535
Short name T1251
Test name
Test status
Simulation time 52259172 ps
CPU time 0.86 seconds
Started May 16 12:59:01 PM PDT 24
Finished May 16 12:59:35 PM PDT 24
Peak memory 199676 kb
Host smart-119fd9bb-4158-441b-99da-5c7a15695663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108302535 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.108302535
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1894860731
Short name T1263
Test name
Test status
Simulation time 12139475 ps
CPU time 0.6 seconds
Started May 16 12:58:59 PM PDT 24
Finished May 16 12:59:35 PM PDT 24
Peak memory 195220 kb
Host smart-dc23ce85-ae75-4e5b-bb17-cc29ec4ab95e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894860731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1894860731
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3624117434
Short name T1301
Test name
Test status
Simulation time 31122597 ps
CPU time 0.58 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 194220 kb
Host smart-ddb619ef-114c-40a2-8326-481dc5a6197a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624117434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3624117434
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1321507750
Short name T1262
Test name
Test status
Simulation time 15928863 ps
CPU time 0.71 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 196752 kb
Host smart-678c5501-8023-474d-9f5f-40a43901ba66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321507750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1321507750
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2618538292
Short name T1299
Test name
Test status
Simulation time 428954440 ps
CPU time 2.13 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:35 PM PDT 24
Peak memory 199928 kb
Host smart-af2e1828-def8-4931-93d3-63f68bbc32f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618538292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2618538292
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1096500816
Short name T75
Test name
Test status
Simulation time 414232694 ps
CPU time 0.96 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 198728 kb
Host smart-4c5b5c80-699f-4feb-935c-5edb5fda71a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096500816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1096500816
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2552568608
Short name T1236
Test name
Test status
Simulation time 21690097 ps
CPU time 1.06 seconds
Started May 16 12:59:00 PM PDT 24
Finished May 16 12:59:35 PM PDT 24
Peak memory 199672 kb
Host smart-8e0a88ce-05c1-49a9-8dd4-12e907af2e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552568608 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2552568608
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2470978488
Short name T1268
Test name
Test status
Simulation time 46723989 ps
CPU time 0.57 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 195216 kb
Host smart-901f19da-13cf-4155-8c5f-f4dd11edc995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470978488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2470978488
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1878115671
Short name T1185
Test name
Test status
Simulation time 27826032 ps
CPU time 0.56 seconds
Started May 16 12:58:56 PM PDT 24
Finished May 16 12:59:30 PM PDT 24
Peak memory 194280 kb
Host smart-085f07e4-2f60-4459-8681-9c3b1da915e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878115671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1878115671
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1415297283
Short name T72
Test name
Test status
Simulation time 117808296 ps
CPU time 0.71 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 196692 kb
Host smart-5841230a-fbd6-40bc-ab54-663d7821e3ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415297283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1415297283
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.735980347
Short name T1189
Test name
Test status
Simulation time 95238976 ps
CPU time 2.53 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:36 PM PDT 24
Peak memory 199884 kb
Host smart-44c7a678-112a-4c88-8fca-582ea90fa6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735980347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.735980347
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2741641477
Short name T1226
Test name
Test status
Simulation time 338809378 ps
CPU time 1.41 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 199232 kb
Host smart-da93de2e-58e3-4a79-aaf5-b74076009393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741641477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2741641477
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2227531783
Short name T1216
Test name
Test status
Simulation time 49248204 ps
CPU time 0.78 seconds
Started May 16 12:58:43 PM PDT 24
Finished May 16 12:59:15 PM PDT 24
Peak memory 196128 kb
Host smart-10bde02c-65dc-4fda-be5c-60207c90f463
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227531783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2227531783
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2052363217
Short name T57
Test name
Test status
Simulation time 116659447 ps
CPU time 1.39 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 197436 kb
Host smart-9a4861d9-2c33-44a9-9793-c0bf9342ed9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052363217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2052363217
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2429853697
Short name T1309
Test name
Test status
Simulation time 16135265 ps
CPU time 0.62 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 195232 kb
Host smart-a6413ab7-89ce-4807-9749-fcd81523b193
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429853697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2429853697
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.493993592
Short name T1271
Test name
Test status
Simulation time 26865793 ps
CPU time 0.65 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 197160 kb
Host smart-79b2ad1b-24fa-4316-81dd-4e2c9d574790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493993592 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.493993592
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2540562209
Short name T1292
Test name
Test status
Simulation time 21181579 ps
CPU time 0.64 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 195256 kb
Host smart-20a6ced5-361e-4605-942d-dd64298b5feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540562209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2540562209
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3125907436
Short name T1202
Test name
Test status
Simulation time 13989844 ps
CPU time 0.55 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 194160 kb
Host smart-548fefa6-53ec-4ce1-8eae-871f0e9f3ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125907436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3125907436
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2014643885
Short name T70
Test name
Test status
Simulation time 23932095 ps
CPU time 0.7 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 196976 kb
Host smart-257a7fc6-20fe-4f0f-b11b-7fa71df9f462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014643885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2014643885
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4265703346
Short name T1256
Test name
Test status
Simulation time 140441844 ps
CPU time 0.96 seconds
Started May 16 12:58:44 PM PDT 24
Finished May 16 12:59:17 PM PDT 24
Peak memory 199688 kb
Host smart-66b572df-b41a-43a7-a0c8-f1bce09ce9d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265703346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4265703346
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4262164711
Short name T82
Test name
Test status
Simulation time 432011231 ps
CPU time 1.25 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 198824 kb
Host smart-dab653e6-7249-4bf0-84ee-e4d8900f5bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262164711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4262164711
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3527192106
Short name T1276
Test name
Test status
Simulation time 103653376 ps
CPU time 0.65 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 194248 kb
Host smart-5fed182a-afef-479d-a82c-394cd5915e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527192106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3527192106
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3331347141
Short name T1267
Test name
Test status
Simulation time 51204898 ps
CPU time 0.58 seconds
Started May 16 12:58:59 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 194088 kb
Host smart-121b8386-eaa6-45e0-b4df-1f0aa6b3ab4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331347141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3331347141
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1156869383
Short name T1249
Test name
Test status
Simulation time 41444644 ps
CPU time 0.56 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194280 kb
Host smart-67ac880e-1eaa-461c-9b90-1bee99547a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156869383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1156869383
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2517979091
Short name T1183
Test name
Test status
Simulation time 13134681 ps
CPU time 0.54 seconds
Started May 16 12:59:07 PM PDT 24
Finished May 16 12:59:43 PM PDT 24
Peak memory 194200 kb
Host smart-fbf9251d-55f6-47a4-aeff-af44bf98e301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517979091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2517979091
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4133025273
Short name T1303
Test name
Test status
Simulation time 12611703 ps
CPU time 0.55 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 194216 kb
Host smart-53400adf-1784-4229-92b6-4985d17b1f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133025273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4133025273
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3991070350
Short name T1211
Test name
Test status
Simulation time 12919464 ps
CPU time 0.55 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194184 kb
Host smart-ddea17b8-66fc-45c9-8a82-c79b4f157e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991070350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3991070350
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3035801636
Short name T1214
Test name
Test status
Simulation time 122028811 ps
CPU time 0.56 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 194264 kb
Host smart-c5c06af8-5f1f-4f8d-9544-c5dd40a8dc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035801636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3035801636
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4117416269
Short name T1209
Test name
Test status
Simulation time 13556208 ps
CPU time 0.56 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194208 kb
Host smart-401d3e2e-9505-42a1-a933-d39eb72e6542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117416269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4117416269
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.346612357
Short name T1315
Test name
Test status
Simulation time 113442632 ps
CPU time 0.56 seconds
Started May 16 12:59:06 PM PDT 24
Finished May 16 12:59:42 PM PDT 24
Peak memory 194152 kb
Host smart-46525270-3d0c-4313-aee3-098459322f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346612357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.346612357
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2381332787
Short name T1246
Test name
Test status
Simulation time 13058883 ps
CPU time 0.56 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 194148 kb
Host smart-59ead933-bf23-4cce-b0f4-e10ffbc38482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381332787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2381332787
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3158276012
Short name T1288
Test name
Test status
Simulation time 27931274 ps
CPU time 0.77 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 196192 kb
Host smart-76b90f09-4ad3-4fe5-914a-34aed9f3d9b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158276012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3158276012
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1308248267
Short name T55
Test name
Test status
Simulation time 517467780 ps
CPU time 2.43 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:14 PM PDT 24
Peak memory 197136 kb
Host smart-279d60c6-13eb-49d9-a01a-10e31aec619f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308248267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1308248267
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1776215349
Short name T1270
Test name
Test status
Simulation time 42311462 ps
CPU time 0.6 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 195232 kb
Host smart-ef4915ea-663b-41a0-9972-991f28a91501
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776215349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1776215349
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.543408471
Short name T1298
Test name
Test status
Simulation time 131805914 ps
CPU time 0.91 seconds
Started May 16 12:58:51 PM PDT 24
Finished May 16 12:59:24 PM PDT 24
Peak memory 199692 kb
Host smart-cec3a2a7-0e96-45de-a5f6-e271f33b0860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543408471 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.543408471
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1859649901
Short name T1255
Test name
Test status
Simulation time 60945425 ps
CPU time 0.62 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 195108 kb
Host smart-c5974b0d-e33e-445c-b492-d28d655e0145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859649901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1859649901
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3477743829
Short name T1201
Test name
Test status
Simulation time 21485075 ps
CPU time 0.59 seconds
Started May 16 12:58:43 PM PDT 24
Finished May 16 12:59:15 PM PDT 24
Peak memory 194196 kb
Host smart-14cab258-8996-4dd0-abe7-46782cb034f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477743829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3477743829
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.435421022
Short name T1223
Test name
Test status
Simulation time 22679926 ps
CPU time 0.63 seconds
Started May 16 12:58:44 PM PDT 24
Finished May 16 12:59:18 PM PDT 24
Peak memory 195468 kb
Host smart-f11e8016-dba6-43cc-9293-8aaf0b0d49ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435421022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.435421022
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.285060732
Short name T1312
Test name
Test status
Simulation time 35206114 ps
CPU time 1.18 seconds
Started May 16 12:58:53 PM PDT 24
Finished May 16 12:59:26 PM PDT 24
Peak memory 199912 kb
Host smart-7eea3558-da23-4d71-9900-93a8c84d04d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285060732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.285060732
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2269034337
Short name T1259
Test name
Test status
Simulation time 465038384 ps
CPU time 0.92 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 198628 kb
Host smart-df811d4f-836e-4151-959d-7067c3cbe54c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269034337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2269034337
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3524452671
Short name T1253
Test name
Test status
Simulation time 34770593 ps
CPU time 0.56 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194160 kb
Host smart-96d40f95-d5e9-4bb2-9509-109ff14388a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524452671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3524452671
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.315364900
Short name T1311
Test name
Test status
Simulation time 38343050 ps
CPU time 0.62 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 194272 kb
Host smart-899db666-1306-41ee-940c-6ebccc3747d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315364900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.315364900
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3278075102
Short name T1203
Test name
Test status
Simulation time 12260696 ps
CPU time 0.55 seconds
Started May 16 12:59:06 PM PDT 24
Finished May 16 12:59:42 PM PDT 24
Peak memory 194208 kb
Host smart-2bb5bf4d-836c-4697-8f23-70854d708133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278075102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3278075102
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3463437515
Short name T1220
Test name
Test status
Simulation time 12225665 ps
CPU time 0.56 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194128 kb
Host smart-a7b65d57-939b-433b-9786-63962736db3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463437515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3463437515
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3289343290
Short name T1304
Test name
Test status
Simulation time 13547710 ps
CPU time 0.62 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194284 kb
Host smart-6c5ae64c-c3fc-4afb-9961-cd153726eeb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289343290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3289343290
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4136538513
Short name T1282
Test name
Test status
Simulation time 47599613 ps
CPU time 0.57 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194176 kb
Host smart-4dc137e4-e4e2-44df-a596-5ab8c432cbf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136538513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4136538513
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2284729842
Short name T1193
Test name
Test status
Simulation time 146415948 ps
CPU time 0.55 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194256 kb
Host smart-c7b99018-21f0-4071-8416-c64c54e9a81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284729842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2284729842
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4075512722
Short name T1279
Test name
Test status
Simulation time 28656943 ps
CPU time 0.53 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194080 kb
Host smart-64b9168b-75c3-4a8a-b6cc-e4430c4204dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075512722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4075512722
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1268654907
Short name T1280
Test name
Test status
Simulation time 13459297 ps
CPU time 0.55 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194300 kb
Host smart-0132d34a-dc96-4edd-a1e0-892e288c1661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268654907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1268654907
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3819054449
Short name T1257
Test name
Test status
Simulation time 18024544 ps
CPU time 0.57 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194196 kb
Host smart-89f66536-8cb7-4150-960e-70a34b7e211e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819054449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3819054449
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3367101866
Short name T1294
Test name
Test status
Simulation time 37625669 ps
CPU time 0.64 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 194608 kb
Host smart-fa56731d-5e68-4c47-8ba6-ffe6d323e115
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367101866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3367101866
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.267770522
Short name T1281
Test name
Test status
Simulation time 88405775 ps
CPU time 1.46 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 197444 kb
Host smart-3dae5f78-c2be-4e7c-ae5c-5099b3a171cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267770522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.267770522
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2612766260
Short name T1229
Test name
Test status
Simulation time 33618327 ps
CPU time 0.55 seconds
Started May 16 12:58:51 PM PDT 24
Finished May 16 12:59:24 PM PDT 24
Peak memory 195248 kb
Host smart-058832c7-f4b0-4eb3-95fa-073442cb616d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612766260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2612766260
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3622672066
Short name T1291
Test name
Test status
Simulation time 36324307 ps
CPU time 0.73 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 198692 kb
Host smart-f18e2057-0f8d-421d-996e-d450f7275986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622672066 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3622672066
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2733219058
Short name T1260
Test name
Test status
Simulation time 37822996 ps
CPU time 0.64 seconds
Started May 16 12:58:41 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 195468 kb
Host smart-7920ca3b-7dc6-4d59-a527-d64d0de0e350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733219058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2733219058
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3899533571
Short name T1248
Test name
Test status
Simulation time 29928040 ps
CPU time 0.55 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 194272 kb
Host smart-19492ea9-439c-4608-be75-213d78272d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899533571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3899533571
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2239223576
Short name T1208
Test name
Test status
Simulation time 25224606 ps
CPU time 0.72 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 195452 kb
Host smart-8c09efda-1848-46c3-a267-99db28a72d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239223576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2239223576
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1088006888
Short name T1307
Test name
Test status
Simulation time 253838885 ps
CPU time 1.6 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 199884 kb
Host smart-c5e5c43b-c4a7-46e4-936b-4dcf1b9dfacd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088006888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1088006888
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4012639098
Short name T122
Test name
Test status
Simulation time 180013051 ps
CPU time 0.84 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 198532 kb
Host smart-589a8292-2397-4f43-914c-895c8e50cc46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012639098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4012639098
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1198397697
Short name T1206
Test name
Test status
Simulation time 23897046 ps
CPU time 0.61 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194244 kb
Host smart-386b94d5-7ae9-4dbf-8464-6cd27f34676d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198397697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1198397697
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.168510652
Short name T1237
Test name
Test status
Simulation time 51719622 ps
CPU time 0.55 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194252 kb
Host smart-e2ebf5e3-8705-4e1b-94a9-734fff37cc7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168510652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.168510652
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.109535878
Short name T1212
Test name
Test status
Simulation time 12147000 ps
CPU time 0.55 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194272 kb
Host smart-7508e4d2-97ee-4df9-8805-adb8815ab56f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109535878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.109535878
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2194536706
Short name T1297
Test name
Test status
Simulation time 40570324 ps
CPU time 0.55 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194140 kb
Host smart-5806758e-7b7d-449c-8d1c-18b34ee3b19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194536706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2194536706
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1824050964
Short name T1186
Test name
Test status
Simulation time 15669946 ps
CPU time 0.55 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194284 kb
Host smart-142c74e8-9617-4d69-8323-b160df95bb5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824050964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1824050964
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.321867690
Short name T1199
Test name
Test status
Simulation time 34556332 ps
CPU time 0.55 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194188 kb
Host smart-0418e153-de6d-448c-98ad-9fb27796cb46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321867690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.321867690
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3703081905
Short name T1286
Test name
Test status
Simulation time 33417483 ps
CPU time 0.53 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 194128 kb
Host smart-a1ecc68a-86a0-4aa2-88e3-c75ad9e92f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703081905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3703081905
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2476850327
Short name T1285
Test name
Test status
Simulation time 10640319 ps
CPU time 0.58 seconds
Started May 16 12:59:07 PM PDT 24
Finished May 16 12:59:43 PM PDT 24
Peak memory 194216 kb
Host smart-bf026e29-a366-4b47-a8be-829bc21fdb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476850327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2476850327
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2448563368
Short name T1230
Test name
Test status
Simulation time 157694318 ps
CPU time 0.63 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:46 PM PDT 24
Peak memory 194288 kb
Host smart-9127c55f-24cf-4a08-b9b0-a15de73d01d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448563368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2448563368
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3055191987
Short name T1296
Test name
Test status
Simulation time 14129250 ps
CPU time 0.55 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 194192 kb
Host smart-1b6bde5b-2ab9-42a1-a771-6171c1d84a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055191987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3055191987
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.169167113
Short name T1289
Test name
Test status
Simulation time 31207327 ps
CPU time 0.83 seconds
Started May 16 12:58:38 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 199660 kb
Host smart-2ecaa14f-5960-4556-b482-8e53bb3918d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169167113 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.169167113
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3534674579
Short name T54
Test name
Test status
Simulation time 17740963 ps
CPU time 0.61 seconds
Started May 16 12:58:40 PM PDT 24
Finished May 16 12:59:13 PM PDT 24
Peak memory 195560 kb
Host smart-c0653e69-a8b9-46f0-891b-bf8da695d00a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534674579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3534674579
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2674163462
Short name T1239
Test name
Test status
Simulation time 23615165 ps
CPU time 0.57 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 194208 kb
Host smart-00fde552-35ab-41a7-ae86-eb28507885dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674163462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2674163462
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3077046985
Short name T1272
Test name
Test status
Simulation time 113610959 ps
CPU time 0.82 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:12 PM PDT 24
Peak memory 197408 kb
Host smart-75553996-9170-4538-afdb-e1d07dfdb8b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077046985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3077046985
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1402642675
Short name T1228
Test name
Test status
Simulation time 161672540 ps
CPU time 1.41 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:26 PM PDT 24
Peak memory 199908 kb
Host smart-341a6be7-15f7-41b4-9580-07becb190f70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402642675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1402642675
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.318897316
Short name T78
Test name
Test status
Simulation time 134702901 ps
CPU time 1.19 seconds
Started May 16 12:58:51 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 199232 kb
Host smart-563617a1-22ec-42b1-b947-6d97342588d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318897316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.318897316
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.133794338
Short name T1192
Test name
Test status
Simulation time 68665365 ps
CPU time 1.13 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 199840 kb
Host smart-e96b38b1-7030-4653-b4c5-237f97229f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133794338 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.133794338
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1435307425
Short name T53
Test name
Test status
Simulation time 16579095 ps
CPU time 0.6 seconds
Started May 16 12:58:57 PM PDT 24
Finished May 16 12:59:33 PM PDT 24
Peak memory 195244 kb
Host smart-d27ae36c-2c49-4d72-8e38-b3fa7851cefc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435307425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1435307425
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1672690277
Short name T1234
Test name
Test status
Simulation time 124240735 ps
CPU time 0.58 seconds
Started May 16 12:58:52 PM PDT 24
Finished May 16 12:59:25 PM PDT 24
Peak memory 194196 kb
Host smart-431ced64-0376-4109-8f00-b48b21822a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672690277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1672690277
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3779978354
Short name T1300
Test name
Test status
Simulation time 18462177 ps
CPU time 0.75 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 195548 kb
Host smart-b641b428-1884-4195-a6a8-eaf51d175d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779978354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3779978354
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2326776372
Short name T1219
Test name
Test status
Simulation time 279332885 ps
CPU time 2.6 seconds
Started May 16 12:58:39 PM PDT 24
Finished May 16 12:59:14 PM PDT 24
Peak memory 199912 kb
Host smart-450b7713-4fee-43c9-8cb2-e744baf6500b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326776372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2326776372
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1647162993
Short name T1235
Test name
Test status
Simulation time 30104867 ps
CPU time 1.35 seconds
Started May 16 12:58:49 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 199916 kb
Host smart-e2defbbd-e70c-475c-8f10-6f9db81df48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647162993 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1647162993
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3139948743
Short name T1293
Test name
Test status
Simulation time 50402541 ps
CPU time 0.54 seconds
Started May 16 12:58:50 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 195244 kb
Host smart-b4892772-9d3b-465c-88f0-527839f163a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139948743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3139948743
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.4251479709
Short name T1218
Test name
Test status
Simulation time 15685807 ps
CPU time 0.55 seconds
Started May 16 12:58:58 PM PDT 24
Finished May 16 12:59:34 PM PDT 24
Peak memory 194180 kb
Host smart-45d9ced2-899f-422b-b99f-9aaa32282a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251479709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4251479709
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.861596201
Short name T1227
Test name
Test status
Simulation time 115594988 ps
CPU time 0.73 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:22 PM PDT 24
Peak memory 195728 kb
Host smart-5477c0f9-c62e-404c-96fc-69b43418add0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861596201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.861596201
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4166346071
Short name T1295
Test name
Test status
Simulation time 204546254 ps
CPU time 1.33 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:22 PM PDT 24
Peak memory 199812 kb
Host smart-1c70218a-1448-479b-97e2-c4000e02b315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166346071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4166346071
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2116321344
Short name T76
Test name
Test status
Simulation time 53420183 ps
CPU time 1.04 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 199056 kb
Host smart-8753710b-ee7f-4ca6-b88b-3607c3e3ab4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116321344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2116321344
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3314204324
Short name T1284
Test name
Test status
Simulation time 29376171 ps
CPU time 0.85 seconds
Started May 16 12:58:51 PM PDT 24
Finished May 16 12:59:24 PM PDT 24
Peak memory 199692 kb
Host smart-5048ded0-f2cb-4517-bb2f-266ed1576422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314204324 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3314204324
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3713281808
Short name T1290
Test name
Test status
Simulation time 16204709 ps
CPU time 0.64 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 195440 kb
Host smart-ac264d4b-fdcc-4922-bf5f-e2a436ab8f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713281808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3713281808
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2651249102
Short name T1196
Test name
Test status
Simulation time 11281203 ps
CPU time 0.63 seconds
Started May 16 12:58:45 PM PDT 24
Finished May 16 12:59:19 PM PDT 24
Peak memory 194164 kb
Host smart-48c806d8-e512-4748-af15-953a37bcf4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651249102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2651249102
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.426483519
Short name T73
Test name
Test status
Simulation time 36630942 ps
CPU time 0.63 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 195364 kb
Host smart-ca765256-0a7c-4600-8b4c-20495d34c0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426483519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.426483519
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1162700342
Short name T1306
Test name
Test status
Simulation time 127284372 ps
CPU time 1.57 seconds
Started May 16 12:58:48 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 199904 kb
Host smart-7f252246-0ccf-4abf-9a3f-25514ccfb2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162700342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1162700342
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1126320028
Short name T1233
Test name
Test status
Simulation time 33894423 ps
CPU time 0.62 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:22 PM PDT 24
Peak memory 197372 kb
Host smart-40532cef-d812-49ce-bc92-4fc73cdcf0f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126320028 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1126320028
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1126327940
Short name T67
Test name
Test status
Simulation time 22278360 ps
CPU time 0.58 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:22 PM PDT 24
Peak memory 195244 kb
Host smart-9131fc4f-bb46-4ea9-931c-ec541224d22d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126327940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1126327940
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2852623586
Short name T1190
Test name
Test status
Simulation time 13015705 ps
CPU time 0.61 seconds
Started May 16 12:58:47 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 194184 kb
Host smart-41ca444b-3865-46af-ae2d-b1eeef986b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852623586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2852623586
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1286742451
Short name T74
Test name
Test status
Simulation time 16991558 ps
CPU time 0.77 seconds
Started May 16 12:58:49 PM PDT 24
Finished May 16 12:59:23 PM PDT 24
Peak memory 196872 kb
Host smart-e3214583-e4a6-48d7-9aa7-d3c32a4723ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286742451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1286742451
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.170078282
Short name T1195
Test name
Test status
Simulation time 41178260 ps
CPU time 1.11 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 199920 kb
Host smart-70fcf5ca-2dc5-4a00-9be4-d66c7334b8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170078282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.170078282
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2031246115
Short name T77
Test name
Test status
Simulation time 264455126 ps
CPU time 0.98 seconds
Started May 16 12:58:46 PM PDT 24
Finished May 16 12:59:21 PM PDT 24
Peak memory 199144 kb
Host smart-2f5023c2-3ede-4c77-8b98-c74109cbe108
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031246115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2031246115
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1952953213
Short name T1108
Test name
Test status
Simulation time 35932521 ps
CPU time 0.56 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:00:49 PM PDT 24
Peak memory 195276 kb
Host smart-608eeb61-d074-49b4-8db6-74a308f0862c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952953213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1952953213
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3712034213
Short name T721
Test name
Test status
Simulation time 215646374350 ps
CPU time 60.87 seconds
Started May 16 01:00:04 PM PDT 24
Finished May 16 01:01:47 PM PDT 24
Peak memory 200496 kb
Host smart-570627e4-de3f-4d14-b8a2-65ca3a09a5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712034213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3712034213
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1274653950
Short name T1161
Test name
Test status
Simulation time 104316505244 ps
CPU time 212.09 seconds
Started May 16 01:00:02 PM PDT 24
Finished May 16 01:04:16 PM PDT 24
Peak memory 200388 kb
Host smart-6ac0fc5c-591c-4d1b-b0d4-0a82edfa7299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274653950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1274653950
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2187234154
Short name T953
Test name
Test status
Simulation time 138415325899 ps
CPU time 70.35 seconds
Started May 16 01:00:05 PM PDT 24
Finished May 16 01:01:57 PM PDT 24
Peak memory 200512 kb
Host smart-e97f8aaa-b672-4dd8-a827-e706f7af49f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187234154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2187234154
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1184661817
Short name T799
Test name
Test status
Simulation time 53280542515 ps
CPU time 26.14 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:01:13 PM PDT 24
Peak memory 200272 kb
Host smart-2078e7f1-8db3-4f48-a79d-86f0c6624a9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184661817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1184661817
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.564495895
Short name T482
Test name
Test status
Simulation time 65800037869 ps
CPU time 296.1 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:05:44 PM PDT 24
Peak memory 200432 kb
Host smart-9210789b-9e2f-464e-bc3d-9dd93e183754
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564495895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.564495895
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2249250792
Short name T913
Test name
Test status
Simulation time 1140602934 ps
CPU time 3.14 seconds
Started May 16 01:00:10 PM PDT 24
Finished May 16 01:00:53 PM PDT 24
Peak memory 197840 kb
Host smart-f0c3e1f0-5196-4173-bb80-a9cb12245e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249250792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2249250792
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.20756989
Short name T1078
Test name
Test status
Simulation time 50688357718 ps
CPU time 82.46 seconds
Started May 16 01:00:05 PM PDT 24
Finished May 16 01:02:09 PM PDT 24
Peak memory 200640 kb
Host smart-ba15b1fb-0c88-456e-a996-34fe50e91d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20756989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.20756989
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.4183930389
Short name T928
Test name
Test status
Simulation time 10880660004 ps
CPU time 160.93 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 200380 kb
Host smart-28abe340-e8e6-4131-923f-fdb622f4810e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183930389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4183930389
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1272846455
Short name T400
Test name
Test status
Simulation time 2328986919 ps
CPU time 4.16 seconds
Started May 16 01:00:04 PM PDT 24
Finished May 16 01:00:51 PM PDT 24
Peak memory 198936 kb
Host smart-1e738802-c34d-471c-852d-8a55719abb3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272846455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1272846455
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.290802118
Short name T930
Test name
Test status
Simulation time 29065239068 ps
CPU time 64.49 seconds
Started May 16 01:00:05 PM PDT 24
Finished May 16 01:01:51 PM PDT 24
Peak memory 200484 kb
Host smart-8138edb6-1c2a-4d7f-bb5a-972bd7453eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290802118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.290802118
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.231902662
Short name T517
Test name
Test status
Simulation time 5783658094 ps
CPU time 10.44 seconds
Started May 16 01:00:04 PM PDT 24
Finished May 16 01:00:56 PM PDT 24
Peak memory 196496 kb
Host smart-3b3b0151-b459-4f97-b14c-9abe5f34ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231902662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.231902662
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2586442316
Short name T86
Test name
Test status
Simulation time 122392446 ps
CPU time 0.84 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:00:49 PM PDT 24
Peak memory 218952 kb
Host smart-39d29b31-b15f-4ec6-a56b-e2b8818072d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586442316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2586442316
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2737641152
Short name T802
Test name
Test status
Simulation time 5465204432 ps
CPU time 11.25 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:00:58 PM PDT 24
Peak memory 200012 kb
Host smart-2cf20cca-272c-4066-84e6-92101e5dfda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737641152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2737641152
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.4240325667
Short name T876
Test name
Test status
Simulation time 434486473385 ps
CPU time 518.71 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:09:35 PM PDT 24
Peak memory 200516 kb
Host smart-7490a90a-04f1-474b-9b33-16a00d209b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240325667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4240325667
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4266001882
Short name T929
Test name
Test status
Simulation time 139209221013 ps
CPU time 2297.12 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:39:06 PM PDT 24
Peak memory 226840 kb
Host smart-f5793955-f3c1-484d-b12e-2c48e95bac8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266001882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4266001882
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2040212077
Short name T968
Test name
Test status
Simulation time 6825566217 ps
CPU time 19.65 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:01:08 PM PDT 24
Peak memory 200300 kb
Host smart-13792c19-2ea8-4377-bd2f-42d8eb62f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040212077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2040212077
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1273165851
Short name T993
Test name
Test status
Simulation time 113605117637 ps
CPU time 98.5 seconds
Started May 16 01:00:03 PM PDT 24
Finished May 16 01:02:24 PM PDT 24
Peak memory 200512 kb
Host smart-0bce2332-48cb-409b-9a10-b99c35ac51bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273165851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1273165851
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.503298879
Short name T381
Test name
Test status
Simulation time 14624108 ps
CPU time 0.56 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:00:48 PM PDT 24
Peak memory 195848 kb
Host smart-0712ce1d-5f00-4cab-980c-88aa1b8b5162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503298879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.503298879
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2411590149
Short name T918
Test name
Test status
Simulation time 90348190140 ps
CPU time 35.1 seconds
Started May 16 01:00:03 PM PDT 24
Finished May 16 01:01:20 PM PDT 24
Peak memory 200488 kb
Host smart-1dd9d932-6c41-4a33-a58e-5104694d67a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411590149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2411590149
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4091726428
Short name T1106
Test name
Test status
Simulation time 239162178680 ps
CPU time 45.34 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:01:34 PM PDT 24
Peak memory 200452 kb
Host smart-a6e3026a-a629-454d-bdcf-9aa4e5886fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091726428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4091726428
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1557439768
Short name T609
Test name
Test status
Simulation time 40355107874 ps
CPU time 17.28 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:01:04 PM PDT 24
Peak memory 200208 kb
Host smart-f56260ab-0394-47e6-9825-1089321abdcf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557439768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1557439768
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1632731456
Short name T317
Test name
Test status
Simulation time 127917671577 ps
CPU time 373.87 seconds
Started May 16 01:00:04 PM PDT 24
Finished May 16 01:07:00 PM PDT 24
Peak memory 200476 kb
Host smart-1fccb2f1-269a-4d95-904e-c086bb7fef3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632731456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1632731456
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2067377619
Short name T635
Test name
Test status
Simulation time 248036055 ps
CPU time 0.84 seconds
Started May 16 01:00:03 PM PDT 24
Finished May 16 01:00:46 PM PDT 24
Peak memory 198636 kb
Host smart-12297f8e-f939-49fd-b918-ad4a55f13da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067377619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2067377619
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.704246794
Short name T886
Test name
Test status
Simulation time 26044288141 ps
CPU time 20.27 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:16 PM PDT 24
Peak memory 200676 kb
Host smart-0480a58a-376f-41c6-8199-faf3b532e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704246794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.704246794
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3403132694
Short name T302
Test name
Test status
Simulation time 7564491238 ps
CPU time 417.69 seconds
Started May 16 01:00:10 PM PDT 24
Finished May 16 01:07:48 PM PDT 24
Peak memory 200460 kb
Host smart-0ab5724e-9bac-481c-9cf1-c9c6d9ddeec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403132694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3403132694
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.311017211
Short name T342
Test name
Test status
Simulation time 6925777174 ps
CPU time 18.66 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:14 PM PDT 24
Peak memory 198624 kb
Host smart-05c5666b-5b67-47a7-b792-34c418e98efe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311017211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.311017211
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4130275886
Short name T1141
Test name
Test status
Simulation time 69533937909 ps
CPU time 19 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:01:06 PM PDT 24
Peak memory 200472 kb
Host smart-12bea6bb-96c0-4df4-a105-9a91863bd181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130275886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4130275886
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.697258077
Short name T702
Test name
Test status
Simulation time 3211409965 ps
CPU time 1.94 seconds
Started May 16 01:00:03 PM PDT 24
Finished May 16 01:00:47 PM PDT 24
Peak memory 196264 kb
Host smart-9d07337b-4b82-49fb-a6b6-55b791a7c81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697258077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.697258077
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.413632899
Short name T268
Test name
Test status
Simulation time 732079731 ps
CPU time 1.03 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:00:48 PM PDT 24
Peak memory 198976 kb
Host smart-81b8bd81-73e3-45b9-9d1c-4719ab153a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413632899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.413632899
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3922968577
Short name T652
Test name
Test status
Simulation time 672475054572 ps
CPU time 462 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:08:30 PM PDT 24
Peak memory 226316 kb
Host smart-2f2fb924-77ad-4ade-b6f0-2fc45531651a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922968577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3922968577
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.965284414
Short name T539
Test name
Test status
Simulation time 1085147178 ps
CPU time 4.42 seconds
Started May 16 01:00:05 PM PDT 24
Finished May 16 01:00:51 PM PDT 24
Peak memory 199932 kb
Host smart-f732cd05-5e51-4aba-a078-cd61518878e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965284414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.965284414
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1155188576
Short name T1033
Test name
Test status
Simulation time 27162738672 ps
CPU time 37.41 seconds
Started May 16 01:00:10 PM PDT 24
Finished May 16 01:01:27 PM PDT 24
Peak memory 200408 kb
Host smart-cbfdbfa7-4220-47c1-a7ff-6c4a22c16091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155188576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1155188576
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.876674264
Short name T1107
Test name
Test status
Simulation time 25690179 ps
CPU time 0.55 seconds
Started May 16 01:00:44 PM PDT 24
Finished May 16 01:01:17 PM PDT 24
Peak memory 194776 kb
Host smart-72bb7c94-53d0-4842-9ae0-070bba4893fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876674264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.876674264
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1660560187
Short name T923
Test name
Test status
Simulation time 21369296353 ps
CPU time 32.53 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 200496 kb
Host smart-5ecd326b-094d-4460-82cb-8f4f89644576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660560187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1660560187
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1848734824
Short name T1062
Test name
Test status
Simulation time 91687960573 ps
CPU time 173.82 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:04:09 PM PDT 24
Peak memory 200428 kb
Host smart-657d1a81-b93a-4e8e-9d01-746d3154e786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848734824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1848734824
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3031591975
Short name T751
Test name
Test status
Simulation time 33879865126 ps
CPU time 30.63 seconds
Started May 16 01:00:38 PM PDT 24
Finished May 16 01:01:44 PM PDT 24
Peak memory 198276 kb
Host smart-9f4318da-1486-4a23-9a95-6e8017dcd961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031591975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3031591975
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.412458494
Short name T290
Test name
Test status
Simulation time 43340550371 ps
CPU time 23.9 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:01:40 PM PDT 24
Peak memory 200488 kb
Host smart-5d5dab67-0c22-4cb8-80dc-c8a280f382b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412458494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.412458494
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2400133116
Short name T481
Test name
Test status
Simulation time 221037467338 ps
CPU time 231.86 seconds
Started May 16 01:00:43 PM PDT 24
Finished May 16 01:05:08 PM PDT 24
Peak memory 200440 kb
Host smart-551f7486-3054-431c-b2b5-3c37815b1ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400133116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2400133116
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2038250286
Short name T102
Test name
Test status
Simulation time 11727385047 ps
CPU time 25.08 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:01:41 PM PDT 24
Peak memory 200180 kb
Host smart-b33e37d4-8d65-491e-9365-9a84e322788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038250286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2038250286
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2955398525
Short name T396
Test name
Test status
Simulation time 57374188597 ps
CPU time 95.05 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 208804 kb
Host smart-d3c4c901-f34c-4d64-93f4-aac9d84378c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955398525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2955398525
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2502950546
Short name T1084
Test name
Test status
Simulation time 35500431810 ps
CPU time 418.25 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:08:14 PM PDT 24
Peak memory 200476 kb
Host smart-a7788030-aad0-45e7-8baa-abc277d75361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2502950546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2502950546
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3128122984
Short name T331
Test name
Test status
Simulation time 5177099271 ps
CPU time 9.73 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:01:26 PM PDT 24
Peak memory 198616 kb
Host smart-3d7dbee7-e14d-4d01-ac1f-667b87d7d555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128122984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3128122984
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3028749588
Short name T393
Test name
Test status
Simulation time 87723564127 ps
CPU time 109.02 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 200276 kb
Host smart-ad2d4ef8-e729-4dbd-b540-d05f71b09840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028749588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3028749588
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3946412192
Short name T1001
Test name
Test status
Simulation time 5021017545 ps
CPU time 8.02 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:01:24 PM PDT 24
Peak memory 196268 kb
Host smart-0ff75a53-e8f2-41d1-b84b-a2e25d289fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946412192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3946412192
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2352232726
Short name T806
Test name
Test status
Simulation time 497106778 ps
CPU time 1.45 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:01:12 PM PDT 24
Peak memory 198784 kb
Host smart-acbfb35c-55b5-419c-92e9-10e9c3144169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352232726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2352232726
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2146372289
Short name T597
Test name
Test status
Simulation time 152388827601 ps
CPU time 329.38 seconds
Started May 16 01:00:43 PM PDT 24
Finished May 16 01:06:46 PM PDT 24
Peak memory 200492 kb
Host smart-8a1b4f35-f30b-4a23-8896-d788de818503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146372289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2146372289
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.258707889
Short name T319
Test name
Test status
Simulation time 807407886 ps
CPU time 1.56 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:16 PM PDT 24
Peak memory 198892 kb
Host smart-748ff6ad-c32d-4f24-ab93-fcf40ac9c7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258707889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.258707889
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.654094064
Short name T310
Test name
Test status
Simulation time 31151293125 ps
CPU time 13.86 seconds
Started May 16 01:00:31 PM PDT 24
Finished May 16 01:01:21 PM PDT 24
Peak memory 200488 kb
Host smart-08977197-9d9f-48f5-9c40-b0bf59c835c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654094064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.654094064
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2732005256
Short name T546
Test name
Test status
Simulation time 32400591222 ps
CPU time 28.26 seconds
Started May 16 01:03:41 PM PDT 24
Finished May 16 01:04:17 PM PDT 24
Peak memory 200484 kb
Host smart-1c6390df-a9a1-42a2-9e6d-83c19195f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732005256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2732005256
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2537485109
Short name T600
Test name
Test status
Simulation time 34475501573 ps
CPU time 57.53 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:04:45 PM PDT 24
Peak memory 200424 kb
Host smart-f1a7534e-64a2-4852-b71a-e41d938cc096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537485109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2537485109
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1893234363
Short name T1151
Test name
Test status
Simulation time 115813940459 ps
CPU time 15.24 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:04:03 PM PDT 24
Peak memory 200500 kb
Host smart-abf771b0-9262-421f-9dcf-14a19e0607c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893234363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1893234363
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3634885961
Short name T742
Test name
Test status
Simulation time 340504939745 ps
CPU time 611.79 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:14:00 PM PDT 24
Peak memory 200416 kb
Host smart-190956d9-5571-4d53-8130-d71b5d6d9b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634885961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3634885961
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1012490104
Short name T535
Test name
Test status
Simulation time 149467979463 ps
CPU time 199.52 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:07:08 PM PDT 24
Peak memory 200428 kb
Host smart-e940c596-9b68-4dd8-82a7-cdb9d6d46b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012490104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1012490104
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1463707257
Short name T58
Test name
Test status
Simulation time 37358908089 ps
CPU time 75.61 seconds
Started May 16 01:03:46 PM PDT 24
Finished May 16 01:05:08 PM PDT 24
Peak memory 200460 kb
Host smart-08a08bda-ea66-48ea-8d10-5dfe6034396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463707257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1463707257
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.192743496
Short name T378
Test name
Test status
Simulation time 9915404845 ps
CPU time 15.44 seconds
Started May 16 01:03:45 PM PDT 24
Finished May 16 01:04:07 PM PDT 24
Peak memory 200332 kb
Host smart-5156d506-5697-4870-af57-c44eb1be5e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192743496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.192743496
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4070585283
Short name T773
Test name
Test status
Simulation time 36471089906 ps
CPU time 62.27 seconds
Started May 16 01:03:41 PM PDT 24
Finished May 16 01:04:51 PM PDT 24
Peak memory 200288 kb
Host smart-93d010e6-42b4-4999-9af9-90577c2e34c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070585283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4070585283
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2963946265
Short name T1032
Test name
Test status
Simulation time 43565169 ps
CPU time 0.55 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:16 PM PDT 24
Peak memory 195572 kb
Host smart-d394f705-83e0-4064-a99e-da6daf87c74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963946265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2963946265
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2476481247
Short name T1066
Test name
Test status
Simulation time 56288015883 ps
CPU time 44.76 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:02:00 PM PDT 24
Peak memory 200508 kb
Host smart-dfff1678-7a53-4220-8773-125f4583870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476481247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2476481247
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.223903528
Short name T715
Test name
Test status
Simulation time 52399657052 ps
CPU time 42.99 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 200252 kb
Host smart-e3a6983d-8da7-4399-ac5c-1aa446e8e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223903528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.223903528
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.974973318
Short name T603
Test name
Test status
Simulation time 30002571121 ps
CPU time 47.29 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:02:03 PM PDT 24
Peak memory 200464 kb
Host smart-82fc6da2-92c9-4a4f-bc62-c130758f6af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974973318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.974973318
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2280697533
Short name T944
Test name
Test status
Simulation time 2688258175 ps
CPU time 1.64 seconds
Started May 16 01:00:39 PM PDT 24
Finished May 16 01:01:16 PM PDT 24
Peak memory 197168 kb
Host smart-b77b1dae-bcd2-4d30-bf79-6497d49fad47
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280697533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2280697533
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2172333944
Short name T1073
Test name
Test status
Simulation time 147135809123 ps
CPU time 343.58 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:06:59 PM PDT 24
Peak memory 200228 kb
Host smart-1f253b3e-8934-4381-a729-f7b56e4d6413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172333944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2172333944
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4202081058
Short name T689
Test name
Test status
Simulation time 6699273450 ps
CPU time 9.52 seconds
Started May 16 01:00:45 PM PDT 24
Finished May 16 01:01:27 PM PDT 24
Peak memory 200024 kb
Host smart-be9aaf45-90cc-4d1c-9a4c-c0ec3dca48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202081058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4202081058
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.792846308
Short name T951
Test name
Test status
Simulation time 69419429184 ps
CPU time 67.21 seconds
Started May 16 01:00:39 PM PDT 24
Finished May 16 01:02:21 PM PDT 24
Peak memory 200676 kb
Host smart-6df226b7-4aee-4451-a3fe-18ecae94dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792846308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.792846308
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.840767713
Short name T575
Test name
Test status
Simulation time 11760291951 ps
CPU time 187.62 seconds
Started May 16 01:00:43 PM PDT 24
Finished May 16 01:04:24 PM PDT 24
Peak memory 200444 kb
Host smart-fc657885-a451-468b-af63-75ac0d94936e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840767713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.840767713
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2231206273
Short name T17
Test name
Test status
Simulation time 5458987777 ps
CPU time 53.64 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:02:09 PM PDT 24
Peak memory 198648 kb
Host smart-3b2a9fef-d0d3-4c22-b8ce-20eff2662202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231206273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2231206273
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2232804820
Short name T24
Test name
Test status
Simulation time 47328752738 ps
CPU time 68.2 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:02:24 PM PDT 24
Peak memory 196468 kb
Host smart-ae85f0c7-0bb1-4d47-b73b-2298400efd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232804820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2232804820
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3611811328
Short name T382
Test name
Test status
Simulation time 6015789506 ps
CPU time 15.95 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:31 PM PDT 24
Peak memory 199652 kb
Host smart-981678d0-6d5b-4e80-885a-5484670bc103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611811328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3611811328
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.769495236
Short name T110
Test name
Test status
Simulation time 184016249473 ps
CPU time 799.41 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:14:35 PM PDT 24
Peak memory 208956 kb
Host smart-49ae4f9d-1ec7-4288-b000-752e7e4e55df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769495236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.769495236
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1830102054
Short name T909
Test name
Test status
Simulation time 551786537829 ps
CPU time 296.74 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:06:12 PM PDT 24
Peak memory 217228 kb
Host smart-af880d21-bde4-4ed9-86be-f08ff6a3ea10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830102054 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1830102054
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2226531247
Short name T926
Test name
Test status
Simulation time 6988850070 ps
CPU time 11.78 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:26 PM PDT 24
Peak memory 199736 kb
Host smart-17639c09-1cf9-4d24-b022-d6ae676eb8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226531247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2226531247
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3599572565
Short name T706
Test name
Test status
Simulation time 33162450296 ps
CPU time 44.84 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:02:00 PM PDT 24
Peak memory 200408 kb
Host smart-2c383018-1f14-4ca6-a493-686a427b2ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599572565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3599572565
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.4138841867
Short name T242
Test name
Test status
Simulation time 131308590184 ps
CPU time 72.21 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:05:00 PM PDT 24
Peak memory 200420 kb
Host smart-6b83726a-890c-487a-87f9-963f8c4401a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138841867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4138841867
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.526070929
Short name T1164
Test name
Test status
Simulation time 23390590194 ps
CPU time 35.32 seconds
Started May 16 01:03:41 PM PDT 24
Finished May 16 01:04:24 PM PDT 24
Peak memory 200468 kb
Host smart-c70f9db7-dcfe-443b-9e85-e96ecbae7d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526070929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.526070929
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.878716294
Short name T162
Test name
Test status
Simulation time 20688128726 ps
CPU time 25.23 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:04:14 PM PDT 24
Peak memory 200468 kb
Host smart-a05b9b76-7cda-4893-aaf2-0df7cba236b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878716294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.878716294
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1941457984
Short name T507
Test name
Test status
Simulation time 62762975484 ps
CPU time 25.34 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:04:13 PM PDT 24
Peak memory 200480 kb
Host smart-a0941b93-a2dc-4cd3-8c60-4ea7eef24c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941457984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1941457984
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2359505384
Short name T437
Test name
Test status
Simulation time 16504231933 ps
CPU time 15.59 seconds
Started May 16 01:03:47 PM PDT 24
Finished May 16 01:04:09 PM PDT 24
Peak memory 200500 kb
Host smart-5a5c32f9-0995-404b-a4c0-ba77852c44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359505384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2359505384
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1771406949
Short name T168
Test name
Test status
Simulation time 142382420950 ps
CPU time 108.85 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:05:37 PM PDT 24
Peak memory 200444 kb
Host smart-555ba933-c956-4521-8552-7f59caf7c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771406949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1771406949
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1458967527
Short name T938
Test name
Test status
Simulation time 43175121216 ps
CPU time 52.21 seconds
Started May 16 01:03:51 PM PDT 24
Finished May 16 01:04:49 PM PDT 24
Peak memory 200432 kb
Host smart-b84e7040-3f9c-4a74-ad59-fb5701ce87e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458967527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1458967527
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3700115222
Short name T730
Test name
Test status
Simulation time 80471179091 ps
CPU time 114.21 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:05:50 PM PDT 24
Peak memory 200460 kb
Host smart-074c6e71-9b9f-4d36-a7b9-6a0a08e10d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700115222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3700115222
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2663334454
Short name T581
Test name
Test status
Simulation time 12172582108 ps
CPU time 24 seconds
Started May 16 01:03:53 PM PDT 24
Finished May 16 01:04:23 PM PDT 24
Peak memory 200440 kb
Host smart-2da40a60-2696-4bd4-a7ae-d10910a067e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663334454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2663334454
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1096560499
Short name T873
Test name
Test status
Simulation time 12834383 ps
CPU time 0.54 seconds
Started May 16 01:00:46 PM PDT 24
Finished May 16 01:01:19 PM PDT 24
Peak memory 195768 kb
Host smart-134a356f-b136-4bc2-8a9b-73d97b9461ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096560499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1096560499
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.4206116247
Short name T167
Test name
Test status
Simulation time 81404625869 ps
CPU time 15.66 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:01:31 PM PDT 24
Peak memory 200452 kb
Host smart-01caddf5-d36e-4a0c-bcc1-5b889331b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206116247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.4206116247
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2353306832
Short name T723
Test name
Test status
Simulation time 278860898134 ps
CPU time 54.77 seconds
Started May 16 01:00:39 PM PDT 24
Finished May 16 01:02:09 PM PDT 24
Peak memory 200472 kb
Host smart-8eb9a925-cc71-4dfc-b951-1071b56dcd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353306832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2353306832
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1749389700
Short name T459
Test name
Test status
Simulation time 10484216191 ps
CPU time 3.68 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:18 PM PDT 24
Peak memory 197144 kb
Host smart-85f09c62-c0dd-46a8-8281-9d97efdd2255
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749389700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1749389700
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1849479710
Short name T848
Test name
Test status
Simulation time 180136404892 ps
CPU time 769.86 seconds
Started May 16 01:00:50 PM PDT 24
Finished May 16 01:14:12 PM PDT 24
Peak memory 200484 kb
Host smart-4fa202bf-12a0-4b2d-b979-c6f79073f74a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849479710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1849479710
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3515605229
Short name T782
Test name
Test status
Simulation time 7434474871 ps
CPU time 6.69 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:01:27 PM PDT 24
Peak memory 199936 kb
Host smart-6ee6a82f-eda5-40b1-b107-a08d54ec0e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515605229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3515605229
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.704745195
Short name T717
Test name
Test status
Simulation time 90481992827 ps
CPU time 43.85 seconds
Started May 16 01:00:43 PM PDT 24
Finished May 16 01:02:00 PM PDT 24
Peak memory 199572 kb
Host smart-807af53e-7836-45ec-a509-041c993b10b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704745195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.704745195
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3276524249
Short name T513
Test name
Test status
Simulation time 21428999333 ps
CPU time 554.7 seconds
Started May 16 01:00:47 PM PDT 24
Finished May 16 01:10:35 PM PDT 24
Peak memory 200528 kb
Host smart-ad4c8e12-0737-468a-8860-468537783f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276524249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3276524249
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.115940299
Short name T772
Test name
Test status
Simulation time 8079247719 ps
CPU time 35.31 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:50 PM PDT 24
Peak memory 199756 kb
Host smart-56057d47-caff-4d89-becd-71f4c4b2dc37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115940299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.115940299
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3571437175
Short name T1037
Test name
Test status
Simulation time 32097550214 ps
CPU time 14.62 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:30 PM PDT 24
Peak memory 200424 kb
Host smart-4a1edc27-c599-48a0-b125-f7dd59f7eda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571437175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3571437175
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4009452813
Short name T270
Test name
Test status
Simulation time 37868003602 ps
CPU time 15.54 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:31 PM PDT 24
Peak memory 196204 kb
Host smart-ebb4b76d-f711-48ac-a723-e3dfbc60a8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009452813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4009452813
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2524172150
Short name T1035
Test name
Test status
Simulation time 724888751 ps
CPU time 1.59 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:16 PM PDT 24
Peak memory 199060 kb
Host smart-2cd8fcc5-c39e-4b95-96f3-0a566def7122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524172150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2524172150
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3334314065
Short name T793
Test name
Test status
Simulation time 1678835942 ps
CPU time 2.29 seconds
Started May 16 01:00:42 PM PDT 24
Finished May 16 01:01:18 PM PDT 24
Peak memory 200264 kb
Host smart-e901f432-1ff7-44e3-868f-63e230d6fa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334314065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3334314065
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.648543622
Short name T932
Test name
Test status
Simulation time 24581375138 ps
CPU time 20.08 seconds
Started May 16 01:00:44 PM PDT 24
Finished May 16 01:01:37 PM PDT 24
Peak memory 200440 kb
Host smart-f09267f7-ed5c-492e-957c-57f6474bd6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648543622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.648543622
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4103181442
Short name T219
Test name
Test status
Simulation time 10853275242 ps
CPU time 18.48 seconds
Started May 16 01:03:48 PM PDT 24
Finished May 16 01:04:13 PM PDT 24
Peak memory 200264 kb
Host smart-e6844a4b-c33c-4cee-9ea5-2b6072665015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103181442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4103181442
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2017095252
Short name T853
Test name
Test status
Simulation time 13441684961 ps
CPU time 20.67 seconds
Started May 16 01:03:52 PM PDT 24
Finished May 16 01:04:18 PM PDT 24
Peak memory 200232 kb
Host smart-54d1bff7-d992-4ea6-a6cd-4e7203baddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017095252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2017095252
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1689460172
Short name T588
Test name
Test status
Simulation time 50796217021 ps
CPU time 20.29 seconds
Started May 16 01:03:52 PM PDT 24
Finished May 16 01:04:18 PM PDT 24
Peak memory 200444 kb
Host smart-828525ef-7f43-494e-a298-cc33ee7302b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689460172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1689460172
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3166180218
Short name T582
Test name
Test status
Simulation time 109906125573 ps
CPU time 171.58 seconds
Started May 16 01:03:50 PM PDT 24
Finished May 16 01:06:47 PM PDT 24
Peak memory 200456 kb
Host smart-d5c27b4e-e98d-43c6-9a2e-9267caa67db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166180218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3166180218
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1974644313
Short name T881
Test name
Test status
Simulation time 86950933285 ps
CPU time 131.95 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:06:07 PM PDT 24
Peak memory 200352 kb
Host smart-26cc246f-99d0-48f3-96c0-1a7fffb04465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974644313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1974644313
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.15933919
Short name T878
Test name
Test status
Simulation time 44538104627 ps
CPU time 17.6 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:04:13 PM PDT 24
Peak memory 200356 kb
Host smart-f76a51d3-18df-4342-994e-2c05fe6a2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15933919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.15933919
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1798418079
Short name T1171
Test name
Test status
Simulation time 83453271206 ps
CPU time 69.83 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:05:05 PM PDT 24
Peak memory 200500 kb
Host smart-14e1b599-4fd8-4223-8374-64473c8e476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798418079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1798418079
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.956435957
Short name T1127
Test name
Test status
Simulation time 36157989525 ps
CPU time 75.33 seconds
Started May 16 01:03:57 PM PDT 24
Finished May 16 01:05:18 PM PDT 24
Peak memory 200496 kb
Host smart-9a8f613c-fff1-4a73-b2d5-f0826470497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956435957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.956435957
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3026072320
Short name T632
Test name
Test status
Simulation time 88933530722 ps
CPU time 236.53 seconds
Started May 16 01:03:50 PM PDT 24
Finished May 16 01:07:52 PM PDT 24
Peak memory 200376 kb
Host smart-b509f7b0-7f48-400d-b676-88c2d2c15c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026072320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3026072320
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.677466899
Short name T407
Test name
Test status
Simulation time 12270323 ps
CPU time 0.59 seconds
Started May 16 01:00:49 PM PDT 24
Finished May 16 01:01:22 PM PDT 24
Peak memory 195816 kb
Host smart-cf04a449-de26-4914-890e-6c9a20aabe85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677466899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.677466899
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1980274766
Short name T1111
Test name
Test status
Simulation time 29943089298 ps
CPU time 70.19 seconds
Started May 16 01:00:49 PM PDT 24
Finished May 16 01:02:32 PM PDT 24
Peak memory 200448 kb
Host smart-15c4dc85-56d0-478d-8946-4ad08b2ad1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980274766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1980274766
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1129619651
Short name T125
Test name
Test status
Simulation time 36480022349 ps
CPU time 35.77 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:02:02 PM PDT 24
Peak memory 200472 kb
Host smart-8d17426c-1eb7-46df-afb1-87ad3cc77ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129619651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1129619651
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4197497238
Short name T614
Test name
Test status
Simulation time 112345809370 ps
CPU time 97.68 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:02:59 PM PDT 24
Peak memory 200460 kb
Host smart-cd87d839-c47a-46a2-beac-5a260a2d28cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197497238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4197497238
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1687625320
Short name T14
Test name
Test status
Simulation time 43146804592 ps
CPU time 22.14 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 200164 kb
Host smart-f9dba01d-9bcd-4e9c-abe7-c921ce3e6829
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687625320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1687625320
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1719123125
Short name T819
Test name
Test status
Simulation time 107209032122 ps
CPU time 185.78 seconds
Started May 16 01:00:56 PM PDT 24
Finished May 16 01:04:35 PM PDT 24
Peak memory 200492 kb
Host smart-8595da44-7c5d-46af-9a9e-2d19441e6d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719123125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1719123125
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3177663764
Short name T1081
Test name
Test status
Simulation time 9195943107 ps
CPU time 7.81 seconds
Started May 16 01:00:54 PM PDT 24
Finished May 16 01:01:35 PM PDT 24
Peak memory 198844 kb
Host smart-bed23c8f-2b5c-462f-b874-c58ab591ad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177663764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3177663764
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.39638859
Short name T704
Test name
Test status
Simulation time 281310930685 ps
CPU time 189.01 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:04:30 PM PDT 24
Peak memory 215732 kb
Host smart-6ce22a8b-f1b2-4be5-9aae-87f91dd065ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39638859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.39638859
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.740736486
Short name T1150
Test name
Test status
Simulation time 5167253224 ps
CPU time 134.89 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:03:36 PM PDT 24
Peak memory 200492 kb
Host smart-61099eae-0022-4a14-bb99-ff4187f9f15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740736486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.740736486
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3957074438
Short name T371
Test name
Test status
Simulation time 3355161585 ps
CPU time 22.98 seconds
Started May 16 01:00:55 PM PDT 24
Finished May 16 01:01:51 PM PDT 24
Peak memory 199372 kb
Host smart-6590f154-4ccc-44a9-b92d-366a8baa1552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957074438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3957074438
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.341165427
Short name T815
Test name
Test status
Simulation time 126926050502 ps
CPU time 88.11 seconds
Started May 16 01:00:47 PM PDT 24
Finished May 16 01:02:49 PM PDT 24
Peak memory 200404 kb
Host smart-57eacd9a-e9a4-4d0e-bdc6-6704e2ff9932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341165427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.341165427
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3350207877
Short name T1166
Test name
Test status
Simulation time 4783007309 ps
CPU time 4.26 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:01:25 PM PDT 24
Peak memory 196456 kb
Host smart-140444dd-f0dd-462f-bab1-f4d0d2fbd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350207877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3350207877
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2194973026
Short name T532
Test name
Test status
Simulation time 490667712 ps
CPU time 2.27 seconds
Started May 16 01:00:49 PM PDT 24
Finished May 16 01:01:24 PM PDT 24
Peak memory 199424 kb
Host smart-a100d1fc-4ef9-4306-ae55-320224696c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194973026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2194973026
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1109404027
Short name T462
Test name
Test status
Simulation time 57540471561 ps
CPU time 101.57 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:03:08 PM PDT 24
Peak memory 200524 kb
Host smart-7d7eb424-793b-42fd-9ab8-f580c051c25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109404027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1109404027
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2618424577
Short name T994
Test name
Test status
Simulation time 38460711510 ps
CPU time 465.18 seconds
Started May 16 01:00:50 PM PDT 24
Finished May 16 01:09:09 PM PDT 24
Peak memory 217208 kb
Host smart-54fdd417-d22d-47b3-9e36-1aa5eace7f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618424577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2618424577
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3825456197
Short name T905
Test name
Test status
Simulation time 6985313512 ps
CPU time 9.41 seconds
Started May 16 01:00:51 PM PDT 24
Finished May 16 01:01:33 PM PDT 24
Peak memory 200460 kb
Host smart-c77f6596-3d7e-47c9-a068-d9a4b311526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825456197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3825456197
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3071544790
Short name T413
Test name
Test status
Simulation time 70771207229 ps
CPU time 31.2 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:01:52 PM PDT 24
Peak memory 200508 kb
Host smart-c83c38ec-44b1-4f1e-9792-72676438fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071544790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3071544790
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1155781646
Short name T699
Test name
Test status
Simulation time 35358802675 ps
CPU time 44.27 seconds
Started May 16 01:03:56 PM PDT 24
Finished May 16 01:04:46 PM PDT 24
Peak memory 200416 kb
Host smart-f7ec5ff4-bf13-4477-b4dc-bcd10a135117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155781646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1155781646
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3679154117
Short name T203
Test name
Test status
Simulation time 20385785457 ps
CPU time 31.09 seconds
Started May 16 01:03:57 PM PDT 24
Finished May 16 01:04:33 PM PDT 24
Peak memory 200452 kb
Host smart-dff26445-70d3-4942-b390-e5ae781bff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679154117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3679154117
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2320075288
Short name T205
Test name
Test status
Simulation time 41598179889 ps
CPU time 19.59 seconds
Started May 16 01:03:56 PM PDT 24
Finished May 16 01:04:20 PM PDT 24
Peak memory 200484 kb
Host smart-3eb84645-0059-41aa-8937-7d05bf43216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320075288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2320075288
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2896285802
Short name T199
Test name
Test status
Simulation time 18727181336 ps
CPU time 36.78 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:04:32 PM PDT 24
Peak memory 200504 kb
Host smart-890e7de2-a46e-4987-80f2-51941e4879c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896285802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2896285802
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1408370042
Short name T237
Test name
Test status
Simulation time 84999567848 ps
CPU time 23.02 seconds
Started May 16 01:03:52 PM PDT 24
Finished May 16 01:04:20 PM PDT 24
Peak memory 200440 kb
Host smart-aea53b7a-0e83-4455-8446-0fe160426d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408370042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1408370042
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1096436633
Short name T861
Test name
Test status
Simulation time 31919136504 ps
CPU time 29.11 seconds
Started May 16 01:03:50 PM PDT 24
Finished May 16 01:04:25 PM PDT 24
Peak memory 200460 kb
Host smart-2333106e-bcf8-48db-977e-5aee65c6bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096436633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1096436633
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3011053295
Short name T724
Test name
Test status
Simulation time 72776366064 ps
CPU time 104.95 seconds
Started May 16 01:03:53 PM PDT 24
Finished May 16 01:05:44 PM PDT 24
Peak memory 200548 kb
Host smart-be3f0c5b-ed08-4573-aa5d-d586d9bef3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011053295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3011053295
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4214321798
Short name T616
Test name
Test status
Simulation time 20988690541 ps
CPU time 27.28 seconds
Started May 16 01:03:53 PM PDT 24
Finished May 16 01:04:26 PM PDT 24
Peak memory 200512 kb
Host smart-58c32bf4-8d57-4b32-beb1-cb145185a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214321798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4214321798
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1308975648
Short name T186
Test name
Test status
Simulation time 19975273125 ps
CPU time 11.37 seconds
Started May 16 01:03:51 PM PDT 24
Finished May 16 01:04:08 PM PDT 24
Peak memory 200428 kb
Host smart-0a341042-5e69-4c10-bf7b-42b9d162de12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308975648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1308975648
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.628579431
Short name T666
Test name
Test status
Simulation time 34697077210 ps
CPU time 17.99 seconds
Started May 16 01:03:53 PM PDT 24
Finished May 16 01:04:17 PM PDT 24
Peak memory 200428 kb
Host smart-ae0acf79-92e0-4e11-9d5c-f86fa906114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628579431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.628579431
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.292726970
Short name T455
Test name
Test status
Simulation time 11809116 ps
CPU time 0.54 seconds
Started May 16 01:00:47 PM PDT 24
Finished May 16 01:01:20 PM PDT 24
Peak memory 194860 kb
Host smart-4b6fa489-c995-4b30-8ef4-fd6cc6fa3bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292726970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.292726970
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3022910228
Short name T284
Test name
Test status
Simulation time 8257050991 ps
CPU time 14.49 seconds
Started May 16 01:00:55 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 200420 kb
Host smart-e987cd6c-a431-4afc-8e08-2612b59691e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022910228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3022910228
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3622086544
Short name T322
Test name
Test status
Simulation time 183299192051 ps
CPU time 70.97 seconds
Started May 16 01:00:51 PM PDT 24
Finished May 16 01:02:35 PM PDT 24
Peak memory 200428 kb
Host smart-e23078a0-e185-4232-8a8a-50ad929f4f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622086544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3622086544
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3298242600
Short name T21
Test name
Test status
Simulation time 19804187990 ps
CPU time 8.45 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:01:29 PM PDT 24
Peak memory 198500 kb
Host smart-481b0be9-9f24-4338-988d-d44004b54ea9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298242600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3298242600
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.349464224
Short name T618
Test name
Test status
Simulation time 47846487405 ps
CPU time 177.38 seconds
Started May 16 01:00:54 PM PDT 24
Finished May 16 01:04:24 PM PDT 24
Peak memory 200552 kb
Host smart-e4b492b4-4bf7-42d3-b763-5f9028852bc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349464224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.349464224
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3962829769
Short name T1094
Test name
Test status
Simulation time 3608766237 ps
CPU time 10.19 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:01:31 PM PDT 24
Peak memory 200416 kb
Host smart-fd91078c-89a9-4dd1-aa63-82b9a81b930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962829769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3962829769
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.602945019
Short name T698
Test name
Test status
Simulation time 96802563487 ps
CPU time 64.37 seconds
Started May 16 01:00:51 PM PDT 24
Finished May 16 01:02:28 PM PDT 24
Peak memory 216396 kb
Host smart-c14ed3a1-a7d9-42aa-b0b1-fbda0a8be8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602945019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.602945019
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.4221543218
Short name T610
Test name
Test status
Simulation time 4863066980 ps
CPU time 178.15 seconds
Started May 16 01:00:55 PM PDT 24
Finished May 16 01:04:27 PM PDT 24
Peak memory 200468 kb
Host smart-59c6cd5a-423b-4a33-9a83-8338b94f1f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221543218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4221543218
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3946135535
Short name T1015
Test name
Test status
Simulation time 5126629995 ps
CPU time 41.69 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:02:08 PM PDT 24
Peak memory 199176 kb
Host smart-61ec031f-6843-4782-b7ca-95115f5d7f06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946135535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3946135535
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.4209290538
Short name T880
Test name
Test status
Simulation time 54922246151 ps
CPU time 35.8 seconds
Started May 16 01:00:51 PM PDT 24
Finished May 16 01:02:00 PM PDT 24
Peak memory 200356 kb
Host smart-a1fd97be-983c-41df-9175-d7594d4a24fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209290538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.4209290538
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.73623282
Short name T287
Test name
Test status
Simulation time 4474528353 ps
CPU time 4.23 seconds
Started May 16 01:00:50 PM PDT 24
Finished May 16 01:01:27 PM PDT 24
Peak memory 196488 kb
Host smart-ba0c04fd-b889-4aea-88a3-68b706c4f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73623282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.73623282
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.191087249
Short name T280
Test name
Test status
Simulation time 5512173865 ps
CPU time 4.53 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:01:30 PM PDT 24
Peak memory 199684 kb
Host smart-cdb6df54-9c67-4963-9d14-fae3710a5610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191087249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.191087249
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1738814168
Short name T201
Test name
Test status
Simulation time 310304281631 ps
CPU time 313.03 seconds
Started May 16 01:00:49 PM PDT 24
Finished May 16 01:06:35 PM PDT 24
Peak memory 200364 kb
Host smart-95292037-0211-4d92-8851-bc636ecb005d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738814168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1738814168
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.589774446
Short name T745
Test name
Test status
Simulation time 51009697882 ps
CPU time 176.3 seconds
Started May 16 01:00:55 PM PDT 24
Finished May 16 01:04:25 PM PDT 24
Peak memory 216368 kb
Host smart-a938bbb8-ce5c-40fb-9821-f507c66c296a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589774446 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.589774446
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2841534514
Short name T1057
Test name
Test status
Simulation time 1286998126 ps
CPU time 2.39 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:01:28 PM PDT 24
Peak memory 199020 kb
Host smart-4f8c6a23-c230-44ef-824d-451008b54318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841534514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2841534514
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2739051364
Short name T692
Test name
Test status
Simulation time 54609326772 ps
CPU time 15.28 seconds
Started May 16 01:00:52 PM PDT 24
Finished May 16 01:01:40 PM PDT 24
Peak memory 200480 kb
Host smart-e756e5fb-ec42-4716-ba23-494f19ff6b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739051364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2739051364
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.846739826
Short name T1050
Test name
Test status
Simulation time 125145537808 ps
CPU time 134.76 seconds
Started May 16 01:03:57 PM PDT 24
Finished May 16 01:06:17 PM PDT 24
Peak memory 200440 kb
Host smart-82cb6e9f-41f3-4f30-bd1f-6ab02275586e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846739826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.846739826
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.661944702
Short name T214
Test name
Test status
Simulation time 97373027333 ps
CPU time 79.41 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:05:15 PM PDT 24
Peak memory 200516 kb
Host smart-872c0eb6-7852-4eae-bcd3-5562d93136f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661944702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.661944702
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.740994801
Short name T1157
Test name
Test status
Simulation time 53523530885 ps
CPU time 41.97 seconds
Started May 16 01:03:48 PM PDT 24
Finished May 16 01:04:36 PM PDT 24
Peak memory 200512 kb
Host smart-7a42de0a-afd3-4e0f-865f-f8ba88064e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740994801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.740994801
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2035757620
Short name T188
Test name
Test status
Simulation time 6102657731 ps
CPU time 12.7 seconds
Started May 16 01:03:53 PM PDT 24
Finished May 16 01:04:12 PM PDT 24
Peak memory 200436 kb
Host smart-9661750a-3a7b-4e57-b80b-70d5992db051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035757620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2035757620
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3725572648
Short name T636
Test name
Test status
Simulation time 26484162196 ps
CPU time 22.54 seconds
Started May 16 01:03:52 PM PDT 24
Finished May 16 01:04:20 PM PDT 24
Peak memory 200524 kb
Host smart-47e881ee-16e0-4dc2-a01a-8afaa1b83784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725572648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3725572648
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2117467260
Short name T783
Test name
Test status
Simulation time 83937478988 ps
CPU time 189.63 seconds
Started May 16 01:03:51 PM PDT 24
Finished May 16 01:07:06 PM PDT 24
Peak memory 200484 kb
Host smart-286a413c-00f8-4f44-837c-0cb557e0f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117467260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2117467260
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.864461889
Short name T195
Test name
Test status
Simulation time 9048142948 ps
CPU time 15.86 seconds
Started May 16 01:03:50 PM PDT 24
Finished May 16 01:04:12 PM PDT 24
Peak memory 200556 kb
Host smart-f02be9c4-2d85-4f7c-bfa1-5aa26bf65e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864461889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.864461889
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.992484990
Short name T709
Test name
Test status
Simulation time 59882932314 ps
CPU time 15.25 seconds
Started May 16 01:03:49 PM PDT 24
Finished May 16 01:04:11 PM PDT 24
Peak memory 200496 kb
Host smart-6fabfb7c-f983-41a1-beb2-d364c63317fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992484990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.992484990
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1329675680
Short name T391
Test name
Test status
Simulation time 10885529 ps
CPU time 0.52 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:01:33 PM PDT 24
Peak memory 194836 kb
Host smart-e8d04936-b521-4971-9aa0-03059457c698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329675680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1329675680
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1477801029
Short name T777
Test name
Test status
Simulation time 94529398325 ps
CPU time 25.5 seconds
Started May 16 01:00:54 PM PDT 24
Finished May 16 01:01:52 PM PDT 24
Peak memory 200536 kb
Host smart-cd0f6b14-64c6-4097-887b-860bbdeff6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477801029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1477801029
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3199082381
Short name T493
Test name
Test status
Simulation time 52107890202 ps
CPU time 89.51 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:02:55 PM PDT 24
Peak memory 200396 kb
Host smart-3106eaf1-0230-48de-ac5a-a23dea4b79ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199082381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3199082381
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1122098576
Short name T872
Test name
Test status
Simulation time 110994440853 ps
CPU time 222.38 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:05:15 PM PDT 24
Peak memory 200452 kb
Host smart-6ded0872-c015-48b9-8f54-12097b9a17b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122098576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1122098576
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3779110009
Short name T1136
Test name
Test status
Simulation time 232805433965 ps
CPU time 281.77 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:06:13 PM PDT 24
Peak memory 200484 kb
Host smart-b339c54b-b8d4-4daa-90be-e3a8d22a3528
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779110009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3779110009
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.940560394
Short name T722
Test name
Test status
Simulation time 184640399488 ps
CPU time 88.32 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:03:02 PM PDT 24
Peak memory 200520 kb
Host smart-8a4181f3-4a71-4af9-9e80-65643ce54fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940560394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.940560394
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.219041528
Short name T833
Test name
Test status
Simulation time 8449598008 ps
CPU time 19.82 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:01:54 PM PDT 24
Peak memory 200296 kb
Host smart-6ffd6f9f-1ed1-45cb-b1fe-d26a083ba92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219041528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.219041528
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1026883960
Short name T703
Test name
Test status
Simulation time 155836238355 ps
CPU time 150.44 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:04:02 PM PDT 24
Peak memory 200728 kb
Host smart-95349ba5-380f-49a2-97af-5b3270ab84bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026883960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1026883960
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1446018278
Short name T962
Test name
Test status
Simulation time 15731593804 ps
CPU time 392.92 seconds
Started May 16 01:00:57 PM PDT 24
Finished May 16 01:08:04 PM PDT 24
Peak memory 200460 kb
Host smart-690dfad3-3870-4b61-9e2c-d91937228404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446018278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1446018278
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1494555214
Short name T856
Test name
Test status
Simulation time 2738716118 ps
CPU time 21.79 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:01:55 PM PDT 24
Peak memory 198416 kb
Host smart-57653afb-443f-4485-9b6e-29aae7870a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494555214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1494555214
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1737649575
Short name T1063
Test name
Test status
Simulation time 277597340602 ps
CPU time 32.26 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:02:06 PM PDT 24
Peak memory 200352 kb
Host smart-983739aa-ae6d-4109-b2fc-a11ccb2083fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737649575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1737649575
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3136564376
Short name T1047
Test name
Test status
Simulation time 3344287160 ps
CPU time 6.29 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:01:40 PM PDT 24
Peak memory 196452 kb
Host smart-6eafb50d-c16f-4149-886c-4331ac6fe32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136564376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3136564376
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2367553027
Short name T718
Test name
Test status
Simulation time 5377171064 ps
CPU time 17.73 seconds
Started May 16 01:00:53 PM PDT 24
Finished May 16 01:01:44 PM PDT 24
Peak memory 200212 kb
Host smart-cf8445ee-daac-4f3d-adc8-4306d9905db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367553027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2367553027
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1271438663
Short name T727
Test name
Test status
Simulation time 137283949563 ps
CPU time 390.72 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:08:03 PM PDT 24
Peak memory 200424 kb
Host smart-2a955952-7702-43ec-bf8b-58e407e5e415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271438663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1271438663
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2177870029
Short name T547
Test name
Test status
Simulation time 1144410085 ps
CPU time 2.4 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:01:36 PM PDT 24
Peak memory 200224 kb
Host smart-b0cc9401-1676-45f1-8c65-dd164e9c6b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177870029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2177870029
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2565256460
Short name T315
Test name
Test status
Simulation time 50356107388 ps
CPU time 77.61 seconds
Started May 16 01:00:48 PM PDT 24
Finished May 16 01:02:38 PM PDT 24
Peak memory 200516 kb
Host smart-58d0de65-7119-4150-92a4-78d32d52fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565256460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2565256460
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3776761845
Short name T1009
Test name
Test status
Simulation time 17623094170 ps
CPU time 32.04 seconds
Started May 16 01:04:02 PM PDT 24
Finished May 16 01:04:41 PM PDT 24
Peak memory 200448 kb
Host smart-3852870c-3360-4c67-a200-53f535e42954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776761845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3776761845
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2601222554
Short name T499
Test name
Test status
Simulation time 37159135529 ps
CPU time 23.14 seconds
Started May 16 01:04:05 PM PDT 24
Finished May 16 01:04:34 PM PDT 24
Peak memory 200416 kb
Host smart-4fab9af5-ba37-47cb-952c-83c178bc9080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601222554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2601222554
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.827635831
Short name T485
Test name
Test status
Simulation time 40282476194 ps
CPU time 24.15 seconds
Started May 16 01:04:05 PM PDT 24
Finished May 16 01:04:35 PM PDT 24
Peak memory 200440 kb
Host smart-8a09e99d-5703-4757-9ad8-30dfc79507d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827635831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.827635831
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.844561524
Short name T1076
Test name
Test status
Simulation time 17632990227 ps
CPU time 30.45 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:04:38 PM PDT 24
Peak memory 200356 kb
Host smart-cd3f71e5-d932-4edc-bf64-b6b163732312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844561524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.844561524
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1399897059
Short name T921
Test name
Test status
Simulation time 88615976727 ps
CPU time 11.93 seconds
Started May 16 01:04:02 PM PDT 24
Finished May 16 01:04:21 PM PDT 24
Peak memory 200456 kb
Host smart-68338186-1a8d-4b15-9c93-96fa4fbc7be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399897059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1399897059
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1461732858
Short name T198
Test name
Test status
Simulation time 32801412840 ps
CPU time 47.31 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:04:54 PM PDT 24
Peak memory 200496 kb
Host smart-e35ed33b-d947-4fff-aed9-b58777f21bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461732858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1461732858
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.4247727223
Short name T529
Test name
Test status
Simulation time 319101127688 ps
CPU time 572.57 seconds
Started May 16 01:04:07 PM PDT 24
Finished May 16 01:13:45 PM PDT 24
Peak memory 200360 kb
Host smart-63f021a2-6b55-43e7-b2d8-4f10a047d08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247727223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4247727223
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1901015751
Short name T961
Test name
Test status
Simulation time 203202542793 ps
CPU time 308.86 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:09:16 PM PDT 24
Peak memory 200444 kb
Host smart-b1ed8edc-c64c-41d8-b006-916b01838269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901015751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1901015751
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2213196521
Short name T174
Test name
Test status
Simulation time 20685387645 ps
CPU time 21.1 seconds
Started May 16 01:04:02 PM PDT 24
Finished May 16 01:04:30 PM PDT 24
Peak memory 200472 kb
Host smart-f0cc4ec1-85ef-4d62-a4b4-5962c8f9c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213196521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2213196521
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1060319798
Short name T985
Test name
Test status
Simulation time 114358034669 ps
CPU time 183.14 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:04:37 PM PDT 24
Peak memory 200416 kb
Host smart-63ff809a-6b9c-4bf5-b1b2-a86bd322e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060319798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1060319798
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1774930854
Short name T1025
Test name
Test status
Simulation time 7261427511 ps
CPU time 13.16 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:01:46 PM PDT 24
Peak memory 199080 kb
Host smart-fe6849ba-145f-458b-a8d1-142222fe6515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774930854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1774930854
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.684676877
Short name T561
Test name
Test status
Simulation time 57651280886 ps
CPU time 43.28 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:02:16 PM PDT 24
Peak memory 200532 kb
Host smart-6763859c-e4ab-4c84-9b1f-1b8cae25cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684676877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.684676877
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1897653117
Short name T469
Test name
Test status
Simulation time 5838100083 ps
CPU time 5.43 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:01:39 PM PDT 24
Peak memory 197012 kb
Host smart-1c09aa09-cd7a-452a-ba28-998a1baf34f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897653117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1897653117
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1389399055
Short name T687
Test name
Test status
Simulation time 144982889699 ps
CPU time 1336.25 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:23:50 PM PDT 24
Peak memory 200388 kb
Host smart-e9a82b92-6646-4d40-aa0f-16882fc20fa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389399055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1389399055
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.4103446132
Short name T997
Test name
Test status
Simulation time 2154490615 ps
CPU time 3.76 seconds
Started May 16 01:01:03 PM PDT 24
Finished May 16 01:01:39 PM PDT 24
Peak memory 196592 kb
Host smart-119e97fb-9f15-4685-b035-f426dba1870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103446132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4103446132
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4006665546
Short name T1134
Test name
Test status
Simulation time 130817896575 ps
CPU time 150.68 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:04:03 PM PDT 24
Peak memory 208940 kb
Host smart-dabf6743-7707-4d0d-82ac-f8c53d7ad8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006665546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4006665546
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2978463194
Short name T638
Test name
Test status
Simulation time 14163167423 ps
CPU time 709.34 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:13:23 PM PDT 24
Peak memory 200412 kb
Host smart-83041d32-a0df-4f56-820a-f622df18ae0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978463194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2978463194
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.292690770
Short name T434
Test name
Test status
Simulation time 1505422398 ps
CPU time 2.06 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:01:34 PM PDT 24
Peak memory 198636 kb
Host smart-e85e9854-a7b2-40dd-bfc4-0afec5c4f4a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292690770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.292690770
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.751183986
Short name T179
Test name
Test status
Simulation time 89222591029 ps
CPU time 136.47 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:03:51 PM PDT 24
Peak memory 200500 kb
Host smart-3a65bd5f-b3bc-4cce-a9e2-29026fb3efc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751183986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.751183986
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3550082795
Short name T787
Test name
Test status
Simulation time 6187440113 ps
CPU time 3.08 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:01:37 PM PDT 24
Peak memory 196712 kb
Host smart-68549cb1-40c8-423c-84d8-9af9a80224ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550082795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3550082795
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1049221431
Short name T700
Test name
Test status
Simulation time 5820829447 ps
CPU time 14.12 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:01:45 PM PDT 24
Peak memory 199724 kb
Host smart-d9eae5ee-2546-41c6-a03c-b0c2d5f294e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049221431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1049221431
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1189440176
Short name T978
Test name
Test status
Simulation time 40917786214 ps
CPU time 22.8 seconds
Started May 16 01:00:58 PM PDT 24
Finished May 16 01:01:54 PM PDT 24
Peak memory 200456 kb
Host smart-aba3faf4-9abe-4ca9-80b0-7b2e194cf450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189440176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1189440176
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.889216212
Short name T654
Test name
Test status
Simulation time 512174530518 ps
CPU time 1785.16 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:31:18 PM PDT 24
Peak memory 233316 kb
Host smart-350cb084-a29c-4de3-8777-ea13e495d42f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889216212 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.889216212
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3376578067
Short name T823
Test name
Test status
Simulation time 1159591937 ps
CPU time 2.57 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:01:37 PM PDT 24
Peak memory 199340 kb
Host smart-1090b1a1-2ddb-4367-add8-1eb33f1f7a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376578067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3376578067
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2971427126
Short name T418
Test name
Test status
Simulation time 79955253855 ps
CPU time 124.96 seconds
Started May 16 01:00:57 PM PDT 24
Finished May 16 01:03:36 PM PDT 24
Peak memory 200460 kb
Host smart-37b80b63-f063-4d66-8eb9-9c5539d017cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971427126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2971427126
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.748570816
Short name T103
Test name
Test status
Simulation time 80444965272 ps
CPU time 93.02 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:05:43 PM PDT 24
Peak memory 200444 kb
Host smart-18a322a3-841f-4f7e-b722-fdc3de72d073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748570816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.748570816
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2074642155
Short name T107
Test name
Test status
Simulation time 130585042649 ps
CPU time 252.03 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:08:22 PM PDT 24
Peak memory 200404 kb
Host smart-27d33936-fb99-48d7-8af1-e4637ea8f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074642155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2074642155
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.608708860
Short name T252
Test name
Test status
Simulation time 78820466966 ps
CPU time 47.6 seconds
Started May 16 01:03:59 PM PDT 24
Finished May 16 01:04:54 PM PDT 24
Peak memory 200556 kb
Host smart-c0c5f661-01a9-4e2c-bbd5-c8bbfabaa17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608708860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.608708860
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.94026486
Short name T641
Test name
Test status
Simulation time 29367094943 ps
CPU time 54.42 seconds
Started May 16 01:04:02 PM PDT 24
Finished May 16 01:05:04 PM PDT 24
Peak memory 200440 kb
Host smart-b76ff0c7-83e2-42d6-a8d2-791a506ec6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94026486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.94026486
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2621323979
Short name T210
Test name
Test status
Simulation time 22467982629 ps
CPU time 33.17 seconds
Started May 16 01:04:02 PM PDT 24
Finished May 16 01:04:43 PM PDT 24
Peak memory 200484 kb
Host smart-74876021-e9bf-4e93-a044-5c67386ee72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621323979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2621323979
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2960037181
Short name T931
Test name
Test status
Simulation time 150457075492 ps
CPU time 14.2 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:04:22 PM PDT 24
Peak memory 200440 kb
Host smart-44387c52-ce21-43c0-a20e-58e7d05dbd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960037181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2960037181
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3552086526
Short name T143
Test name
Test status
Simulation time 38075610277 ps
CPU time 20.11 seconds
Started May 16 01:03:59 PM PDT 24
Finished May 16 01:04:25 PM PDT 24
Peak memory 200440 kb
Host smart-488084e8-91df-4acd-9fbc-564e36cb25d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552086526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3552086526
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2640222346
Short name T59
Test name
Test status
Simulation time 62329146485 ps
CPU time 25.41 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:04:35 PM PDT 24
Peak memory 200424 kb
Host smart-a24168b3-a863-4269-9c18-a1708ca63475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640222346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2640222346
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1983513267
Short name T1113
Test name
Test status
Simulation time 133255394907 ps
CPU time 133.7 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:06:21 PM PDT 24
Peak memory 200428 kb
Host smart-fc384dc8-6b80-4fa8-807b-8f9137212832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983513267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1983513267
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4196308848
Short name T840
Test name
Test status
Simulation time 20426607 ps
CPU time 0.53 seconds
Started May 16 01:01:01 PM PDT 24
Finished May 16 01:01:35 PM PDT 24
Peak memory 195784 kb
Host smart-64e6ee0e-0d44-4030-9cde-18358ab82b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196308848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4196308848
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2403525885
Short name T1102
Test name
Test status
Simulation time 84571852625 ps
CPU time 116 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 200324 kb
Host smart-222edb07-ac63-4939-8cd5-3e265fd546c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403525885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2403525885
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2648592789
Short name T771
Test name
Test status
Simulation time 139738909721 ps
CPU time 119.55 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:03:32 PM PDT 24
Peak memory 200424 kb
Host smart-64ef03d4-fa83-453a-a9c9-e527a542b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648592789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2648592789
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1217769407
Short name T390
Test name
Test status
Simulation time 32205596928 ps
CPU time 50.92 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:02:24 PM PDT 24
Peak memory 200500 kb
Host smart-a24b3979-8236-4082-939a-80b603837a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217769407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1217769407
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2710503587
Short name T1120
Test name
Test status
Simulation time 42848608427 ps
CPU time 15.9 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:01:49 PM PDT 24
Peak memory 200100 kb
Host smart-1a96fc1d-465b-4c6b-8c0b-8c97be71222b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710503587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2710503587
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3787917699
Short name T803
Test name
Test status
Simulation time 85494194543 ps
CPU time 440.17 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:08:53 PM PDT 24
Peak memory 200464 kb
Host smart-6cf2f277-944d-4784-8249-aaf305509f1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787917699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3787917699
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.444127347
Short name T497
Test name
Test status
Simulation time 4079404806 ps
CPU time 2.54 seconds
Started May 16 01:00:57 PM PDT 24
Finished May 16 01:01:33 PM PDT 24
Peak memory 198156 kb
Host smart-9113f24f-2ba5-4a6e-88b8-9aa36487547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444127347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.444127347
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2424833851
Short name T312
Test name
Test status
Simulation time 166649776045 ps
CPU time 79.37 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:02:52 PM PDT 24
Peak memory 200516 kb
Host smart-320fc0aa-8555-430e-a167-52af9896dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424833851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2424833851
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3722772228
Short name T712
Test name
Test status
Simulation time 15220902997 ps
CPU time 414.57 seconds
Started May 16 01:00:56 PM PDT 24
Finished May 16 01:08:24 PM PDT 24
Peak memory 200484 kb
Host smart-a3076163-0fbc-4360-b731-4081d5da8bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722772228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3722772228
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2918171910
Short name T867
Test name
Test status
Simulation time 5549168586 ps
CPU time 14.15 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:01:47 PM PDT 24
Peak memory 199580 kb
Host smart-b1550ccf-9ced-4a94-b2bf-c4d5d690820a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918171910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2918171910
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2865247963
Short name T1112
Test name
Test status
Simulation time 204342487242 ps
CPU time 24.2 seconds
Started May 16 01:00:59 PM PDT 24
Finished May 16 01:01:57 PM PDT 24
Peak memory 200468 kb
Host smart-c658fde3-9fe7-4691-b656-70575e7e6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865247963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2865247963
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.200952783
Short name T365
Test name
Test status
Simulation time 3999807319 ps
CPU time 3.61 seconds
Started May 16 01:00:57 PM PDT 24
Finished May 16 01:01:35 PM PDT 24
Peak memory 196468 kb
Host smart-c44cae29-5a74-469b-b848-c8e9f80b9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200952783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.200952783
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2616610373
Short name T607
Test name
Test status
Simulation time 483203228 ps
CPU time 2.24 seconds
Started May 16 01:01:04 PM PDT 24
Finished May 16 01:01:39 PM PDT 24
Peak memory 198712 kb
Host smart-5327c6c3-9677-4ffd-a755-172c5869456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616610373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2616610373
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.295810041
Short name T307
Test name
Test status
Simulation time 481334650736 ps
CPU time 878.96 seconds
Started May 16 01:00:57 PM PDT 24
Finished May 16 01:16:10 PM PDT 24
Peak memory 200456 kb
Host smart-d1ff3355-20b7-4b64-b998-55ae2c577bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295810041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.295810041
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2299433388
Short name T1010
Test name
Test status
Simulation time 29606832165 ps
CPU time 292.83 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:06:27 PM PDT 24
Peak memory 217184 kb
Host smart-74a1846f-e8a3-4720-b183-ddb71ab89702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299433388 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2299433388
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2690811928
Short name T420
Test name
Test status
Simulation time 741124171 ps
CPU time 2.05 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:01:35 PM PDT 24
Peak memory 199120 kb
Host smart-ed760318-dd7a-42d2-9a80-e2af13637828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690811928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2690811928
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3056468568
Short name T852
Test name
Test status
Simulation time 92990394025 ps
CPU time 235.73 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:05:29 PM PDT 24
Peak memory 200432 kb
Host smart-cf9bab85-289a-4af1-a807-20591ec9c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056468568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3056468568
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.726376915
Short name T1101
Test name
Test status
Simulation time 33236818244 ps
CPU time 27.95 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:04:38 PM PDT 24
Peak memory 199652 kb
Host smart-1890e35d-579a-40f7-9724-f9645316d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726376915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.726376915
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2036005286
Short name T1089
Test name
Test status
Simulation time 92408321389 ps
CPU time 299.45 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:09:06 PM PDT 24
Peak memory 200524 kb
Host smart-2001e50a-a726-4595-be24-2eb3f6d7ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036005286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2036005286
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1037555051
Short name T422
Test name
Test status
Simulation time 22062109339 ps
CPU time 23.87 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:04:34 PM PDT 24
Peak memory 200484 kb
Host smart-d652a9f4-107e-46bb-b4d0-73c0ff55fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037555051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1037555051
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.576597157
Short name T220
Test name
Test status
Simulation time 9049333077 ps
CPU time 13.78 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:04:22 PM PDT 24
Peak memory 200264 kb
Host smart-d493e4f2-691b-46be-b9ce-9d67ccb228a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576597157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.576597157
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1547654759
Short name T941
Test name
Test status
Simulation time 276418328748 ps
CPU time 44.65 seconds
Started May 16 01:04:01 PM PDT 24
Finished May 16 01:04:53 PM PDT 24
Peak memory 200492 kb
Host smart-148f7923-633e-49e4-9dd0-b593afde45fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547654759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1547654759
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.858834629
Short name T526
Test name
Test status
Simulation time 143724291459 ps
CPU time 54.4 seconds
Started May 16 01:04:01 PM PDT 24
Finished May 16 01:05:03 PM PDT 24
Peak memory 200472 kb
Host smart-e48013a3-0a96-432e-9db8-e87ba9795b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858834629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.858834629
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.543552024
Short name T501
Test name
Test status
Simulation time 101351233461 ps
CPU time 69.12 seconds
Started May 16 01:04:01 PM PDT 24
Finished May 16 01:05:17 PM PDT 24
Peak memory 200504 kb
Host smart-82399cfe-64cc-4399-aca9-bbe66e9261fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543552024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.543552024
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3461375361
Short name T1109
Test name
Test status
Simulation time 161458613686 ps
CPU time 59.24 seconds
Started May 16 01:03:59 PM PDT 24
Finished May 16 01:05:05 PM PDT 24
Peak memory 200492 kb
Host smart-3022519f-3ef9-48dd-a3ce-33b49c90025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461375361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3461375361
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3524430209
Short name T194
Test name
Test status
Simulation time 14238698585 ps
CPU time 20.37 seconds
Started May 16 01:04:01 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200540 kb
Host smart-d7549e0d-9466-46d4-b24d-fd0249d8ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524430209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3524430209
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.532185636
Short name T202
Test name
Test status
Simulation time 18316692191 ps
CPU time 29.03 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:04:37 PM PDT 24
Peak memory 200376 kb
Host smart-a93f280c-12d7-421f-b698-f2ee82d5e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532185636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.532185636
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3349102252
Short name T752
Test name
Test status
Simulation time 28859079 ps
CPU time 0.56 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:41 PM PDT 24
Peak memory 195860 kb
Host smart-a9a2880f-6737-49f4-95a1-6a42262430d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349102252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3349102252
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.768974514
Short name T451
Test name
Test status
Simulation time 25771340113 ps
CPU time 43.52 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:02:17 PM PDT 24
Peak memory 200400 kb
Host smart-2186c7a2-5f21-4360-84ac-8a3d31d75bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768974514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.768974514
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.4281567471
Short name T946
Test name
Test status
Simulation time 9792174874 ps
CPU time 16.91 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:57 PM PDT 24
Peak memory 200244 kb
Host smart-d0d81b15-4146-4e1a-81bf-633c9adaa952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281567471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4281567471
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1663565466
Short name T216
Test name
Test status
Simulation time 47466873482 ps
CPU time 67.38 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:02:47 PM PDT 24
Peak memory 200220 kb
Host smart-c0f59473-8849-4d4a-9493-7235b897bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663565466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1663565466
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3759033113
Short name T1068
Test name
Test status
Simulation time 271762303499 ps
CPU time 358.22 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:07:40 PM PDT 24
Peak memory 200268 kb
Host smart-3afd04b5-fa86-4705-b1cd-082b432d9689
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759033113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3759033113
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3915899739
Short name T299
Test name
Test status
Simulation time 41449357043 ps
CPU time 220.23 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:05:20 PM PDT 24
Peak memory 200532 kb
Host smart-40a3424c-0685-4f94-93a2-84581ab246d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915899739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3915899739
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2644448164
Short name T542
Test name
Test status
Simulation time 7756105661 ps
CPU time 14.69 seconds
Started May 16 01:01:14 PM PDT 24
Finished May 16 01:01:59 PM PDT 24
Peak memory 198844 kb
Host smart-92012808-5541-470c-9be0-a4325b6e92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644448164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2644448164
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2647170827
Short name T463
Test name
Test status
Simulation time 190087886513 ps
CPU time 91.52 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:03:13 PM PDT 24
Peak memory 200020 kb
Host smart-a15e13c1-463c-4dd0-a3f6-0bf6c8340a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647170827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2647170827
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3769579440
Short name T1129
Test name
Test status
Simulation time 10367471299 ps
CPU time 648.98 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:12:30 PM PDT 24
Peak memory 200440 kb
Host smart-c158ff71-0a72-470d-b799-58b1e56e7c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769579440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3769579440
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1955083313
Short name T394
Test name
Test status
Simulation time 6059636048 ps
CPU time 11.7 seconds
Started May 16 01:01:07 PM PDT 24
Finished May 16 01:01:51 PM PDT 24
Peak memory 199360 kb
Host smart-a4e29542-1fa2-4587-8521-3cfc9eab7d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955083313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1955083313
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.250204554
Short name T271
Test name
Test status
Simulation time 87414200343 ps
CPU time 72.02 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:02:53 PM PDT 24
Peak memory 200436 kb
Host smart-ff856794-e025-4c46-a0d7-063cea9773cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250204554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.250204554
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3879146190
Short name T647
Test name
Test status
Simulation time 3394101823 ps
CPU time 6.51 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:47 PM PDT 24
Peak memory 196772 kb
Host smart-9000330e-8a56-4606-8765-c9c3719973d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879146190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3879146190
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1241478893
Short name T1104
Test name
Test status
Simulation time 904150219 ps
CPU time 1.85 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:01:35 PM PDT 24
Peak memory 200380 kb
Host smart-1b8516b5-4bce-4b1b-a68e-66ccb5d2c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241478893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1241478893
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3676438825
Short name T558
Test name
Test status
Simulation time 212554753112 ps
CPU time 350.59 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:07:31 PM PDT 24
Peak memory 200484 kb
Host smart-42b61f5b-4c2f-41c3-9404-ceabbb4550c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676438825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3676438825
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1073169831
Short name T670
Test name
Test status
Simulation time 31033841729 ps
CPU time 153.8 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:04:14 PM PDT 24
Peak memory 208620 kb
Host smart-57213bdb-ecd6-4597-8fb1-e362a81eaeed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073169831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1073169831
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4278993503
Short name T18
Test name
Test status
Simulation time 738616794 ps
CPU time 1.87 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:42 PM PDT 24
Peak memory 198980 kb
Host smart-5e6c91c5-4bbc-44d0-a27a-a505c7bb0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278993503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4278993503
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1096999925
Short name T761
Test name
Test status
Simulation time 81840982751 ps
CPU time 9.03 seconds
Started May 16 01:01:00 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 198508 kb
Host smart-fa94ad47-4018-4b5d-afaa-e872cebcbc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096999925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1096999925
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1048871848
Short name T148
Test name
Test status
Simulation time 113379622580 ps
CPU time 20.14 seconds
Started May 16 01:04:07 PM PDT 24
Finished May 16 01:04:32 PM PDT 24
Peak memory 200408 kb
Host smart-5b6376d0-4c4f-4f89-8745-3b6fde51337e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048871848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1048871848
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2325149588
Short name T950
Test name
Test status
Simulation time 61111745431 ps
CPU time 196.58 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:07:27 PM PDT 24
Peak memory 200456 kb
Host smart-04cbacdb-0a3f-4bfb-835b-c4b33fdb125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325149588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2325149588
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1426528575
Short name T1019
Test name
Test status
Simulation time 43612324581 ps
CPU time 32.31 seconds
Started May 16 01:04:01 PM PDT 24
Finished May 16 01:04:41 PM PDT 24
Peak memory 199992 kb
Host smart-ca5d2660-5c1f-4972-bb9e-46edb679d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426528575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1426528575
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1388885176
Short name T869
Test name
Test status
Simulation time 41588003617 ps
CPU time 45.5 seconds
Started May 16 01:04:02 PM PDT 24
Finished May 16 01:04:54 PM PDT 24
Peak memory 200516 kb
Host smart-6e8abc60-c4dd-4cdf-86f2-0593ec69e03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388885176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1388885176
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2580573995
Short name T1061
Test name
Test status
Simulation time 18571444061 ps
CPU time 9.57 seconds
Started May 16 01:04:03 PM PDT 24
Finished May 16 01:04:19 PM PDT 24
Peak memory 200508 kb
Host smart-b361772c-d8b9-41cf-8e2d-0b62e22607d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580573995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2580573995
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1840063677
Short name T325
Test name
Test status
Simulation time 54653330115 ps
CPU time 119.04 seconds
Started May 16 01:04:00 PM PDT 24
Finished May 16 01:06:07 PM PDT 24
Peak memory 200552 kb
Host smart-da0b1941-9254-4122-a347-78240d8ab133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840063677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1840063677
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3265571637
Short name T100
Test name
Test status
Simulation time 53503156170 ps
CPU time 103.45 seconds
Started May 16 01:05:09 PM PDT 24
Finished May 16 01:07:02 PM PDT 24
Peak memory 200536 kb
Host smart-8521a570-a7c3-4922-ad6c-ca908401ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265571637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3265571637
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.105110762
Short name T363
Test name
Test status
Simulation time 44389737294 ps
CPU time 67.3 seconds
Started May 16 01:05:10 PM PDT 24
Finished May 16 01:06:27 PM PDT 24
Peak memory 199728 kb
Host smart-9547ffdc-a90b-4fbd-a38e-ac69ecd383cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105110762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.105110762
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1361872477
Short name T204
Test name
Test status
Simulation time 22646134868 ps
CPU time 35.22 seconds
Started May 16 01:05:11 PM PDT 24
Finished May 16 01:05:56 PM PDT 24
Peak memory 200488 kb
Host smart-dd1af154-30bb-434b-b980-106636425f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361872477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1361872477
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.4018447725
Short name T471
Test name
Test status
Simulation time 15583370 ps
CPU time 0.54 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:01:41 PM PDT 24
Peak memory 194848 kb
Host smart-095fab9f-333f-46d2-8542-5308ab26b436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018447725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4018447725
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4215976885
Short name T1118
Test name
Test status
Simulation time 25120747004 ps
CPU time 12.59 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:01:52 PM PDT 24
Peak memory 200468 kb
Host smart-58440b32-51bf-4fc1-868c-56bcfa4f2202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215976885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4215976885
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1086621221
Short name T93
Test name
Test status
Simulation time 20951735833 ps
CPU time 20.27 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:06 PM PDT 24
Peak memory 200320 kb
Host smart-b6d93ee8-fb3c-44c4-b510-ada86f35ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086621221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1086621221
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1874066188
Short name T988
Test name
Test status
Simulation time 68769065265 ps
CPU time 9.58 seconds
Started May 16 01:01:13 PM PDT 24
Finished May 16 01:01:53 PM PDT 24
Peak memory 200496 kb
Host smart-9b7c38fb-358f-41f4-b212-39c769a800e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874066188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1874066188
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2774631233
Short name T13
Test name
Test status
Simulation time 50787536921 ps
CPU time 70.73 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 200500 kb
Host smart-1b47edea-b074-4931-85e5-343d3b7f8f6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774631233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2774631233
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.33578812
Short name T1030
Test name
Test status
Simulation time 241149250913 ps
CPU time 268.12 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:06:07 PM PDT 24
Peak memory 200504 kb
Host smart-3ee1bdb7-0818-42c8-99a7-7349b035a5d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33578812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.33578812
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.865253509
Short name T786
Test name
Test status
Simulation time 4227073123 ps
CPU time 3.04 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:44 PM PDT 24
Peak memory 199832 kb
Host smart-4b417b1d-5820-4416-ae58-66cc781d77bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865253509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.865253509
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3305887543
Short name T555
Test name
Test status
Simulation time 115352455590 ps
CPU time 67.94 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:02:48 PM PDT 24
Peak memory 199672 kb
Host smart-134e5f88-8f84-43ad-92cc-fbf1e8a7d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305887543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3305887543
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.392951876
Short name T484
Test name
Test status
Simulation time 8014361569 ps
CPU time 453.47 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:09:14 PM PDT 24
Peak memory 200356 kb
Host smart-14fb4a52-3c76-4a85-9dd9-51092a43d108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392951876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.392951876
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3263556486
Short name T1060
Test name
Test status
Simulation time 6028944057 ps
CPU time 64.1 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:02:44 PM PDT 24
Peak memory 199964 kb
Host smart-8f1f4afd-b610-49f9-81df-5add1153b940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263556486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3263556486
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.637518193
Short name T933
Test name
Test status
Simulation time 109942336028 ps
CPU time 164.25 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:04:24 PM PDT 24
Peak memory 200472 kb
Host smart-9608b6e1-5c89-4cc2-b458-698349a266ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637518193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.637518193
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1076366416
Short name T567
Test name
Test status
Simulation time 39234650544 ps
CPU time 48.89 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 196492 kb
Host smart-14549058-55e3-42e5-9bc0-1b7d6a7556d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076366416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1076366416
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1694147494
Short name T297
Test name
Test status
Simulation time 463569856 ps
CPU time 2.78 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 200220 kb
Host smart-73fd5dcf-f97e-4ea1-9087-91f6fe712992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694147494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1694147494
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3469787273
Short name T294
Test name
Test status
Simulation time 83036304769 ps
CPU time 358.54 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:07:39 PM PDT 24
Peak memory 200504 kb
Host smart-6f61d1d8-73de-4fc2-95c2-8a56de19a6cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469787273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3469787273
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1580742389
Short name T826
Test name
Test status
Simulation time 23598904802 ps
CPU time 1248.85 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:22:35 PM PDT 24
Peak memory 217148 kb
Host smart-c803ebbb-3585-49be-954b-a5421af7e5b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580742389 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1580742389
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.452098333
Short name T1064
Test name
Test status
Simulation time 1094239853 ps
CPU time 2.21 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 199228 kb
Host smart-71e278fc-49f6-410d-9dab-a7bc1d00c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452098333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.452098333
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3306083535
Short name T989
Test name
Test status
Simulation time 51595919209 ps
CPU time 76.05 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:02:57 PM PDT 24
Peak memory 200500 kb
Host smart-150af96b-9939-47f8-ba09-4f0755e31fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306083535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3306083535
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1287588894
Short name T185
Test name
Test status
Simulation time 133841497009 ps
CPU time 70.7 seconds
Started May 16 01:05:10 PM PDT 24
Finished May 16 01:06:31 PM PDT 24
Peak memory 200432 kb
Host smart-b680fb4c-f0d6-4042-9c78-4f536157c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287588894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1287588894
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.52231476
Short name T1071
Test name
Test status
Simulation time 19108026489 ps
CPU time 18.59 seconds
Started May 16 01:05:10 PM PDT 24
Finished May 16 01:05:39 PM PDT 24
Peak memory 200388 kb
Host smart-b903fbb5-14fa-45f1-a4d6-77a6e1fc1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52231476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.52231476
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2394084244
Short name T1148
Test name
Test status
Simulation time 46550304432 ps
CPU time 44.65 seconds
Started May 16 01:05:09 PM PDT 24
Finished May 16 01:06:03 PM PDT 24
Peak memory 200540 kb
Host smart-99b98e49-1ff4-4287-8e97-122c018a8803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394084244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2394084244
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.510578499
Short name T435
Test name
Test status
Simulation time 74629122298 ps
CPU time 57.31 seconds
Started May 16 01:05:09 PM PDT 24
Finished May 16 01:06:16 PM PDT 24
Peak memory 200436 kb
Host smart-2c6040c7-1dcd-4a0b-8b97-d873912080f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510578499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.510578499
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.321632407
Short name T207
Test name
Test status
Simulation time 14382266290 ps
CPU time 10.32 seconds
Started May 16 01:05:08 PM PDT 24
Finished May 16 01:05:29 PM PDT 24
Peak memory 200424 kb
Host smart-b80a9f43-d406-49e7-8127-3eb6b82f6336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321632407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.321632407
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2921182800
Short name T533
Test name
Test status
Simulation time 34074545038 ps
CPU time 30.02 seconds
Started May 16 01:05:10 PM PDT 24
Finished May 16 01:05:50 PM PDT 24
Peak memory 200512 kb
Host smart-22c8d2b8-0d87-4a83-8ef5-24e0af334729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921182800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2921182800
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2968985416
Short name T871
Test name
Test status
Simulation time 126896605926 ps
CPU time 193.6 seconds
Started May 16 01:05:11 PM PDT 24
Finished May 16 01:08:34 PM PDT 24
Peak memory 200488 kb
Host smart-79763f68-2b04-4c11-b2d7-0e969e0d3ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968985416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2968985416
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.835026121
Short name T276
Test name
Test status
Simulation time 26826636150 ps
CPU time 30.43 seconds
Started May 16 01:05:09 PM PDT 24
Finished May 16 01:05:49 PM PDT 24
Peak memory 200548 kb
Host smart-68140486-8636-45cb-966a-bbc521a55850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835026121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.835026121
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3713702274
Short name T1100
Test name
Test status
Simulation time 51508415 ps
CPU time 0.57 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:00:53 PM PDT 24
Peak memory 195780 kb
Host smart-0718abe8-3738-464b-b77e-2fcb29583219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713702274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3713702274
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2792449361
Short name T177
Test name
Test status
Simulation time 69877093119 ps
CPU time 21.5 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:01:09 PM PDT 24
Peak memory 200456 kb
Host smart-9358887e-2105-4e38-a5d6-139e93fa5429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792449361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2792449361
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2868556246
Short name T927
Test name
Test status
Simulation time 128156326430 ps
CPU time 183.35 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:03:52 PM PDT 24
Peak memory 200384 kb
Host smart-be7be3d1-2c11-49c3-8f3f-ee0b65d3237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868556246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2868556246
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.2926308221
Short name T708
Test name
Test status
Simulation time 46923573311 ps
CPU time 13.11 seconds
Started May 16 01:00:05 PM PDT 24
Finished May 16 01:01:00 PM PDT 24
Peak memory 200400 kb
Host smart-ca8ecf4f-ceaa-4047-87ef-3adf7a455bc3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926308221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2926308221
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.271442896
Short name T389
Test name
Test status
Simulation time 51125888768 ps
CPU time 208.79 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:04:20 PM PDT 24
Peak memory 200492 kb
Host smart-983f85a5-4a30-4e25-9ccb-b9769c211a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271442896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.271442896
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1510405255
Short name T821
Test name
Test status
Simulation time 2945932954 ps
CPU time 4.29 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:00:52 PM PDT 24
Peak memory 196288 kb
Host smart-239359f5-e9f0-41b9-9cb3-ac5801a459da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510405255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1510405255
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3498836400
Short name T375
Test name
Test status
Simulation time 184942582247 ps
CPU time 103.08 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:02:31 PM PDT 24
Peak memory 200828 kb
Host smart-66797dac-153c-44e1-9994-04a9ec42c51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498836400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3498836400
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3784809256
Short name T277
Test name
Test status
Simulation time 32466197345 ps
CPU time 223.59 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:04:36 PM PDT 24
Peak memory 200448 kb
Host smart-26e7d661-619a-46cc-a831-bbc25f364ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784809256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3784809256
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.389874387
Short name T1082
Test name
Test status
Simulation time 2860573629 ps
CPU time 20.27 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:01:08 PM PDT 24
Peak memory 198844 kb
Host smart-eae1ab8d-2397-4d74-a7e5-0c5d2ce3c8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389874387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.389874387
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2041136816
Short name T1075
Test name
Test status
Simulation time 19796354368 ps
CPU time 32.92 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:29 PM PDT 24
Peak memory 200472 kb
Host smart-8a42853b-52e9-4fcf-b759-9eac7d8fde5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041136816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2041136816
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2884134048
Short name T274
Test name
Test status
Simulation time 46140907407 ps
CPU time 14.49 seconds
Started May 16 01:00:07 PM PDT 24
Finished May 16 01:01:03 PM PDT 24
Peak memory 196784 kb
Host smart-070b5406-8942-4f84-9466-eaa4620ab80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884134048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2884134048
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3634981694
Short name T29
Test name
Test status
Simulation time 65770900 ps
CPU time 0.83 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:00:55 PM PDT 24
Peak memory 218908 kb
Host smart-fd454098-428c-443c-9aba-3264c5c65a88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634981694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3634981694
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3830815043
Short name T940
Test name
Test status
Simulation time 6090688590 ps
CPU time 8.27 seconds
Started May 16 01:00:06 PM PDT 24
Finished May 16 01:00:56 PM PDT 24
Peak memory 200436 kb
Host smart-a24b4565-e185-47f0-a121-1e18982be4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830815043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3830815043
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3448573628
Short name T716
Test name
Test status
Simulation time 20065967101 ps
CPU time 106.52 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:02:38 PM PDT 24
Peak memory 216604 kb
Host smart-4de55754-2520-4025-848e-b440eb35e444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448573628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3448573628
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2428624205
Short name T619
Test name
Test status
Simulation time 8035428280 ps
CPU time 12.18 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:08 PM PDT 24
Peak memory 200424 kb
Host smart-bffc402a-e5dc-4c6f-b2a5-27eacf418ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428624205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2428624205
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.181321035
Short name T314
Test name
Test status
Simulation time 86275237946 ps
CPU time 207.16 seconds
Started May 16 01:00:03 PM PDT 24
Finished May 16 01:04:12 PM PDT 24
Peak memory 200420 kb
Host smart-19eb13dd-733d-4fe0-bcb2-3dabee31bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181321035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.181321035
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3523822084
Short name T27
Test name
Test status
Simulation time 19977696 ps
CPU time 0.55 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:01:42 PM PDT 24
Peak memory 195848 kb
Host smart-fee565ee-6230-421f-9a41-51512c6d36ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523822084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3523822084
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1738730700
Short name T884
Test name
Test status
Simulation time 169325005682 ps
CPU time 37.22 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:02:18 PM PDT 24
Peak memory 200528 kb
Host smart-4787fb4e-67d5-46b9-95eb-413e0385b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738730700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1738730700
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3944982179
Short name T755
Test name
Test status
Simulation time 22359920396 ps
CPU time 23.48 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:02:03 PM PDT 24
Peak memory 200440 kb
Host smart-f93d7a5b-4133-46a3-9160-1f1adc937cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944982179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3944982179
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.1959280970
Short name T472
Test name
Test status
Simulation time 22801317699 ps
CPU time 8.28 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:01:50 PM PDT 24
Peak memory 200292 kb
Host smart-45b0a1b0-c199-4be3-b752-707e5f178efb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959280970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1959280970
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2218524396
Short name T1115
Test name
Test status
Simulation time 49376599564 ps
CPU time 68.58 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:02:48 PM PDT 24
Peak memory 200396 kb
Host smart-644e863f-5d80-47f9-a28d-6341e491c1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218524396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2218524396
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1569592964
Short name T854
Test name
Test status
Simulation time 3630611740 ps
CPU time 2.48 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:01:42 PM PDT 24
Peak memory 199252 kb
Host smart-e9f52dc8-1a7a-44e5-9aac-4c697e9f8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569592964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1569592964
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3790180091
Short name T866
Test name
Test status
Simulation time 32026163980 ps
CPU time 13.07 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:54 PM PDT 24
Peak memory 199320 kb
Host smart-7e595aaa-4f63-4697-848e-a8694310f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790180091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3790180091
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1924867958
Short name T875
Test name
Test status
Simulation time 7151758320 ps
CPU time 94.34 seconds
Started May 16 01:01:13 PM PDT 24
Finished May 16 01:03:18 PM PDT 24
Peak memory 200364 kb
Host smart-4bf3666b-a38d-4a2c-8bab-8b272901ced7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924867958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1924867958
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3805699375
Short name T403
Test name
Test status
Simulation time 3704839605 ps
CPU time 7.28 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:01:48 PM PDT 24
Peak memory 198564 kb
Host smart-166399c5-64ef-4a1c-b1d1-d8691e39e354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805699375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3805699375
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3726507292
Short name T955
Test name
Test status
Simulation time 116540579551 ps
CPU time 204.39 seconds
Started May 16 01:01:14 PM PDT 24
Finished May 16 01:05:10 PM PDT 24
Peak memory 200440 kb
Host smart-e00f005d-e857-491e-bd88-2c28a94bd364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726507292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3726507292
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4137884341
Short name T947
Test name
Test status
Simulation time 29674341152 ps
CPU time 12.12 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:01:52 PM PDT 24
Peak memory 196484 kb
Host smart-aa91181c-727f-47c6-aea5-f11c15f9d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137884341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4137884341
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.448403849
Short name T1143
Test name
Test status
Simulation time 269737769 ps
CPU time 1.39 seconds
Started May 16 01:01:10 PM PDT 24
Finished May 16 01:01:42 PM PDT 24
Peak memory 199000 kb
Host smart-a478cf9a-ce60-4be5-9f48-e7aa381f6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448403849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.448403849
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3461879168
Short name T984
Test name
Test status
Simulation time 97912724368 ps
CPU time 82.46 seconds
Started May 16 01:01:14 PM PDT 24
Finished May 16 01:03:07 PM PDT 24
Peak memory 200468 kb
Host smart-f2305e88-f865-4b4a-ae75-395f405a6545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461879168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3461879168
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3801948611
Short name T172
Test name
Test status
Simulation time 85228323755 ps
CPU time 745.39 seconds
Started May 16 01:01:14 PM PDT 24
Finished May 16 01:14:10 PM PDT 24
Peak memory 217176 kb
Host smart-4b78dff7-a20b-4bb9-b6a1-5b70974d17bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801948611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3801948611
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1275283279
Short name T1044
Test name
Test status
Simulation time 405206127 ps
CPU time 1.37 seconds
Started May 16 01:01:07 PM PDT 24
Finished May 16 01:01:40 PM PDT 24
Peak memory 197440 kb
Host smart-c1af2d1b-a08a-4f3b-90eb-ca6fdfec8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275283279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1275283279
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2287143843
Short name T335
Test name
Test status
Simulation time 44584298952 ps
CPU time 20.67 seconds
Started May 16 01:01:08 PM PDT 24
Finished May 16 01:02:00 PM PDT 24
Peak memory 200512 kb
Host smart-25838002-f20a-4902-9941-422f30df2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287143843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2287143843
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2450470011
Short name T1079
Test name
Test status
Simulation time 7637653290 ps
CPU time 12.17 seconds
Started May 16 01:05:11 PM PDT 24
Finished May 16 01:05:32 PM PDT 24
Peak memory 200420 kb
Host smart-bda45086-42b9-44ba-a527-361404dc7382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450470011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2450470011
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1452484879
Short name T222
Test name
Test status
Simulation time 33823213740 ps
CPU time 94.54 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:07:06 PM PDT 24
Peak memory 200420 kb
Host smart-34054a3e-f121-4b9b-a9cc-34833b5299f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452484879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1452484879
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1502540209
Short name T503
Test name
Test status
Simulation time 90147813089 ps
CPU time 157.12 seconds
Started May 16 01:05:20 PM PDT 24
Finished May 16 01:08:07 PM PDT 24
Peak memory 200492 kb
Host smart-f212e08a-12e5-403e-9a8e-b73d2c82bcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502540209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1502540209
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1312468168
Short name T1165
Test name
Test status
Simulation time 23023053537 ps
CPU time 38.81 seconds
Started May 16 01:05:21 PM PDT 24
Finished May 16 01:06:08 PM PDT 24
Peak memory 200532 kb
Host smart-849c3eeb-1465-4fff-b53f-ce4de2c967b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312468168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1312468168
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1242485443
Short name T295
Test name
Test status
Simulation time 90582405988 ps
CPU time 56.72 seconds
Started May 16 01:05:18 PM PDT 24
Finished May 16 01:06:23 PM PDT 24
Peak memory 200436 kb
Host smart-fdf77a62-9db7-4f6c-a088-6bdf7276adc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242485443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1242485443
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.402830644
Short name T857
Test name
Test status
Simulation time 158841174198 ps
CPU time 380.19 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:11:52 PM PDT 24
Peak memory 200424 kb
Host smart-0ec5ee86-bc21-4469-83a0-fe2a2eda1039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402830644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.402830644
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3496115825
Short name T675
Test name
Test status
Simulation time 18565155277 ps
CPU time 19.58 seconds
Started May 16 01:05:21 PM PDT 24
Finished May 16 01:05:49 PM PDT 24
Peak memory 200456 kb
Host smart-74a8643a-02ab-4d13-860a-ac597308d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496115825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3496115825
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3250665266
Short name T159
Test name
Test status
Simulation time 133727202990 ps
CPU time 58.34 seconds
Started May 16 01:05:20 PM PDT 24
Finished May 16 01:06:27 PM PDT 24
Peak memory 200432 kb
Host smart-bb8763fa-db57-43da-9730-25fbb075d3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250665266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3250665266
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2502275590
Short name T965
Test name
Test status
Simulation time 70836277448 ps
CPU time 231.16 seconds
Started May 16 01:05:20 PM PDT 24
Finished May 16 01:09:20 PM PDT 24
Peak memory 200428 kb
Host smart-2cefceef-ffb4-4f75-83df-3d7afc2a4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502275590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2502275590
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.304397103
Short name T466
Test name
Test status
Simulation time 36718815 ps
CPU time 0.54 seconds
Started May 16 01:01:14 PM PDT 24
Finished May 16 01:01:46 PM PDT 24
Peak memory 195816 kb
Host smart-1765575d-b608-4276-9a06-f670c686d59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304397103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.304397103
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3531292457
Short name T631
Test name
Test status
Simulation time 56402637511 ps
CPU time 15.08 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:01:57 PM PDT 24
Peak memory 200400 kb
Host smart-6cacf3e5-83d1-4e2f-ab36-5be9bd757375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531292457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3531292457
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3313457825
Short name T12
Test name
Test status
Simulation time 53713357318 ps
CPU time 46.09 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:02:26 PM PDT 24
Peak memory 200508 kb
Host smart-4d88483d-859a-48a5-8fc2-982f928a0bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313457825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3313457825
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.367334311
Short name T571
Test name
Test status
Simulation time 43596442633 ps
CPU time 36.65 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:23 PM PDT 24
Peak memory 198488 kb
Host smart-4fc0c77f-85fa-485c-8be4-b1e8467ca9e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367334311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.367334311
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2649962540
Short name T604
Test name
Test status
Simulation time 115183794680 ps
CPU time 294.62 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:06:41 PM PDT 24
Peak memory 200440 kb
Host smart-513c6a00-2357-4f17-95db-1f58fa9292d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649962540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2649962540
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2779096305
Short name T392
Test name
Test status
Simulation time 4967025322 ps
CPU time 15.47 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 199224 kb
Host smart-06f8effc-4090-44a7-949f-5ea9acf1255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779096305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2779096305
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3052187414
Short name T653
Test name
Test status
Simulation time 22140312366 ps
CPU time 39.37 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:02:20 PM PDT 24
Peak memory 199648 kb
Host smart-83a0d9dd-2d50-4421-908b-67f53240ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052187414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3052187414
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3176967445
Short name T496
Test name
Test status
Simulation time 19224111702 ps
CPU time 1049.47 seconds
Started May 16 01:01:18 PM PDT 24
Finished May 16 01:19:19 PM PDT 24
Peak memory 200452 kb
Host smart-467c533a-0af2-4be2-bc44-0ce844fde30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176967445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3176967445
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2205337635
Short name T639
Test name
Test status
Simulation time 5080112380 ps
CPU time 8.31 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:01:49 PM PDT 24
Peak memory 198620 kb
Host smart-97001eb4-ac55-4ade-a293-766263b13add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205337635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2205337635
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4293080332
Short name T1128
Test name
Test status
Simulation time 54976908292 ps
CPU time 97.22 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:03:20 PM PDT 24
Peak memory 200444 kb
Host smart-10fdaf06-bcd2-4d58-8cda-6124aa8c20ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293080332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4293080332
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1606029881
Short name T491
Test name
Test status
Simulation time 32124862357 ps
CPU time 11.9 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:01:54 PM PDT 24
Peak memory 196480 kb
Host smart-3e56f806-6851-47bd-af39-75683f126868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606029881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1606029881
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.407114324
Short name T694
Test name
Test status
Simulation time 295338314 ps
CPU time 1.03 seconds
Started May 16 01:01:11 PM PDT 24
Finished May 16 01:01:43 PM PDT 24
Peak memory 198684 kb
Host smart-b4287513-6289-4525-bd3d-75c5243e2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407114324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.407114324
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.775388695
Short name T834
Test name
Test status
Simulation time 219398927443 ps
CPU time 92.76 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:03:15 PM PDT 24
Peak memory 200424 kb
Host smart-42052336-eee7-4b1d-ab7c-e8098459076b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775388695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.775388695
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4224903408
Short name T433
Test name
Test status
Simulation time 334734292068 ps
CPU time 649.89 seconds
Started May 16 01:01:13 PM PDT 24
Finished May 16 01:12:33 PM PDT 24
Peak memory 214100 kb
Host smart-658b10b2-a625-4d96-a136-c47e9776f563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224903408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4224903408
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1482293786
Short name T500
Test name
Test status
Simulation time 6968045139 ps
CPU time 14.47 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:01 PM PDT 24
Peak memory 200428 kb
Host smart-9f8efd4c-da6f-446a-9ff3-444f32983f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482293786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1482293786
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.87188019
Short name T1087
Test name
Test status
Simulation time 35327681445 ps
CPU time 65.76 seconds
Started May 16 01:01:09 PM PDT 24
Finished May 16 01:02:46 PM PDT 24
Peak memory 200444 kb
Host smart-51499d44-e744-41d8-8c76-b9d63e5c4bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87188019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.87188019
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3767157564
Short name T835
Test name
Test status
Simulation time 6850196119 ps
CPU time 5.82 seconds
Started May 16 01:05:22 PM PDT 24
Finished May 16 01:05:36 PM PDT 24
Peak memory 200432 kb
Host smart-b2f7b5e0-d909-4c6e-aea7-26cc5df583f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767157564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3767157564
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.760401958
Short name T797
Test name
Test status
Simulation time 59792918442 ps
CPU time 37.79 seconds
Started May 16 01:05:24 PM PDT 24
Finished May 16 01:06:10 PM PDT 24
Peak memory 200360 kb
Host smart-bfe09276-a083-457e-b64a-229947961d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760401958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.760401958
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2719068159
Short name T246
Test name
Test status
Simulation time 116673687979 ps
CPU time 33.82 seconds
Started May 16 01:05:24 PM PDT 24
Finished May 16 01:06:06 PM PDT 24
Peak memory 200532 kb
Host smart-5a1a10dd-42f3-4d59-979b-2bdeaa681481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719068159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2719068159
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2082344804
Short name T733
Test name
Test status
Simulation time 153221115867 ps
CPU time 144.85 seconds
Started May 16 01:05:22 PM PDT 24
Finished May 16 01:07:56 PM PDT 24
Peak memory 200372 kb
Host smart-f52ff699-a640-440d-a52d-950a6c19162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082344804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2082344804
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.997113295
Short name T992
Test name
Test status
Simulation time 6989874794 ps
CPU time 10.2 seconds
Started May 16 01:05:19 PM PDT 24
Finished May 16 01:05:38 PM PDT 24
Peak memory 200444 kb
Host smart-b2809cba-bc18-42e6-9597-cc309e761063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997113295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.997113295
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1896841386
Short name T324
Test name
Test status
Simulation time 131023631834 ps
CPU time 183.74 seconds
Started May 16 01:05:21 PM PDT 24
Finished May 16 01:08:34 PM PDT 24
Peak memory 200488 kb
Host smart-a2c70f56-02d8-4708-ba60-432694cce485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896841386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1896841386
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1668073126
Short name T126
Test name
Test status
Simulation time 36479857579 ps
CPU time 31.47 seconds
Started May 16 01:05:19 PM PDT 24
Finished May 16 01:05:59 PM PDT 24
Peak memory 200464 kb
Host smart-8bc59b24-4c87-492a-82f4-6b83faaaf69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668073126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1668073126
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1271562257
Short name T568
Test name
Test status
Simulation time 84065680560 ps
CPU time 153.24 seconds
Started May 16 01:05:25 PM PDT 24
Finished May 16 01:08:06 PM PDT 24
Peak memory 200504 kb
Host smart-0fc15b23-c725-429e-96af-1400786cfd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271562257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1271562257
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1596209484
Short name T1159
Test name
Test status
Simulation time 168896524552 ps
CPU time 75.61 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:06:48 PM PDT 24
Peak memory 200484 kb
Host smart-27bf030c-01cb-4fc6-a4fb-db6eee4f0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596209484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1596209484
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1782625700
Short name T142
Test name
Test status
Simulation time 81365681912 ps
CPU time 39.54 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:06:11 PM PDT 24
Peak memory 200364 kb
Host smart-f5f5d114-a228-464e-8d77-aca1ddc0ef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782625700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1782625700
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4050185237
Short name T1096
Test name
Test status
Simulation time 19285326 ps
CPU time 0.53 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:01:49 PM PDT 24
Peak memory 195292 kb
Host smart-6dcd9417-b86a-43c5-be76-6098583f1235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050185237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4050185237
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2879491023
Short name T136
Test name
Test status
Simulation time 59151578808 ps
CPU time 42.49 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 200500 kb
Host smart-074b510e-ce45-450e-9bdc-68218eb675b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879491023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2879491023
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2989966791
Short name T1007
Test name
Test status
Simulation time 31724294705 ps
CPU time 48.64 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:02:37 PM PDT 24
Peak memory 200572 kb
Host smart-38d05d59-6108-478a-ac18-bd5f13c5e5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989966791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2989966791
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2871580966
Short name T191
Test name
Test status
Simulation time 71386921072 ps
CPU time 76.87 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 200424 kb
Host smart-b9f39df9-9747-400f-8dbd-a8bda3e99c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871580966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2871580966
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.674810141
Short name T859
Test name
Test status
Simulation time 156229325470 ps
CPU time 115.91 seconds
Started May 16 01:01:21 PM PDT 24
Finished May 16 01:03:47 PM PDT 24
Peak memory 200476 kb
Host smart-0e492e78-fc9d-4d5e-b731-98e64ab46a4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674810141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.674810141
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3190164272
Short name T860
Test name
Test status
Simulation time 48809629279 ps
CPU time 145.08 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:04:13 PM PDT 24
Peak memory 200436 kb
Host smart-ccbf32a2-4f9f-4874-9c4e-050d2a962d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190164272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3190164272
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.137931168
Short name T673
Test name
Test status
Simulation time 3056340015 ps
CPU time 2.57 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:01:50 PM PDT 24
Peak memory 200372 kb
Host smart-e33b99e6-784d-4eaf-912d-1fe027a4c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137931168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.137931168
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.778870765
Short name T572
Test name
Test status
Simulation time 238991474590 ps
CPU time 127.28 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:03:55 PM PDT 24
Peak memory 208896 kb
Host smart-1a824111-5d14-46ae-a3b5-495c4814786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778870765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.778870765
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3719928640
Short name T912
Test name
Test status
Simulation time 15808327264 ps
CPU time 747.94 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:14:18 PM PDT 24
Peak memory 200420 kb
Host smart-74452e51-8682-4bfe-8810-e80608d50556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719928640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3719928640
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2392497399
Short name T811
Test name
Test status
Simulation time 6495600027 ps
CPU time 58.14 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:45 PM PDT 24
Peak memory 199812 kb
Host smart-887c8a9c-fd78-4e32-86eb-f65315057cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392497399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2392497399
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.396577858
Short name T416
Test name
Test status
Simulation time 21696442759 ps
CPU time 19.68 seconds
Started May 16 01:01:21 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 200404 kb
Host smart-fac68b05-64df-47d1-b3cd-c3cb286f06c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396577858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.396577858
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.627042240
Short name T562
Test name
Test status
Simulation time 4216907084 ps
CPU time 7.53 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:01:56 PM PDT 24
Peak memory 196448 kb
Host smart-43ca69f1-6785-4375-b26c-4c7efb4d51e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627042240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.627042240
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3849054657
Short name T975
Test name
Test status
Simulation time 449949876 ps
CPU time 2.04 seconds
Started May 16 01:01:12 PM PDT 24
Finished May 16 01:01:44 PM PDT 24
Peak memory 200356 kb
Host smart-17fafad7-ad42-43bd-9e20-392db10981b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849054657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3849054657
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1461426139
Short name T156
Test name
Test status
Simulation time 84604875674 ps
CPU time 1680.73 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:29:48 PM PDT 24
Peak memory 226368 kb
Host smart-f8a90a1b-4014-4352-b500-6ae0f6883faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461426139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1461426139
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.641681324
Short name T1048
Test name
Test status
Simulation time 828147628 ps
CPU time 1.27 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:01:49 PM PDT 24
Peak memory 198876 kb
Host smart-200b7537-739f-485e-92c5-d5ef22234168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641681324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.641681324
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1133171275
Short name T625
Test name
Test status
Simulation time 121299610653 ps
CPU time 70.56 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:57 PM PDT 24
Peak memory 200432 kb
Host smart-9f7d689d-453b-466b-b394-2ba216b83f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133171275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1133171275
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.226415835
Short name T594
Test name
Test status
Simulation time 86391116586 ps
CPU time 190.86 seconds
Started May 16 01:05:20 PM PDT 24
Finished May 16 01:08:40 PM PDT 24
Peak memory 200432 kb
Host smart-b995e06d-ecee-4941-ab1e-5bc25478d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226415835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.226415835
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1249036009
Short name T615
Test name
Test status
Simulation time 46641413267 ps
CPU time 80.01 seconds
Started May 16 01:05:22 PM PDT 24
Finished May 16 01:06:50 PM PDT 24
Peak memory 200436 kb
Host smart-8ab0f2df-17ca-49e5-89bd-370c232e0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249036009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1249036009
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1812910645
Short name T296
Test name
Test status
Simulation time 159067482281 ps
CPU time 76.48 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:06:48 PM PDT 24
Peak memory 200480 kb
Host smart-295c9290-2b3f-4ee5-9d0c-277fef5acbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812910645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1812910645
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1926359989
Short name T1123
Test name
Test status
Simulation time 13072717792 ps
CPU time 22.52 seconds
Started May 16 01:05:19 PM PDT 24
Finished May 16 01:05:50 PM PDT 24
Peak memory 200496 kb
Host smart-82d009c0-33c6-4088-9bdc-a3656f197fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926359989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1926359989
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2914783246
Short name T147
Test name
Test status
Simulation time 112351802665 ps
CPU time 169.47 seconds
Started May 16 01:05:19 PM PDT 24
Finished May 16 01:08:17 PM PDT 24
Peak memory 200408 kb
Host smart-3e6e7237-cd0b-44ec-ba2b-a2b1e4caa60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914783246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2914783246
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1222958106
Short name T476
Test name
Test status
Simulation time 77907978835 ps
CPU time 21.24 seconds
Started May 16 01:05:19 PM PDT 24
Finished May 16 01:05:49 PM PDT 24
Peak memory 200500 kb
Host smart-e6a0244e-f0fe-4fb4-97fa-54afdfb49b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222958106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1222958106
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2534792725
Short name T149
Test name
Test status
Simulation time 16381742891 ps
CPU time 32.99 seconds
Started May 16 01:05:24 PM PDT 24
Finished May 16 01:06:05 PM PDT 24
Peak memory 200476 kb
Host smart-c270bf15-782d-4880-984d-f750ec50d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534792725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2534792725
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.72506435
Short name T1181
Test name
Test status
Simulation time 12367776973 ps
CPU time 7.35 seconds
Started May 16 01:05:20 PM PDT 24
Finished May 16 01:05:36 PM PDT 24
Peak memory 200504 kb
Host smart-75f14ef7-5a60-4168-bcbe-a5be74424305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72506435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.72506435
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1446693892
Short name T244
Test name
Test status
Simulation time 95215125638 ps
CPU time 50.23 seconds
Started May 16 01:05:21 PM PDT 24
Finished May 16 01:06:19 PM PDT 24
Peak memory 200524 kb
Host smart-1d6ebbe3-dacd-458d-ad86-d67c46786a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446693892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1446693892
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3128937069
Short name T26
Test name
Test status
Simulation time 14709219 ps
CPU time 0.53 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:01:48 PM PDT 24
Peak memory 195236 kb
Host smart-1c925297-b8fa-4c75-a40d-489307aca935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128937069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3128937069
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.161389440
Short name T1051
Test name
Test status
Simulation time 273316940027 ps
CPU time 52.13 seconds
Started May 16 01:01:14 PM PDT 24
Finished May 16 01:02:38 PM PDT 24
Peak memory 200392 kb
Host smart-29bc15cd-a595-401c-a7bd-dfa6b0ead186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161389440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.161389440
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1139245355
Short name T345
Test name
Test status
Simulation time 8596825669 ps
CPU time 17.78 seconds
Started May 16 01:01:23 PM PDT 24
Finished May 16 01:02:12 PM PDT 24
Peak memory 200472 kb
Host smart-43f55f69-c403-47c4-9c85-3856d5236a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139245355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1139245355
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2505124343
Short name T133
Test name
Test status
Simulation time 91972825289 ps
CPU time 41.06 seconds
Started May 16 01:01:19 PM PDT 24
Finished May 16 01:02:31 PM PDT 24
Peak memory 200484 kb
Host smart-0403fea3-ec69-46a4-b2ea-220c1903c09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505124343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2505124343
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.337886296
Short name T554
Test name
Test status
Simulation time 17851212959 ps
CPU time 8.64 seconds
Started May 16 01:01:18 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 197996 kb
Host smart-f5e8255a-ed71-4fe3-afd6-a2fac6b18d22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337886296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.337886296
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4064815806
Short name T948
Test name
Test status
Simulation time 151902900399 ps
CPU time 525.59 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 200420 kb
Host smart-6430e758-1914-4e37-80d3-8cf58e7f2e26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064815806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4064815806
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1043005911
Short name T508
Test name
Test status
Simulation time 1935771685 ps
CPU time 2.22 seconds
Started May 16 01:01:19 PM PDT 24
Finished May 16 01:01:52 PM PDT 24
Peak memory 196344 kb
Host smart-d9155bbf-6a98-4aad-92a3-b67495d54e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043005911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1043005911
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.681018520
Short name T404
Test name
Test status
Simulation time 117149639822 ps
CPU time 97.54 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:03:28 PM PDT 24
Peak memory 208776 kb
Host smart-6e87cde5-2658-40fc-9300-216e5218ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681018520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.681018520
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1060455979
Short name T346
Test name
Test status
Simulation time 17422347996 ps
CPU time 227.77 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:05:35 PM PDT 24
Peak memory 200452 kb
Host smart-829c1d4b-e522-4298-b180-6052261166b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060455979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1060455979
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3652706426
Short name T672
Test name
Test status
Simulation time 4088986370 ps
CPU time 32.52 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:20 PM PDT 24
Peak memory 199712 kb
Host smart-02495a5e-9607-4653-a53c-f39f2c2e7a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652706426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3652706426
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1066920729
Short name T898
Test name
Test status
Simulation time 144217308288 ps
CPU time 37.14 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:02:28 PM PDT 24
Peak memory 200176 kb
Host smart-bf957d69-6ef9-46d4-8adc-4842faed5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066920729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1066920729
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.291905180
Short name T309
Test name
Test status
Simulation time 34505798472 ps
CPU time 47.78 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:34 PM PDT 24
Peak memory 196476 kb
Host smart-dadc8432-d9a8-4b0d-8932-f0f5f996bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291905180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.291905180
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.224505154
Short name T300
Test name
Test status
Simulation time 501983305 ps
CPU time 1.57 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:01:50 PM PDT 24
Peak memory 198924 kb
Host smart-1f47c554-fba8-4345-8be0-71c58628ccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224505154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.224505154
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.599038948
Short name T327
Test name
Test status
Simulation time 511829462924 ps
CPU time 2032.8 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:35:39 PM PDT 24
Peak memory 200452 kb
Host smart-6d720450-4c71-48ca-9d16-a86d9fa182b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599038948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.599038948
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1813968702
Short name T213
Test name
Test status
Simulation time 349448997187 ps
CPU time 1885.08 seconds
Started May 16 01:01:17 PM PDT 24
Finished May 16 01:33:14 PM PDT 24
Peak memory 225572 kb
Host smart-23e8fb07-db08-491d-a0bc-b9bb27df2e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813968702 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1813968702
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1709498756
Short name T936
Test name
Test status
Simulation time 7931312200 ps
CPU time 9.92 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:01:56 PM PDT 24
Peak memory 200392 kb
Host smart-270c9d75-ac2e-4ba6-a2b6-93b074106a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709498756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1709498756
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3909073800
Short name T397
Test name
Test status
Simulation time 79998296680 ps
CPU time 57.69 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:45 PM PDT 24
Peak memory 200360 kb
Host smart-53cc8164-7cee-48d5-a9b1-6abde8c0d92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909073800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3909073800
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1206624041
Short name T589
Test name
Test status
Simulation time 25945438114 ps
CPU time 47.22 seconds
Started May 16 01:05:22 PM PDT 24
Finished May 16 01:06:18 PM PDT 24
Peak memory 200540 kb
Host smart-ec2fb31a-b699-4531-a777-e6fb0d6c6b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206624041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1206624041
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.179256691
Short name T384
Test name
Test status
Simulation time 18138501119 ps
CPU time 10.16 seconds
Started May 16 01:05:25 PM PDT 24
Finished May 16 01:05:43 PM PDT 24
Peak memory 200456 kb
Host smart-307ecc38-5fc3-45d8-adbf-bff69e1efed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179256691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.179256691
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1085949781
Short name T825
Test name
Test status
Simulation time 216187716534 ps
CPU time 539.07 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:14:31 PM PDT 24
Peak memory 200484 kb
Host smart-e50dde4d-97b8-4575-83b3-5a269299ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085949781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1085949781
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3626659915
Short name T211
Test name
Test status
Simulation time 153998238603 ps
CPU time 225.83 seconds
Started May 16 01:05:23 PM PDT 24
Finished May 16 01:09:18 PM PDT 24
Peak memory 200432 kb
Host smart-9fa9d67b-bed7-43df-96a1-65cdd2d5b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626659915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3626659915
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1467047777
Short name T862
Test name
Test status
Simulation time 176781435656 ps
CPU time 52.17 seconds
Started May 16 01:05:22 PM PDT 24
Finished May 16 01:06:22 PM PDT 24
Peak memory 200492 kb
Host smart-ca9148ea-7e79-4102-b182-52e7c20b6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467047777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1467047777
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2842729454
Short name T189
Test name
Test status
Simulation time 18019940709 ps
CPU time 30.95 seconds
Started May 16 01:09:42 PM PDT 24
Finished May 16 01:10:25 PM PDT 24
Peak memory 200460 kb
Host smart-fd658ce9-8510-45c1-8e1f-5ab7d860fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842729454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2842729454
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1177262221
Short name T145
Test name
Test status
Simulation time 33171190084 ps
CPU time 43.86 seconds
Started May 16 01:09:49 PM PDT 24
Finished May 16 01:10:48 PM PDT 24
Peak memory 200488 kb
Host smart-2a6cd275-c335-418d-a8f2-c0c1b38ee2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177262221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1177262221
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2177972819
Short name T738
Test name
Test status
Simulation time 5396688809 ps
CPU time 9.51 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:10:10 PM PDT 24
Peak memory 200504 kb
Host smart-4d1bdcb4-0340-4f58-897b-22d4a7489f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177972819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2177972819
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1791429553
Short name T155
Test name
Test status
Simulation time 24684231178 ps
CPU time 43.26 seconds
Started May 16 01:09:53 PM PDT 24
Finished May 16 01:10:51 PM PDT 24
Peak memory 200500 kb
Host smart-a22be0a5-b510-45d5-8eba-379ccffa4ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791429553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1791429553
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2380927722
Short name T1012
Test name
Test status
Simulation time 32507685 ps
CPU time 0.56 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:01:48 PM PDT 24
Peak memory 195852 kb
Host smart-cb9561b5-9055-46e6-9299-dc27909fad0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380927722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2380927722
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1316230775
Short name T135
Test name
Test status
Simulation time 184331541870 ps
CPU time 45.53 seconds
Started May 16 01:01:17 PM PDT 24
Finished May 16 01:02:34 PM PDT 24
Peak memory 200508 kb
Host smart-14843ff3-5f12-4e5a-8eab-bd11312d6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316230775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1316230775
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1132284537
Short name T1028
Test name
Test status
Simulation time 48346219457 ps
CPU time 18.03 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:02:06 PM PDT 24
Peak memory 200460 kb
Host smart-30d84fca-7272-4d10-8382-761acd6689b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132284537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1132284537
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3129570047
Short name T719
Test name
Test status
Simulation time 57851310965 ps
CPU time 138.37 seconds
Started May 16 01:01:23 PM PDT 24
Finished May 16 01:04:13 PM PDT 24
Peak memory 200484 kb
Host smart-a9a19161-8549-450d-a0d6-80752544f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129570047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3129570047
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1756514090
Short name T1154
Test name
Test status
Simulation time 42644198416 ps
CPU time 190.57 seconds
Started May 16 01:01:23 PM PDT 24
Finished May 16 01:05:05 PM PDT 24
Peak memory 200440 kb
Host smart-1da41af1-e10a-4630-802f-e05c4793f79d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756514090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1756514090
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2781589152
Short name T456
Test name
Test status
Simulation time 8700751521 ps
CPU time 17.6 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:02:08 PM PDT 24
Peak memory 200424 kb
Host smart-f6397684-d3ff-4562-9c5b-62170965b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781589152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2781589152
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.764032355
Short name T970
Test name
Test status
Simulation time 73508101326 ps
CPU time 36.28 seconds
Started May 16 01:01:23 PM PDT 24
Finished May 16 01:02:30 PM PDT 24
Peak memory 208944 kb
Host smart-20683186-3858-4a11-8a0c-0625df1372cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764032355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.764032355
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.765937880
Short name T37
Test name
Test status
Simulation time 5159875937 ps
CPU time 129.98 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:04:01 PM PDT 24
Peak memory 200460 kb
Host smart-c7a8061b-20c2-4ccb-a5ea-f86802a89707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765937880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.765937880
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3483834910
Short name T1
Test name
Test status
Simulation time 1986014495 ps
CPU time 8.55 seconds
Started May 16 01:01:23 PM PDT 24
Finished May 16 01:02:03 PM PDT 24
Peak memory 199560 kb
Host smart-1534c848-df26-454b-9e04-d3b01410db3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483834910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3483834910
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2910049998
Short name T355
Test name
Test status
Simulation time 56093216533 ps
CPU time 21.73 seconds
Started May 16 01:01:16 PM PDT 24
Finished May 16 01:02:10 PM PDT 24
Peak memory 200204 kb
Host smart-d5b19b3c-53f3-4c26-b93a-b6e7ea89c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910049998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2910049998
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3682487767
Short name T765
Test name
Test status
Simulation time 41574839432 ps
CPU time 18.05 seconds
Started May 16 01:01:17 PM PDT 24
Finished May 16 01:02:07 PM PDT 24
Peak memory 196204 kb
Host smart-db9d3508-1b29-4122-8ab7-75b74c00319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682487767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3682487767
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3212650871
Short name T423
Test name
Test status
Simulation time 5640471143 ps
CPU time 8.78 seconds
Started May 16 01:01:17 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 199692 kb
Host smart-c9055efe-a2cf-4433-b81d-b34cc4db4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212650871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3212650871
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.638041270
Short name T870
Test name
Test status
Simulation time 343568023668 ps
CPU time 214.16 seconds
Started May 16 01:01:19 PM PDT 24
Finished May 16 01:05:24 PM PDT 24
Peak memory 200420 kb
Host smart-7b61ab5a-601d-481b-8eb0-b4dc903aa53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638041270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.638041270
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2404660769
Short name T1138
Test name
Test status
Simulation time 53387625144 ps
CPU time 555.01 seconds
Started May 16 01:01:23 PM PDT 24
Finished May 16 01:11:08 PM PDT 24
Peak memory 217244 kb
Host smart-585c2eb5-0b23-4103-b645-ad946842bb3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404660769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2404660769
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2160428404
Short name T711
Test name
Test status
Simulation time 1360517977 ps
CPU time 1.39 seconds
Started May 16 01:01:20 PM PDT 24
Finished May 16 01:01:52 PM PDT 24
Peak memory 198284 kb
Host smart-6950c802-9a92-4c5a-bf6f-e730e43f6d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160428404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2160428404
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.834858359
Short name T8
Test name
Test status
Simulation time 22158215486 ps
CPU time 39.7 seconds
Started May 16 01:01:15 PM PDT 24
Finished May 16 01:02:26 PM PDT 24
Peak memory 200468 kb
Host smart-47559310-18fd-46fb-8754-6cc399f08283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834858359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.834858359
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3991936087
Short name T1177
Test name
Test status
Simulation time 176704925476 ps
CPU time 49.92 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:10:49 PM PDT 24
Peak memory 200424 kb
Host smart-1884a837-4c72-4c9c-b736-5f9613d12211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991936087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3991936087
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.666513806
Short name T1067
Test name
Test status
Simulation time 119426543036 ps
CPU time 185.71 seconds
Started May 16 01:09:49 PM PDT 24
Finished May 16 01:13:10 PM PDT 24
Peak memory 200472 kb
Host smart-669e62e4-ae6d-4be1-82c3-4d7e8b51d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666513806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.666513806
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2825805889
Short name T206
Test name
Test status
Simulation time 30986018593 ps
CPU time 64.4 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:11:03 PM PDT 24
Peak memory 200524 kb
Host smart-cdea25b7-ce18-4f4d-a632-21aed28f6da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825805889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2825805889
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1283947604
Short name T696
Test name
Test status
Simulation time 74587858270 ps
CPU time 53.72 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:10:52 PM PDT 24
Peak memory 200524 kb
Host smart-d4f42cc2-83cd-4e3d-85ab-3174a03e5305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283947604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1283947604
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3927165153
Short name T1174
Test name
Test status
Simulation time 293223054815 ps
CPU time 197.13 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:13:20 PM PDT 24
Peak memory 200460 kb
Host smart-b6a2efdf-c22d-456a-9909-3d5ccc95ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927165153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3927165153
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2359550752
Short name T668
Test name
Test status
Simulation time 68907765939 ps
CPU time 79.39 seconds
Started May 16 01:09:45 PM PDT 24
Finished May 16 01:11:16 PM PDT 24
Peak memory 200496 kb
Host smart-0a1172a9-8449-42c2-ac17-43efea7e346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359550752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2359550752
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3719595673
Short name T778
Test name
Test status
Simulation time 87446001258 ps
CPU time 39.57 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:10:38 PM PDT 24
Peak memory 200524 kb
Host smart-48d813de-6a62-4dc1-9b84-a6fb3b74fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719595673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3719595673
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3509938323
Short name T1040
Test name
Test status
Simulation time 6368652116 ps
CPU time 14.33 seconds
Started May 16 01:09:45 PM PDT 24
Finished May 16 01:10:12 PM PDT 24
Peak memory 200236 kb
Host smart-7502ffa5-1756-47c4-ad7f-399327369c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509938323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3509938323
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.879048967
Short name T193
Test name
Test status
Simulation time 209468469417 ps
CPU time 236.93 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:13:57 PM PDT 24
Peak memory 200448 kb
Host smart-ede045b7-473c-47f6-9861-45a8c9cf4de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879048967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.879048967
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3274009316
Short name T1042
Test name
Test status
Simulation time 248272696912 ps
CPU time 159.4 seconds
Started May 16 01:09:45 PM PDT 24
Finished May 16 01:12:37 PM PDT 24
Peak memory 200432 kb
Host smart-5948a4ec-e015-4f79-94c9-6736df1afeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274009316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3274009316
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1717374311
Short name T1013
Test name
Test status
Simulation time 37886683 ps
CPU time 0.54 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 195816 kb
Host smart-5b6bb9e8-2ab6-4411-9ef6-8aa23e5aee7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717374311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1717374311
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3914243587
Short name T888
Test name
Test status
Simulation time 65632259609 ps
CPU time 118.98 seconds
Started May 16 01:01:26 PM PDT 24
Finished May 16 01:03:55 PM PDT 24
Peak memory 200492 kb
Host smart-43f793df-769d-474d-bac6-9e638f45778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914243587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3914243587
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1617331540
Short name T882
Test name
Test status
Simulation time 132454225512 ps
CPU time 450.65 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:09:27 PM PDT 24
Peak memory 200384 kb
Host smart-368dbe5b-f805-4c12-942f-eefd93e037f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617331540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1617331540
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1746619804
Short name T814
Test name
Test status
Simulation time 17652205934 ps
CPU time 16.14 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:02:13 PM PDT 24
Peak memory 199376 kb
Host smart-f2c69d40-4046-43cc-a7db-67b51a32b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746619804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1746619804
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.794925336
Short name T1140
Test name
Test status
Simulation time 52746433338 ps
CPU time 13.55 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:08 PM PDT 24
Peak memory 200240 kb
Host smart-7ef13dbc-1b91-44c3-8331-9cb34c4a0254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794925336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.794925336
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3047100668
Short name T419
Test name
Test status
Simulation time 180494704983 ps
CPU time 440.35 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:09:15 PM PDT 24
Peak memory 200444 kb
Host smart-f4bca4b5-226b-4f46-b4d3-2b47d4fb4c7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047100668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3047100668
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3192603159
Short name T1170
Test name
Test status
Simulation time 6380049416 ps
CPU time 11.63 seconds
Started May 16 01:01:26 PM PDT 24
Finished May 16 01:02:08 PM PDT 24
Peak memory 199856 kb
Host smart-4846ecc5-07f2-4aee-8afb-442a4bd92176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192603159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3192603159
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.4244991567
Short name T348
Test name
Test status
Simulation time 23948088077 ps
CPU time 18.78 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:14 PM PDT 24
Peak memory 196168 kb
Host smart-d39b48d8-3af0-43a2-a143-2ee3670439da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244991567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.4244991567
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3571264071
Short name T1169
Test name
Test status
Simulation time 5562337408 ps
CPU time 144.51 seconds
Started May 16 01:01:26 PM PDT 24
Finished May 16 01:04:22 PM PDT 24
Peak memory 200400 kb
Host smart-8647d854-09fe-4f8f-bd79-787504d5d032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3571264071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3571264071
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.595364557
Short name T333
Test name
Test status
Simulation time 6092042486 ps
CPU time 28.06 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:23 PM PDT 24
Peak memory 199732 kb
Host smart-4db891b8-a809-47a4-8b1e-78bcbfa30123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595364557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.595364557
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.548929766
Short name T693
Test name
Test status
Simulation time 278698221718 ps
CPU time 150.85 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:04:26 PM PDT 24
Peak memory 200432 kb
Host smart-4662276d-503b-430b-8d9b-e57f21dd1f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548929766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.548929766
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.593695620
Short name T1146
Test name
Test status
Simulation time 3010735009 ps
CPU time 4.81 seconds
Started May 16 01:01:37 PM PDT 24
Finished May 16 01:02:10 PM PDT 24
Peak memory 196260 kb
Host smart-ebd7866d-667c-4fbe-aa33-317fbb2dd318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593695620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.593695620
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.538746056
Short name T38
Test name
Test status
Simulation time 84998335 ps
CPU time 0.82 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:01:55 PM PDT 24
Peak memory 197736 kb
Host smart-5759530c-c1c1-48b8-9d4c-462d2449bdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538746056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.538746056
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3477011415
Short name T897
Test name
Test status
Simulation time 25836668766 ps
CPU time 301 seconds
Started May 16 01:01:26 PM PDT 24
Finished May 16 01:06:58 PM PDT 24
Peak memory 208788 kb
Host smart-bdea8d9c-6d57-422a-b65f-ff51ca1f0f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477011415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3477011415
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1265886063
Short name T766
Test name
Test status
Simulation time 1430786817 ps
CPU time 4.04 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:02:10 PM PDT 24
Peak memory 199332 kb
Host smart-b105be19-d6b2-4a2c-9ae4-2492118714b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265886063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1265886063
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3658943612
Short name T691
Test name
Test status
Simulation time 10009568572 ps
CPU time 8.49 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:02:05 PM PDT 24
Peak memory 200260 kb
Host smart-10dab9e5-ac6c-4dba-b1d9-614db8360b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658943612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3658943612
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4174572293
Short name T234
Test name
Test status
Simulation time 81126143035 ps
CPU time 30 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:10:31 PM PDT 24
Peak memory 200336 kb
Host smart-18b36cbb-611c-4107-ae4e-7c518442fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174572293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4174572293
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.989142068
Short name T183
Test name
Test status
Simulation time 51136271770 ps
CPU time 12.81 seconds
Started May 16 01:09:53 PM PDT 24
Finished May 16 01:10:21 PM PDT 24
Peak memory 200388 kb
Host smart-aedcc83a-b122-4d8e-8c66-74bf0ad15668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989142068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.989142068
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1181562492
Short name T190
Test name
Test status
Simulation time 11247484521 ps
CPU time 15.09 seconds
Started May 16 01:09:48 PM PDT 24
Finished May 16 01:10:18 PM PDT 24
Peak memory 200480 kb
Host smart-00be86f1-3457-4ae1-b9c3-d97ea80201c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181562492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1181562492
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.4148395354
Short name T714
Test name
Test status
Simulation time 35689715505 ps
CPU time 17.04 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:10:20 PM PDT 24
Peak memory 200440 kb
Host smart-5cd7fe39-3f50-434f-9a15-73102cd38c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148395354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.4148395354
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.550098593
Short name T612
Test name
Test status
Simulation time 25428482562 ps
CPU time 14.25 seconds
Started May 16 01:09:53 PM PDT 24
Finished May 16 01:10:22 PM PDT 24
Peak memory 200476 kb
Host smart-0c1e25b2-67bb-4500-8e07-9346c58c6690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550098593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.550098593
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1640974515
Short name T453
Test name
Test status
Simulation time 130329693187 ps
CPU time 22.26 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:10:20 PM PDT 24
Peak memory 200340 kb
Host smart-4cf7738b-037b-4cbb-a131-5b5cfe8f67a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640974515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1640974515
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.275001005
Short name T633
Test name
Test status
Simulation time 59102635 ps
CPU time 0.56 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 194780 kb
Host smart-81c1c330-b480-44d1-ad8e-cb7df502d9dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275001005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.275001005
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1120750560
Short name T516
Test name
Test status
Simulation time 22686924268 ps
CPU time 18.62 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:02:16 PM PDT 24
Peak memory 200456 kb
Host smart-c4cf8d13-ad55-4ba4-80f9-3b5c014a0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120750560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1120750560
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1085264221
Short name T1122
Test name
Test status
Simulation time 66066161008 ps
CPU time 59.15 seconds
Started May 16 01:01:28 PM PDT 24
Finished May 16 01:02:57 PM PDT 24
Peak memory 200348 kb
Host smart-9cee3fe5-8f2a-470c-8a99-f2293dfce944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085264221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1085264221
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1529277792
Short name T445
Test name
Test status
Simulation time 76579557422 ps
CPU time 30.96 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:26 PM PDT 24
Peak memory 200420 kb
Host smart-f1f5fa07-4f13-45af-b8da-e76aba00dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529277792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1529277792
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.971194633
Short name T1002
Test name
Test status
Simulation time 43721168258 ps
CPU time 30.06 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:25 PM PDT 24
Peak memory 200300 kb
Host smart-7944389b-c1ab-4d50-8cda-e879eaaf73de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971194633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.971194633
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1378056452
Short name T894
Test name
Test status
Simulation time 76892629275 ps
CPU time 113.47 seconds
Started May 16 01:01:29 PM PDT 24
Finished May 16 01:03:52 PM PDT 24
Peak memory 200504 kb
Host smart-7f3d2001-e10a-4a8e-be16-5fdb5bb1cf73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378056452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1378056452
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2993050702
Short name T357
Test name
Test status
Simulation time 7813170042 ps
CPU time 9.33 seconds
Started May 16 01:01:26 PM PDT 24
Finished May 16 01:02:06 PM PDT 24
Peak memory 200520 kb
Host smart-6a3544e0-c237-4369-a982-0f2da19dac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993050702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2993050702
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2743341632
Short name T5
Test name
Test status
Simulation time 141897243629 ps
CPU time 58.12 seconds
Started May 16 01:01:29 PM PDT 24
Finished May 16 01:02:57 PM PDT 24
Peak memory 200608 kb
Host smart-09859da8-75bf-4f7e-b0b2-86ace0883542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743341632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2743341632
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1948206823
Short name T809
Test name
Test status
Simulation time 28390537631 ps
CPU time 224.82 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:05:40 PM PDT 24
Peak memory 200488 kb
Host smart-b873a68c-caad-4a25-bb03-5a24e5cd4343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948206823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1948206823
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.480840583
Short name T334
Test name
Test status
Simulation time 3334771844 ps
CPU time 25.25 seconds
Started May 16 01:01:26 PM PDT 24
Finished May 16 01:02:21 PM PDT 24
Peak memory 199128 kb
Host smart-46e56473-c4e5-4dd9-9876-d4fc2bb3b563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480840583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.480840583
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1748927988
Short name T269
Test name
Test status
Simulation time 143743879856 ps
CPU time 210.2 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:05:36 PM PDT 24
Peak memory 200408 kb
Host smart-b2cc64f5-e090-4180-95e9-19f2299cea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748927988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1748927988
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.433696636
Short name T417
Test name
Test status
Simulation time 3628784646 ps
CPU time 1 seconds
Started May 16 01:01:28 PM PDT 24
Finished May 16 01:01:59 PM PDT 24
Peak memory 196788 kb
Host smart-ba09f989-d698-439f-8904-aa2c90627c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433696636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.433696636
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4282212362
Short name T757
Test name
Test status
Simulation time 676131137 ps
CPU time 1.96 seconds
Started May 16 01:01:28 PM PDT 24
Finished May 16 01:01:59 PM PDT 24
Peak memory 199128 kb
Host smart-63579b82-e8e2-4244-aa19-f76f9bfdda73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282212362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4282212362
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3440249282
Short name T695
Test name
Test status
Simulation time 509559262908 ps
CPU time 152.22 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200452 kb
Host smart-3358f185-a366-4925-927e-fb57bf7089dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440249282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3440249282
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3851059139
Short name T502
Test name
Test status
Simulation time 109611772977 ps
CPU time 287.97 seconds
Started May 16 01:01:22 PM PDT 24
Finished May 16 01:06:41 PM PDT 24
Peak memory 217208 kb
Host smart-b4a3eb5d-5dbf-400a-8999-5b995586eaf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851059139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3851059139
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4229518441
Short name T748
Test name
Test status
Simulation time 1813761420 ps
CPU time 1.71 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:01:58 PM PDT 24
Peak memory 198424 kb
Host smart-8069a0d6-60a1-4aa9-9b7e-72d810f769c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229518441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4229518441
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.383664550
Short name T395
Test name
Test status
Simulation time 55326889999 ps
CPU time 6.38 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:02:12 PM PDT 24
Peak memory 197144 kb
Host smart-c4b96fa4-46fc-47dc-b3b7-346d85e787c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383664550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.383664550
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2500852844
Short name T116
Test name
Test status
Simulation time 53621750374 ps
CPU time 79.58 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:11:17 PM PDT 24
Peak memory 200420 kb
Host smart-01d244cf-8323-407e-84f8-4455cd3b84f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500852844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2500852844
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.386087981
Short name T129
Test name
Test status
Simulation time 57260113998 ps
CPU time 39.74 seconds
Started May 16 01:09:49 PM PDT 24
Finished May 16 01:10:44 PM PDT 24
Peak memory 200544 kb
Host smart-77de7dc2-7ed6-4b4c-b4c0-1dce4d39e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386087981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.386087981
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3539235915
Short name T1036
Test name
Test status
Simulation time 86855005692 ps
CPU time 14.41 seconds
Started May 16 01:09:47 PM PDT 24
Finished May 16 01:10:14 PM PDT 24
Peak memory 200252 kb
Host smart-49d78c2a-045e-4402-892e-4b465e66436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539235915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3539235915
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2974465669
Short name T402
Test name
Test status
Simulation time 19791977122 ps
CPU time 23.29 seconds
Started May 16 01:09:44 PM PDT 24
Finished May 16 01:10:20 PM PDT 24
Peak memory 200416 kb
Host smart-f0f64beb-a512-4118-a9ac-9661932c948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974465669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2974465669
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3758479835
Short name T662
Test name
Test status
Simulation time 34061312569 ps
CPU time 18.54 seconds
Started May 16 01:09:46 PM PDT 24
Finished May 16 01:10:17 PM PDT 24
Peak memory 200476 kb
Host smart-601cf63f-e8e0-465d-a1d6-88a189f68a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758479835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3758479835
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2837679756
Short name T683
Test name
Test status
Simulation time 73134701347 ps
CPU time 33.77 seconds
Started May 16 01:09:54 PM PDT 24
Finished May 16 01:10:42 PM PDT 24
Peak memory 200420 kb
Host smart-bdf9aa85-514e-4656-9b6c-01ed8243e962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837679756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2837679756
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.685516314
Short name T229
Test name
Test status
Simulation time 111591805945 ps
CPU time 203.04 seconds
Started May 16 01:09:56 PM PDT 24
Finished May 16 01:13:33 PM PDT 24
Peak memory 200508 kb
Host smart-9f81e23e-a28b-4bf0-aec2-cbe9bd5c4502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685516314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.685516314
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2736709784
Short name T903
Test name
Test status
Simulation time 11420182237 ps
CPU time 21.12 seconds
Started May 16 01:10:00 PM PDT 24
Finished May 16 01:10:33 PM PDT 24
Peak memory 200476 kb
Host smart-4d94b004-8450-4477-a869-836136b8a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736709784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2736709784
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.873740954
Short name T326
Test name
Test status
Simulation time 10899854430 ps
CPU time 31.05 seconds
Started May 16 01:09:59 PM PDT 24
Finished May 16 01:10:43 PM PDT 24
Peak memory 200536 kb
Host smart-df6e41c6-078e-4d39-866f-5932242b9f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873740954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.873740954
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1057026832
Short name T62
Test name
Test status
Simulation time 20075309 ps
CPU time 0.55 seconds
Started May 16 01:01:34 PM PDT 24
Finished May 16 01:02:02 PM PDT 24
Peak memory 195872 kb
Host smart-866a9c26-79dc-4b77-a06e-851b3bda2be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057026832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1057026832
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3369675654
Short name T967
Test name
Test status
Simulation time 35189257123 ps
CPU time 61.55 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:03:08 PM PDT 24
Peak memory 200444 kb
Host smart-a4080572-d045-4443-99f4-7cd63866e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369675654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3369675654
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2000412779
Short name T344
Test name
Test status
Simulation time 61702259872 ps
CPU time 22.45 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:02:19 PM PDT 24
Peak memory 200064 kb
Host smart-513046ac-954c-4110-8d03-ab97a4fd640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000412779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2000412779
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.553531651
Short name T879
Test name
Test status
Simulation time 45883377878 ps
CPU time 35.81 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:31 PM PDT 24
Peak memory 200240 kb
Host smart-1065d4c3-0ecd-4f88-86fe-baf3abf492bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553531651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.553531651
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2119396432
Short name T816
Test name
Test status
Simulation time 169063601416 ps
CPU time 381.88 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:08:18 PM PDT 24
Peak memory 200432 kb
Host smart-5b69c2e6-9c11-4a48-885a-a9fa4f282d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119396432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2119396432
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.534525201
Short name T405
Test name
Test status
Simulation time 2867551004 ps
CPU time 5.39 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 199560 kb
Host smart-6993fce9-c7bd-4d1f-9730-3d47b48b123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534525201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.534525201
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2362706262
Short name T566
Test name
Test status
Simulation time 34389440461 ps
CPU time 14.29 seconds
Started May 16 01:01:29 PM PDT 24
Finished May 16 01:02:13 PM PDT 24
Peak memory 195152 kb
Host smart-acc1097b-8b02-43ca-b2b2-df829e915c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362706262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2362706262
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3175991317
Short name T963
Test name
Test status
Simulation time 18086223501 ps
CPU time 434.36 seconds
Started May 16 01:01:30 PM PDT 24
Finished May 16 01:09:13 PM PDT 24
Peak memory 200492 kb
Host smart-d5a9c5d9-09e8-4399-a15e-98df86201b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175991317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3175991317
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4105815259
Short name T1147
Test name
Test status
Simulation time 2873609441 ps
CPU time 6.07 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:01 PM PDT 24
Peak memory 198592 kb
Host smart-d26172e9-6a3b-4663-bf21-4a00f6d804e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105815259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4105815259
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.180114871
Short name T519
Test name
Test status
Simulation time 109306243832 ps
CPU time 53.4 seconds
Started May 16 01:01:38 PM PDT 24
Finished May 16 01:03:00 PM PDT 24
Peak memory 200412 kb
Host smart-3d1c4362-5f93-4805-a806-050127888353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180114871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.180114871
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3104976245
Short name T278
Test name
Test status
Simulation time 4204890658 ps
CPU time 7.66 seconds
Started May 16 01:01:27 PM PDT 24
Finished May 16 01:02:05 PM PDT 24
Peak memory 196764 kb
Host smart-08a00a0c-2df6-480c-8c83-54a4ed3e708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104976245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3104976245
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.967758675
Short name T829
Test name
Test status
Simulation time 311102231 ps
CPU time 1.42 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:01:57 PM PDT 24
Peak memory 199096 kb
Host smart-5774adb9-6630-4352-92aa-bb2eab3d2528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967758675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.967758675
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3831991115
Short name T293
Test name
Test status
Simulation time 139830638773 ps
CPU time 217.75 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:05:41 PM PDT 24
Peak memory 200472 kb
Host smart-ed826371-7b01-4b83-850a-9fdfc29486fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831991115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3831991115
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1435684635
Short name T32
Test name
Test status
Simulation time 85245481179 ps
CPU time 206.07 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:05:22 PM PDT 24
Peak memory 217128 kb
Host smart-7ad23cb4-fa62-4d35-a799-9f93e5ac4ff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435684635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1435684635
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1274492851
Short name T682
Test name
Test status
Simulation time 9335415063 ps
CPU time 11.39 seconds
Started May 16 01:01:25 PM PDT 24
Finished May 16 01:02:07 PM PDT 24
Peak memory 200260 kb
Host smart-9974625e-4a2d-4eec-adc0-1eca1eec0932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274492851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1274492851
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3413689619
Short name T671
Test name
Test status
Simulation time 101693702968 ps
CPU time 50.19 seconds
Started May 16 01:01:24 PM PDT 24
Finished May 16 01:02:45 PM PDT 24
Peak memory 200420 kb
Host smart-fa81e02b-65f7-4a62-ae99-056f1d8573d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413689619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3413689619
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1657033514
Short name T431
Test name
Test status
Simulation time 27431271618 ps
CPU time 10.94 seconds
Started May 16 01:09:55 PM PDT 24
Finished May 16 01:10:20 PM PDT 24
Peak memory 200424 kb
Host smart-93e6ca2d-5269-4193-81d3-d1e3d7b13abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657033514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1657033514
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2397811075
Short name T367
Test name
Test status
Simulation time 252284309903 ps
CPU time 99.38 seconds
Started May 16 01:09:54 PM PDT 24
Finished May 16 01:11:48 PM PDT 24
Peak memory 200484 kb
Host smart-ad571c10-7074-44f7-95d9-238e90c821a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397811075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2397811075
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2592409701
Short name T241
Test name
Test status
Simulation time 35656314470 ps
CPU time 18.08 seconds
Started May 16 01:09:56 PM PDT 24
Finished May 16 01:10:28 PM PDT 24
Peak memory 200456 kb
Host smart-f86bf738-eba5-461b-8fb0-b43f81b8a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592409701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2592409701
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1867009494
Short name T781
Test name
Test status
Simulation time 120212435857 ps
CPU time 101.23 seconds
Started May 16 01:09:58 PM PDT 24
Finished May 16 01:11:52 PM PDT 24
Peak memory 200472 kb
Host smart-3f4b4963-3592-4752-8939-5720dcfdd2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867009494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1867009494
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2141191941
Short name T218
Test name
Test status
Simulation time 97568716659 ps
CPU time 174.38 seconds
Started May 16 01:10:01 PM PDT 24
Finished May 16 01:13:06 PM PDT 24
Peak memory 200508 kb
Host smart-662656a6-b653-4180-90ed-6b12e0237434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141191941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2141191941
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1480988270
Short name T598
Test name
Test status
Simulation time 43211873673 ps
CPU time 59.83 seconds
Started May 16 01:10:00 PM PDT 24
Finished May 16 01:11:11 PM PDT 24
Peak memory 200532 kb
Host smart-a4164b1a-a42f-45dc-9a1a-cf49bcec6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480988270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1480988270
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.978504170
Short name T934
Test name
Test status
Simulation time 32551072253 ps
CPU time 28.41 seconds
Started May 16 01:09:54 PM PDT 24
Finished May 16 01:10:37 PM PDT 24
Peak memory 200436 kb
Host smart-4728befa-8dff-4947-bbd3-e367b5664f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978504170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.978504170
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.583778057
Short name T35
Test name
Test status
Simulation time 71438618796 ps
CPU time 52.37 seconds
Started May 16 01:09:55 PM PDT 24
Finished May 16 01:11:02 PM PDT 24
Peak memory 200388 kb
Host smart-49ee5793-5d8d-44dc-9d6a-7636704914c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583778057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.583778057
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2511846413
Short name T943
Test name
Test status
Simulation time 11989126 ps
CPU time 0.55 seconds
Started May 16 01:01:33 PM PDT 24
Finished May 16 01:02:02 PM PDT 24
Peak memory 195876 kb
Host smart-f0b2a643-c051-43ce-94a6-0a003f9caa98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511846413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2511846413
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1421578181
Short name T552
Test name
Test status
Simulation time 179485058585 ps
CPU time 275.19 seconds
Started May 16 01:01:33 PM PDT 24
Finished May 16 01:06:36 PM PDT 24
Peak memory 200196 kb
Host smart-f089db9b-21ab-44b6-9bd5-fc2f427742e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421578181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1421578181
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4230284986
Short name T545
Test name
Test status
Simulation time 122757586163 ps
CPU time 44.24 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:02:46 PM PDT 24
Peak memory 200232 kb
Host smart-d9503f4b-9f2f-459f-bcf7-ec58d109820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230284986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4230284986
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.142524566
Short name T991
Test name
Test status
Simulation time 106317552191 ps
CPU time 87.19 seconds
Started May 16 01:01:34 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 200320 kb
Host smart-bcf49634-c75b-4b32-ae0f-f3fdeff8ea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142524566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.142524566
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.156424619
Short name T648
Test name
Test status
Simulation time 297491753066 ps
CPU time 92.9 seconds
Started May 16 01:01:36 PM PDT 24
Finished May 16 01:03:36 PM PDT 24
Peak memory 200464 kb
Host smart-8eb89459-92eb-4106-a469-cc5261e29ff0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156424619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.156424619
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1921034184
Short name T563
Test name
Test status
Simulation time 132275386982 ps
CPU time 351.46 seconds
Started May 16 01:01:33 PM PDT 24
Finished May 16 01:07:53 PM PDT 24
Peak memory 200488 kb
Host smart-60d1fd63-72d0-4e33-bd95-3a34631748db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921034184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1921034184
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.315702045
Short name T376
Test name
Test status
Simulation time 2735840951 ps
CPU time 1.71 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:02:05 PM PDT 24
Peak memory 198036 kb
Host smart-271aef35-61b3-41d2-a3fe-3c90b70cdc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315702045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.315702045
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3316551766
Short name T734
Test name
Test status
Simulation time 122355400617 ps
CPU time 64.75 seconds
Started May 16 01:01:34 PM PDT 24
Finished May 16 01:03:07 PM PDT 24
Peak memory 208932 kb
Host smart-5d002f5a-b93f-4325-9b1f-07eb60d1f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316551766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3316551766
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4048657498
Short name T914
Test name
Test status
Simulation time 16916642224 ps
CPU time 239.46 seconds
Started May 16 01:01:37 PM PDT 24
Finished May 16 01:06:05 PM PDT 24
Peak memory 200464 kb
Host smart-33753f3a-94a8-4c64-829c-d46a515712e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048657498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4048657498
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2091981023
Short name T23
Test name
Test status
Simulation time 6300220101 ps
CPU time 58.44 seconds
Started May 16 01:01:37 PM PDT 24
Finished May 16 01:03:03 PM PDT 24
Peak memory 198648 kb
Host smart-952eb169-18c8-4b9e-9247-5300531e3688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091981023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2091981023
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1337976660
Short name T987
Test name
Test status
Simulation time 35884131199 ps
CPU time 14.23 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:02:17 PM PDT 24
Peak memory 200092 kb
Host smart-fc309904-5ad4-424e-9196-7c52d9420ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337976660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1337976660
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1889198324
Short name T685
Test name
Test status
Simulation time 1874948745 ps
CPU time 1.38 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:02:03 PM PDT 24
Peak memory 196120 kb
Host smart-30467fc4-8648-486d-81e4-6ecec5a66c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889198324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1889198324
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3076582861
Short name T768
Test name
Test status
Simulation time 669698770 ps
CPU time 1.64 seconds
Started May 16 01:01:33 PM PDT 24
Finished May 16 01:02:03 PM PDT 24
Peak memory 200232 kb
Host smart-8bedfd27-4b82-4683-966d-94604f4f59b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076582861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3076582861
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2139921754
Short name T837
Test name
Test status
Simulation time 15053046224 ps
CPU time 13.45 seconds
Started May 16 01:01:36 PM PDT 24
Finished May 16 01:02:17 PM PDT 24
Peak memory 200456 kb
Host smart-8a7f4780-dd25-44d6-952d-b65d554dc089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139921754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2139921754
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.985181904
Short name T47
Test name
Test status
Simulation time 174883541865 ps
CPU time 462.09 seconds
Started May 16 01:01:32 PM PDT 24
Finished May 16 01:09:42 PM PDT 24
Peak memory 227732 kb
Host smart-d2cfd709-1466-4dc6-8a06-336868a5711b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985181904 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.985181904
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.309299150
Short name T353
Test name
Test status
Simulation time 405118823 ps
CPU time 2.16 seconds
Started May 16 01:01:39 PM PDT 24
Finished May 16 01:02:09 PM PDT 24
Peak memory 198812 kb
Host smart-e266ceee-79c4-437b-8d24-052e9527303f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309299150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.309299150
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2064472130
Short name T265
Test name
Test status
Simulation time 54396033540 ps
CPU time 45.5 seconds
Started May 16 01:01:34 PM PDT 24
Finished May 16 01:02:47 PM PDT 24
Peak memory 200428 kb
Host smart-062c30a1-524c-4e9a-a4fa-b8da71133cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064472130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2064472130
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2340249767
Short name T240
Test name
Test status
Simulation time 30082722807 ps
CPU time 35.99 seconds
Started May 16 01:09:56 PM PDT 24
Finished May 16 01:10:46 PM PDT 24
Peak memory 200508 kb
Host smart-90e64c45-6596-46f9-84d2-7daf8151e98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340249767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2340249767
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3783901842
Short name T144
Test name
Test status
Simulation time 155524014091 ps
CPU time 64.1 seconds
Started May 16 01:10:00 PM PDT 24
Finished May 16 01:11:16 PM PDT 24
Peak memory 200548 kb
Host smart-93a4cff9-e5f9-4dfc-95fe-1fd3c7bcbc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783901842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3783901842
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2432978606
Short name T94
Test name
Test status
Simulation time 26411538357 ps
CPU time 11.34 seconds
Started May 16 01:09:55 PM PDT 24
Finished May 16 01:10:20 PM PDT 24
Peak memory 200464 kb
Host smart-1133111a-7b44-4397-b334-77402de1889b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432978606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2432978606
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2607317470
Short name T223
Test name
Test status
Simulation time 163003477292 ps
CPU time 254.19 seconds
Started May 16 01:09:54 PM PDT 24
Finished May 16 01:14:22 PM PDT 24
Peak memory 200424 kb
Host smart-99fe76e9-d69c-496f-941d-be36b9fd6e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607317470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2607317470
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2912296060
Short name T753
Test name
Test status
Simulation time 249987092903 ps
CPU time 148.56 seconds
Started May 16 01:09:55 PM PDT 24
Finished May 16 01:12:38 PM PDT 24
Peak memory 200488 kb
Host smart-8148aad2-64bf-45d9-9145-311dc0efbfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912296060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2912296060
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2553630624
Short name T901
Test name
Test status
Simulation time 321949839395 ps
CPU time 74.48 seconds
Started May 16 01:09:58 PM PDT 24
Finished May 16 01:11:25 PM PDT 24
Peak memory 200464 kb
Host smart-de0cb345-a501-430b-92c8-26eb5032418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553630624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2553630624
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2332003581
Short name T1053
Test name
Test status
Simulation time 106190050006 ps
CPU time 164.95 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:13:11 PM PDT 24
Peak memory 200388 kb
Host smart-54513b7d-63d8-4d5a-ad7e-e8f7b90b7b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332003581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2332003581
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1071162104
Short name T178
Test name
Test status
Simulation time 184724437825 ps
CPU time 48.76 seconds
Started May 16 01:09:59 PM PDT 24
Finished May 16 01:11:00 PM PDT 24
Peak memory 200464 kb
Host smart-88c60c69-e93b-461f-a7ea-0116bcbbad90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071162104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1071162104
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1514372310
Short name T169
Test name
Test status
Simulation time 15100584620 ps
CPU time 26.67 seconds
Started May 16 01:10:02 PM PDT 24
Finished May 16 01:10:39 PM PDT 24
Peak memory 200432 kb
Host smart-827b27d8-ccff-41f4-ac19-5dbe5cfbed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514372310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1514372310
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1870457620
Short name T583
Test name
Test status
Simulation time 35079377002 ps
CPU time 18.92 seconds
Started May 16 01:09:56 PM PDT 24
Finished May 16 01:10:29 PM PDT 24
Peak memory 200472 kb
Host smart-70a140b2-ecfb-4703-bdf7-35d524472f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870457620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1870457620
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2046681849
Short name T430
Test name
Test status
Simulation time 10577869 ps
CPU time 0.54 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 194860 kb
Host smart-ec492f72-bacf-42f2-a026-c50d1af018d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046681849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2046681849
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.478085105
Short name T505
Test name
Test status
Simulation time 137620392164 ps
CPU time 181.74 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:05:05 PM PDT 24
Peak memory 200420 kb
Host smart-3254cf5d-fe6a-498d-bbb2-655179d22387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478085105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.478085105
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3020644574
Short name T283
Test name
Test status
Simulation time 12046113576 ps
CPU time 22.73 seconds
Started May 16 01:01:37 PM PDT 24
Finished May 16 01:02:28 PM PDT 24
Peak memory 200480 kb
Host smart-33d66e4d-9240-44f6-b95c-f3decee428be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020644574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3020644574
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3577395751
Short name T130
Test name
Test status
Simulation time 59844324176 ps
CPU time 251.7 seconds
Started May 16 01:01:39 PM PDT 24
Finished May 16 01:06:18 PM PDT 24
Peak memory 200396 kb
Host smart-eacaac2c-4788-4332-a1bf-a85a4c78b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577395751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3577395751
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2038253110
Short name T320
Test name
Test status
Simulation time 38960131040 ps
CPU time 10.31 seconds
Started May 16 01:01:34 PM PDT 24
Finished May 16 01:02:12 PM PDT 24
Peak memory 199228 kb
Host smart-0c3661a5-e745-4128-b057-b74ff8631f33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038253110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2038253110
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.4164317902
Short name T656
Test name
Test status
Simulation time 117376428778 ps
CPU time 708.58 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:13:59 PM PDT 24
Peak memory 200456 kb
Host smart-1a857364-ca71-42ce-8093-f6162f8c6497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164317902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.4164317902
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2089416649
Short name T996
Test name
Test status
Simulation time 10202798328 ps
CPU time 13.8 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:02:24 PM PDT 24
Peak memory 198880 kb
Host smart-f7adb185-2f91-4479-a2b2-9964e4252ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089416649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2089416649
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2612663614
Short name T1142
Test name
Test status
Simulation time 43310158872 ps
CPU time 15.55 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:02:25 PM PDT 24
Peak memory 200512 kb
Host smart-fe649bfd-6deb-4a8c-b8c1-e731078e72e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612663614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2612663614
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.758498832
Short name T758
Test name
Test status
Simulation time 7371325310 ps
CPU time 73.57 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:03:24 PM PDT 24
Peak memory 200512 kb
Host smart-3fd9e546-7c4b-4103-93a6-7e8ee7ae0f6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758498832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.758498832
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3594389549
Short name T817
Test name
Test status
Simulation time 1305282910 ps
CPU time 0.66 seconds
Started May 16 01:01:35 PM PDT 24
Finished May 16 01:02:04 PM PDT 24
Peak memory 196124 kb
Host smart-132fc797-fa7b-45b7-a8b2-3ef9d0f30f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594389549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3594389549
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.183158187
Short name T165
Test name
Test status
Simulation time 117493730861 ps
CPU time 51.06 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:03:02 PM PDT 24
Peak memory 200496 kb
Host smart-9ca0bc29-e57b-4802-9c64-6771914c27f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183158187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.183158187
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.63126348
Short name T559
Test name
Test status
Simulation time 894028857 ps
CPU time 0.87 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:02:10 PM PDT 24
Peak memory 195656 kb
Host smart-88003e72-29d8-450d-bccd-e1889157cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63126348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.63126348
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2847096453
Short name T380
Test name
Test status
Simulation time 6049975548 ps
CPU time 15.84 seconds
Started May 16 01:01:34 PM PDT 24
Finished May 16 01:02:18 PM PDT 24
Peak memory 199700 kb
Host smart-69792ab8-2378-4394-84ee-e5d9d0c08e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847096453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2847096453
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.105487175
Short name T565
Test name
Test status
Simulation time 127412565581 ps
CPU time 550.16 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:11:20 PM PDT 24
Peak memory 216468 kb
Host smart-556315ac-f542-4908-a714-b1a57fa3ef05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105487175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.105487175
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3539804660
Short name T48
Test name
Test status
Simulation time 22738236038 ps
CPU time 603.57 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:12:14 PM PDT 24
Peak memory 216160 kb
Host smart-91e285a9-5af9-4b7e-8a4c-c2f4c1714ed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539804660 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3539804660
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1241603207
Short name T1027
Test name
Test status
Simulation time 1776798738 ps
CPU time 1.69 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 199252 kb
Host smart-c966a13e-942f-4f6c-9d7e-ca3df914a8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241603207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1241603207
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4239505155
Short name T1125
Test name
Test status
Simulation time 104246497571 ps
CPU time 39.8 seconds
Started May 16 01:01:33 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 200440 kb
Host smart-9dfd0a75-aa08-47fb-bb6d-14455852e81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239505155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4239505155
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2586110458
Short name T36
Test name
Test status
Simulation time 127258507052 ps
CPU time 103.06 seconds
Started May 16 01:09:56 PM PDT 24
Finished May 16 01:11:53 PM PDT 24
Peak memory 200464 kb
Host smart-4e21c98c-69bc-4136-81d8-208040825985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586110458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2586110458
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1527633189
Short name T789
Test name
Test status
Simulation time 57003723052 ps
CPU time 49.58 seconds
Started May 16 01:10:09 PM PDT 24
Finished May 16 01:11:08 PM PDT 24
Peak memory 200404 kb
Host smart-d5ae6fb7-1b57-43a5-87a5-1dcb9c5c0697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527633189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1527633189
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.717714940
Short name T1095
Test name
Test status
Simulation time 83951262290 ps
CPU time 60.39 seconds
Started May 16 01:10:02 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 200464 kb
Host smart-950e9ed8-e4ad-44d1-b22a-ceba318cf6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717714940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.717714940
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1932767459
Short name T650
Test name
Test status
Simulation time 22972744332 ps
CPU time 44.03 seconds
Started May 16 01:10:08 PM PDT 24
Finished May 16 01:11:01 PM PDT 24
Peak memory 200404 kb
Host smart-eb6afe39-6374-4f5b-b6e8-a4b74f81286f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932767459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1932767459
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4289127992
Short name T677
Test name
Test status
Simulation time 17575157111 ps
CPU time 30.39 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:44 PM PDT 24
Peak memory 200456 kb
Host smart-34e4cc57-957a-46ea-91ed-c8bce1ccf2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289127992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4289127992
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3675446044
Short name T4
Test name
Test status
Simulation time 157726811061 ps
CPU time 66.06 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:11:20 PM PDT 24
Peak memory 200524 kb
Host smart-10eb856b-366c-4fc3-9c5b-9cf3e070b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675446044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3675446044
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1673299821
Short name T377
Test name
Test status
Simulation time 103867190945 ps
CPU time 14.22 seconds
Started May 16 01:10:08 PM PDT 24
Finished May 16 01:10:31 PM PDT 24
Peak memory 200464 kb
Host smart-c4cb28f7-5acf-4a33-b248-7ed93cdf3581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673299821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1673299821
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2683534802
Short name T739
Test name
Test status
Simulation time 188963280674 ps
CPU time 87.23 seconds
Started May 16 01:10:02 PM PDT 24
Finished May 16 01:11:40 PM PDT 24
Peak memory 200524 kb
Host smart-3f8807e8-6872-432e-89f4-58f8571d21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683534802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2683534802
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2629826569
Short name T443
Test name
Test status
Simulation time 26612296 ps
CPU time 0.53 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:00:53 PM PDT 24
Peak memory 195832 kb
Host smart-9b8d73e8-c93e-4e0a-8156-a180da82fe1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629826569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2629826569
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.5920516
Short name T254
Test name
Test status
Simulation time 60506763583 ps
CPU time 28.32 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:01:23 PM PDT 24
Peak memory 200480 kb
Host smart-f5fe13c8-f53d-4266-b795-36500b7e7fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5920516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.5920516
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.4200464516
Short name T690
Test name
Test status
Simulation time 133015992112 ps
CPU time 210.31 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:04:22 PM PDT 24
Peak memory 200388 kb
Host smart-3b6b1c5f-0073-41ea-8c83-51e0ec8262bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200464516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4200464516
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4021141920
Short name T579
Test name
Test status
Simulation time 9310963098 ps
CPU time 34.31 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:01:34 PM PDT 24
Peak memory 200508 kb
Host smart-5a5def4b-9136-45bd-a8b0-da9b8cdb8a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021141920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4021141920
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2460600150
Short name T118
Test name
Test status
Simulation time 53497193749 ps
CPU time 51.31 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:47 PM PDT 24
Peak memory 200404 kb
Host smart-53789131-9f44-4985-a10e-59769ea40849
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460600150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2460600150
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.561626789
Short name T1105
Test name
Test status
Simulation time 87829476631 ps
CPU time 423.83 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:08:04 PM PDT 24
Peak memory 200456 kb
Host smart-1f77a39c-0194-4f9b-998e-10c4885a92ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561626789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.561626789
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.501306562
Short name T954
Test name
Test status
Simulation time 7713922513 ps
CPU time 7.44 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:03 PM PDT 24
Peak memory 199372 kb
Host smart-c50032ce-f30f-4d4d-a5ac-88a6fee9f373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501306562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.501306562
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3809882609
Short name T414
Test name
Test status
Simulation time 9107976303 ps
CPU time 8.24 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:01:01 PM PDT 24
Peak memory 200508 kb
Host smart-422a262c-5e80-4ce8-89a9-5eb928c7778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809882609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3809882609
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3775857371
Short name T644
Test name
Test status
Simulation time 16229367301 ps
CPU time 886.04 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:15:41 PM PDT 24
Peak memory 200400 kb
Host smart-f90474d7-2b46-49b3-b408-faab2625433d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775857371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3775857371
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3447795999
Short name T457
Test name
Test status
Simulation time 7073599213 ps
CPU time 63.68 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:01:56 PM PDT 24
Peak memory 198636 kb
Host smart-45ed1dcc-1235-470c-b5dc-f10ffd906073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447795999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3447795999
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.344715918
Short name T576
Test name
Test status
Simulation time 125051559591 ps
CPU time 233.14 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:04:53 PM PDT 24
Peak memory 200412 kb
Host smart-eabb4949-8c76-46c0-b598-c3bd7a35afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344715918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.344715918
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.630316265
Short name T822
Test name
Test status
Simulation time 4913149407 ps
CPU time 8.62 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:04 PM PDT 24
Peak memory 196412 kb
Host smart-b8d15d47-a6fe-4a41-b9ad-e681cda94f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630316265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.630316265
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1596071028
Short name T30
Test name
Test status
Simulation time 178026675 ps
CPU time 0.78 seconds
Started May 16 01:00:14 PM PDT 24
Finished May 16 01:00:54 PM PDT 24
Peak memory 218888 kb
Host smart-6fbaa969-d669-4a06-a444-74e97dbd384b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596071028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1596071028
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.205104448
Short name T686
Test name
Test status
Simulation time 5348853921 ps
CPU time 5.5 seconds
Started May 16 01:00:18 PM PDT 24
Finished May 16 01:01:03 PM PDT 24
Peak memory 199892 kb
Host smart-f038dcd1-37bc-4b62-a726-25298af376c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205104448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.205104448
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3301004098
Short name T1149
Test name
Test status
Simulation time 13761785198 ps
CPU time 25.43 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:01:18 PM PDT 24
Peak memory 200444 kb
Host smart-597ed650-42fe-4ea8-867a-54ba72dc9683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301004098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3301004098
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.705142646
Short name T1058
Test name
Test status
Simulation time 41895220257 ps
CPU time 156.32 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:03:28 PM PDT 24
Peak memory 215884 kb
Host smart-8f5ccf21-ed4e-4e72-a698-a140548a1cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705142646 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.705142646
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2367516329
Short name T678
Test name
Test status
Simulation time 1418716828 ps
CPU time 1.99 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:00:54 PM PDT 24
Peak memory 198492 kb
Host smart-994693c6-0e6d-4f1e-bbd5-5f04838a08a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367516329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2367516329
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.4096492381
Short name T267
Test name
Test status
Simulation time 62263695121 ps
CPU time 164.31 seconds
Started May 16 01:00:11 PM PDT 24
Finished May 16 01:03:35 PM PDT 24
Peak memory 200432 kb
Host smart-edc35b47-1135-402d-923a-5f1ae5047954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096492381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.4096492381
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3304248410
Short name T523
Test name
Test status
Simulation time 12252545 ps
CPU time 0.56 seconds
Started May 16 01:01:42 PM PDT 24
Finished May 16 01:02:10 PM PDT 24
Peak memory 195852 kb
Host smart-958164c7-8bc9-4e17-822e-c1c9e806bace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304248410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3304248410
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.810273992
Short name T139
Test name
Test status
Simulation time 37288327027 ps
CPU time 17.46 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 200456 kb
Host smart-9f87cbd1-9ec5-4721-9a04-c3ac18ba1491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810273992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.810273992
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2105374092
Short name T1103
Test name
Test status
Simulation time 122325569728 ps
CPU time 49.46 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:03:00 PM PDT 24
Peak memory 200348 kb
Host smart-5e25f6e7-9f21-45cd-a8d4-ac573bd0762d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105374092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2105374092
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2967712686
Short name T362
Test name
Test status
Simulation time 23611721800 ps
CPU time 40.71 seconds
Started May 16 01:01:46 PM PDT 24
Finished May 16 01:02:52 PM PDT 24
Peak memory 200516 kb
Host smart-52b43664-b828-4237-bdb2-352279911d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967712686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2967712686
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.833078932
Short name T383
Test name
Test status
Simulation time 40059967239 ps
CPU time 16.04 seconds
Started May 16 01:01:42 PM PDT 24
Finished May 16 01:02:26 PM PDT 24
Peak memory 200480 kb
Host smart-5ce372dc-8c70-4d88-9e6e-11e505aac3f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833078932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.833078932
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_loopback.1577697929
Short name T328
Test name
Test status
Simulation time 1157914155 ps
CPU time 0.79 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 196172 kb
Host smart-eab9f4ca-dacd-4274-b2b0-50a6de5784b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577697929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1577697929
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3967692500
Short name T551
Test name
Test status
Simulation time 93644256361 ps
CPU time 40.43 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:02:51 PM PDT 24
Peak memory 200648 kb
Host smart-ccad534a-de85-44a3-8221-987074e8857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967692500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3967692500
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2186265914
Short name T1133
Test name
Test status
Simulation time 20259202106 ps
CPU time 237.68 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:06:08 PM PDT 24
Peak memory 200444 kb
Host smart-d0a74f1c-21fe-4c2b-9f6a-2fdd738707a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186265914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2186265914
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3395214972
Short name T406
Test name
Test status
Simulation time 1376231068 ps
CPU time 5.89 seconds
Started May 16 01:01:43 PM PDT 24
Finished May 16 01:02:15 PM PDT 24
Peak memory 198484 kb
Host smart-a20fba85-1946-43bb-a420-d0fce8d739d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395214972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3395214972
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1185240406
Short name T1168
Test name
Test status
Simulation time 24229352416 ps
CPU time 26.84 seconds
Started May 16 01:01:42 PM PDT 24
Finished May 16 01:02:36 PM PDT 24
Peak memory 200360 kb
Host smart-15862412-360e-4b11-8509-eb8ec2f472f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185240406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1185240406
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4185394142
Short name T1083
Test name
Test status
Simulation time 1842791343 ps
CPU time 2.09 seconds
Started May 16 01:01:42 PM PDT 24
Finished May 16 01:02:12 PM PDT 24
Peak memory 195844 kb
Host smart-4172f58c-32c4-4db0-bc1d-efef09066b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185394142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4185394142
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1770053826
Short name T337
Test name
Test status
Simulation time 696674845 ps
CPU time 1.9 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:02:13 PM PDT 24
Peak memory 198692 kb
Host smart-e3e06b51-3fac-4a40-957c-1bd4f6757e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770053826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1770053826
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3355414305
Short name T184
Test name
Test status
Simulation time 178112711251 ps
CPU time 836.59 seconds
Started May 16 01:01:46 PM PDT 24
Finished May 16 01:16:08 PM PDT 24
Peak memory 216032 kb
Host smart-82d544e5-863e-4a13-bda8-409b791a1896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355414305 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3355414305
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2533500026
Short name T657
Test name
Test status
Simulation time 1619191106 ps
CPU time 1.81 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:02:13 PM PDT 24
Peak memory 199132 kb
Host smart-bd6ea4e9-8dc8-4134-abae-3897275ee259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533500026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2533500026
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2799554094
Short name T1022
Test name
Test status
Simulation time 78079294775 ps
CPU time 39.98 seconds
Started May 16 01:01:41 PM PDT 24
Finished May 16 01:02:48 PM PDT 24
Peak memory 200456 kb
Host smart-ac023015-c8b4-4388-960e-ec1d25f18739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799554094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2799554094
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1192934348
Short name T977
Test name
Test status
Simulation time 13874867 ps
CPU time 0.54 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:02:17 PM PDT 24
Peak memory 194840 kb
Host smart-c43fd4f1-8f9d-4f6f-aaaf-976819480be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192934348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1192934348
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1233936311
Short name T643
Test name
Test status
Simulation time 46535547145 ps
CPU time 74.96 seconds
Started May 16 01:01:56 PM PDT 24
Finished May 16 01:03:33 PM PDT 24
Peak memory 200192 kb
Host smart-ba2cd594-ae36-41f5-b447-475f63e3cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233936311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1233936311
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3029373206
Short name T595
Test name
Test status
Simulation time 141977868271 ps
CPU time 165.43 seconds
Started May 16 01:01:52 PM PDT 24
Finished May 16 01:05:01 PM PDT 24
Peak memory 200368 kb
Host smart-cb07f2c9-fcac-470a-8ede-a504819a8ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029373206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3029373206
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3023942740
Short name T313
Test name
Test status
Simulation time 27181045443 ps
CPU time 21.19 seconds
Started May 16 01:01:57 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 199360 kb
Host smart-321d52d5-8d65-40cd-91a6-10495afd6e79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023942740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3023942740
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.464506215
Short name T1024
Test name
Test status
Simulation time 184185875094 ps
CPU time 1288.46 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:23:45 PM PDT 24
Peak memory 200432 kb
Host smart-89a85acc-85e1-488a-aeed-9c6693d3a432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464506215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.464506215
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1956465291
Short name T911
Test name
Test status
Simulation time 2858860262 ps
CPU time 5.45 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:02:22 PM PDT 24
Peak memory 197796 kb
Host smart-26da8880-5a7c-49ff-a234-f3bbb9e1f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956465291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1956465291
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.48641222
Short name T907
Test name
Test status
Simulation time 50312309738 ps
CPU time 68.8 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:03:26 PM PDT 24
Peak memory 199272 kb
Host smart-a70dc0e2-3c2b-42dd-9459-6ea510c5aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48641222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.48641222
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4236916876
Short name T680
Test name
Test status
Simulation time 4586455817 ps
CPU time 30.56 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:02:47 PM PDT 24
Peak memory 200432 kb
Host smart-858e2020-6092-4d3c-903d-a9c0ce5a38d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236916876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4236916876
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2685671779
Short name T893
Test name
Test status
Simulation time 7612632352 ps
CPU time 12.55 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 199796 kb
Host smart-8e6fdfa8-8766-4812-9b10-a06cd9c18cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685671779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2685671779
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4115635367
Short name T264
Test name
Test status
Simulation time 35008173999 ps
CPU time 50.11 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:03:07 PM PDT 24
Peak memory 196464 kb
Host smart-7356f21c-2094-4da7-b875-d7587ec3017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115635367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4115635367
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.849357848
Short name T920
Test name
Test status
Simulation time 672263044 ps
CPU time 3.22 seconds
Started May 16 01:01:46 PM PDT 24
Finished May 16 01:02:15 PM PDT 24
Peak memory 200424 kb
Host smart-96cb56fe-6fbe-4d94-84ed-80979290cb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849357848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.849357848
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1326869221
Short name T1124
Test name
Test status
Simulation time 210458763087 ps
CPU time 380.58 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:08:37 PM PDT 24
Peak memory 216276 kb
Host smart-61034cef-6d91-4bef-9084-ca983d4a3c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326869221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1326869221
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1868093963
Short name T180
Test name
Test status
Simulation time 477091270582 ps
CPU time 881.38 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:16:58 PM PDT 24
Peak memory 216892 kb
Host smart-f4910582-f093-4c0e-9594-197de3b99bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868093963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1868093963
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1964239510
Short name T1145
Test name
Test status
Simulation time 986009629 ps
CPU time 1.26 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:02:18 PM PDT 24
Peak memory 198816 kb
Host smart-aa2e3bc1-c977-448c-9dda-68507ba793a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964239510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1964239510
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3912909018
Short name T917
Test name
Test status
Simulation time 65074824873 ps
CPU time 123.78 seconds
Started May 16 01:01:44 PM PDT 24
Finished May 16 01:04:14 PM PDT 24
Peak memory 200420 kb
Host smart-aed62fac-3c8d-407f-9bae-ccc4f7039582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912909018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3912909018
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1046009080
Short name T440
Test name
Test status
Simulation time 31677101 ps
CPU time 0.54 seconds
Started May 16 01:02:06 PM PDT 24
Finished May 16 01:02:26 PM PDT 24
Peak memory 195860 kb
Host smart-c9dad21d-803c-4d6b-a526-bcb16af86c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046009080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1046009080
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.559531199
Short name T467
Test name
Test status
Simulation time 297649648583 ps
CPU time 97.26 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:03:53 PM PDT 24
Peak memory 200528 kb
Host smart-02c8331d-a2b6-4a4f-ae5e-bc14538d7bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559531199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.559531199
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.837328513
Short name T617
Test name
Test status
Simulation time 107124944067 ps
CPU time 22.73 seconds
Started May 16 01:01:56 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 200484 kb
Host smart-69ab48fb-7634-4375-8295-aed2e9d18cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837328513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.837328513
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3200342678
Short name T731
Test name
Test status
Simulation time 167637679327 ps
CPU time 140.28 seconds
Started May 16 01:01:55 PM PDT 24
Finished May 16 01:04:38 PM PDT 24
Peak memory 200520 kb
Host smart-39f626ad-1f24-4e15-84d4-3ec79b6e481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200342678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3200342678
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2026575730
Short name T842
Test name
Test status
Simulation time 14510458956 ps
CPU time 12.14 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 199072 kb
Host smart-3ddfcbf1-a7ab-42a0-a92d-6196cfb94c61
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026575730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2026575730
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1600565501
Short name T88
Test name
Test status
Simulation time 67928430347 ps
CPU time 315.71 seconds
Started May 16 01:01:55 PM PDT 24
Finished May 16 01:07:33 PM PDT 24
Peak memory 200392 kb
Host smart-489b3df9-9a37-4c93-bc9e-8a64aa2a2c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600565501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1600565501
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2656769572
Short name T425
Test name
Test status
Simulation time 6260907620 ps
CPU time 3.06 seconds
Started May 16 01:01:59 PM PDT 24
Finished May 16 01:02:24 PM PDT 24
Peak memory 200376 kb
Host smart-fed55485-3aab-4044-ac21-41d16b84ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656769572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2656769572
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1105177399
Short name T891
Test name
Test status
Simulation time 115331387302 ps
CPU time 35.97 seconds
Started May 16 01:01:57 PM PDT 24
Finished May 16 01:02:55 PM PDT 24
Peak memory 200708 kb
Host smart-04084712-8f30-4c82-af44-c89600d349fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105177399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1105177399
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2486101017
Short name T1038
Test name
Test status
Simulation time 7586654518 ps
CPU time 89.37 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:03:46 PM PDT 24
Peak memory 200496 kb
Host smart-a26fe5fa-ac57-4dcb-b8e4-8425bdce0618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486101017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2486101017
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2483593579
Short name T64
Test name
Test status
Simulation time 2230112660 ps
CPU time 12.76 seconds
Started May 16 01:01:53 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 198648 kb
Host smart-fa840663-3fc7-4c4e-b47e-58689785b41f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483593579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2483593579
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1646217100
Short name T732
Test name
Test status
Simulation time 176382637015 ps
CPU time 107.09 seconds
Started May 16 01:01:56 PM PDT 24
Finished May 16 01:04:06 PM PDT 24
Peak memory 200500 kb
Host smart-8c1e457c-bfd1-4fe5-acd2-54aeb8d4eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646217100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1646217100
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.908918986
Short name T986
Test name
Test status
Simulation time 6911545328 ps
CPU time 3.45 seconds
Started May 16 01:01:56 PM PDT 24
Finished May 16 01:02:22 PM PDT 24
Peak memory 196788 kb
Host smart-59cc7e7a-ab95-41db-bcf5-c7ce6012ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908918986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.908918986
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.129020307
Short name T660
Test name
Test status
Simulation time 779600826 ps
CPU time 1.18 seconds
Started May 16 01:01:57 PM PDT 24
Finished May 16 01:02:21 PM PDT 24
Peak memory 198732 kb
Host smart-08f9e596-f86d-4030-a607-92620f04655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129020307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.129020307
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.4290268149
Short name T1021
Test name
Test status
Simulation time 587308718543 ps
CPU time 134.28 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:04:39 PM PDT 24
Peak memory 216136 kb
Host smart-fd53cb0a-bf47-467b-8aaf-f6cf397dd509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290268149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4290268149
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3994605630
Short name T889
Test name
Test status
Simulation time 162281430870 ps
CPU time 863.96 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:16:41 PM PDT 24
Peak memory 229040 kb
Host smart-1fc47a64-a4a3-4043-9bf6-48dc3e169935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994605630 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3994605630
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3962419340
Short name T899
Test name
Test status
Simulation time 804927354 ps
CPU time 1.36 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:02:18 PM PDT 24
Peak memory 198752 kb
Host smart-fb7d10cc-6413-4881-8bb0-ad0f74fcb40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962419340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3962419340
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.776182207
Short name T1016
Test name
Test status
Simulation time 24805775995 ps
CPU time 53.8 seconds
Started May 16 01:01:54 PM PDT 24
Finished May 16 01:03:11 PM PDT 24
Peak memory 200452 kb
Host smart-8ca1acdb-8705-41bf-9b6b-0cf9ec9e2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776182207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.776182207
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.4177388845
Short name T790
Test name
Test status
Simulation time 11752652 ps
CPU time 0.54 seconds
Started May 16 01:02:07 PM PDT 24
Finished May 16 01:02:27 PM PDT 24
Peak memory 195884 kb
Host smart-c6265489-a32e-4372-b0e8-44c216bd7b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177388845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4177388845
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1672694966
Short name T316
Test name
Test status
Simulation time 113921415932 ps
CPU time 48.93 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:03:14 PM PDT 24
Peak memory 200448 kb
Host smart-dcc8e607-77fc-4544-93b5-b4aa937b1ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672694966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1672694966
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4178358485
Short name T154
Test name
Test status
Simulation time 339153399167 ps
CPU time 302.52 seconds
Started May 16 01:02:02 PM PDT 24
Finished May 16 01:07:26 PM PDT 24
Peak memory 200436 kb
Host smart-85e2be83-1f3c-4eb3-9c01-2cc558b5dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178358485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4178358485
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1862705924
Short name T735
Test name
Test status
Simulation time 89292003942 ps
CPU time 41.85 seconds
Started May 16 01:02:02 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 200428 kb
Host smart-93265491-4713-4b73-b97f-b5ab9e036822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862705924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1862705924
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.810323547
Short name T514
Test name
Test status
Simulation time 39174072842 ps
CPU time 18.87 seconds
Started May 16 01:02:03 PM PDT 24
Finished May 16 01:02:42 PM PDT 24
Peak memory 200332 kb
Host smart-3882da7b-6f67-4b2a-9417-dee9e837031b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810323547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.810323547
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.168247038
Short name T743
Test name
Test status
Simulation time 46447785526 ps
CPU time 165.73 seconds
Started May 16 01:02:05 PM PDT 24
Finished May 16 01:05:11 PM PDT 24
Peak memory 200488 kb
Host smart-6040dced-f07b-4c96-afb6-03718eb7a357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168247038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.168247038
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2927062248
Short name T578
Test name
Test status
Simulation time 2296706392 ps
CPU time 3.03 seconds
Started May 16 01:02:06 PM PDT 24
Finished May 16 01:02:29 PM PDT 24
Peak memory 198080 kb
Host smart-f39ee075-566c-4d22-8720-e821ce598a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927062248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2927062248
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1860153476
Short name T667
Test name
Test status
Simulation time 70405029474 ps
CPU time 54.37 seconds
Started May 16 01:02:06 PM PDT 24
Finished May 16 01:03:21 PM PDT 24
Peak memory 200780 kb
Host smart-c2303ecc-914f-46f5-8f8e-bd53cdbbfe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860153476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1860153476
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2887311060
Short name T904
Test name
Test status
Simulation time 22848926824 ps
CPU time 496.98 seconds
Started May 16 01:02:03 PM PDT 24
Finished May 16 01:10:41 PM PDT 24
Peak memory 200456 kb
Host smart-7864a051-4238-4b08-bbe8-acc31d36dc10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887311060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2887311060
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3133389218
Short name T1020
Test name
Test status
Simulation time 3162957646 ps
CPU time 19.83 seconds
Started May 16 01:02:03 PM PDT 24
Finished May 16 01:02:43 PM PDT 24
Peak memory 198848 kb
Host smart-2c75cee8-f999-4a8c-9cf8-659055dec2db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133389218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3133389218
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2408587582
Short name T1055
Test name
Test status
Simulation time 360661922342 ps
CPU time 32.08 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:02:56 PM PDT 24
Peak memory 200448 kb
Host smart-db8ddd91-4090-4a11-90fb-d000a8366b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408587582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2408587582
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2300889445
Short name T593
Test name
Test status
Simulation time 5640046543 ps
CPU time 2.97 seconds
Started May 16 01:02:02 PM PDT 24
Finished May 16 01:02:26 PM PDT 24
Peak memory 196472 kb
Host smart-a5dc4a3a-8776-4f93-bf29-46dffa369376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300889445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2300889445
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1296340167
Short name T828
Test name
Test status
Simulation time 11068672163 ps
CPU time 40.48 seconds
Started May 16 01:02:02 PM PDT 24
Finished May 16 01:03:04 PM PDT 24
Peak memory 199964 kb
Host smart-1e975ba2-e6c4-451f-bc83-f8abfba6a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296340167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1296340167
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2854025062
Short name T966
Test name
Test status
Simulation time 207272212331 ps
CPU time 284.9 seconds
Started May 16 01:02:03 PM PDT 24
Finished May 16 01:07:08 PM PDT 24
Peak memory 216848 kb
Host smart-9e1d2fd9-0115-4216-9bf6-f247e61bef8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854025062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2854025062
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2253361118
Short name T887
Test name
Test status
Simulation time 22245551902 ps
CPU time 228.45 seconds
Started May 16 01:02:01 PM PDT 24
Finished May 16 01:06:11 PM PDT 24
Peak memory 208768 kb
Host smart-ebada0b0-ea03-4dfb-9181-0c97bd211c21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253361118 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2253361118
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1113953689
Short name T520
Test name
Test status
Simulation time 1687177168 ps
CPU time 1.55 seconds
Started May 16 01:02:05 PM PDT 24
Finished May 16 01:02:27 PM PDT 24
Peak memory 199068 kb
Host smart-740025d2-9ce9-4fa4-95af-2017829ee061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113953689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1113953689
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1477028933
Short name T531
Test name
Test status
Simulation time 17973334571 ps
CPU time 12.05 seconds
Started May 16 01:02:07 PM PDT 24
Finished May 16 01:02:38 PM PDT 24
Peak memory 199748 kb
Host smart-d7addd0a-5314-4748-889b-782ed4a35883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477028933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1477028933
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.607516457
Short name T976
Test name
Test status
Simulation time 39404259 ps
CPU time 0.53 seconds
Started May 16 01:02:16 PM PDT 24
Finished May 16 01:02:34 PM PDT 24
Peak memory 195844 kb
Host smart-e2000f65-2035-4b15-abfa-faa0cdd69484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607516457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.607516457
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3378014288
Short name T292
Test name
Test status
Simulation time 70402036853 ps
CPU time 228.71 seconds
Started May 16 01:02:05 PM PDT 24
Finished May 16 01:06:14 PM PDT 24
Peak memory 200440 kb
Host smart-6b489a90-ae07-4dd7-b9c0-4159c620c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378014288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3378014288
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.643705498
Short name T1080
Test name
Test status
Simulation time 51816466802 ps
CPU time 19.18 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:02:44 PM PDT 24
Peak memory 200424 kb
Host smart-00c829a5-c783-4d06-8ca5-8ed55bf19c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643705498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.643705498
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2800612948
Short name T486
Test name
Test status
Simulation time 21725740279 ps
CPU time 12.02 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:02:37 PM PDT 24
Peak memory 200376 kb
Host smart-92b1126b-9988-4718-bf03-5d783abb7df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800612948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2800612948
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3519287288
Short name T298
Test name
Test status
Simulation time 251018667674 ps
CPU time 397.93 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:09:02 PM PDT 24
Peak memory 200444 kb
Host smart-920d5ad5-99b6-4674-88a5-3d38e28600ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519287288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3519287288
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3413089592
Short name T580
Test name
Test status
Simulation time 82178508974 ps
CPU time 679.6 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:13:50 PM PDT 24
Peak memory 200424 kb
Host smart-5e2ddd2b-6e1d-4567-8e3d-2bce322ae811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413089592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3413089592
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2433050196
Short name T640
Test name
Test status
Simulation time 6783077430 ps
CPU time 6.02 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:02:36 PM PDT 24
Peak memory 200436 kb
Host smart-ef00d6eb-a700-4ead-9f36-5c2cf2196135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433050196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2433050196
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.4259387278
Short name T454
Test name
Test status
Simulation time 128848398363 ps
CPU time 74.36 seconds
Started May 16 01:02:15 PM PDT 24
Finished May 16 01:03:47 PM PDT 24
Peak memory 200480 kb
Host smart-1e83d9e6-7b87-4aa0-91b3-20a03b7904fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259387278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.4259387278
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.70406927
Short name T256
Test name
Test status
Simulation time 25231077956 ps
CPU time 138.1 seconds
Started May 16 01:02:12 PM PDT 24
Finished May 16 01:04:49 PM PDT 24
Peak memory 200520 kb
Host smart-040d5a53-919c-4dda-a07e-12f6877b44a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70406927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.70406927
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1744959213
Short name T601
Test name
Test status
Simulation time 4147650337 ps
CPU time 18.2 seconds
Started May 16 01:02:02 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 198588 kb
Host smart-1e302cf9-bd3c-487f-9f7a-73290109fddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744959213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1744959213
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.500839936
Short name T937
Test name
Test status
Simulation time 59555188865 ps
CPU time 26.37 seconds
Started May 16 01:02:15 PM PDT 24
Finished May 16 01:02:59 PM PDT 24
Peak memory 199668 kb
Host smart-41cd23a2-6fd4-4600-be19-2273fd06365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500839936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.500839936
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.435455628
Short name T410
Test name
Test status
Simulation time 4251750770 ps
CPU time 7.93 seconds
Started May 16 01:02:13 PM PDT 24
Finished May 16 01:02:39 PM PDT 24
Peak memory 196504 kb
Host smart-bbf7700a-c897-4695-b497-8f4d28629faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435455628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.435455628
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2276512084
Short name T272
Test name
Test status
Simulation time 5980001889 ps
CPU time 12.44 seconds
Started May 16 01:02:03 PM PDT 24
Finished May 16 01:02:36 PM PDT 24
Peak memory 200452 kb
Host smart-46a63f74-b712-419c-9ba0-de44f521d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276512084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2276512084
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3371894491
Short name T45
Test name
Test status
Simulation time 304523036827 ps
CPU time 376.1 seconds
Started May 16 01:02:16 PM PDT 24
Finished May 16 01:08:50 PM PDT 24
Peak memory 216960 kb
Host smart-958152e5-2065-42fb-b374-85a647d40427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371894491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3371894491
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2743086009
Short name T896
Test name
Test status
Simulation time 6601892738 ps
CPU time 12.61 seconds
Started May 16 01:02:12 PM PDT 24
Finished May 16 01:02:43 PM PDT 24
Peak memory 199960 kb
Host smart-c066b92e-dcb4-4753-b6d7-1ad7f3be6401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743086009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2743086009
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3094554376
Short name T9
Test name
Test status
Simulation time 12052204519 ps
CPU time 15.52 seconds
Started May 16 01:02:04 PM PDT 24
Finished May 16 01:02:40 PM PDT 24
Peak memory 200468 kb
Host smart-5657eeb8-c2b7-4798-8978-b9ce64228145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094554376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3094554376
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3849631300
Short name T659
Test name
Test status
Simulation time 11585094 ps
CPU time 0.56 seconds
Started May 16 01:02:18 PM PDT 24
Finished May 16 01:02:35 PM PDT 24
Peak memory 195880 kb
Host smart-b69d1613-e71c-4700-96f0-76ecf2e88916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849631300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3849631300
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3221389735
Short name T452
Test name
Test status
Simulation time 196582971542 ps
CPU time 152.97 seconds
Started May 16 01:02:13 PM PDT 24
Finished May 16 01:05:05 PM PDT 24
Peak memory 200524 kb
Host smart-2e0afc70-24ed-49b3-ae84-ec642dfdd951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221389735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3221389735
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1792821705
Short name T261
Test name
Test status
Simulation time 201170592217 ps
CPU time 352.08 seconds
Started May 16 01:02:14 PM PDT 24
Finished May 16 01:08:24 PM PDT 24
Peak memory 200392 kb
Host smart-4e2016ca-5256-4b8c-a8f3-e1dfb1817ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792821705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1792821705
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.1466823048
Short name T838
Test name
Test status
Simulation time 23865938997 ps
CPU time 6.68 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:02:37 PM PDT 24
Peak memory 200336 kb
Host smart-8c65ab24-0b62-4148-895b-8e9eb4fae1ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466823048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1466823048
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2037156845
Short name T372
Test name
Test status
Simulation time 120125653858 ps
CPU time 584.51 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:12:15 PM PDT 24
Peak memory 200492 kb
Host smart-cdf75d6d-5580-4407-9279-d1326966fa72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037156845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2037156845
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.55560919
Short name T339
Test name
Test status
Simulation time 1647780019 ps
CPU time 0.99 seconds
Started May 16 01:02:14 PM PDT 24
Finished May 16 01:02:33 PM PDT 24
Peak memory 196424 kb
Host smart-f1b36bd7-f3ca-462a-8f1a-308de8a77452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55560919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.55560919
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2729076959
Short name T369
Test name
Test status
Simulation time 76858561985 ps
CPU time 131.58 seconds
Started May 16 01:02:13 PM PDT 24
Finished May 16 01:04:43 PM PDT 24
Peak memory 199728 kb
Host smart-9203f93d-ecf2-4469-87ae-4977d42f47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729076959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2729076959
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1677978024
Short name T1008
Test name
Test status
Simulation time 14264758220 ps
CPU time 207.21 seconds
Started May 16 01:02:12 PM PDT 24
Finished May 16 01:05:58 PM PDT 24
Peak memory 200448 kb
Host smart-3b1f9048-a139-4d68-905d-e64163dd9d7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677978024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1677978024
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3582543213
Short name T343
Test name
Test status
Simulation time 5534998185 ps
CPU time 49.61 seconds
Started May 16 01:02:18 PM PDT 24
Finished May 16 01:03:24 PM PDT 24
Peak memory 199668 kb
Host smart-c26d51d8-eb83-417e-a7c1-c9ab1129e9ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582543213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3582543213
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1323682216
Short name T623
Test name
Test status
Simulation time 187862258061 ps
CPU time 86.03 seconds
Started May 16 01:02:18 PM PDT 24
Finished May 16 01:04:00 PM PDT 24
Peak memory 200452 kb
Host smart-f57e3061-16ba-41c7-9c74-2d878bb708e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323682216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1323682216
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.829607738
Short name T495
Test name
Test status
Simulation time 7872906303 ps
CPU time 3.92 seconds
Started May 16 01:02:13 PM PDT 24
Finished May 16 01:02:35 PM PDT 24
Peak memory 196800 kb
Host smart-b6ed6f74-b75c-4a0c-8d0d-a0b57f4b9d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829607738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.829607738
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.447619759
Short name T906
Test name
Test status
Simulation time 888110598 ps
CPU time 3.19 seconds
Started May 16 01:02:16 PM PDT 24
Finished May 16 01:02:37 PM PDT 24
Peak memory 199844 kb
Host smart-9c0a9fdc-8af5-4c70-bacb-52f84bb8cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447619759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.447619759
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2981573639
Short name T830
Test name
Test status
Simulation time 196405641270 ps
CPU time 402.57 seconds
Started May 16 01:02:13 PM PDT 24
Finished May 16 01:09:14 PM PDT 24
Peak memory 208948 kb
Host smart-3e112336-3f1a-485b-8dad-ba14d46bc6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981573639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2981573639
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1071093438
Short name T925
Test name
Test status
Simulation time 39230251630 ps
CPU time 769.82 seconds
Started May 16 01:02:14 PM PDT 24
Finished May 16 01:15:22 PM PDT 24
Peak memory 215976 kb
Host smart-b54fde73-ce90-46cf-8bf5-784ef2cb8340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071093438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1071093438
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4095853895
Short name T759
Test name
Test status
Simulation time 1238101664 ps
CPU time 3.39 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:02:33 PM PDT 24
Peak memory 198796 kb
Host smart-0584d231-0947-4df3-9694-6dee54bbcf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095853895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4095853895
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3165090438
Short name T849
Test name
Test status
Simulation time 134176941861 ps
CPU time 343.75 seconds
Started May 16 01:02:14 PM PDT 24
Finished May 16 01:08:16 PM PDT 24
Peak memory 200340 kb
Host smart-eaa8f544-d150-4f0d-82c3-6050390e400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165090438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3165090438
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2817616666
Short name T359
Test name
Test status
Simulation time 33633526 ps
CPU time 0.57 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:02:37 PM PDT 24
Peak memory 195852 kb
Host smart-e6cae1f0-1a08-44be-91af-1019e48ab977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817616666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2817616666
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.330427853
Short name T89
Test name
Test status
Simulation time 117105675377 ps
CPU time 337.08 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:08:08 PM PDT 24
Peak memory 200432 kb
Host smart-70e2e0f8-53e3-4fc9-9ab5-9ba7646053ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330427853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.330427853
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.696998492
Short name T1173
Test name
Test status
Simulation time 80046230503 ps
CPU time 16.66 seconds
Started May 16 01:02:18 PM PDT 24
Finished May 16 01:02:51 PM PDT 24
Peak memory 200532 kb
Host smart-4de56c5e-bd2b-429e-b714-7846fc262d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696998492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.696998492
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.2708501462
Short name T1152
Test name
Test status
Simulation time 24406884469 ps
CPU time 10.84 seconds
Started May 16 01:02:12 PM PDT 24
Finished May 16 01:02:42 PM PDT 24
Peak memory 198988 kb
Host smart-e2472333-9248-478a-80b4-a18b6d74f9c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708501462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2708501462
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.301531793
Short name T577
Test name
Test status
Simulation time 55326982885 ps
CPU time 70.24 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:03:46 PM PDT 24
Peak memory 200564 kb
Host smart-d12d7b68-fa25-4e32-9742-ae1aa8f4b4ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301531793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.301531793
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.4090740252
Short name T684
Test name
Test status
Simulation time 1493334460 ps
CPU time 1.18 seconds
Started May 16 01:02:21 PM PDT 24
Finished May 16 01:02:39 PM PDT 24
Peak memory 196160 kb
Host smart-b86a9d82-cfe2-45fc-8fc6-704f76248db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090740252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4090740252
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2287819637
Short name T586
Test name
Test status
Simulation time 472635804143 ps
CPU time 44.38 seconds
Started May 16 01:02:14 PM PDT 24
Finished May 16 01:03:16 PM PDT 24
Peak memory 200764 kb
Host smart-f4ede28d-6172-44ba-9c4d-4dc7ac3200c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287819637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2287819637
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3539674363
Short name T301
Test name
Test status
Simulation time 11445938154 ps
CPU time 514.05 seconds
Started May 16 01:02:19 PM PDT 24
Finished May 16 01:11:10 PM PDT 24
Peak memory 200476 kb
Host smart-4b04547b-0897-439d-a145-3c2f9814bb7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539674363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3539674363
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1920602099
Short name T626
Test name
Test status
Simulation time 6507632903 ps
CPU time 14.47 seconds
Started May 16 01:02:16 PM PDT 24
Finished May 16 01:02:48 PM PDT 24
Peak memory 199728 kb
Host smart-64552e4a-5672-4a3a-9859-296c453a3202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920602099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1920602099
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2326103652
Short name T138
Test name
Test status
Simulation time 40378207550 ps
CPU time 65.46 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:03:43 PM PDT 24
Peak memory 200396 kb
Host smart-4f2f3c2f-b052-4a96-90b5-81e6c3494fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326103652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2326103652
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.559293866
Short name T1011
Test name
Test status
Simulation time 3137522201 ps
CPU time 2.99 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:02:33 PM PDT 24
Peak memory 196452 kb
Host smart-33bd4087-b140-4a9f-b6e6-06bb7d1a3162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559293866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.559293866
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2996132079
Short name T749
Test name
Test status
Simulation time 655683482 ps
CPU time 1.9 seconds
Started May 16 01:02:11 PM PDT 24
Finished May 16 01:02:32 PM PDT 24
Peak memory 200332 kb
Host smart-41e294e6-9923-4937-b239-3a8fae89a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996132079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2996132079
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3654599990
Short name T449
Test name
Test status
Simulation time 240438871449 ps
CPU time 576.16 seconds
Started May 16 01:02:23 PM PDT 24
Finished May 16 01:12:15 PM PDT 24
Peak memory 200444 kb
Host smart-da3b31a6-71da-40b7-9bac-82fd5a88f189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654599990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3654599990
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2651815219
Short name T939
Test name
Test status
Simulation time 789775614 ps
CPU time 2.63 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 200288 kb
Host smart-e2a351cc-3756-4ce5-95a6-969a277afab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651815219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2651815219
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1978385452
Short name T11
Test name
Test status
Simulation time 87608378845 ps
CPU time 197.51 seconds
Started May 16 01:02:13 PM PDT 24
Finished May 16 01:05:49 PM PDT 24
Peak memory 200532 kb
Host smart-67df25b1-70e8-4f37-b0ae-ac71cca28f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978385452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1978385452
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1500816748
Short name T942
Test name
Test status
Simulation time 73202575 ps
CPU time 0.58 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:02:39 PM PDT 24
Peak memory 195856 kb
Host smart-1f58a024-b9fe-4f51-8d59-c472ed3f14d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500816748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1500816748
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1917674393
Short name T124
Test name
Test status
Simulation time 21066007942 ps
CPU time 33.98 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:03:12 PM PDT 24
Peak memory 200496 kb
Host smart-d921d5b9-9734-4831-a74c-941a32ad86cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917674393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1917674393
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1710432411
Short name T161
Test name
Test status
Simulation time 39659193554 ps
CPU time 22.95 seconds
Started May 16 01:02:21 PM PDT 24
Finished May 16 01:03:00 PM PDT 24
Peak memory 200408 kb
Host smart-b703b5e8-05f2-48b9-9e0e-91329837faf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710432411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1710432411
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3364240162
Short name T713
Test name
Test status
Simulation time 48370560365 ps
CPU time 75.04 seconds
Started May 16 01:02:23 PM PDT 24
Finished May 16 01:03:54 PM PDT 24
Peak memory 200412 kb
Host smart-16d72ee7-ccc3-49b1-aff4-82682a6aef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364240162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3364240162
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.263871702
Short name T767
Test name
Test status
Simulation time 45892239766 ps
CPU time 84.2 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:04:02 PM PDT 24
Peak memory 200460 kb
Host smart-b233006f-53de-4382-8257-fbe356a00edb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263871702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.263871702
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.76561141
Short name T427
Test name
Test status
Simulation time 115959280021 ps
CPU time 720.98 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:14:37 PM PDT 24
Peak memory 200384 kb
Host smart-11f6fe4f-1fee-4ccd-a0f9-965cb715fcb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76561141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.76561141
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2231766303
Short name T374
Test name
Test status
Simulation time 2121908498 ps
CPU time 4.15 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:02:43 PM PDT 24
Peak memory 198524 kb
Host smart-54e75fdb-26ab-42ba-b07a-6484c64f1737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231766303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2231766303
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1247011873
Short name T850
Test name
Test status
Simulation time 37339216356 ps
CPU time 69.99 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:03:47 PM PDT 24
Peak memory 200656 kb
Host smart-257abab8-71aa-4563-9cac-89ee14a9b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247011873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1247011873
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1631090965
Short name T521
Test name
Test status
Simulation time 10543051738 ps
CPU time 307.21 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:07:44 PM PDT 24
Peak memory 200468 kb
Host smart-0a320e80-d9cb-4457-b4a1-3535650a35d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1631090965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1631090965
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.8916674
Short name T65
Test name
Test status
Simulation time 6951268773 ps
CPU time 9.95 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:02:49 PM PDT 24
Peak memory 199668 kb
Host smart-5f91ea35-af50-42ac-a78b-6287a899ae43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8916674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.8916674
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3717897781
Short name T1039
Test name
Test status
Simulation time 16502984301 ps
CPU time 27.13 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 200204 kb
Host smart-8309e431-9b26-4d01-aec1-2cc6982a9a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717897781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3717897781
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3398997829
Short name T874
Test name
Test status
Simulation time 6582395311 ps
CPU time 5.37 seconds
Started May 16 01:02:21 PM PDT 24
Finished May 16 01:02:42 PM PDT 24
Peak memory 196488 kb
Host smart-662cd53f-4a1a-4ab7-89e1-19b5168e7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398997829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3398997829
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3232907414
Short name T1072
Test name
Test status
Simulation time 83807386 ps
CPU time 0.85 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:02:37 PM PDT 24
Peak memory 197436 kb
Host smart-4ed01ae8-e3c3-47d0-b2e5-f149d88e6fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232907414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3232907414
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3090439988
Short name T726
Test name
Test status
Simulation time 231371163160 ps
CPU time 346.13 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:08:24 PM PDT 24
Peak memory 200504 kb
Host smart-2d117524-733e-4e8e-a71f-f10e7aa5f605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090439988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3090439988
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.4250052065
Short name T96
Test name
Test status
Simulation time 70762670786 ps
CPU time 170.4 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:05:27 PM PDT 24
Peak memory 217156 kb
Host smart-251b467a-098e-41a3-b894-f2a908bbbeb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250052065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4250052065
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3079810496
Short name T411
Test name
Test status
Simulation time 1078536948 ps
CPU time 2.22 seconds
Started May 16 01:02:21 PM PDT 24
Finished May 16 01:02:40 PM PDT 24
Peak memory 199160 kb
Host smart-c488f231-cde4-4344-bb48-61a1915c0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079810496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3079810496
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.910457871
Short name T624
Test name
Test status
Simulation time 62271023380 ps
CPU time 26.75 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 200496 kb
Host smart-ffbd89ac-c012-48ed-b9cb-0e70e1d82ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910457871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.910457871
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.704673665
Short name T341
Test name
Test status
Simulation time 12225951 ps
CPU time 0.57 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:02:46 PM PDT 24
Peak memory 195844 kb
Host smart-72f5fdce-1fde-4be3-a45b-96e8902a9d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704673665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.704673665
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2788483778
Short name T140
Test name
Test status
Simulation time 44277452333 ps
CPU time 17.42 seconds
Started May 16 01:02:24 PM PDT 24
Finished May 16 01:02:57 PM PDT 24
Peak memory 200400 kb
Host smart-901b2bb2-c96e-4b73-8b9d-628c0dd6458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788483778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2788483778
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3800086098
Short name T105
Test name
Test status
Simulation time 124775906505 ps
CPU time 246.39 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:06:42 PM PDT 24
Peak memory 200420 kb
Host smart-81a45d70-550c-461b-a910-47326463ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800086098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3800086098
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.309478239
Short name T868
Test name
Test status
Simulation time 55352058967 ps
CPU time 22.91 seconds
Started May 16 01:02:21 PM PDT 24
Finished May 16 01:03:00 PM PDT 24
Peak memory 200504 kb
Host smart-7dbf32f4-7cda-4345-8022-bba02050cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309478239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.309478239
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2993464690
Short name T1014
Test name
Test status
Simulation time 39240064042 ps
CPU time 19.25 seconds
Started May 16 01:02:20 PM PDT 24
Finished May 16 01:02:55 PM PDT 24
Peak memory 198996 kb
Host smart-c8b96a51-2616-4848-8994-be520eed94b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993464690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2993464690
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2627937417
Short name T649
Test name
Test status
Simulation time 98346876389 ps
CPU time 677.91 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:14:03 PM PDT 24
Peak memory 200444 kb
Host smart-2aa19e4b-b0a5-4f96-b20c-8b9968bea443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627937417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2627937417
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2772968637
Short name T1056
Test name
Test status
Simulation time 3295185526 ps
CPU time 3.2 seconds
Started May 16 01:02:37 PM PDT 24
Finished May 16 01:02:52 PM PDT 24
Peak memory 196204 kb
Host smart-bfa8a0cb-bebd-4e06-aa29-f84a6acf7472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772968637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2772968637
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3714258248
Short name T916
Test name
Test status
Simulation time 39628213203 ps
CPU time 25.36 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:03:04 PM PDT 24
Peak memory 200676 kb
Host smart-2086e83c-7e93-42b0-899b-c3f1aa6f3149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714258248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3714258248
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.741708605
Short name T518
Test name
Test status
Simulation time 18462213070 ps
CPU time 252.08 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:06:59 PM PDT 24
Peak memory 200516 kb
Host smart-f17b6b82-1204-4db3-b746-bf721dbc3dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741708605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.741708605
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1477314213
Short name T470
Test name
Test status
Simulation time 1803594297 ps
CPU time 6.88 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:02:46 PM PDT 24
Peak memory 199120 kb
Host smart-e8de9c91-f7f5-4665-a0c1-3ff92f57941f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477314213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1477314213
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3820807597
Short name T845
Test name
Test status
Simulation time 106301495061 ps
CPU time 187.93 seconds
Started May 16 01:02:32 PM PDT 24
Finished May 16 01:05:52 PM PDT 24
Peak memory 200404 kb
Host smart-93aa8c39-c58d-4a41-a704-47f6893da547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820807597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3820807597
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1231013733
Short name T780
Test name
Test status
Simulation time 3487414969 ps
CPU time 3.27 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 196252 kb
Host smart-c7466599-0035-49ed-be14-6487c2c0bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231013733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1231013733
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1618273800
Short name T366
Test name
Test status
Simulation time 673781838 ps
CPU time 2.41 seconds
Started May 16 01:02:22 PM PDT 24
Finished May 16 01:02:41 PM PDT 24
Peak memory 198696 kb
Host smart-cb9a0133-1982-4914-8432-7bd9fcdf0fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618273800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1618273800
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3295162350
Short name T527
Test name
Test status
Simulation time 417428421659 ps
CPU time 518.52 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:11:25 PM PDT 24
Peak memory 200500 kb
Host smart-e269b1b0-cb8a-4edf-a69e-d85cf131a99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295162350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3295162350
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3586471777
Short name T477
Test name
Test status
Simulation time 251643653160 ps
CPU time 182.84 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:05:48 PM PDT 24
Peak memory 209760 kb
Host smart-eecf9f0e-6f08-4a5e-877b-e781360ffdc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586471777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3586471777
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.564685882
Short name T415
Test name
Test status
Simulation time 6858055103 ps
CPU time 24.29 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:03:09 PM PDT 24
Peak memory 200264 kb
Host smart-c08ce534-857c-46e0-9d4d-9c1c6a40e77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564685882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.564685882
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2130099337
Short name T824
Test name
Test status
Simulation time 35621744747 ps
CPU time 64.75 seconds
Started May 16 01:02:21 PM PDT 24
Finished May 16 01:03:42 PM PDT 24
Peak memory 200372 kb
Host smart-ae990be8-10c4-4ce9-9ebc-cae37a5cb54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130099337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2130099337
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1754140854
Short name T1135
Test name
Test status
Simulation time 84319055 ps
CPU time 0.53 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:02:46 PM PDT 24
Peak memory 195856 kb
Host smart-bd0dccc0-cfd8-409c-a191-46bdeba99989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754140854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1754140854
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.487825744
Short name T637
Test name
Test status
Simulation time 63210308257 ps
CPU time 45.96 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:03:32 PM PDT 24
Peak memory 200452 kb
Host smart-a3290a10-bac1-4c58-a067-bc94d498be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487825744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.487825744
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3775094530
Short name T952
Test name
Test status
Simulation time 68108889451 ps
CPU time 111.29 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:04:36 PM PDT 24
Peak memory 200336 kb
Host smart-50e606cc-ec6e-47be-b4cd-b372c1bfa808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775094530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3775094530
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.751070447
Short name T908
Test name
Test status
Simulation time 72194866819 ps
CPU time 48.94 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:03:33 PM PDT 24
Peak memory 200380 kb
Host smart-cbdcc9a2-2f23-4184-80fa-7fd081323ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751070447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.751070447
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3768675633
Short name T915
Test name
Test status
Simulation time 59474359531 ps
CPU time 103.8 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200460 kb
Host smart-80885423-cf22-4f74-b9d3-78b36bcae70c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768675633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3768675633
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2899416541
Short name T841
Test name
Test status
Simulation time 90641007233 ps
CPU time 577.51 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:12:24 PM PDT 24
Peak memory 200484 kb
Host smart-846064e6-250c-46cd-830e-f98a19c53c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899416541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2899416541
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2789471016
Short name T605
Test name
Test status
Simulation time 3745166563 ps
CPU time 2.26 seconds
Started May 16 01:02:36 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 196996 kb
Host smart-803942ca-1465-4de4-9931-e7c2c3cbe879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789471016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2789471016
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2795573440
Short name T1004
Test name
Test status
Simulation time 38318430605 ps
CPU time 34.61 seconds
Started May 16 01:02:37 PM PDT 24
Finished May 16 01:03:23 PM PDT 24
Peak memory 199332 kb
Host smart-74e5e501-0670-4e9a-87bd-23e41140c5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795573440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2795573440
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2797705018
Short name T530
Test name
Test status
Simulation time 5287700536 ps
CPU time 333.69 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:08:20 PM PDT 24
Peak memory 200240 kb
Host smart-dfdc11cc-e765-4d63-aa42-423e101cc559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797705018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2797705018
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3412901337
Short name T661
Test name
Test status
Simulation time 5046527829 ps
CPU time 3.85 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 199712 kb
Host smart-7e2ab906-9279-46a9-939c-567e88afae20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412901337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3412901337
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3655064972
Short name T1144
Test name
Test status
Simulation time 62118229963 ps
CPU time 75.09 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:04:00 PM PDT 24
Peak memory 200364 kb
Host smart-2265fc30-bee2-4744-a1f0-91addd7f9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655064972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3655064972
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1675315171
Short name T480
Test name
Test status
Simulation time 42133347198 ps
CPU time 58.51 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:03:45 PM PDT 24
Peak memory 196192 kb
Host smart-76d373df-c39c-4173-9b1c-1692cf9f59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675315171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1675315171
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.734711848
Short name T464
Test name
Test status
Simulation time 5370981909 ps
CPU time 8.87 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:02:54 PM PDT 24
Peak memory 199796 kb
Host smart-5a1cb946-295f-469c-a2bd-223a07108bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734711848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.734711848
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.901439932
Short name T858
Test name
Test status
Simulation time 50957132342 ps
CPU time 236.28 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:06:43 PM PDT 24
Peak memory 200476 kb
Host smart-f4feada5-c7c6-4c65-8c02-0d486052361e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901439932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.901439932
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2238677772
Short name T627
Test name
Test status
Simulation time 359799995825 ps
CPU time 977.88 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:19:04 PM PDT 24
Peak memory 225380 kb
Host smart-91fb5266-c64a-44ff-b3b7-c9cfb20594b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238677772 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2238677772
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1056699
Short name T892
Test name
Test status
Simulation time 6802366895 ps
CPU time 11.3 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:02:58 PM PDT 24
Peak memory 200400 kb
Host smart-3e6f7028-4afd-42f4-88e7-b77c3e1a2485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1056699
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2799285622
Short name T321
Test name
Test status
Simulation time 90189125539 ps
CPU time 37.76 seconds
Started May 16 01:02:34 PM PDT 24
Finished May 16 01:03:24 PM PDT 24
Peak memory 200440 kb
Host smart-ffbc2f3b-ace1-4f30-ae6f-444c15eaf68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799285622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2799285622
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1452747981
Short name T548
Test name
Test status
Simulation time 21511867 ps
CPU time 0.56 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:00:56 PM PDT 24
Peak memory 195880 kb
Host smart-3478e54d-e922-4625-9ec6-43bf007dfca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452747981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1452747981
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2901112465
Short name T1054
Test name
Test status
Simulation time 278722644576 ps
CPU time 80.45 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:02:12 PM PDT 24
Peak memory 200488 kb
Host smart-f0e95a02-a006-4709-9c84-b4b1b5701326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901112465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2901112465
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1203919643
Short name T1131
Test name
Test status
Simulation time 142754725361 ps
CPU time 209.49 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:04:25 PM PDT 24
Peak memory 200472 kb
Host smart-399cead3-1a28-4c5c-b02b-b2009cb61420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203919643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1203919643
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3855263724
Short name T804
Test name
Test status
Simulation time 30263860831 ps
CPU time 12.62 seconds
Started May 16 01:00:14 PM PDT 24
Finished May 16 01:01:06 PM PDT 24
Peak memory 200444 kb
Host smart-a30c0c20-875d-4f93-b888-34b667ffc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855263724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3855263724
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3886721030
Short name T651
Test name
Test status
Simulation time 234877721857 ps
CPU time 93.51 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:02:34 PM PDT 24
Peak memory 200408 kb
Host smart-93ff5b4a-730b-48c0-9452-e0e0dc514e39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886721030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3886721030
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2724872071
Short name T1045
Test name
Test status
Simulation time 109096960458 ps
CPU time 695.76 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:12:28 PM PDT 24
Peak memory 200468 kb
Host smart-256cb3f0-e8ef-4627-8abc-902e32214a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724872071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2724872071
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.938047829
Short name T707
Test name
Test status
Simulation time 4920201775 ps
CPU time 11.35 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:01:04 PM PDT 24
Peak memory 199868 kb
Host smart-3705557b-2afe-4758-92f3-53ffe00d919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938047829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.938047829
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.211194048
Short name T843
Test name
Test status
Simulation time 23514837195 ps
CPU time 11.32 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:01:04 PM PDT 24
Peak memory 197540 kb
Host smart-6a9ee8fa-32fe-4130-ade7-b99b9ccfb38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211194048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.211194048
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2865741552
Short name T510
Test name
Test status
Simulation time 23288644024 ps
CPU time 143.54 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:03:17 PM PDT 24
Peak memory 200456 kb
Host smart-9a941fdc-dda7-457a-8dfb-da2330b2db24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865741552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2865741552
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2759404325
Short name T490
Test name
Test status
Simulation time 1818251826 ps
CPU time 2.53 seconds
Started May 16 01:00:19 PM PDT 24
Finished May 16 01:01:01 PM PDT 24
Peak memory 198632 kb
Host smart-4e224021-d53f-43fb-9120-e8c27973281a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759404325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2759404325
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2077895818
Short name T444
Test name
Test status
Simulation time 53777573757 ps
CPU time 29.95 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:25 PM PDT 24
Peak memory 200392 kb
Host smart-02c9b96d-41ad-43ed-9c13-751bfcd51f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077895818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2077895818
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.500253181
Short name T1006
Test name
Test status
Simulation time 633290833 ps
CPU time 1.09 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:00:54 PM PDT 24
Peak memory 195808 kb
Host smart-5f164c9c-1606-4e1f-8292-705723d3ab34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500253181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.500253181
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.643776722
Short name T85
Test name
Test status
Simulation time 189255837 ps
CPU time 0.83 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:00:54 PM PDT 24
Peak memory 219040 kb
Host smart-f2ec2a68-dec9-40d4-ace5-79e8aaad0737
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643776722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.643776722
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1810878673
Short name T1090
Test name
Test status
Simulation time 6316633568 ps
CPU time 19.3 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:01:14 PM PDT 24
Peak memory 200200 kb
Host smart-f4ee8da5-074c-4c2d-b56a-92c6d7303e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810878673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1810878673
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1343348545
Short name T109
Test name
Test status
Simulation time 231189057670 ps
CPU time 686.13 seconds
Started May 16 01:00:19 PM PDT 24
Finished May 16 01:12:25 PM PDT 24
Peak memory 200476 kb
Host smart-8e4ac1a4-2ec4-466d-90f0-14aeb6c8a0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343348545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1343348545
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2744525105
Short name T1070
Test name
Test status
Simulation time 19367332936 ps
CPU time 245.55 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:04:59 PM PDT 24
Peak memory 217096 kb
Host smart-1051d6a2-e249-4d1c-82be-dcb8f9d28cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744525105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2744525105
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3598862028
Short name T705
Test name
Test status
Simulation time 1232560475 ps
CPU time 2.53 seconds
Started May 16 01:00:13 PM PDT 24
Finished May 16 01:00:55 PM PDT 24
Peak memory 199388 kb
Host smart-990fb856-550c-408e-b7db-53161737a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598862028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3598862028
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2992802954
Short name T697
Test name
Test status
Simulation time 96640520552 ps
CPU time 75.03 seconds
Started May 16 01:00:15 PM PDT 24
Finished May 16 01:02:10 PM PDT 24
Peak memory 200484 kb
Host smart-e032bd77-855f-4880-91ae-25a3b65556b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992802954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2992802954
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3610835361
Short name T25
Test name
Test status
Simulation time 36391538 ps
CPU time 0.55 seconds
Started May 16 01:02:44 PM PDT 24
Finished May 16 01:02:54 PM PDT 24
Peak memory 195856 kb
Host smart-1c62956b-fe32-458f-9a38-d9d6f31e9b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610835361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3610835361
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.437596042
Short name T468
Test name
Test status
Simulation time 311556314489 ps
CPU time 109.15 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:04:36 PM PDT 24
Peak memory 200496 kb
Host smart-be366c7c-4fcb-4073-b6f2-5a6d3e62cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437596042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.437596042
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.472257416
Short name T979
Test name
Test status
Simulation time 120736705988 ps
CPU time 210.17 seconds
Started May 16 01:02:35 PM PDT 24
Finished May 16 01:06:17 PM PDT 24
Peak memory 200532 kb
Host smart-171b4531-5813-46cf-97d6-5796e08b372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472257416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.472257416
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2723941440
Short name T769
Test name
Test status
Simulation time 145300653536 ps
CPU time 1163.93 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:22:21 PM PDT 24
Peak memory 200460 kb
Host smart-faa9d4a6-8327-4f8c-80a5-d73e9de08973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723941440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2723941440
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4199981994
Short name T458
Test name
Test status
Simulation time 1893510163 ps
CPU time 1.55 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:02:53 PM PDT 24
Peak memory 199124 kb
Host smart-6841731a-e01e-40d3-b9db-c1e0e6b644c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199981994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4199981994
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3606073160
Short name T1069
Test name
Test status
Simulation time 115685219058 ps
CPU time 84.96 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:04:18 PM PDT 24
Peak memory 200724 kb
Host smart-8cdf961c-88de-4811-91b4-ee705aa3000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606073160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3606073160
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.838152449
Short name T584
Test name
Test status
Simulation time 7606954020 ps
CPU time 463.05 seconds
Started May 16 01:02:44 PM PDT 24
Finished May 16 01:10:37 PM PDT 24
Peak memory 200416 kb
Host smart-93e09986-8704-410a-8fd3-3da2cd91950c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838152449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.838152449
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.181182309
Short name T895
Test name
Test status
Simulation time 4986969744 ps
CPU time 42.96 seconds
Started May 16 01:02:50 PM PDT 24
Finished May 16 01:03:42 PM PDT 24
Peak memory 199660 kb
Host smart-c657e923-73f3-46d6-88a3-a754908d113f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181182309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.181182309
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1164965390
Short name T885
Test name
Test status
Simulation time 81204241348 ps
CPU time 159.7 seconds
Started May 16 01:02:46 PM PDT 24
Finished May 16 01:05:35 PM PDT 24
Peak memory 200480 kb
Host smart-236bb374-00b6-46c8-a804-88fd66ecd802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164965390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1164965390
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.163302733
Short name T791
Test name
Test status
Simulation time 38513156955 ps
CPU time 39.2 seconds
Started May 16 01:02:46 PM PDT 24
Finished May 16 01:03:35 PM PDT 24
Peak memory 196764 kb
Host smart-fb023b5b-d18c-43bb-aa56-b3a0d4e7a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163302733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.163302733
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2536417797
Short name T1130
Test name
Test status
Simulation time 882813664 ps
CPU time 1.89 seconds
Started May 16 01:02:37 PM PDT 24
Finished May 16 01:02:50 PM PDT 24
Peak memory 200320 kb
Host smart-5cf53d1d-1296-4a9e-8c6d-a58dcba177e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536417797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2536417797
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2653912965
Short name T494
Test name
Test status
Simulation time 314783612875 ps
CPU time 301.66 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:07:54 PM PDT 24
Peak memory 200420 kb
Host smart-503c6bdc-e842-4d5b-a746-99a6965e4fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653912965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2653912965
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3913109557
Short name T774
Test name
Test status
Simulation time 96560169281 ps
CPU time 1660.44 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:30:34 PM PDT 24
Peak memory 225440 kb
Host smart-7cbab996-8875-44fc-bbff-e5ebd16d57ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913109557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3913109557
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3140789991
Short name T801
Test name
Test status
Simulation time 845997860 ps
CPU time 2.56 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:02:54 PM PDT 24
Peak memory 198896 kb
Host smart-9533cd8c-82a2-4c48-a290-1bab1351a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140789991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3140789991
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1703528792
Short name T658
Test name
Test status
Simulation time 96726581863 ps
CPU time 42.88 seconds
Started May 16 01:02:33 PM PDT 24
Finished May 16 01:03:28 PM PDT 24
Peak memory 200436 kb
Host smart-8dbeafd9-6f88-4b76-b470-8344f79d781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703528792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1703528792
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1578214252
Short name T336
Test name
Test status
Simulation time 29870781 ps
CPU time 0.53 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:02:53 PM PDT 24
Peak memory 195364 kb
Host smart-b48a2ecd-ff28-4ade-8ae1-36d8b5be3e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578214252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1578214252
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1750737846
Short name T1114
Test name
Test status
Simulation time 141792615444 ps
CPU time 148.82 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:05:20 PM PDT 24
Peak memory 200420 kb
Host smart-4dbc36cb-7330-40c5-879d-bc81450c3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750737846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1750737846
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2760745997
Short name T429
Test name
Test status
Simulation time 57091100362 ps
CPU time 126.95 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:04:58 PM PDT 24
Peak memory 200476 kb
Host smart-e5e51a0d-4a12-4423-abe0-63fb9caed796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760745997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2760745997
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3354092067
Short name T489
Test name
Test status
Simulation time 105189170699 ps
CPU time 34.62 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 200500 kb
Host smart-3095d66d-92d4-4915-9ac8-60639c474b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354092067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3354092067
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1465719018
Short name T119
Test name
Test status
Simulation time 44469956809 ps
CPU time 62.3 seconds
Started May 16 01:02:46 PM PDT 24
Finished May 16 01:03:58 PM PDT 24
Peak memory 200476 kb
Host smart-839df742-b5be-491a-8857-d3a6f741e0ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465719018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1465719018
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.468840746
Short name T263
Test name
Test status
Simulation time 159748559989 ps
CPU time 1573.59 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:29:08 PM PDT 24
Peak memory 200432 kb
Host smart-9c247345-4949-4598-adec-e68bbdc5b440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468840746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.468840746
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2398894245
Short name T596
Test name
Test status
Simulation time 8740202063 ps
CPU time 22.58 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:03:15 PM PDT 24
Peak memory 199504 kb
Host smart-cce1609f-090c-4249-8e22-c93a9bb96087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398894245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2398894245
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2657414721
Short name T1046
Test name
Test status
Simulation time 65158490802 ps
CPU time 118.43 seconds
Started May 16 01:02:44 PM PDT 24
Finished May 16 01:04:52 PM PDT 24
Peak memory 200708 kb
Host smart-24da447e-3466-4233-ac1c-6ff6966514a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657414721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2657414721
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3406959343
Short name T275
Test name
Test status
Simulation time 4312022996 ps
CPU time 131.71 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:05:04 PM PDT 24
Peak memory 200508 kb
Host smart-47a58cfb-dd60-4d83-b801-f21267cd4204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406959343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3406959343
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2106261672
Short name T356
Test name
Test status
Simulation time 4197498292 ps
CPU time 17.09 seconds
Started May 16 01:02:46 PM PDT 24
Finished May 16 01:03:13 PM PDT 24
Peak memory 199428 kb
Host smart-764c94c2-74d5-447f-beb5-92281e45e550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106261672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2106261672
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2072435112
Short name T524
Test name
Test status
Simulation time 147653185576 ps
CPU time 134.93 seconds
Started May 16 01:02:46 PM PDT 24
Finished May 16 01:05:10 PM PDT 24
Peak memory 200456 kb
Host smart-917a42fd-b8a8-484b-ae2a-eacdf57fa983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072435112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2072435112
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.36271998
Short name T569
Test name
Test status
Simulation time 5940994785 ps
CPU time 2.33 seconds
Started May 16 01:02:44 PM PDT 24
Finished May 16 01:02:55 PM PDT 24
Peak memory 196520 kb
Host smart-9d098317-c1b6-46ae-8290-0f0c0a3157f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36271998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.36271998
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2000556568
Short name T305
Test name
Test status
Simulation time 5307239817 ps
CPU time 26.24 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:03:23 PM PDT 24
Peak memory 200148 kb
Host smart-ba493394-d087-47d0-87b6-b789b7123bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000556568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2000556568
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.199022487
Short name T487
Test name
Test status
Simulation time 144440183645 ps
CPU time 190.17 seconds
Started May 16 01:02:47 PM PDT 24
Finished May 16 01:06:06 PM PDT 24
Peak memory 200476 kb
Host smart-7578cdba-1b17-4150-9771-91217034df2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199022487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.199022487
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3658913542
Short name T764
Test name
Test status
Simulation time 252881103508 ps
CPU time 517.59 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:11:32 PM PDT 24
Peak memory 216636 kb
Host smart-ace6f609-5469-4991-8817-10b31491220d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658913542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3658913542
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1657663082
Short name T332
Test name
Test status
Simulation time 898683272 ps
CPU time 3.01 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:02:57 PM PDT 24
Peak memory 198836 kb
Host smart-f1920bfa-db78-4ab6-bc41-18da6dab2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657663082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1657663082
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2043573368
Short name T679
Test name
Test status
Simulation time 70422346462 ps
CPU time 54.28 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:03:49 PM PDT 24
Peak memory 200276 kb
Host smart-82859ad8-dc9a-49f5-ad53-7d46ad04cdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043573368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2043573368
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2324020174
Short name T973
Test name
Test status
Simulation time 45502720 ps
CPU time 0.58 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:02:55 PM PDT 24
Peak memory 195864 kb
Host smart-acbbee5f-c14c-4cdc-aa28-779243f94640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324020174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2324020174
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1052232923
Short name T436
Test name
Test status
Simulation time 3431059245 ps
CPU time 6.7 seconds
Started May 16 01:02:50 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 199184 kb
Host smart-59bd0055-1136-4ebc-979f-07d4c16267ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052232923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1052232923
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2261039803
Short name T655
Test name
Test status
Simulation time 276321531751 ps
CPU time 140.46 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:05:15 PM PDT 24
Peak memory 200412 kb
Host smart-83f5492b-9c57-4ddb-a9b3-84d8d310bb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261039803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2261039803
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1987118769
Short name T999
Test name
Test status
Simulation time 42808498492 ps
CPU time 38.15 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:03:33 PM PDT 24
Peak memory 200440 kb
Host smart-5231032f-2054-4b03-a881-ed73e82923d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987118769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1987118769
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.812115130
Short name T983
Test name
Test status
Simulation time 8216572431 ps
CPU time 13.88 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:03:11 PM PDT 24
Peak memory 197108 kb
Host smart-e271c17e-c9b3-4c1e-ab37-c11a55502a27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812115130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.812115130
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3967303080
Short name T1086
Test name
Test status
Simulation time 91795069262 ps
CPU time 1018.97 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:19:54 PM PDT 24
Peak memory 200508 kb
Host smart-b499a293-7019-43d1-80c7-88774555a0d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967303080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3967303080
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.50147490
Short name T338
Test name
Test status
Simulation time 1557748536 ps
CPU time 1.94 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:02:54 PM PDT 24
Peak memory 196172 kb
Host smart-55498677-0ba2-4cf3-8aa7-8f6746297c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50147490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.50147490
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2400792686
Short name T550
Test name
Test status
Simulation time 91681640423 ps
CPU time 48.93 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:03:46 PM PDT 24
Peak memory 199392 kb
Host smart-b37a867d-27b3-4170-932e-fd80d56ad540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400792686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2400792686
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3706215292
Short name T498
Test name
Test status
Simulation time 17125494855 ps
CPU time 166.21 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:05:39 PM PDT 24
Peak memory 200480 kb
Host smart-b156650a-aa19-43d1-ad04-610b0007fb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706215292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3706215292
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3615072939
Short name T525
Test name
Test status
Simulation time 7414324419 ps
CPU time 33.88 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:03:31 PM PDT 24
Peak memory 198608 kb
Host smart-2447fe3b-5d87-4f63-ac82-485ae68de847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615072939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3615072939
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.757351644
Short name T1163
Test name
Test status
Simulation time 18844519301 ps
CPU time 37.98 seconds
Started May 16 01:02:41 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 200400 kb
Host smart-1898acd8-9ed0-43ab-a8ef-d5b02d91b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757351644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.757351644
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.932205786
Short name T398
Test name
Test status
Simulation time 4611857620 ps
CPU time 3.21 seconds
Started May 16 01:02:49 PM PDT 24
Finished May 16 01:03:01 PM PDT 24
Peak memory 196496 kb
Host smart-fc69bea7-6ab8-4888-8001-13833b981e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932205786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.932205786
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2856595651
Short name T528
Test name
Test status
Simulation time 459029284 ps
CPU time 1.74 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:02:56 PM PDT 24
Peak memory 199012 kb
Host smart-b11ba34e-f4ab-4286-b515-f7e4c6bd6c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856595651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2856595651
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1391129571
Short name T688
Test name
Test status
Simulation time 228207314192 ps
CPU time 836.38 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:16:51 PM PDT 24
Peak memory 216772 kb
Host smart-3e1e6b68-3e36-40df-92e4-90e90ebc3e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391129571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1391129571
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1136166562
Short name T537
Test name
Test status
Simulation time 198605397228 ps
CPU time 619.1 seconds
Started May 16 01:02:47 PM PDT 24
Finished May 16 01:13:15 PM PDT 24
Peak memory 225432 kb
Host smart-50278082-9558-4df3-bf89-2c229138dd75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136166562 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1136166562
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2149075893
Short name T424
Test name
Test status
Simulation time 8722523282 ps
CPU time 3.65 seconds
Started May 16 01:02:50 PM PDT 24
Finished May 16 01:03:02 PM PDT 24
Peak memory 200496 kb
Host smart-3d2724aa-13af-4e3e-b13e-bd5eb4993f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149075893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2149075893
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2216007489
Short name T553
Test name
Test status
Simulation time 65097282156 ps
CPU time 24.23 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:03:17 PM PDT 24
Peak memory 200368 kb
Host smart-6d02b2ec-e33e-4755-8cc8-915a6d1dd43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216007489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2216007489
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3702131846
Short name T1158
Test name
Test status
Simulation time 114029055 ps
CPU time 0.54 seconds
Started May 16 01:02:53 PM PDT 24
Finished May 16 01:03:02 PM PDT 24
Peak memory 195864 kb
Host smart-1ffc2c87-794f-4585-bb59-240c8abe8a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702131846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3702131846
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1618182959
Short name T350
Test name
Test status
Simulation time 160307056072 ps
CPU time 486.97 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:10:59 PM PDT 24
Peak memory 200376 kb
Host smart-42200c91-a58b-4d85-b70d-ec1ff753cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618182959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1618182959
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1985530400
Short name T146
Test name
Test status
Simulation time 21514796690 ps
CPU time 13.73 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 200456 kb
Host smart-de0fd0a9-dcbc-4905-8d16-126b02bf8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985530400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1985530400
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.710592100
Short name T226
Test name
Test status
Simulation time 64059429985 ps
CPU time 98.33 seconds
Started May 16 01:02:43 PM PDT 24
Finished May 16 01:04:31 PM PDT 24
Peak memory 200580 kb
Host smart-afba0df7-48e4-4f46-b487-b5cfecdd6760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710592100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.710592100
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.520576451
Short name T902
Test name
Test status
Simulation time 25460609399 ps
CPU time 4.74 seconds
Started May 16 01:02:44 PM PDT 24
Finished May 16 01:02:58 PM PDT 24
Peak memory 199928 kb
Host smart-480d0b06-9ec6-4d96-86c7-d9abe607acbf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520576451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.520576451
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3502777423
Short name T1003
Test name
Test status
Simulation time 86510822560 ps
CPU time 413.93 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:09:56 PM PDT 24
Peak memory 200432 kb
Host smart-0fa83bdf-fe47-4376-9c80-3ef57f0c2a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502777423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3502777423
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2862205740
Short name T573
Test name
Test status
Simulation time 6160069142 ps
CPU time 15.57 seconds
Started May 16 01:02:57 PM PDT 24
Finished May 16 01:03:19 PM PDT 24
Peak memory 200484 kb
Host smart-4b724ce5-c9b4-4dcc-8d10-cb28f33f787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862205740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2862205740
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1906896338
Short name T421
Test name
Test status
Simulation time 42007869192 ps
CPU time 181.58 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:06:04 PM PDT 24
Peak memory 216100 kb
Host smart-edd72e4d-6c02-425b-aa76-d935e5376cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906896338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1906896338
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1490505835
Short name T681
Test name
Test status
Simulation time 10704566953 ps
CPU time 457.46 seconds
Started May 16 01:02:55 PM PDT 24
Finished May 16 01:10:40 PM PDT 24
Peak memory 200520 kb
Host smart-ed764c14-727b-4833-a5c6-284c55f938d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490505835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1490505835
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2484586902
Short name T474
Test name
Test status
Simulation time 5810602359 ps
CPU time 9.12 seconds
Started May 16 01:02:45 PM PDT 24
Finished May 16 01:03:03 PM PDT 24
Peak memory 199244 kb
Host smart-6dc679e5-a9d9-4346-aa29-40b45648820d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484586902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2484586902
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.4063776208
Short name T663
Test name
Test status
Simulation time 12881932750 ps
CPU time 21.08 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:03:32 PM PDT 24
Peak memory 198820 kb
Host smart-09e2c65f-cfff-4680-943a-7b7832ea4cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063776208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.4063776208
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3929189272
Short name T1119
Test name
Test status
Simulation time 3288810601 ps
CPU time 5.19 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:03:16 PM PDT 24
Peak memory 196704 kb
Host smart-808e7bac-10f9-429e-a772-8eea71ad47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929189272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3929189272
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2429675785
Short name T1077
Test name
Test status
Simulation time 11573256558 ps
CPU time 28.8 seconds
Started May 16 01:02:42 PM PDT 24
Finished May 16 01:03:21 PM PDT 24
Peak memory 200420 kb
Host smart-931def42-4539-453e-8183-83b0bfbd8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429675785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2429675785
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3319716300
Short name T674
Test name
Test status
Simulation time 215513105398 ps
CPU time 363.34 seconds
Started May 16 01:02:52 PM PDT 24
Finished May 16 01:09:04 PM PDT 24
Peak memory 200444 kb
Host smart-98fd6198-806e-429d-ab04-4629d2b85b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319716300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3319716300
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1921019530
Short name T974
Test name
Test status
Simulation time 105756856957 ps
CPU time 495.71 seconds
Started May 16 01:02:53 PM PDT 24
Finished May 16 01:11:17 PM PDT 24
Peak memory 227276 kb
Host smart-dd679b34-926e-4564-95dc-47087dd7df7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921019530 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1921019530
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1340164107
Short name T564
Test name
Test status
Simulation time 459783269 ps
CPU time 1.76 seconds
Started May 16 01:02:56 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 199044 kb
Host smart-effce865-0844-4011-9c3b-437af5512ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340164107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1340164107
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1236972609
Short name T286
Test name
Test status
Simulation time 21822026156 ps
CPU time 45.22 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:03:42 PM PDT 24
Peak memory 200392 kb
Host smart-1ef92700-c447-4fb6-911e-bc7835823932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236972609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1236972609
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3414352590
Short name T361
Test name
Test status
Simulation time 48293692 ps
CPU time 0.56 seconds
Started May 16 01:02:51 PM PDT 24
Finished May 16 01:03:01 PM PDT 24
Peak memory 195856 kb
Host smart-efa54f43-488c-4c65-aa5e-ff1f4adbf191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414352590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3414352590
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1667942266
Short name T39
Test name
Test status
Simulation time 35526772180 ps
CPU time 29.74 seconds
Started May 16 01:03:04 PM PDT 24
Finished May 16 01:03:41 PM PDT 24
Peak memory 200412 kb
Host smart-9ba253e6-b142-4551-8310-7526ad48d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667942266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1667942266
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.228268008
Short name T750
Test name
Test status
Simulation time 88638325540 ps
CPU time 165.97 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:05:48 PM PDT 24
Peak memory 200512 kb
Host smart-390cc07f-3dc5-465f-aca1-0775af5598ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228268008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.228268008
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2485780642
Short name T253
Test name
Test status
Simulation time 34107686657 ps
CPU time 29.26 seconds
Started May 16 01:02:52 PM PDT 24
Finished May 16 01:03:30 PM PDT 24
Peak memory 200432 kb
Host smart-be48a4e3-1cc3-45aa-bb3d-439e77fccf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485780642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2485780642
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1669650871
Short name T599
Test name
Test status
Simulation time 70264886995 ps
CPU time 128.66 seconds
Started May 16 01:02:55 PM PDT 24
Finished May 16 01:05:11 PM PDT 24
Peak memory 200460 kb
Host smart-4116caa3-c673-43ed-a26f-f4a1f5f8a494
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669650871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1669650871
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.914273083
Short name T379
Test name
Test status
Simulation time 38781881270 ps
CPU time 342.36 seconds
Started May 16 01:02:56 PM PDT 24
Finished May 16 01:08:46 PM PDT 24
Peak memory 200424 kb
Host smart-3ff937be-5157-4f87-9359-35e8f72b7c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914273083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.914273083
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1961930665
Short name T800
Test name
Test status
Simulation time 10300784098 ps
CPU time 7.66 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:03:18 PM PDT 24
Peak memory 199992 kb
Host smart-f2a2e0b3-8edf-4ce1-b169-cab08e7966ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961930665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1961930665
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1348148072
Short name T1031
Test name
Test status
Simulation time 53856649641 ps
CPU time 100.28 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:04:51 PM PDT 24
Peak memory 200676 kb
Host smart-92d30cc9-bfd2-49b7-9fc7-cececc2e6c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348148072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1348148072
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2705053846
Short name T1043
Test name
Test status
Simulation time 12884539241 ps
CPU time 537.04 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:11:59 PM PDT 24
Peak memory 200512 kb
Host smart-2fb4c2c1-2fe8-4b81-84a0-ef4d1e181be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705053846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2705053846
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4191596090
Short name T611
Test name
Test status
Simulation time 4378156546 ps
CPU time 2.93 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:03:05 PM PDT 24
Peak memory 199228 kb
Host smart-e04b3dcb-48f3-4804-8aa0-d942586e4efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191596090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4191596090
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.379099960
Short name T602
Test name
Test status
Simulation time 98692470889 ps
CPU time 12.75 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:03:23 PM PDT 24
Peak memory 200356 kb
Host smart-b71a25ff-0434-4137-8ea2-4336a2f8777a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379099960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.379099960
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.87923073
Short name T820
Test name
Test status
Simulation time 33878578873 ps
CPU time 12.55 seconds
Started May 16 01:02:53 PM PDT 24
Finished May 16 01:03:14 PM PDT 24
Peak memory 196784 kb
Host smart-00b3c913-e706-44ca-9001-11f2a195c38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87923073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.87923073
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.477520053
Short name T483
Test name
Test status
Simulation time 291904232 ps
CPU time 1.58 seconds
Started May 16 01:02:55 PM PDT 24
Finished May 16 01:03:04 PM PDT 24
Peak memory 198720 kb
Host smart-3c99a6fa-5b33-4ae2-a6d1-6946f34736ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477520053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.477520053
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.4259921947
Short name T1156
Test name
Test status
Simulation time 243195064059 ps
CPU time 456.74 seconds
Started May 16 01:02:57 PM PDT 24
Finished May 16 01:10:41 PM PDT 24
Peak memory 200528 kb
Host smart-472655cc-bfde-4f0c-936d-0946fd3d49b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259921947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.4259921947
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1088962010
Short name T770
Test name
Test status
Simulation time 93909696626 ps
CPU time 420.46 seconds
Started May 16 01:02:57 PM PDT 24
Finished May 16 01:10:04 PM PDT 24
Peak memory 214876 kb
Host smart-06241aaf-d408-4f19-839e-54bc84ca4f5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088962010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1088962010
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.151244072
Short name T412
Test name
Test status
Simulation time 1528826689 ps
CPU time 1.37 seconds
Started May 16 01:03:04 PM PDT 24
Finished May 16 01:03:13 PM PDT 24
Peak memory 199016 kb
Host smart-d707aa5e-c321-4b5d-980b-0b3f84fc0d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151244072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.151244072
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1965121567
Short name T399
Test name
Test status
Simulation time 16239554905 ps
CPU time 17.51 seconds
Started May 16 01:02:51 PM PDT 24
Finished May 16 01:03:18 PM PDT 24
Peak memory 200160 kb
Host smart-b7ec5c1a-461a-45d5-8b33-53615edd2ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965121567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1965121567
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4106080581
Short name T972
Test name
Test status
Simulation time 24585371 ps
CPU time 0.54 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:03:03 PM PDT 24
Peak memory 194812 kb
Host smart-77250f30-d972-41ca-aea7-b95d865a1868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106080581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4106080581
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3167551484
Short name T447
Test name
Test status
Simulation time 172065899509 ps
CPU time 162.86 seconds
Started May 16 01:02:57 PM PDT 24
Finished May 16 01:05:47 PM PDT 24
Peak memory 200472 kb
Host smart-4b70d653-ce6c-470e-a751-22fe1c764fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167551484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3167551484
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1407376328
Short name T1132
Test name
Test status
Simulation time 45318712898 ps
CPU time 76.18 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:04:18 PM PDT 24
Peak memory 200364 kb
Host smart-6554c9f1-4bee-49e2-b1f7-fa914c06fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407376328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1407376328
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2233309611
Short name T556
Test name
Test status
Simulation time 82542193297 ps
CPU time 69.57 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:04:12 PM PDT 24
Peak memory 200404 kb
Host smart-2b9ed50e-4915-4fe6-8a13-63f70d319f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233309611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2233309611
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2018130436
Short name T1018
Test name
Test status
Simulation time 13632394108 ps
CPU time 3.03 seconds
Started May 16 01:03:04 PM PDT 24
Finished May 16 01:03:14 PM PDT 24
Peak memory 197500 kb
Host smart-d012e2f1-5180-4974-ad6e-66deb282bea0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018130436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2018130436
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2414285826
Short name T465
Test name
Test status
Simulation time 118859763593 ps
CPU time 678.92 seconds
Started May 16 01:03:02 PM PDT 24
Finished May 16 01:14:29 PM PDT 24
Peak memory 200456 kb
Host smart-8e26b8d2-7c99-4145-99a0-9d0971b437e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414285826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2414285826
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.435852299
Short name T922
Test name
Test status
Simulation time 3630271106 ps
CPU time 2.93 seconds
Started May 16 01:02:56 PM PDT 24
Finished May 16 01:03:06 PM PDT 24
Peak memory 200428 kb
Host smart-9e839e89-de2b-4432-b42b-53a2685181b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435852299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.435852299
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2872678448
Short name T488
Test name
Test status
Simulation time 30498309897 ps
CPU time 13.99 seconds
Started May 16 01:03:04 PM PDT 24
Finished May 16 01:03:25 PM PDT 24
Peak memory 199212 kb
Host smart-b7ce3fff-9037-481e-a7ef-b8490c398e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872678448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2872678448
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.4203905288
Short name T266
Test name
Test status
Simulation time 9810913410 ps
CPU time 86.92 seconds
Started May 16 01:02:55 PM PDT 24
Finished May 16 01:04:30 PM PDT 24
Peak memory 200456 kb
Host smart-c32f2b26-d316-4387-ae78-7affb0792806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203905288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4203905288
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1611244844
Short name T536
Test name
Test status
Simulation time 7367714699 ps
CPU time 64.88 seconds
Started May 16 01:02:52 PM PDT 24
Finished May 16 01:04:06 PM PDT 24
Peak memory 198680 kb
Host smart-6731bda3-6f02-44ba-a569-91cb0bcfdcf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611244844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1611244844
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.25862841
Short name T760
Test name
Test status
Simulation time 54675707604 ps
CPU time 26.16 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 200508 kb
Host smart-c49d7ff4-9b67-427c-b515-9e25e19e6862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25862841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.25862841
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3123319401
Short name T1091
Test name
Test status
Simulation time 4140089039 ps
CPU time 7.07 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:03:09 PM PDT 24
Peak memory 196464 kb
Host smart-1705add7-c3f3-49db-9a97-fba9953ab1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123319401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3123319401
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1507404095
Short name T832
Test name
Test status
Simulation time 511245962 ps
CPU time 1.16 seconds
Started May 16 01:02:53 PM PDT 24
Finished May 16 01:03:02 PM PDT 24
Peak memory 200368 kb
Host smart-e2de0cf2-126f-4491-8074-07b054d3a233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507404095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1507404095
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3760074578
Short name T1017
Test name
Test status
Simulation time 170456929011 ps
CPU time 209.11 seconds
Started May 16 01:02:56 PM PDT 24
Finished May 16 01:06:32 PM PDT 24
Peak memory 200752 kb
Host smart-df7da946-9ce7-4fb3-ab2c-34d42b1901a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760074578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3760074578
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1983183581
Short name T844
Test name
Test status
Simulation time 110995826867 ps
CPU time 1136.01 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:22:06 PM PDT 24
Peak memory 216856 kb
Host smart-e98811b5-d7c9-43b3-aa94-395f19f14c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983183581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1983183581
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2213941760
Short name T549
Test name
Test status
Simulation time 6024194849 ps
CPU time 41.52 seconds
Started May 16 01:02:48 PM PDT 24
Finished May 16 01:03:39 PM PDT 24
Peak memory 200436 kb
Host smart-8f9de1f8-7d5d-4473-84a4-6552e749c49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213941760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2213941760
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2750337321
Short name T257
Test name
Test status
Simulation time 154929939354 ps
CPU time 252.84 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:07:15 PM PDT 24
Peak memory 200416 kb
Host smart-fee038b1-c0dc-4706-8386-7c49ad947186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750337321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2750337321
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.500269074
Short name T710
Test name
Test status
Simulation time 16521951 ps
CPU time 0.57 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:03:15 PM PDT 24
Peak memory 195816 kb
Host smart-b05f6c6e-47b2-4536-bc4a-c4696ba80c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500269074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.500269074
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.473677558
Short name T448
Test name
Test status
Simulation time 149422971651 ps
CPU time 32.68 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:03:35 PM PDT 24
Peak memory 200412 kb
Host smart-a3376b2b-5e17-4a67-bccb-4cc242b7d6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473677558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.473677558
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2932597840
Short name T971
Test name
Test status
Simulation time 277757517783 ps
CPU time 229.45 seconds
Started May 16 01:02:55 PM PDT 24
Finished May 16 01:06:52 PM PDT 24
Peak memory 200496 kb
Host smart-51564c42-0bf6-46c6-a712-b7e34adffe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932597840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2932597840
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2773355705
Short name T428
Test name
Test status
Simulation time 363786956613 ps
CPU time 41.53 seconds
Started May 16 01:02:53 PM PDT 24
Finished May 16 01:03:43 PM PDT 24
Peak memory 200400 kb
Host smart-c665b73f-76d2-4377-ba8b-f2bd5d82c559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773355705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2773355705
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.456165137
Short name T446
Test name
Test status
Simulation time 37895746016 ps
CPU time 12.91 seconds
Started May 16 01:03:03 PM PDT 24
Finished May 16 01:03:24 PM PDT 24
Peak memory 200444 kb
Host smart-25b77160-078d-4674-98ed-b002d4c50917
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456165137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.456165137
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3216536624
Short name T585
Test name
Test status
Simulation time 80796921717 ps
CPU time 466.69 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:11:02 PM PDT 24
Peak memory 200528 kb
Host smart-832f209b-6402-4cf3-91ff-5024c298c081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216536624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3216536624
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.714878272
Short name T776
Test name
Test status
Simulation time 938936321 ps
CPU time 2.21 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:03:16 PM PDT 24
Peak memory 195944 kb
Host smart-f7c2bd83-fa3e-4402-be47-0e634241e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714878272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.714878272
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4261444641
Short name T281
Test name
Test status
Simulation time 90721330150 ps
CPU time 113.12 seconds
Started May 16 01:02:55 PM PDT 24
Finished May 16 01:04:56 PM PDT 24
Peak memory 200896 kb
Host smart-0d45478b-edae-4ee9-8b2e-c771318120bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261444641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4261444641
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1867483634
Short name T995
Test name
Test status
Simulation time 20796797007 ps
CPU time 73.91 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200492 kb
Host smart-950476a4-7292-409a-9c90-225004f3a594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867483634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1867483634
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3227812908
Short name T945
Test name
Test status
Simulation time 3576004864 ps
CPU time 24.56 seconds
Started May 16 01:02:57 PM PDT 24
Finished May 16 01:03:28 PM PDT 24
Peak memory 199320 kb
Host smart-4742e1d2-8ee2-45c7-a2b5-05fcb0e0a51e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227812908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3227812908
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1891149028
Short name T1175
Test name
Test status
Simulation time 157956866563 ps
CPU time 45.33 seconds
Started May 16 01:02:54 PM PDT 24
Finished May 16 01:03:48 PM PDT 24
Peak memory 200464 kb
Host smart-bdd36ff9-594c-4d94-8dc0-eb260981eb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891149028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1891149028
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1314753188
Short name T10
Test name
Test status
Simulation time 5775771432 ps
CPU time 3.04 seconds
Started May 16 01:02:56 PM PDT 24
Finished May 16 01:03:06 PM PDT 24
Peak memory 196480 kb
Host smart-8f5a3fd8-ffb7-4692-843e-796ead3090d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314753188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1314753188
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.120336649
Short name T729
Test name
Test status
Simulation time 693252732 ps
CPU time 3.03 seconds
Started May 16 01:02:51 PM PDT 24
Finished May 16 01:03:03 PM PDT 24
Peak memory 199376 kb
Host smart-a02aac6b-4e31-41de-b274-1e16e2f56716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120336649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.120336649
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3915121086
Short name T792
Test name
Test status
Simulation time 82261140702 ps
CPU time 19.46 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:33 PM PDT 24
Peak memory 200440 kb
Host smart-7e654462-bc94-4447-a344-09dc43aed984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915121086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3915121086
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.415170908
Short name T877
Test name
Test status
Simulation time 71510949565 ps
CPU time 881.04 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:17:56 PM PDT 24
Peak memory 215784 kb
Host smart-0c14d7da-e9b0-46c6-ac5a-b6e60bd97162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415170908 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.415170908
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1531199826
Short name T720
Test name
Test status
Simulation time 6831561229 ps
CPU time 14.12 seconds
Started May 16 01:02:53 PM PDT 24
Finished May 16 01:03:16 PM PDT 24
Peak memory 200448 kb
Host smart-038e470e-2186-4658-9a43-8b51e32c5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531199826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1531199826
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2624334087
Short name T439
Test name
Test status
Simulation time 99724603255 ps
CPU time 42.55 seconds
Started May 16 01:03:04 PM PDT 24
Finished May 16 01:03:54 PM PDT 24
Peak memory 200388 kb
Host smart-ca94c2a4-b75c-42a3-86fc-db7cfd7859fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624334087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2624334087
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.796424625
Short name T1029
Test name
Test status
Simulation time 14875766 ps
CPU time 0.57 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:14 PM PDT 24
Peak memory 195768 kb
Host smart-1be81859-9ea3-4f35-8a9e-3d55dead650d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796424625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.796424625
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3884647384
Short name T794
Test name
Test status
Simulation time 14015630113 ps
CPU time 25.8 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:03:41 PM PDT 24
Peak memory 200496 kb
Host smart-4384fe5c-b859-4776-9d8e-5ca472d51d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884647384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3884647384
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.757507847
Short name T964
Test name
Test status
Simulation time 121082250096 ps
CPU time 95.71 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:04:49 PM PDT 24
Peak memory 200492 kb
Host smart-6586b96a-b370-4b3e-8705-d34575be96a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757507847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.757507847
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.163389228
Short name T910
Test name
Test status
Simulation time 23808514889 ps
CPU time 38.4 seconds
Started May 16 01:03:11 PM PDT 24
Finished May 16 01:03:55 PM PDT 24
Peak memory 200464 kb
Host smart-5b8d927f-4833-490d-91ab-1a90bd83caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163389228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.163389228
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2943626796
Short name T373
Test name
Test status
Simulation time 49438988040 ps
CPU time 24.08 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:03:39 PM PDT 24
Peak memory 200448 kb
Host smart-64122586-37d0-4fb2-882b-a4aa79bbd0f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943626796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2943626796
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.367300150
Short name T438
Test name
Test status
Simulation time 45821387606 ps
CPU time 325.92 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:08:40 PM PDT 24
Peak memory 200448 kb
Host smart-523eac49-3674-46d1-830a-bbf6a7068b9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367300150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.367300150
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.818753663
Short name T347
Test name
Test status
Simulation time 8413063162 ps
CPU time 7.77 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:03:22 PM PDT 24
Peak memory 199212 kb
Host smart-3ada6ecb-130e-4497-b076-7d4993f1acd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818753663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.818753663
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3635023514
Short name T370
Test name
Test status
Simulation time 26409699566 ps
CPU time 10.82 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:03:25 PM PDT 24
Peak memory 200672 kb
Host smart-ed175826-b553-4be1-a033-fe06a5bf3ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635023514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3635023514
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3058612779
Short name T1000
Test name
Test status
Simulation time 21337055334 ps
CPU time 334.96 seconds
Started May 16 01:03:10 PM PDT 24
Finished May 16 01:08:51 PM PDT 24
Peak memory 200480 kb
Host smart-90770878-9fe8-47fc-ae2b-0d5f74e64f79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058612779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3058612779
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2374504449
Short name T368
Test name
Test status
Simulation time 2680771773 ps
CPU time 1.54 seconds
Started May 16 01:03:06 PM PDT 24
Finished May 16 01:03:14 PM PDT 24
Peak memory 199308 kb
Host smart-48b18a95-68ab-41b5-9e28-0195ffbd0688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374504449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2374504449
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3112174681
Short name T620
Test name
Test status
Simulation time 280679324572 ps
CPU time 77.88 seconds
Started May 16 01:03:10 PM PDT 24
Finished May 16 01:04:33 PM PDT 24
Peak memory 200444 kb
Host smart-6cd72790-fa4f-4450-ae2d-dc366e3ea2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112174681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3112174681
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4283844720
Short name T628
Test name
Test status
Simulation time 5476538310 ps
CPU time 10 seconds
Started May 16 01:03:10 PM PDT 24
Finished May 16 01:03:25 PM PDT 24
Peak memory 196452 kb
Host smart-a1cbb229-888b-46a6-8847-c43829e112d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283844720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4283844720
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.913032293
Short name T1139
Test name
Test status
Simulation time 916916996 ps
CPU time 2.16 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:03:16 PM PDT 24
Peak memory 198808 kb
Host smart-cd970008-fbd3-4765-baac-08c73f255ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913032293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.913032293
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1575886684
Short name T31
Test name
Test status
Simulation time 178716809652 ps
CPU time 306.45 seconds
Started May 16 01:03:08 PM PDT 24
Finished May 16 01:08:21 PM PDT 24
Peak memory 215432 kb
Host smart-551989cd-3b81-42af-ae11-7aa1294c8d74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575886684 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1575886684
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.442511053
Short name T308
Test name
Test status
Simulation time 6709807875 ps
CPU time 16.8 seconds
Started May 16 01:03:12 PM PDT 24
Finished May 16 01:03:34 PM PDT 24
Peak memory 199624 kb
Host smart-0d4fe3c4-e710-4c1c-9006-108823b97b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442511053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.442511053
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3806781637
Short name T1097
Test name
Test status
Simulation time 10352739989 ps
CPU time 18.89 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:32 PM PDT 24
Peak memory 200420 kb
Host smart-bec116c3-9b92-4569-9145-3a53015a984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806781637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3806781637
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.105691941
Short name T1065
Test name
Test status
Simulation time 36406812 ps
CPU time 0.55 seconds
Started May 16 01:03:21 PM PDT 24
Finished May 16 01:03:29 PM PDT 24
Peak memory 195816 kb
Host smart-e95ea2c3-c0d0-43cd-ab78-be62439d76fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105691941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.105691941
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.62358693
Short name T279
Test name
Test status
Simulation time 189325513869 ps
CPU time 393.67 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:09:47 PM PDT 24
Peak memory 200492 kb
Host smart-875b8173-fb60-4eca-b2d3-b47abef83281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62358693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.62358693
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2089783520
Short name T890
Test name
Test status
Simulation time 93186053612 ps
CPU time 127.32 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:05:22 PM PDT 24
Peak memory 200436 kb
Host smart-28cdc7de-030c-477d-8d47-677efed2e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089783520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2089783520
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.4041486043
Short name T741
Test name
Test status
Simulation time 108395539292 ps
CPU time 40.72 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:54 PM PDT 24
Peak memory 200424 kb
Host smart-4a357bbe-31fe-4aff-b451-a13eb40449fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041486043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4041486043
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1993105880
Short name T669
Test name
Test status
Simulation time 2542422672 ps
CPU time 4.37 seconds
Started May 16 01:03:06 PM PDT 24
Finished May 16 01:03:17 PM PDT 24
Peak memory 196292 kb
Host smart-4f792154-9fc1-4ea6-a42d-450929b155f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993105880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1993105880
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1600923291
Short name T1059
Test name
Test status
Simulation time 154540922199 ps
CPU time 495.47 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:11:46 PM PDT 24
Peak memory 200380 kb
Host smart-14b9b14b-f11d-4c09-b44d-19616ffcc6c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600923291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1600923291
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1757298743
Short name T935
Test name
Test status
Simulation time 5089037894 ps
CPU time 6.43 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:03:39 PM PDT 24
Peak memory 200412 kb
Host smart-26b6b444-cb2b-40ea-b48d-ba0d56d913cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757298743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1757298743
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1399412159
Short name T318
Test name
Test status
Simulation time 163087613917 ps
CPU time 72.24 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:04:28 PM PDT 24
Peak memory 199996 kb
Host smart-c9ed5957-c11e-4bf5-a3bc-d21c42c3fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399412159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1399412159
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3242656371
Short name T676
Test name
Test status
Simulation time 23307495463 ps
CPU time 85.13 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:04:58 PM PDT 24
Peak memory 200456 kb
Host smart-a76ed942-c845-4e83-820d-b48a6641cd80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242656371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3242656371
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.868489570
Short name T865
Test name
Test status
Simulation time 4410904075 ps
CPU time 8.94 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:22 PM PDT 24
Peak memory 199700 kb
Host smart-bc87e29b-d9eb-4c9d-b2b9-99aa0a89a59b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868489570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.868489570
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3502330241
Short name T754
Test name
Test status
Simulation time 61581072463 ps
CPU time 97.45 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:05:11 PM PDT 24
Peak memory 200432 kb
Host smart-61d81c2d-fd35-4fa5-af7a-a3a9f5eb22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502330241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3502330241
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1316333896
Short name T475
Test name
Test status
Simulation time 5564431351 ps
CPU time 9.91 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:23 PM PDT 24
Peak memory 196744 kb
Host smart-da0a37b9-4071-4b1b-a63a-8d8bd1e94e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316333896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1316333896
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3647610262
Short name T288
Test name
Test status
Simulation time 662221243 ps
CPU time 2.54 seconds
Started May 16 01:03:09 PM PDT 24
Finished May 16 01:03:18 PM PDT 24
Peak memory 199204 kb
Host smart-86836a62-74d6-4c62-ac25-e024f83c35a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647610262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3647610262
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.222951951
Short name T41
Test name
Test status
Simulation time 68323557162 ps
CPU time 621.61 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:13:52 PM PDT 24
Peak memory 216952 kb
Host smart-2aa3549b-563a-4347-892d-de286b44a0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222951951 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.222951951
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3730399773
Short name T432
Test name
Test status
Simulation time 802855585 ps
CPU time 1.53 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:03:28 PM PDT 24
Peak memory 198768 kb
Host smart-08ea9b75-6ab4-4504-8441-069cdb5d7d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730399773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3730399773
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2572907637
Short name T592
Test name
Test status
Simulation time 14508972940 ps
CPU time 12.39 seconds
Started May 16 01:03:07 PM PDT 24
Finished May 16 01:03:26 PM PDT 24
Peak memory 197660 kb
Host smart-701362e4-5c76-4491-a2f1-4f21f2a3efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572907637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2572907637
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1431009565
Short name T450
Test name
Test status
Simulation time 14696232 ps
CPU time 0.56 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:03:27 PM PDT 24
Peak memory 195844 kb
Host smart-7befc20f-12c3-42bc-916f-7c8636072569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431009565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1431009565
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3236418191
Short name T441
Test name
Test status
Simulation time 43922460505 ps
CPU time 36.64 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:04:09 PM PDT 24
Peak memory 200448 kb
Host smart-46e4ec98-3998-42a2-8f64-bacd1977fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236418191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3236418191
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.31291173
Short name T352
Test name
Test status
Simulation time 89097790331 ps
CPU time 32.77 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:04:04 PM PDT 24
Peak memory 200444 kb
Host smart-bd72f8fe-9686-46d5-8eb3-7fd7ad4e8a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31291173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.31291173
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1737916559
Short name T141
Test name
Test status
Simulation time 50636373162 ps
CPU time 21.38 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:03:51 PM PDT 24
Peak memory 200484 kb
Host smart-5679e40c-d986-42d2-aad6-2bf7f6322308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737916559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1737916559
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2275332161
Short name T784
Test name
Test status
Simulation time 15485098779 ps
CPU time 26.64 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:03:54 PM PDT 24
Peak memory 197464 kb
Host smart-470800ed-97d6-4d4a-92be-11b7d0c5b1e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275332161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2275332161
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1486083663
Short name T60
Test name
Test status
Simulation time 179569877035 ps
CPU time 576.74 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:13:07 PM PDT 24
Peak memory 200392 kb
Host smart-5c9d17dc-05a9-446a-87b7-5724a441e236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486083663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1486083663
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.170099490
Short name T1023
Test name
Test status
Simulation time 3921652624 ps
CPU time 7.78 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:03:35 PM PDT 24
Peak memory 198672 kb
Host smart-711eb8ca-46ef-4529-802d-f7751aced252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170099490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.170099490
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3676540331
Short name T591
Test name
Test status
Simulation time 19325868868 ps
CPU time 16.99 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:03:43 PM PDT 24
Peak memory 200488 kb
Host smart-bb9a5674-6ab1-46c7-a27c-94040b0f4c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676540331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3676540331
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.722965619
Short name T846
Test name
Test status
Simulation time 11081567933 ps
CPU time 35.11 seconds
Started May 16 01:03:21 PM PDT 24
Finished May 16 01:04:04 PM PDT 24
Peak memory 200580 kb
Host smart-2586a49a-327d-44cd-a19f-108f1290f366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722965619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.722965619
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1137947497
Short name T949
Test name
Test status
Simulation time 5745811811 ps
CPU time 3.21 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:03:35 PM PDT 24
Peak memory 200324 kb
Host smart-b00ee66d-aea7-46d8-863f-969ea6b8dae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137947497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1137947497
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.4080563230
Short name T504
Test name
Test status
Simulation time 33772098052 ps
CPU time 17.42 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:03:49 PM PDT 24
Peak memory 200416 kb
Host smart-25405744-1ce7-40bb-99ef-c132a5ecb5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080563230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.4080563230
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2118340139
Short name T788
Test name
Test status
Simulation time 3604392544 ps
CPU time 1.32 seconds
Started May 16 01:03:28 PM PDT 24
Finished May 16 01:03:39 PM PDT 24
Peak memory 196524 kb
Host smart-d7a410d4-b31c-4654-8a56-7cdad7278b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118340139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2118340139
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2329512001
Short name T1110
Test name
Test status
Simulation time 859639072 ps
CPU time 1.8 seconds
Started May 16 01:03:21 PM PDT 24
Finished May 16 01:03:30 PM PDT 24
Peak memory 199288 kb
Host smart-82e6c83d-3cd8-4c05-8a51-b86a9f228989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329512001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2329512001
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.4091324019
Short name T173
Test name
Test status
Simulation time 287859896911 ps
CPU time 239.91 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:07:25 PM PDT 24
Peak memory 208924 kb
Host smart-fe6f03a8-79b4-4e5c-9f41-dcb0f52e1817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091324019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.4091324019
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2246907981
Short name T839
Test name
Test status
Simulation time 21603680642 ps
CPU time 263.89 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:07:58 PM PDT 24
Peak memory 216172 kb
Host smart-50ac25a6-0e4c-47d0-8596-66316db25645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246907981 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2246907981
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1024363161
Short name T864
Test name
Test status
Simulation time 6735127423 ps
CPU time 19.83 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:03:52 PM PDT 24
Peak memory 200356 kb
Host smart-8e1fb43c-4a8c-4388-b8c7-2c5a718ddd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024363161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1024363161
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.662070473
Short name T303
Test name
Test status
Simulation time 69766306174 ps
CPU time 63.2 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:04:28 PM PDT 24
Peak memory 200404 kb
Host smart-1d9e90bd-95b8-4cae-97d1-e09783056319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662070473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.662070473
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3554298468
Short name T354
Test name
Test status
Simulation time 33399455 ps
CPU time 0.52 seconds
Started May 16 01:00:22 PM PDT 24
Finished May 16 01:01:01 PM PDT 24
Peak memory 194848 kb
Host smart-c745ae38-215a-4b42-8f0e-356933e55f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554298468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3554298468
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1309241364
Short name T385
Test name
Test status
Simulation time 87681160387 ps
CPU time 19.11 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:14 PM PDT 24
Peak memory 200448 kb
Host smart-0e692ab7-1fb4-4aa2-a022-e323c7f38422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309241364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1309241364
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1632242302
Short name T1162
Test name
Test status
Simulation time 75219804914 ps
CPU time 44.51 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:01:37 PM PDT 24
Peak memory 200504 kb
Host smart-1e63e038-23f2-4d9b-b40c-55d6b072529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632242302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1632242302
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.343996401
Short name T642
Test name
Test status
Simulation time 22497032268 ps
CPU time 9.93 seconds
Started May 16 01:00:18 PM PDT 24
Finished May 16 01:01:07 PM PDT 24
Peak memory 200488 kb
Host smart-fb0beae0-49f6-44e2-b864-b98444a942d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343996401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.343996401
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.562004877
Short name T351
Test name
Test status
Simulation time 100168254950 ps
CPU time 290.22 seconds
Started May 16 01:00:25 PM PDT 24
Finished May 16 01:05:52 PM PDT 24
Peak memory 200296 kb
Host smart-0d5d51f3-5a0c-4f3d-82ba-e471fbe1c343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562004877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.562004877
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2095697664
Short name T883
Test name
Test status
Simulation time 7494846470 ps
CPU time 13.16 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:01:13 PM PDT 24
Peak memory 200472 kb
Host smart-ebfecd03-a382-4f0c-8ced-643fa675e268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095697664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2095697664
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2188550493
Short name T1098
Test name
Test status
Simulation time 117450166282 ps
CPU time 168.66 seconds
Started May 16 01:00:09 PM PDT 24
Finished May 16 01:03:38 PM PDT 24
Peak memory 200108 kb
Host smart-3e7ba1f1-50d1-48b7-81dd-c048c6340496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188550493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2188550493
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.829443927
Short name T442
Test name
Test status
Simulation time 20469768877 ps
CPU time 1199.56 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:21:00 PM PDT 24
Peak memory 200508 kb
Host smart-2abd518d-4b93-415b-ac41-621d6c6380f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829443927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.829443927
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1047812394
Short name T836
Test name
Test status
Simulation time 2359726882 ps
CPU time 3.09 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:00:55 PM PDT 24
Peak memory 199408 kb
Host smart-870b2b9e-faf0-45a9-a0e6-170180074c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047812394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1047812394
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.675523307
Short name T1034
Test name
Test status
Simulation time 80904379964 ps
CPU time 61.14 seconds
Started May 16 01:00:12 PM PDT 24
Finished May 16 01:01:53 PM PDT 24
Peak memory 200408 kb
Host smart-6cf5a36a-7500-45b4-b42f-81b55328d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675523307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.675523307
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2411490854
Short name T1074
Test name
Test status
Simulation time 696282932 ps
CPU time 0.9 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:01:01 PM PDT 24
Peak memory 195820 kb
Host smart-cb5b68b5-5fd3-45ce-a08c-eaa3bada0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411490854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2411490854
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2852818751
Short name T900
Test name
Test status
Simulation time 841426958 ps
CPU time 4.24 seconds
Started May 16 01:00:14 PM PDT 24
Finished May 16 01:00:58 PM PDT 24
Peak memory 198780 kb
Host smart-fd4a2c50-257b-41c1-bad5-51953ce1cc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852818751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2852818751
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3006478490
Short name T851
Test name
Test status
Simulation time 156233955763 ps
CPU time 876.23 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:15:38 PM PDT 24
Peak memory 200416 kb
Host smart-904a897d-3098-498e-ad65-d5099120095d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006478490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3006478490
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3075477086
Short name T360
Test name
Test status
Simulation time 1991741604 ps
CPU time 2.47 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:01:02 PM PDT 24
Peak memory 199448 kb
Host smart-97a9ed63-2901-408f-909f-f2bee337bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075477086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3075477086
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.482271759
Short name T1092
Test name
Test status
Simulation time 3872160949 ps
CPU time 6.49 seconds
Started May 16 01:00:16 PM PDT 24
Finished May 16 01:01:02 PM PDT 24
Peak memory 199396 kb
Host smart-748e3d93-0d2e-451f-8217-b8f23bb079be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482271759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.482271759
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1978798645
Short name T919
Test name
Test status
Simulation time 215263408909 ps
CPU time 398.47 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:10:08 PM PDT 24
Peak memory 200452 kb
Host smart-df81d961-4fe8-43ee-b099-3d78351e7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978798645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1978798645
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2765974716
Short name T1052
Test name
Test status
Simulation time 33489225694 ps
CPU time 715.53 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:15:23 PM PDT 24
Peak memory 216408 kb
Host smart-525168c3-081d-4b84-8997-8650c947890b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765974716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2765974716
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2817475721
Short name T560
Test name
Test status
Simulation time 77410337970 ps
CPU time 38.11 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:04:09 PM PDT 24
Peak memory 200268 kb
Host smart-c68a2ec4-a900-448f-a176-37e289e64059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817475721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2817475721
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1695972625
Short name T796
Test name
Test status
Simulation time 57643714540 ps
CPU time 1077.37 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:21:29 PM PDT 24
Peak memory 216972 kb
Host smart-f50d941d-59aa-4d6a-9b9f-5837472def72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695972625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1695972625
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2614843842
Short name T217
Test name
Test status
Simulation time 66334659025 ps
CPU time 28.06 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:03:55 PM PDT 24
Peak memory 200248 kb
Host smart-5669edfb-d41a-4868-9600-04d1113bb889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614843842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2614843842
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1135749319
Short name T97
Test name
Test status
Simulation time 80959651950 ps
CPU time 701.44 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:15:13 PM PDT 24
Peak memory 217180 kb
Host smart-28652d02-d420-4f93-986d-c07e04deb080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135749319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1135749319
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3492397011
Short name T725
Test name
Test status
Simulation time 22732655162 ps
CPU time 39.3 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:04:12 PM PDT 24
Peak memory 200432 kb
Host smart-290d4df9-2032-486a-b462-59306a7808e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492397011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3492397011
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1957964958
Short name T522
Test name
Test status
Simulation time 226172448154 ps
CPU time 1172.1 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:22:59 PM PDT 24
Peak memory 216952 kb
Host smart-d423abf1-9267-4691-a5bb-e85d858fc98c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957964958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1957964958
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3235819402
Short name T98
Test name
Test status
Simulation time 413456222502 ps
CPU time 579.66 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:13:04 PM PDT 24
Peak memory 216932 kb
Host smart-0b27a9c9-3f53-4b79-96d0-f7485399a12f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235819402 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3235819402
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2459148376
Short name T150
Test name
Test status
Simulation time 126335152482 ps
CPU time 57.79 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:04:28 PM PDT 24
Peak memory 200476 kb
Host smart-e015e4ca-a15a-413a-8474-21c7ae4623e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459148376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2459148376
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3172385219
Short name T99
Test name
Test status
Simulation time 304017217336 ps
CPU time 575.7 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:13:07 PM PDT 24
Peak memory 225384 kb
Host smart-e8abc3f1-59b2-4cb5-81c0-5a7ab9a25b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172385219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3172385219
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1727052870
Short name T512
Test name
Test status
Simulation time 34476036932 ps
CPU time 53.87 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:04:27 PM PDT 24
Peak memory 200412 kb
Host smart-03fb2353-1df4-4b1d-a19f-268484f6cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727052870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1727052870
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3216020151
Short name T95
Test name
Test status
Simulation time 250541076537 ps
CPU time 109.96 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:05:15 PM PDT 24
Peak memory 200432 kb
Host smart-cfa97fe2-f7bc-437b-9dfe-38fd4e7673aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216020151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3216020151
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3546554614
Short name T779
Test name
Test status
Simulation time 230435410831 ps
CPU time 314.25 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:08:44 PM PDT 24
Peak memory 216928 kb
Host smart-0a1826bf-c64a-47f6-9d7d-35be35640134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546554614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3546554614
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4168962746
Short name T665
Test name
Test status
Simulation time 189005590611 ps
CPU time 380.7 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:09:52 PM PDT 24
Peak memory 200492 kb
Host smart-4b1d9001-97ce-4d0f-9f2e-12be398ead84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168962746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4168962746
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3028866754
Short name T541
Test name
Test status
Simulation time 176105606178 ps
CPU time 1500.72 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 227972 kb
Host smart-cac5cb4e-c9a3-4e5a-ac56-24dfcadde91d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028866754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3028866754
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2424894094
Short name T115
Test name
Test status
Simulation time 10263161181 ps
CPU time 5.93 seconds
Started May 16 01:03:25 PM PDT 24
Finished May 16 01:03:41 PM PDT 24
Peak memory 200496 kb
Host smart-7c586468-21d0-4262-b78c-109f511e220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424894094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2424894094
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3398731883
Short name T15
Test name
Test status
Simulation time 36169324260 ps
CPU time 628.21 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:13:52 PM PDT 24
Peak memory 217272 kb
Host smart-c200b6e3-bcf2-4b86-967e-48f8857e672a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398731883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3398731883
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3204927080
Short name T831
Test name
Test status
Simulation time 32909117 ps
CPU time 0.56 seconds
Started May 16 01:00:24 PM PDT 24
Finished May 16 01:01:02 PM PDT 24
Peak memory 195676 kb
Host smart-7a54e3ab-ce59-4a12-8808-e58a755bb992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204927080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3204927080
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3704458431
Short name T570
Test name
Test status
Simulation time 71250764499 ps
CPU time 108.23 seconds
Started May 16 01:00:25 PM PDT 24
Finished May 16 01:02:51 PM PDT 24
Peak memory 200480 kb
Host smart-33195223-e099-4e5c-b952-07bd6606ee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704458431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3704458431
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3297847387
Short name T1116
Test name
Test status
Simulation time 217349356843 ps
CPU time 41.26 seconds
Started May 16 01:00:26 PM PDT 24
Finished May 16 01:01:46 PM PDT 24
Peak memory 200420 kb
Host smart-9ddc3b8f-5bbd-4d9d-8046-5436830901bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297847387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3297847387
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.235672294
Short name T969
Test name
Test status
Simulation time 14901349802 ps
CPU time 13.2 seconds
Started May 16 01:00:26 PM PDT 24
Finished May 16 01:01:17 PM PDT 24
Peak memory 200252 kb
Host smart-11897cf8-a3cb-44a9-ae53-20e98de01f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235672294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.235672294
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3466855322
Short name T959
Test name
Test status
Simulation time 182188302942 ps
CPU time 531.1 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:09:51 PM PDT 24
Peak memory 200420 kb
Host smart-577d3e2f-1436-4c82-9ec4-26aef543b321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466855322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3466855322
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2110917098
Short name T737
Test name
Test status
Simulation time 5265361384 ps
CPU time 5.01 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:01:05 PM PDT 24
Peak memory 199356 kb
Host smart-fa8be46f-fc10-4c35-9759-cf13a866d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110917098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2110917098
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1216523415
Short name T104
Test name
Test status
Simulation time 41384613505 ps
CPU time 10.88 seconds
Started May 16 01:00:20 PM PDT 24
Finished May 16 01:01:11 PM PDT 24
Peak memory 197708 kb
Host smart-896a2a29-7326-476a-b108-d3654240ba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216523415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1216523415
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1652548518
Short name T630
Test name
Test status
Simulation time 13832854329 ps
CPU time 721.23 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:13:03 PM PDT 24
Peak memory 200460 kb
Host smart-9c8f24f0-3089-439a-a152-2499a75aea13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652548518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1652548518
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.361227603
Short name T664
Test name
Test status
Simulation time 5047987349 ps
CPU time 10.41 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:12 PM PDT 24
Peak memory 198652 kb
Host smart-5ede7ef7-47c0-4763-868c-e4803befc363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361227603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.361227603
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3555727244
Short name T387
Test name
Test status
Simulation time 45689283182 ps
CPU time 34.05 seconds
Started May 16 01:00:26 PM PDT 24
Finished May 16 01:01:38 PM PDT 24
Peak memory 200432 kb
Host smart-6f860bf8-2a8e-4427-8ae6-931432ea024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555727244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3555727244
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1879473555
Short name T349
Test name
Test status
Simulation time 2302202078 ps
CPU time 1.71 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:01:02 PM PDT 24
Peak memory 195992 kb
Host smart-a2b8316f-a74f-448f-adb7-6c343303f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879473555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1879473555
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.749475151
Short name T728
Test name
Test status
Simulation time 431612147 ps
CPU time 1.87 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:03 PM PDT 24
Peak memory 199024 kb
Host smart-8048fa52-73b1-4adb-a842-76224d37a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749475151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.749475151
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2217644854
Short name T1172
Test name
Test status
Simulation time 15995124311 ps
CPU time 139.53 seconds
Started May 16 01:00:26 PM PDT 24
Finished May 16 01:03:23 PM PDT 24
Peak memory 217216 kb
Host smart-fecc344b-d8ad-4f44-bddf-5ecb0dc5c6a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217644854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2217644854
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2473647857
Short name T621
Test name
Test status
Simulation time 564470833 ps
CPU time 2.3 seconds
Started May 16 01:00:24 PM PDT 24
Finished May 16 01:01:04 PM PDT 24
Peak memory 198512 kb
Host smart-ba6adaa8-dcf6-434f-8b96-8ee29f35e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473647857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2473647857
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3498944637
Short name T557
Test name
Test status
Simulation time 111463386910 ps
CPU time 120.41 seconds
Started May 16 01:00:21 PM PDT 24
Finished May 16 01:03:01 PM PDT 24
Peak memory 200532 kb
Host smart-7b17b363-5d1c-483c-ae10-771107e1916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498944637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3498944637
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.348479615
Short name T478
Test name
Test status
Simulation time 18601995127 ps
CPU time 16.71 seconds
Started May 16 01:03:26 PM PDT 24
Finished May 16 01:03:53 PM PDT 24
Peak memory 200544 kb
Host smart-0d196b48-3d47-4e6f-bfe8-560a3f0f0f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348479615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.348479615
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1332596874
Short name T540
Test name
Test status
Simulation time 93518548263 ps
CPU time 1341.95 seconds
Started May 16 01:03:26 PM PDT 24
Finished May 16 01:25:58 PM PDT 24
Peak memory 227600 kb
Host smart-f7accf1b-99ff-46c3-bf73-1a3583336b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332596874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1332596874
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3069099780
Short name T515
Test name
Test status
Simulation time 7841277014 ps
CPU time 12.97 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:03:37 PM PDT 24
Peak memory 199404 kb
Host smart-dbb116dd-1418-4079-b89b-ad1057de67be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069099780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3069099780
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.27276696
Short name T1178
Test name
Test status
Simulation time 143577848352 ps
CPU time 816.08 seconds
Started May 16 01:03:23 PM PDT 24
Finished May 16 01:17:07 PM PDT 24
Peak memory 216856 kb
Host smart-1db20244-0cd8-4aee-ab4e-f8d4e233d585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276696 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.27276696
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3178557775
Short name T187
Test name
Test status
Simulation time 61225598326 ps
CPU time 48.7 seconds
Started May 16 01:03:21 PM PDT 24
Finished May 16 01:04:18 PM PDT 24
Peak memory 200492 kb
Host smart-f36f90f5-e104-4652-897a-37a12130b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178557775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3178557775
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1344450213
Short name T123
Test name
Test status
Simulation time 88357773534 ps
CPU time 1249.65 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:24:20 PM PDT 24
Peak memory 229668 kb
Host smart-55501193-a796-4100-839b-3739c628a93e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344450213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1344450213
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2890142461
Short name T196
Test name
Test status
Simulation time 5962402756 ps
CPU time 13.41 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:03:44 PM PDT 24
Peak memory 200416 kb
Host smart-d40ef227-4b0e-4b71-942a-cc3f43f7a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890142461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2890142461
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3253670774
Short name T645
Test name
Test status
Simulation time 118822498847 ps
CPU time 383.08 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:09:50 PM PDT 24
Peak memory 216988 kb
Host smart-f85f9066-2b10-4ba7-99b0-001486fd7c6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253670774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3253670774
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2944840350
Short name T960
Test name
Test status
Simulation time 143227988535 ps
CPU time 48.71 seconds
Started May 16 01:03:22 PM PDT 24
Finished May 16 01:04:19 PM PDT 24
Peak memory 200476 kb
Host smart-918ddb44-22a7-4a52-bac2-1c3742dee037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944840350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2944840350
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3474361974
Short name T805
Test name
Test status
Simulation time 37393706825 ps
CPU time 253.79 seconds
Started May 16 01:03:26 PM PDT 24
Finished May 16 01:07:50 PM PDT 24
Peak memory 216512 kb
Host smart-92fe41e9-7045-4b89-9709-cee158428c60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474361974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3474361974
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.561393831
Short name T544
Test name
Test status
Simulation time 24892234695 ps
CPU time 40.55 seconds
Started May 16 01:03:19 PM PDT 24
Finished May 16 01:04:05 PM PDT 24
Peak memory 200428 kb
Host smart-9d378911-59ce-4320-ba6b-823def27654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561393831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.561393831
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3008043612
Short name T230
Test name
Test status
Simulation time 176308137964 ps
CPU time 77.24 seconds
Started May 16 01:03:20 PM PDT 24
Finished May 16 01:04:44 PM PDT 24
Peak memory 200488 kb
Host smart-2dbf8337-370d-4a3c-a99c-38112c87c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008043612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3008043612
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.304879635
Short name T855
Test name
Test status
Simulation time 35980787354 ps
CPU time 398.15 seconds
Started May 16 01:03:24 PM PDT 24
Finished May 16 01:10:12 PM PDT 24
Peak memory 217036 kb
Host smart-1fa61101-6fb1-461d-b3fa-3f6c1e2563ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304879635 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.304879635
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.349070227
Short name T235
Test name
Test status
Simulation time 254441658875 ps
CPU time 39.47 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:04:22 PM PDT 24
Peak memory 200372 kb
Host smart-0275c978-53d8-4c91-89fb-c32956f5daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349070227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.349070227
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2630758994
Short name T473
Test name
Test status
Simulation time 201264166608 ps
CPU time 52.19 seconds
Started May 16 01:03:28 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200424 kb
Host smart-e3d365a2-487b-4c7e-9962-40ec1bce9e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630758994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2630758994
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.795601385
Short name T46
Test name
Test status
Simulation time 510052022641 ps
CPU time 1039.13 seconds
Started May 16 01:03:29 PM PDT 24
Finished May 16 01:20:57 PM PDT 24
Peak memory 225420 kb
Host smart-b1c4968f-cd72-48a5-bef1-8d73d2b8abca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795601385 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.795601385
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2578814146
Short name T818
Test name
Test status
Simulation time 72172414826 ps
CPU time 32.77 seconds
Started May 16 01:03:29 PM PDT 24
Finished May 16 01:04:11 PM PDT 24
Peak memory 200512 kb
Host smart-2d56e82d-889f-470f-a662-11cd79b7fdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578814146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2578814146
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.4132942349
Short name T479
Test name
Test status
Simulation time 16126351 ps
CPU time 0.53 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:01:10 PM PDT 24
Peak memory 195284 kb
Host smart-7fe6649d-b4f6-4f21-8eb7-8f190c9879ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132942349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.4132942349
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2221519706
Short name T61
Test name
Test status
Simulation time 190799666651 ps
CPU time 723.41 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:13:05 PM PDT 24
Peak memory 200456 kb
Host smart-38c9245c-c728-4514-8c38-3f6ea6098479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221519706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2221519706
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.218017370
Short name T1005
Test name
Test status
Simulation time 117291798908 ps
CPU time 138.34 seconds
Started May 16 01:00:26 PM PDT 24
Finished May 16 01:03:22 PM PDT 24
Peak memory 200504 kb
Host smart-3ed967b6-6ddd-4322-b280-0d875794b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218017370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.218017370
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1634217850
Short name T982
Test name
Test status
Simulation time 29383185670 ps
CPU time 47.33 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:49 PM PDT 24
Peak memory 200512 kb
Host smart-85e0f1f1-46d0-4101-85c2-9cef42f40fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634217850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1634217850
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1328930495
Short name T998
Test name
Test status
Simulation time 29466031639 ps
CPU time 58.2 seconds
Started May 16 01:00:26 PM PDT 24
Finished May 16 01:02:01 PM PDT 24
Peak memory 200320 kb
Host smart-b0297991-8d90-434e-a1cb-21f5e204002d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328930495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1328930495
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3481208677
Short name T364
Test name
Test status
Simulation time 28861546255 ps
CPU time 155.28 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:03:44 PM PDT 24
Peak memory 200472 kb
Host smart-224f7809-2620-4395-b6ad-b84914f3ad9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481208677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3481208677
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.954032163
Short name T330
Test name
Test status
Simulation time 4398959539 ps
CPU time 7.77 seconds
Started May 16 01:00:22 PM PDT 24
Finished May 16 01:01:09 PM PDT 24
Peak memory 196724 kb
Host smart-f4f9d6f7-8c6c-4d60-b520-b7529c9bf0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954032163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.954032163
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1445221526
Short name T259
Test name
Test status
Simulation time 37962964248 ps
CPU time 58.64 seconds
Started May 16 01:00:22 PM PDT 24
Finished May 16 01:01:59 PM PDT 24
Peak memory 200680 kb
Host smart-ca4ff13d-bee6-40a4-95e4-62c01f48a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445221526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1445221526
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.4004366436
Short name T1121
Test name
Test status
Simulation time 11664621151 ps
CPU time 68.13 seconds
Started May 16 01:00:25 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 200484 kb
Host smart-d59baf47-54c0-48f6-a1eb-a0f2e9fada13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004366436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4004366436
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.468522921
Short name T329
Test name
Test status
Simulation time 2882560600 ps
CPU time 2.51 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:04 PM PDT 24
Peak memory 198460 kb
Host smart-7f4ca458-a536-4392-91fe-d0d472fa45dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468522921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.468522921
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1127775033
Short name T981
Test name
Test status
Simulation time 78181130158 ps
CPU time 31.86 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:33 PM PDT 24
Peak memory 200136 kb
Host smart-a9bbdab9-764c-4442-857f-472e0a1a240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127775033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1127775033
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1589136352
Short name T388
Test name
Test status
Simulation time 4088812436 ps
CPU time 5.89 seconds
Started May 16 01:00:19 PM PDT 24
Finished May 16 01:01:05 PM PDT 24
Peak memory 196480 kb
Host smart-0da37ff9-553b-493e-a360-da9f717f2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589136352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1589136352
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1228802586
Short name T106
Test name
Test status
Simulation time 285808455 ps
CPU time 1.87 seconds
Started May 16 01:00:22 PM PDT 24
Finished May 16 01:01:02 PM PDT 24
Peak memory 199368 kb
Host smart-2fcb4654-ed9a-483b-b57e-fa20dfd5b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228802586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1228802586
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1133422998
Short name T813
Test name
Test status
Simulation time 505979954737 ps
CPU time 264.91 seconds
Started May 16 01:00:31 PM PDT 24
Finished May 16 01:05:33 PM PDT 24
Peak memory 208852 kb
Host smart-efee35b9-086e-4f50-9288-805236825fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133422998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1133422998
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.578047134
Short name T49
Test name
Test status
Simulation time 836931227974 ps
CPU time 1101.94 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:19:31 PM PDT 24
Peak memory 217256 kb
Host smart-9a386a76-f1b6-4e84-b398-11bf3cbe06f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578047134 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.578047134
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3067860733
Short name T1041
Test name
Test status
Simulation time 339639448 ps
CPU time 1.35 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:03 PM PDT 24
Peak memory 198432 kb
Host smart-0280cc4e-429c-4fec-80a7-69bcafb1b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067860733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3067860733
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1750778379
Short name T606
Test name
Test status
Simulation time 33106822447 ps
CPU time 21.44 seconds
Started May 16 01:00:23 PM PDT 24
Finished May 16 01:01:23 PM PDT 24
Peak memory 200404 kb
Host smart-ebfe893e-bb0b-45da-9a51-eb1434d6811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750778379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1750778379
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.87118835
Short name T1126
Test name
Test status
Simulation time 36785897883 ps
CPU time 17.76 seconds
Started May 16 01:03:37 PM PDT 24
Finished May 16 01:04:03 PM PDT 24
Peak memory 200464 kb
Host smart-d7ecb843-b6bf-4534-86f5-7c2d6b1352be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87118835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.87118835
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2191909269
Short name T160
Test name
Test status
Simulation time 193063310584 ps
CPU time 467.28 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:11:29 PM PDT 24
Peak memory 216824 kb
Host smart-22a51847-4cd4-46f3-bf2a-0b11066992d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191909269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2191909269
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2399489927
Short name T212
Test name
Test status
Simulation time 89918032822 ps
CPU time 137.37 seconds
Started May 16 01:03:29 PM PDT 24
Finished May 16 01:05:56 PM PDT 24
Peak memory 200404 kb
Host smart-36783485-644f-4b00-a9df-60568d416290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399489927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2399489927
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.82169084
Short name T574
Test name
Test status
Simulation time 65355227813 ps
CPU time 531.08 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:12:33 PM PDT 24
Peak memory 216944 kb
Host smart-6cf718c3-7945-40b0-b6eb-da8392e422d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82169084 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.82169084
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1155013817
Short name T1160
Test name
Test status
Simulation time 13890403824 ps
CPU time 21.18 seconds
Started May 16 01:03:36 PM PDT 24
Finished May 16 01:04:06 PM PDT 24
Peak memory 200428 kb
Host smart-05c554b7-cf15-41e2-b8ea-50e90c4ade27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155013817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1155013817
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2861400588
Short name T34
Test name
Test status
Simulation time 92218092601 ps
CPU time 203.6 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:07:06 PM PDT 24
Peak memory 216944 kb
Host smart-81d33469-c06b-4bd9-b542-1173580f8be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861400588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2861400588
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3862747510
Short name T608
Test name
Test status
Simulation time 112152336687 ps
CPU time 85.95 seconds
Started May 16 01:03:31 PM PDT 24
Finished May 16 01:05:06 PM PDT 24
Peak memory 200488 kb
Host smart-cb86f437-d414-4214-9100-9147a5035b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862747510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3862747510
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1274623398
Short name T3
Test name
Test status
Simulation time 8756051415 ps
CPU time 299.2 seconds
Started May 16 01:03:31 PM PDT 24
Finished May 16 01:08:39 PM PDT 24
Peak memory 216100 kb
Host smart-827c70d6-5d8b-424b-8f7f-7c45ff605869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274623398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1274623398
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1438393697
Short name T701
Test name
Test status
Simulation time 19774930602 ps
CPU time 17.52 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:03:57 PM PDT 24
Peak memory 198852 kb
Host smart-432e65e1-066b-4437-a384-bc324df5a8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438393697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1438393697
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1379863530
Short name T176
Test name
Test status
Simulation time 28201367166 ps
CPU time 60.1 seconds
Started May 16 01:03:34 PM PDT 24
Finished May 16 01:04:42 PM PDT 24
Peak memory 200456 kb
Host smart-1fcbe27d-9446-4ee2-835d-b93f3a0f5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379863530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1379863530
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2016684012
Short name T590
Test name
Test status
Simulation time 125773060722 ps
CPU time 558.26 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:12:58 PM PDT 24
Peak memory 217212 kb
Host smart-936b66fc-50f9-4783-a4ad-2d265a7551a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016684012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2016684012
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2048146009
Short name T1153
Test name
Test status
Simulation time 94816943228 ps
CPU time 16.82 seconds
Started May 16 01:03:31 PM PDT 24
Finished May 16 01:03:57 PM PDT 24
Peak memory 200392 kb
Host smart-91006edb-8c98-4d3d-8147-2361bf56cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048146009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2048146009
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3171366338
Short name T1085
Test name
Test status
Simulation time 60333900128 ps
CPU time 103.82 seconds
Started May 16 01:03:36 PM PDT 24
Finished May 16 01:05:29 PM PDT 24
Peak memory 200400 kb
Host smart-f54878a8-c398-4319-b1dc-ae421a87b2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171366338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3171366338
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3625501331
Short name T42
Test name
Test status
Simulation time 200488924889 ps
CPU time 1024.22 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:20:44 PM PDT 24
Peak memory 225496 kb
Host smart-cb5a34ba-22b2-4164-b5c9-e18d2bd54425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625501331 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3625501331
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2043700191
Short name T613
Test name
Test status
Simulation time 157256234519 ps
CPU time 268.46 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:08:08 PM PDT 24
Peak memory 200464 kb
Host smart-12b04011-9b8b-4aaf-8b46-6aa9d5916d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043700191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2043700191
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3014817607
Short name T401
Test name
Test status
Simulation time 85722777836 ps
CPU time 430.64 seconds
Started May 16 01:03:32 PM PDT 24
Finished May 16 01:10:52 PM PDT 24
Peak memory 217176 kb
Host smart-3cc7e346-45fd-4955-bd85-9e89415145d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014817607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3014817607
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3330956676
Short name T810
Test name
Test status
Simulation time 13013919 ps
CPU time 0.55 seconds
Started May 16 01:00:30 PM PDT 24
Finished May 16 01:01:08 PM PDT 24
Peak memory 195204 kb
Host smart-2bbeb121-ba48-4326-8cce-87bcbef0d19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330956676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3330956676
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.107455807
Short name T1176
Test name
Test status
Simulation time 65489107857 ps
CPU time 29.85 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:01:41 PM PDT 24
Peak memory 200584 kb
Host smart-0dde9fc3-791c-4327-b54a-d695dd2a612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107455807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.107455807
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1440906264
Short name T1167
Test name
Test status
Simulation time 105560853226 ps
CPU time 45.02 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:01:55 PM PDT 24
Peak memory 200356 kb
Host smart-2c71a99f-d440-45d9-9ad7-0e7e83da96b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440906264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1440906264
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1491987501
Short name T736
Test name
Test status
Simulation time 28967405939 ps
CPU time 21.66 seconds
Started May 16 01:00:30 PM PDT 24
Finished May 16 01:01:29 PM PDT 24
Peak memory 200512 kb
Host smart-230eb505-1b76-4a27-bf6e-6e04369bac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491987501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1491987501
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1129119915
Short name T587
Test name
Test status
Simulation time 45012009616 ps
CPU time 41.33 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:57 PM PDT 24
Peak memory 200452 kb
Host smart-c758eaf3-0d67-4759-96b9-b0c0b7399d6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129119915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1129119915
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.485523423
Short name T260
Test name
Test status
Simulation time 115098005671 ps
CPU time 678.63 seconds
Started May 16 01:00:31 PM PDT 24
Finished May 16 01:12:27 PM PDT 24
Peak memory 200500 kb
Host smart-fd149509-3ffd-455b-a39c-b7ec8f10caac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485523423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.485523423
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1620924579
Short name T740
Test name
Test status
Simulation time 2725600174 ps
CPU time 1.18 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:16 PM PDT 24
Peak memory 197820 kb
Host smart-0a16783f-3a72-4c81-b21c-5b8bd21c7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620924579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1620924579
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.696156257
Short name T798
Test name
Test status
Simulation time 36463836745 ps
CPU time 60.82 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 200776 kb
Host smart-729a15fb-9b66-4566-85d6-9986aa12190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696156257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.696156257
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2971739612
Short name T289
Test name
Test status
Simulation time 5321477941 ps
CPU time 128.85 seconds
Started May 16 01:00:31 PM PDT 24
Finished May 16 01:03:17 PM PDT 24
Peak memory 200416 kb
Host smart-b46c48bc-926e-4b10-8a78-7f84da5421c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971739612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2971739612
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3846408091
Short name T90
Test name
Test status
Simulation time 7725046717 ps
CPU time 65.23 seconds
Started May 16 01:00:30 PM PDT 24
Finished May 16 01:02:11 PM PDT 24
Peak memory 198612 kb
Host smart-5054cdb2-3dbc-41d2-93a0-46eea9157d17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846408091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3846408091
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.215792735
Short name T827
Test name
Test status
Simulation time 32031591976 ps
CPU time 60.47 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:02:16 PM PDT 24
Peak memory 200032 kb
Host smart-00adcd7f-6c42-4372-94cc-bfdfb1bab7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215792735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.215792735
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.829313501
Short name T958
Test name
Test status
Simulation time 4562944134 ps
CPU time 2.63 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:01:12 PM PDT 24
Peak memory 196756 kb
Host smart-09d6ae10-a360-424a-852e-c1b2f6d10a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829313501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.829313501
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3893325806
Short name T340
Test name
Test status
Simulation time 562670300 ps
CPU time 0.88 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:01:11 PM PDT 24
Peak memory 199392 kb
Host smart-d895ef1f-2df2-46f2-8d69-0bbc79594dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893325806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3893325806
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.949499308
Short name T746
Test name
Test status
Simulation time 283709337050 ps
CPU time 109.58 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:02:58 PM PDT 24
Peak memory 200476 kb
Host smart-c0d27445-6644-4dbf-bd74-f92e2597bcef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949499308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.949499308
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3467453125
Short name T43
Test name
Test status
Simulation time 72895839694 ps
CPU time 650.05 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:11:59 PM PDT 24
Peak memory 214328 kb
Host smart-6de7a9a2-8374-420d-8670-e476935d7eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467453125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3467453125
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2193216288
Short name T957
Test name
Test status
Simulation time 8316596628 ps
CPU time 8.57 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:01:19 PM PDT 24
Peak memory 200376 kb
Host smart-0e732958-d463-4cb7-a8ec-b093e45305ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193216288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2193216288
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3085869150
Short name T255
Test name
Test status
Simulation time 35471773317 ps
CPU time 57.42 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:02:08 PM PDT 24
Peak memory 200408 kb
Host smart-c8f9c955-4b70-4068-a888-2b1e7198d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085869150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3085869150
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2023943135
Short name T762
Test name
Test status
Simulation time 13069316508 ps
CPU time 16.42 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:03:55 PM PDT 24
Peak memory 200392 kb
Host smart-d2a9c5fb-f6fe-4776-8f08-0c69611c8567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023943135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2023943135
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2563382289
Short name T304
Test name
Test status
Simulation time 20706357319 ps
CPU time 243.43 seconds
Started May 16 01:03:29 PM PDT 24
Finished May 16 01:07:42 PM PDT 24
Peak memory 216408 kb
Host smart-bd5274e0-f926-4518-8375-87b582eeb752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563382289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2563382289
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1058660407
Short name T506
Test name
Test status
Simulation time 40343236441 ps
CPU time 26.61 seconds
Started May 16 01:03:31 PM PDT 24
Finished May 16 01:04:07 PM PDT 24
Peak memory 200420 kb
Host smart-c46175d0-acf0-41b1-aad1-538f8826e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058660407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1058660407
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1426598326
Short name T808
Test name
Test status
Simulation time 51997711272 ps
CPU time 388.22 seconds
Started May 16 01:03:28 PM PDT 24
Finished May 16 01:10:06 PM PDT 24
Peak memory 213628 kb
Host smart-e04c56e1-6d4c-4dd1-ad7b-237780c229de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426598326 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1426598326
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.498757017
Short name T812
Test name
Test status
Simulation time 14526891064 ps
CPU time 12.99 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:03:55 PM PDT 24
Peak memory 200548 kb
Host smart-abcdb5ee-973d-4807-9625-a77b91294b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498757017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.498757017
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1084505188
Short name T534
Test name
Test status
Simulation time 350033224918 ps
CPU time 1039.86 seconds
Started May 16 01:03:32 PM PDT 24
Finished May 16 01:21:01 PM PDT 24
Peak memory 233260 kb
Host smart-f8a8e34a-563d-4f94-a5f1-4079e9d51717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084505188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1084505188
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3254369875
Short name T224
Test name
Test status
Simulation time 75067785698 ps
CPU time 28.8 seconds
Started May 16 01:03:28 PM PDT 24
Finished May 16 01:04:07 PM PDT 24
Peak memory 200280 kb
Host smart-8adfe893-b363-444a-834b-e0cf857bb6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254369875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3254369875
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.202827343
Short name T1180
Test name
Test status
Simulation time 37127650753 ps
CPU time 112.93 seconds
Started May 16 01:03:29 PM PDT 24
Finished May 16 01:05:31 PM PDT 24
Peak memory 216152 kb
Host smart-7da9de4d-f9fe-4ff7-825a-a1c774ec4b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202827343 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.202827343
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3197424630
Short name T863
Test name
Test status
Simulation time 153672743482 ps
CPU time 275.64 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:08:18 PM PDT 24
Peak memory 200108 kb
Host smart-b53a9ce2-9666-4214-87b1-2ea0c9350bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197424630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3197424630
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1526975564
Short name T1049
Test name
Test status
Simulation time 388576135675 ps
CPU time 908.83 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:18:49 PM PDT 24
Peak memory 225820 kb
Host smart-181ac25e-4a2f-4f96-9469-e1f879cad128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526975564 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1526975564
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1746584554
Short name T763
Test name
Test status
Simulation time 21550161353 ps
CPU time 35.04 seconds
Started May 16 01:03:31 PM PDT 24
Finished May 16 01:04:16 PM PDT 24
Peak memory 200520 kb
Host smart-3c8d8727-98de-4cd7-9cdf-c21ff45c6c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746584554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1746584554
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1179570754
Short name T492
Test name
Test status
Simulation time 111440374258 ps
CPU time 637.24 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:14:19 PM PDT 24
Peak memory 217100 kb
Host smart-c2ff957d-80f5-4807-a341-c8819f0b665a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179570754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1179570754
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3279167133
Short name T208
Test name
Test status
Simulation time 123900038928 ps
CPU time 19.71 seconds
Started May 16 01:03:29 PM PDT 24
Finished May 16 01:03:58 PM PDT 24
Peak memory 200524 kb
Host smart-cf9d33bf-8bf0-4a1e-87f1-3b04f64b4f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279167133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3279167133
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2913608246
Short name T509
Test name
Test status
Simulation time 213882210603 ps
CPU time 552.84 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:12:53 PM PDT 24
Peak memory 217212 kb
Host smart-22feae76-ad72-429d-a05c-0ffebcaf7191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913608246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2913608246
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4043470719
Short name T248
Test name
Test status
Simulation time 29490241111 ps
CPU time 49.3 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:04:29 PM PDT 24
Peak memory 200436 kb
Host smart-776ecccf-accf-414f-953c-7ac9491ffd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043470719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4043470719
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2138252985
Short name T1088
Test name
Test status
Simulation time 161864156909 ps
CPU time 795.9 seconds
Started May 16 01:03:30 PM PDT 24
Finished May 16 01:16:55 PM PDT 24
Peak memory 216992 kb
Host smart-7e07808b-976c-4bcc-bef6-9a4788a40eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138252985 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2138252985
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2565586494
Short name T215
Test name
Test status
Simulation time 255938345717 ps
CPU time 23.98 seconds
Started May 16 01:03:33 PM PDT 24
Finished May 16 01:04:06 PM PDT 24
Peak memory 200220 kb
Host smart-f6e64323-67e9-4137-8566-8a4540a97d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565586494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2565586494
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1020138356
Short name T956
Test name
Test status
Simulation time 163167837223 ps
CPU time 719.15 seconds
Started May 16 01:03:45 PM PDT 24
Finished May 16 01:15:51 PM PDT 24
Peak memory 228736 kb
Host smart-252897e6-7255-4169-b15e-7bd5f7c1c5a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020138356 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1020138356
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3988482808
Short name T924
Test name
Test status
Simulation time 90808112006 ps
CPU time 41.76 seconds
Started May 16 01:03:41 PM PDT 24
Finished May 16 01:04:31 PM PDT 24
Peak memory 200432 kb
Host smart-0659e3d3-a309-4d99-ba86-cd83abdccc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988482808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3988482808
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3133908797
Short name T158
Test name
Test status
Simulation time 85903172414 ps
CPU time 225.43 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:07:34 PM PDT 24
Peak memory 216956 kb
Host smart-32495e2a-37e0-4412-b9a2-6f91625b46b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133908797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3133908797
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3184373390
Short name T1137
Test name
Test status
Simulation time 12895512 ps
CPU time 0.54 seconds
Started May 16 01:00:30 PM PDT 24
Finished May 16 01:01:08 PM PDT 24
Peak memory 195336 kb
Host smart-16ef2f46-a688-41ed-82d3-474c438ce26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184373390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3184373390
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3732911108
Short name T847
Test name
Test status
Simulation time 28377806778 ps
CPU time 53.87 seconds
Started May 16 01:00:31 PM PDT 24
Finished May 16 01:02:02 PM PDT 24
Peak memory 200516 kb
Host smart-bf584562-0dad-4fb1-9b54-f20bc9b160f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732911108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3732911108
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.129452963
Short name T622
Test name
Test status
Simulation time 173155931775 ps
CPU time 353.26 seconds
Started May 16 01:00:31 PM PDT 24
Finished May 16 01:07:01 PM PDT 24
Peak memory 200400 kb
Host smart-2489df53-1a73-4669-883c-a91fcc4e6723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129452963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.129452963
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.3267527864
Short name T1117
Test name
Test status
Simulation time 40611434747 ps
CPU time 69.8 seconds
Started May 16 01:00:35 PM PDT 24
Finished May 16 01:02:21 PM PDT 24
Peak memory 200448 kb
Host smart-d4be94c6-af65-4205-97b3-951e65823fc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267527864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3267527864
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3930667058
Short name T92
Test name
Test status
Simulation time 226461233842 ps
CPU time 273.11 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:05:42 PM PDT 24
Peak memory 200464 kb
Host smart-f01afa83-eb27-448e-be4a-7213bb78c765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930667058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3930667058
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2117841772
Short name T990
Test name
Test status
Simulation time 4836270388 ps
CPU time 4.02 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:19 PM PDT 24
Peak memory 200100 kb
Host smart-1e744b3a-dc02-483e-867e-2034697cb4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117841772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2117841772
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3575193498
Short name T756
Test name
Test status
Simulation time 103382771294 ps
CPU time 67.8 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:02:19 PM PDT 24
Peak memory 200800 kb
Host smart-1baaf916-ff11-4efe-b7bf-44db803aacd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575193498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3575193498
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3388903009
Short name T1026
Test name
Test status
Simulation time 19853346030 ps
CPU time 219.36 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:04:48 PM PDT 24
Peak memory 200516 kb
Host smart-975a6e44-0981-4389-a158-1bdd9788065f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388903009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3388903009
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3155452041
Short name T543
Test name
Test status
Simulation time 3947120076 ps
CPU time 4.24 seconds
Started May 16 01:00:41 PM PDT 24
Finished May 16 01:01:19 PM PDT 24
Peak memory 198368 kb
Host smart-f3994498-937e-46da-9ccc-fed99a544bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155452041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3155452041
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3084425902
Short name T409
Test name
Test status
Simulation time 66574392603 ps
CPU time 15.06 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:01:24 PM PDT 24
Peak memory 200456 kb
Host smart-3ecdd9fd-4f76-437c-a41c-225698fba96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084425902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3084425902
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1398634269
Short name T358
Test name
Test status
Simulation time 32014003759 ps
CPU time 11.01 seconds
Started May 16 01:00:30 PM PDT 24
Finished May 16 01:01:18 PM PDT 24
Peak memory 196464 kb
Host smart-126a4f72-5594-4dab-92e1-5f0919298c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398634269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1398634269
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3804204720
Short name T426
Test name
Test status
Simulation time 708133808 ps
CPU time 1.78 seconds
Started May 16 01:00:32 PM PDT 24
Finished May 16 01:01:11 PM PDT 24
Peak memory 198716 kb
Host smart-5a2445f4-6072-4d53-8728-c2b2a64ed677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804204720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3804204720
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1917646053
Short name T111
Test name
Test status
Simulation time 78898577620 ps
CPU time 70.65 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:02:21 PM PDT 24
Peak memory 200412 kb
Host smart-89da99af-3515-4227-8d4f-a857f04efcdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917646053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1917646053
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2941834951
Short name T634
Test name
Test status
Simulation time 50044013390 ps
CPU time 156.59 seconds
Started May 16 01:00:33 PM PDT 24
Finished May 16 01:03:46 PM PDT 24
Peak memory 216796 kb
Host smart-96bcff00-d106-4fff-a2a3-ee5ae2d1a667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941834951 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2941834951
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.381360975
Short name T386
Test name
Test status
Simulation time 8042481694 ps
CPU time 9.04 seconds
Started May 16 01:00:40 PM PDT 24
Finished May 16 01:01:24 PM PDT 24
Peak memory 200312 kb
Host smart-1f6e47c1-d633-4060-a7f4-9363ce5841df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381360975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.381360975
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2205421331
Short name T323
Test name
Test status
Simulation time 38399188587 ps
CPU time 29.45 seconds
Started May 16 01:00:34 PM PDT 24
Finished May 16 01:01:40 PM PDT 24
Peak memory 200176 kb
Host smart-fab50436-23f1-4011-b105-58fe73072cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205421331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2205421331
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.979064184
Short name T629
Test name
Test status
Simulation time 10877705216 ps
CPU time 144.12 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:06:11 PM PDT 24
Peak memory 209920 kb
Host smart-3d798532-ac81-468a-a23f-94497b8ce998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979064184 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.979064184
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1490466828
Short name T1155
Test name
Test status
Simulation time 28279697057 ps
CPU time 21.9 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:04:10 PM PDT 24
Peak memory 200392 kb
Host smart-00e67f7f-b2a5-4bc8-8f40-5df1ffab018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490466828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1490466828
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.4205813611
Short name T785
Test name
Test status
Simulation time 95205957819 ps
CPU time 649.17 seconds
Started May 16 01:03:38 PM PDT 24
Finished May 16 01:14:36 PM PDT 24
Peak memory 225468 kb
Host smart-e3736665-d78d-4b68-9b3c-d9780aa222e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205813611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.4205813611
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.948943346
Short name T1099
Test name
Test status
Simulation time 21867609469 ps
CPU time 19.15 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:04:07 PM PDT 24
Peak memory 200468 kb
Host smart-65f844db-d06f-4358-bdd7-ec2f0deaf550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948943346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.948943346
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3012720416
Short name T408
Test name
Test status
Simulation time 37218487888 ps
CPU time 12.43 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:03:59 PM PDT 24
Peak memory 200484 kb
Host smart-3820a720-328c-4b66-aa08-5408bbe214d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012720416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3012720416
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3767095053
Short name T980
Test name
Test status
Simulation time 13664039027 ps
CPU time 16.79 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:04:05 PM PDT 24
Peak memory 200448 kb
Host smart-68a2bf3a-b404-4b18-8ba2-5167ffdfc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767095053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3767095053
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.4271654666
Short name T795
Test name
Test status
Simulation time 116309395661 ps
CPU time 198.93 seconds
Started May 16 01:03:38 PM PDT 24
Finished May 16 01:07:05 PM PDT 24
Peak memory 200500 kb
Host smart-b8bfdf50-7227-4a67-b2b2-84471bd49fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271654666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4271654666
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.4061523207
Short name T511
Test name
Test status
Simulation time 91787256316 ps
CPU time 328.16 seconds
Started May 16 01:03:45 PM PDT 24
Finished May 16 01:09:20 PM PDT 24
Peak memory 216792 kb
Host smart-2db8bc44-2f1a-472d-87d6-0e38b57faab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061523207 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.4061523207
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3918427574
Short name T744
Test name
Test status
Simulation time 44838409320 ps
CPU time 66.99 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:04:54 PM PDT 24
Peak memory 200404 kb
Host smart-9664ce7a-9482-4339-958e-613a784fae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918427574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3918427574
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1953559864
Short name T646
Test name
Test status
Simulation time 89546835184 ps
CPU time 456.22 seconds
Started May 16 01:03:42 PM PDT 24
Finished May 16 01:11:26 PM PDT 24
Peak memory 225452 kb
Host smart-3247c1e7-50f2-4d7c-a2e8-e60c8e3813a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953559864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1953559864
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3913102411
Short name T209
Test name
Test status
Simulation time 75723440121 ps
CPU time 110.74 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:05:38 PM PDT 24
Peak memory 200492 kb
Host smart-7758ee0b-8895-428e-95b6-f2675afe9041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913102411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3913102411
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2418072094
Short name T538
Test name
Test status
Simulation time 185387758039 ps
CPU time 674.01 seconds
Started May 16 01:03:45 PM PDT 24
Finished May 16 01:15:06 PM PDT 24
Peak memory 225464 kb
Host smart-57f71fd3-4963-4376-afe3-0af3d5fa886f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418072094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2418072094
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1994615939
Short name T747
Test name
Test status
Simulation time 14695237672 ps
CPU time 23.72 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:04:11 PM PDT 24
Peak memory 200488 kb
Host smart-2f6076a3-eb4d-4a29-913a-38eca6d30011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994615939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1994615939
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3755431895
Short name T22
Test name
Test status
Simulation time 134860993671 ps
CPU time 838.56 seconds
Started May 16 01:03:46 PM PDT 24
Finished May 16 01:17:52 PM PDT 24
Peak memory 217264 kb
Host smart-b7735d4c-a78f-45d1-a82a-5507841e18ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755431895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3755431895
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.28345990
Short name T200
Test name
Test status
Simulation time 21559769488 ps
CPU time 31.12 seconds
Started May 16 01:03:40 PM PDT 24
Finished May 16 01:04:20 PM PDT 24
Peak memory 200528 kb
Host smart-8e6c8867-ecd9-46f0-abdf-2fdedd598332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28345990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.28345990
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2516476830
Short name T291
Test name
Test status
Simulation time 51693705572 ps
CPU time 212.1 seconds
Started May 16 01:03:39 PM PDT 24
Finished May 16 01:07:20 PM PDT 24
Peak memory 216052 kb
Host smart-98c53bf0-e20d-46b5-b818-25b67692133b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516476830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2516476830
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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