Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	129915	1			T1	33		T2	1		T3	4
all_values[1]	129915	1			T1	33		T2	1		T3	4
all_values[2]	129915	1			T1	33		T2	1		T3	4
all_values[3]	129915	1			T1	33		T2	1		T3	4
all_values[4]	129915	1			T1	33		T2	1		T3	4
all_values[5]	129915	1			T1	33		T2	1		T3	4
all_values[6]	129915	1			T1	33		T2	1		T3	4
all_values[7]	129915	1			T1	33		T2	1		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524249

1

T1

127

T2

5

T3

21

auto[1]

515071

1

T1

137

T2

3

T3

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977273

1

T1

222

T2

7

T3

25

auto[1]

62047

1

T1

42

T2

1

T3

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	37727	1			T5	26		T9	189		T13	39
all_values[0]	auto[0]	auto[1]	24195	1			T3	2		T4	2		T8	18
all_values[0]	auto[1]	auto[0]	41922	1			T5	31		T9	238		T12	3
all_values[0]	auto[1]	auto[1]	26071	1			T1	33		T2	1		T3	2
all_values[1]	auto[0]	auto[0]	65826	1			T1	25		T4	2		T5	26
all_values[1]	auto[0]	auto[1]	1783	1			T1	3		T3	1		T5	20
all_values[1]	auto[1]	auto[0]	60709	1			T1	1		T2	1		T3	3
all_values[1]	auto[1]	auto[1]	1597	1			T1	4		T5	16		T9	8
all_values[2]	auto[0]	auto[0]	62740	1			T1	31		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2879	1			T1	2		T3	2		T4	1
all_values[2]	auto[1]	auto[0]	61792	1			T3	1		T5	29		T6	1
all_values[2]	auto[1]	auto[1]	2504	1			T5	6		T9	12		T13	13
all_values[3]	auto[0]	auto[0]	64778	1			T1	5		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	327	1			T9	1		T14	2		T21	1
all_values[3]	auto[1]	auto[0]	64519	1			T1	28		T3	2		T5	17
all_values[3]	auto[1]	auto[1]	291	1			T8	1		T9	1		T15	1
all_values[4]	auto[0]	auto[0]	61948	1			T1	33		T3	3		T4	2
all_values[4]	auto[0]	auto[1]	439	1			T14	2		T17	10		T21	1
all_values[4]	auto[1]	auto[0]	67057	1			T2	1		T3	1		T5	32
all_values[4]	auto[1]	auto[1]	471	1			T84	4		T16	7		T21	3
all_values[5]	auto[0]	auto[0]	64693	1			T2	1		T3	2		T4	2
all_values[5]	auto[0]	auto[1]	181	1			T31	2		T34	1		T36	1
all_values[5]	auto[1]	auto[0]	64878	1			T1	33		T3	2		T5	34
all_values[5]	auto[1]	auto[1]	163	1			T31	1		T34	1		T101	3
all_values[6]	auto[0]	auto[0]	69727	1			T1	28		T2	1		T3	4
all_values[6]	auto[0]	auto[1]	155	1			T36	2		T101	3		T54	3
all_values[6]	auto[1]	auto[0]	59815	1			T1	5		T5	28		T6	1
all_values[6]	auto[1]	auto[1]	218	1			T31	5		T101	1		T54	2
all_values[7]	auto[0]	auto[0]	66460	1			T2	1		T3	4		T4	2
all_values[7]	auto[0]	auto[1]	391	1			T9	1		T14	2		T23	1
all_values[7]	auto[1]	auto[0]	62682	1			T1	33		T5	11		T6	1
all_values[7]	auto[1]	auto[1]	382	1			T16	1		T42	2		T17	8