Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2576

1

T1

1

T2

1

T3

1

auto[UartRx]

2576

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4567	1			T1	2		T2	2		T3	2
values[1]	39	1			T24	1		T33	1		T34	1
values[2]	62	1			T34	3		T37	1		T101	3
values[3]	59	1			T24	1		T21	1		T34	1
values[4]	64	1			T19	1		T34	1		T36	3
values[5]	50	1			T37	2		T101	1		T120	1
values[6]	54	1			T19	1		T31	1		T33	2
values[7]	58	1			T19	3		T31	2		T101	2
values[8]	42	1			T24	2		T21	2		T19	1
values[9]	65	1			T21	2		T19	2		T34	1
values[10]	64	1			T32	1		T151	1		T273	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2383	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	11	1			T273	1		T320	1		T244	2
auto[UartTx]	values[2]	23	1			T34	1		T37	1		T273	1
auto[UartTx]	values[3]	17	1			T21	1		T34	1		T101	1
auto[UartTx]	values[4]	26	1			T34	1		T36	1		T120	1
auto[UartTx]	values[5]	15	1			T101	1		T273	1		T56	1
auto[UartTx]	values[6]	17	1			T33	1		T35	1		T109	2
auto[UartTx]	values[7]	20	1			T19	1		T31	1		T101	1
auto[UartTx]	values[8]	11	1			T24	1		T21	1		T19	1
auto[UartTx]	values[9]	20	1			T19	2		T311	1		T58	1
auto[UartTx]	values[10]	23	1			T151	1		T107	1		T58	1
auto[UartRx]	values[0]	2184	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	28	1			T24	1		T33	1		T34	1
auto[UartRx]	values[2]	39	1			T34	2		T101	3		T55	1
auto[UartRx]	values[3]	42	1			T24	1		T35	1		T101	1
auto[UartRx]	values[4]	38	1			T19	1		T36	2		T101	1
auto[UartRx]	values[5]	35	1			T37	2		T120	1		T56	1
auto[UartRx]	values[6]	37	1			T19	1		T31	1		T33	1
auto[UartRx]	values[7]	38	1			T19	2		T31	1		T101	1
auto[UartRx]	values[8]	31	1			T24	1		T21	1		T34	1
auto[UartRx]	values[9]	45	1			T21	2		T34	1		T35	1
auto[UartRx]	values[10]	41	1			T32	1		T273	1		T56	1