Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2409	1			T1	3		T3	1		T5	1
auto[BaudRate115200]	1972	1			T1	1		T4	1		T5	2
auto[BaudRate230400]	2076	1			T1	1		T3	2		T5	2
auto[BaudRate128Kbps]	1923	1			T3	1		T4	1		T5	1
auto[BaudRate256Kbps]	2142	1			T1	1		T6	12		T8	1
auto[BaudRate1Mbps]	1786	1			T1	2		T2	3		T3	1
auto[BaudRate1p5Mbps]	1313	1			T5	3		T10	1		T13	4

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1281	1			T123	6		T132	7		T47	5
freqs[25]	1255	1			T8	5		T18	2		T112	8
freqs[48]	553	1			T149	9		T321	14		T282	12
freqs[50]	784	1			T2	3		T268	11		T258	7
freqs[100]	1295	1			T23	22		T122	10		T22	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	221	1			T123	2		T41	4		T135	3
auto[BaudRate9600]	freqs[25]	225	1			T8	1		T18	1		T24	5
auto[BaudRate9600]	freqs[48]	94	1			T321	14		T282	3		T191	2
auto[BaudRate9600]	freqs[50]	141	1			T268	1		T258	1		T48	6
auto[BaudRate9600]	freqs[100]	191	1			T23	5		T122	1		T22	5
auto[BaudRate115200]	freqs[24]	166	1			T132	2		T135	1		T31	1
auto[BaudRate115200]	freqs[25]	190	1			T8	1		T112	1		T24	3
auto[BaudRate115200]	freqs[48]	81	1			T149	1		T282	1		T191	2
auto[BaudRate115200]	freqs[50]	124	1			T268	3		T127	3		T113	1
auto[BaudRate115200]	freqs[100]	160	1			T23	2		T122	3		T263	2
auto[BaudRate230400]	freqs[24]	206	1			T123	1		T132	3		T135	2
auto[BaudRate230400]	freqs[25]	202	1			T8	1		T18	1		T24	7
auto[BaudRate230400]	freqs[48]	79	1			T149	4		T282	5		T322	1
auto[BaudRate230400]	freqs[50]	121	1			T268	2		T258	1		T286	3
auto[BaudRate230400]	freqs[100]	163	1			T23	1		T122	2		T16	1
auto[BaudRate128Kbps]	freqs[24]	197	1			T123	2		T31	3		T121	2
auto[BaudRate128Kbps]	freqs[25]	170	1			T8	1		T112	2		T24	3
auto[BaudRate128Kbps]	freqs[48]	62	1			T282	1		T322	1		T323	2
auto[BaudRate128Kbps]	freqs[50]	101	1			T258	2		T286	2		T266	4
auto[BaudRate128Kbps]	freqs[100]	184	1			T23	5		T122	1		T84	1
auto[BaudRate256Kbps]	freqs[24]	181	1			T123	1		T132	1		T47	3
auto[BaudRate256Kbps]	freqs[25]	202	1			T8	1		T112	2		T24	12
auto[BaudRate256Kbps]	freqs[48]	75	1			T149	1		T324	1		T322	2
auto[BaudRate256Kbps]	freqs[50]	91	1			T268	2		T258	1		T266	1
auto[BaudRate256Kbps]	freqs[100]	197	1			T23	3		T122	1		T293	1
auto[BaudRate1Mbps]	freqs[24]	196	1			T132	1		T47	1		T31	3
auto[BaudRate1Mbps]	freqs[25]	181	1			T112	2		T24	8		T43	1
auto[BaudRate1Mbps]	freqs[48]	79	1			T149	3		T322	1		T191	1
auto[BaudRate1Mbps]	freqs[50]	111	1			T2	3		T268	1		T258	2
auto[BaudRate1Mbps]	freqs[100]	205	1			T23	3		T122	2		T254	3
auto[BaudRate1p5Mbps]	freqs[25]	85	1			T112	1		T24	3		T34	8
auto[BaudRate1p5Mbps]	freqs[48]	83	1			T282	2		T324	1		T322	1
auto[BaudRate1p5Mbps]	freqs[50]	95	1			T268	2		T266	3		T127	2
auto[BaudRate1p5Mbps]	freqs[100]	195	1			T23	3		T251	2		T269	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded