Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	36381031	1			T1	10		T2	1		T3	17
all_levels[1]	177743	1			T1	4		T3	1		T5	20
all_levels[2]	2413	1			T1	14		T5	6		T8	4
all_levels[3]	1051	1			T1	4		T5	3		T8	2
all_levels[4]	728	1			T1	2		T3	1		T5	5
all_levels[5]	513	1			T1	1		T5	1		T13	2
all_levels[6]	412	1			T1	3		T5	2		T9	1
all_levels[7]	396	1			T1	2		T5	1		T8	3
all_levels[8]	291	1			T1	1		T5	3		T9	1
all_levels[9]	232	1			T5	2		T9	2		T13	1
all_levels[10]	239	1			T1	1		T5	3		T9	1
all_levels[11]	193	1			T5	1		T9	1		T23	5
all_levels[12]	164	1			T1	1		T5	2		T9	3
all_levels[13]	175	1			T9	1		T23	1		T15	2
all_levels[14]	117	1			T5	1		T14	1		T23	1
all_levels[15]	134	1			T14	1		T23	2		T111	3
all_levels[16]	133	1			T5	1		T9	2		T12	1
all_levels[17]	75	1			T5	1		T9	1		T23	2
all_levels[18]	81	1			T3	1		T5	1		T13	1
all_levels[19]	95	1			T112	1		T24	1		T121	1
all_levels[20]	68	1			T122	1		T123	2		T124	1
all_levels[21]	55	1			T111	1		T40	2		T51	2
all_levels[22]	69	1			T5	1		T13	1		T14	1
all_levels[23]	55	1			T1	1		T23	2		T24	1
all_levels[24]	57	1			T5	1		T125	1		T126	1
all_levels[25]	62	1			T5	1		T14	1		T24	1
all_levels[26]	51	1			T13	1		T15	1		T33	1
all_levels[27]	48	1			T5	1		T9	1		T13	1
all_levels[28]	43	1			T45	1		T19	1		T127	1
all_levels[29]	42	1			T14	1		T128	1		T129	1
all_levels[30]	51	1			T5	1		T14	1		T124	1
all_levels[31]	44	1			T5	1		T23	1		T130	1
all_levels[32]	33	1			T15	1		T125	1		T56	1
all_levels[33]	23	1			T13	1		T128	1		T131	1
all_levels[34]	30	1			T5	1		T112	1		T132	1
all_levels[35]	30	1			T3	2		T39	2		T40	1
all_levels[36]	26	1			T36	1		T133	1		T105	2
all_levels[37]	18	1			T14	1		T134	2		T107	1
all_levels[38]	13	1			T135	2		T136	1		T137	1
all_levels[39]	23	1			T111	1		T112	2		T31	1
all_levels[40]	23	1			T128	1		T36	1		T105	1
all_levels[41]	14	1			T127	1		T113	1		T138	1
all_levels[42]	15	1			T8	3		T139	1		T140	1
all_levels[43]	20	1			T124	2		T141	1		T36	1
all_levels[44]	18	1			T142	1		T130	1		T143	2
all_levels[45]	24	1			T45	2		T143	1		T54	1
all_levels[46]	17	1			T112	1		T144	1		T145	1
all_levels[47]	6	1			T143	1		T146	1		T147	1
all_levels[48]	18	1			T24	1		T36	1		T148	2
all_levels[49]	19	1			T149	1		T127	1		T150	2
all_levels[50]	19	1			T36	1		T151	1		T152	1
all_levels[51]	13	1			T153	2		T154	1		T137	1
all_levels[52]	6	1			T136	1		T155	1		T156	1
all_levels[53]	7	1			T157	1		T137	1		T155	1
all_levels[54]	9	1			T156	1		T158	1		T159	1
all_levels[55]	8	1			T5	1		T160	1		T138	1
all_levels[56]	6	1			T161	2		T162	1		T163	1
all_levels[57]	7	1			T121	1		T164	1		T165	1
all_levels[58]	6	1			T114	1		T155	1		T166	1
all_levels[59]	4	1			T167	1		T168	1		T169	1
all_levels[60]	8	1			T170	2		T162	1		T171	2
all_levels[61]	9	1			T105	1		T172	1		T173	1
all_levels[62]	9	1			T174	1		T175	1		T147	4
all_levels[63]	6	1			T176	3		T177	1		T178	1
all_levels[64]	101	1			T15	1		T112	1		T33	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36562729

1

T1

39

T3

22

T5

144

auto[1]

4720

1

T1

5

T2

1

T6

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[52] , all_levels[53] , all_levels[54] , all_levels[55]]	[auto[1]]	--	--	4
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	36376773	1			T1	8		T3	17		T5	83
all_levels[0]	auto[1]	4258	1			T1	2		T2	1		T6	5
all_levels[1]	auto[0]	177676	1			T1	4		T3	1		T5	20
all_levels[1]	auto[1]	67	1			T8	2		T132	2		T24	2
all_levels[2]	auto[0]	2383	1			T1	13		T5	6		T8	4
all_levels[2]	auto[1]	30	1			T1	1		T54	1		T179	2
all_levels[3]	auto[0]	1037	1			T1	4		T5	3		T8	2
all_levels[3]	auto[1]	14	1			T113	2		T105	1		T180	1
all_levels[4]	auto[0]	698	1			T1	2		T3	1		T5	5
all_levels[4]	auto[1]	30	1			T124	1		T135	1		T133	1
all_levels[5]	auto[0]	497	1			T1	1		T5	1		T13	2
all_levels[5]	auto[1]	16	1			T133	1		T181	5		T182	1
all_levels[6]	auto[0]	397	1			T1	1		T5	2		T9	1
all_levels[6]	auto[1]	15	1			T1	2		T134	1		T183	1
all_levels[7]	auto[0]	377	1			T1	2		T5	1		T8	3
all_levels[7]	auto[1]	19	1			T184	1		T105	1		T131	4
all_levels[8]	auto[0]	278	1			T1	1		T5	3		T9	1
all_levels[8]	auto[1]	13	1			T185	1		T154	1		T186	1
all_levels[9]	auto[0]	220	1			T5	2		T9	2		T13	1
all_levels[9]	auto[1]	12	1			T135	1		T176	2		T187	3
all_levels[10]	auto[0]	224	1			T1	1		T5	3		T9	1
all_levels[10]	auto[1]	15	1			T188	1		T189	1		T190	1
all_levels[11]	auto[0]	177	1			T5	1		T9	1		T23	5
all_levels[11]	auto[1]	16	1			T54	2		T182	1		T191	2
all_levels[12]	auto[0]	153	1			T1	1		T5	2		T9	1
all_levels[12]	auto[1]	11	1			T9	2		T112	4		T192	1
all_levels[13]	auto[0]	166	1			T9	1		T23	1		T15	2
all_levels[13]	auto[1]	9	1			T54	2		T193	1		T194	1
all_levels[14]	auto[0]	105	1			T5	1		T14	1		T23	1
all_levels[14]	auto[1]	12	1			T195	1		T196	1		T197	3
all_levels[15]	auto[0]	124	1			T14	1		T23	2		T111	3
all_levels[15]	auto[1]	10	1			T198	1		T189	1		T199	1
all_levels[16]	auto[0]	110	1			T5	1		T9	1		T12	1
all_levels[16]	auto[1]	23	1			T9	1		T200	2		T105	1
all_levels[17]	auto[0]	71	1			T5	1		T9	1		T23	2
all_levels[17]	auto[1]	4	1			T54	2		T201	2		-	-
all_levels[18]	auto[0]	77	1			T3	1		T5	1		T13	1
all_levels[18]	auto[1]	4	1			T202	1		T177	1		T203	1
all_levels[19]	auto[0]	90	1			T112	1		T24	1		T121	1
all_levels[19]	auto[1]	5	1			T179	1		T204	1		T190	2
all_levels[20]	auto[0]	61	1			T122	1		T123	1		T124	1
all_levels[20]	auto[1]	7	1			T123	1		T205	1		T206	3
all_levels[21]	auto[0]	51	1			T111	1		T40	1		T51	2
all_levels[21]	auto[1]	4	1			T40	1		T170	1		T207	2
all_levels[22]	auto[0]	66	1			T5	1		T13	1		T14	1
all_levels[22]	auto[1]	3	1			T208	1		T156	1		T209	1
all_levels[23]	auto[0]	49	1			T1	1		T23	2		T24	1
all_levels[23]	auto[1]	6	1			T210	3		T211	1		T212	2
all_levels[24]	auto[0]	51	1			T5	1		T125	1		T126	1
all_levels[24]	auto[1]	6	1			T213	2		T199	1		T214	2
all_levels[25]	auto[0]	55	1			T5	1		T14	1		T24	1
all_levels[25]	auto[1]	7	1			T208	1		T202	2		T215	1
all_levels[26]	auto[0]	47	1			T13	1		T15	1		T33	1
all_levels[26]	auto[1]	4	1			T216	1		T70	1		T217	2
all_levels[27]	auto[0]	40	1			T5	1		T9	1		T13	1
all_levels[27]	auto[1]	8	1			T152	1		T218	1		T157	2
all_levels[28]	auto[0]	40	1			T45	1		T19	1		T127	1
all_levels[28]	auto[1]	3	1			T219	1		T220	2		-	-
all_levels[29]	auto[0]	40	1			T14	1		T128	1		T129	1
all_levels[29]	auto[1]	2	1			T221	1		T222	1		-	-
all_levels[30]	auto[0]	46	1			T5	1		T14	1		T124	1
all_levels[30]	auto[1]	5	1			T223	1		T224	1		T225	2
all_levels[31]	auto[0]	38	1			T5	1		T23	1		T130	1
all_levels[31]	auto[1]	6	1			T226	1		T150	1		T227	1
all_levels[32]	auto[0]	29	1			T15	1		T125	1		T56	1
all_levels[32]	auto[1]	4	1			T197	4		-	-		-	-
all_levels[33]	auto[0]	23	1			T13	1		T128	1		T131	1
all_levels[34]	auto[0]	24	1			T5	1		T112	1		T132	1
all_levels[34]	auto[1]	6	1			T218	1		T190	1		T228	2
all_levels[35]	auto[0]	28	1			T3	2		T39	2		T40	1
all_levels[35]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[36]	auto[0]	22	1			T36	1		T133	1		T105	2
all_levels[36]	auto[1]	4	1			T231	2		T197	1		T232	1
all_levels[37]	auto[0]	17	1			T14	1		T134	1		T107	1
all_levels[37]	auto[1]	1	1			T134	1		-	-		-	-
all_levels[38]	auto[0]	12	1			T135	1		T136	1		T137	1
all_levels[38]	auto[1]	1	1			T135	1		-	-		-	-
all_levels[39]	auto[0]	22	1			T111	1		T112	1		T31	1
all_levels[39]	auto[1]	1	1			T112	1		-	-		-	-
all_levels[40]	auto[0]	21	1			T128	1		T36	1		T105	1
all_levels[40]	auto[1]	2	1			T134	1		T233	1		-	-
all_levels[41]	auto[0]	14	1			T127	1		T113	1		T138	1
all_levels[42]	auto[0]	11	1			T8	1		T139	1		T140	1
all_levels[42]	auto[1]	4	1			T8	2		T234	1		T235	1
all_levels[43]	auto[0]	19	1			T124	1		T141	1		T36	1
all_levels[43]	auto[1]	1	1			T124	1		-	-		-	-
all_levels[44]	auto[0]	17	1			T142	1		T130	1		T143	2
all_levels[44]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[45]	auto[0]	20	1			T45	2		T143	1		T54	1
all_levels[45]	auto[1]	4	1			T237	1		T238	3		-	-
all_levels[46]	auto[0]	14	1			T112	1		T144	1		T145	1
all_levels[46]	auto[1]	3	1			T239	3		-	-		-	-
all_levels[47]	auto[0]	6	1			T143	1		T146	1		T147	1
all_levels[48]	auto[0]	13	1			T24	1		T36	1		T148	1
all_levels[48]	auto[1]	5	1			T148	1		T226	2		T240	1
all_levels[49]	auto[0]	13	1			T149	1		T127	1		T150	1
all_levels[49]	auto[1]	6	1			T150	1		T177	3		T241	2
all_levels[50]	auto[0]	17	1			T36	1		T151	1		T152	1
all_levels[50]	auto[1]	2	1			T223	2		-	-		-	-
all_levels[51]	auto[0]	12	1			T153	1		T154	1		T137	1
all_levels[51]	auto[1]	1	1			T153	1		-	-		-	-
all_levels[52]	auto[0]	6	1			T136	1		T155	1		T156	1
all_levels[53]	auto[0]	7	1			T157	1		T137	1		T155	1
all_levels[54]	auto[0]	9	1			T156	1		T158	1		T159	1
all_levels[55]	auto[0]	8	1			T5	1		T160	1		T138	1
all_levels[56]	auto[0]	5	1			T161	1		T162	1		T163	1
all_levels[56]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[57]	auto[0]	7	1			T121	1		T164	1		T165	1
all_levels[58]	auto[0]	5	1			T114	1		T155	1		T166	1
all_levels[58]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[59]	auto[0]	4	1			T167	1		T168	1		T169	1
all_levels[60]	auto[0]	5	1			T170	1		T162	1		T171	1
all_levels[60]	auto[1]	3	1			T170	1		T171	1		T146	1
all_levels[61]	auto[0]	9	1			T105	1		T172	1		T173	1
all_levels[62]	auto[0]	6	1			T174	1		T175	1		T147	1
all_levels[62]	auto[1]	3	1			T147	3		-	-		-	-
all_levels[63]	auto[0]	4	1			T176	1		T177	1		T178	1
all_levels[63]	auto[1]	2	1			T176	2		-	-		-	-
all_levels[64]	auto[0]	83	1			T15	1		T112	1		T33	1
all_levels[64]	auto[1]	18	1			T243	1		T183	1		T244	1