Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1353 |
1 |
|
|
T5 |
16 |
|
T9 |
17 |
|
T13 |
4 |
all_levels[1] |
744 |
1 |
|
|
T1 |
3 |
|
T45 |
8 |
|
T112 |
1 |
all_levels[2] |
497 |
1 |
|
|
T1 |
4 |
|
T5 |
17 |
|
T42 |
4 |
all_levels[3] |
408 |
1 |
|
|
T3 |
1 |
|
T5 |
3 |
|
T84 |
3 |
all_levels[4] |
103 |
1 |
|
|
T113 |
2 |
|
T114 |
2 |
|
T56 |
2 |
all_levels[5] |
206 |
1 |
|
|
T111 |
6 |
|
T112 |
1 |
|
T34 |
3 |
all_levels[6] |
59 |
1 |
|
|
T106 |
2 |
|
T115 |
4 |
|
T116 |
4 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |