Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	129915	1			T1	33		T2	1		T3	4
all_pins[1]	129915	1			T1	33		T2	1		T3	4
all_pins[2]	129915	1			T1	33		T2	1		T3	4
all_pins[3]	129915	1			T1	33		T2	1		T3	4
all_pins[4]	129915	1			T1	33		T2	1		T3	4
all_pins[5]	129915	1			T1	33		T2	1		T3	4
all_pins[6]	129915	1			T1	33		T2	1		T3	4
all_pins[7]	129915	1			T1	33		T2	1		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1006797	1			T1	226		T2	7		T3	30
values[0x1]	32523	1			T1	38		T2	1		T3	2
transitions[0x0=>0x1]	31438	1			T1	34		T2	1		T3	2
transitions[0x1=>0x0]	30998	1			T1	33		T3	2		T5	26

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	103777	1			T3	2		T4	2		T5	57
all_pins[0]	values[0x1]	26138	1			T1	33		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	25635	1			T1	29		T2	1		T3	2
all_pins[0]	transitions[0x1=>0x0]	1092	1			T5	16		T9	1		T14	16
all_pins[1]	values[0x0]	128320	1			T1	29		T2	1		T3	4
all_pins[1]	values[0x1]	1595	1			T1	4		T5	16		T9	8
all_pins[1]	transitions[0x0=>0x1]	1486	1			T1	4		T5	16		T9	3
all_pins[1]	transitions[0x1=>0x0]	2461	1			T5	6		T9	7		T13	13
all_pins[2]	values[0x0]	127345	1			T1	33		T2	1		T3	4
all_pins[2]	values[0x1]	2570	1			T5	6		T9	12		T13	13
all_pins[2]	transitions[0x0=>0x1]	2514	1			T5	6		T9	11		T13	13
all_pins[2]	transitions[0x1=>0x0]	235	1			T8	1		T112	1		T33	2
all_pins[3]	values[0x0]	129624	1			T1	33		T2	1		T3	4
all_pins[3]	values[0x1]	291	1			T8	1		T9	1		T15	1
all_pins[3]	transitions[0x0=>0x1]	254	1			T8	1		T9	1		T15	1
all_pins[3]	transitions[0x1=>0x0]	434	1			T84	4		T16	7		T21	3
all_pins[4]	values[0x0]	129444	1			T1	33		T2	1		T3	4
all_pins[4]	values[0x1]	471	1			T84	4		T16	7		T21	3
all_pins[4]	transitions[0x0=>0x1]	395	1			T84	4		T16	5		T21	3
all_pins[4]	transitions[0x1=>0x0]	148	1			T17	2		T34	3		T245	3
all_pins[5]	values[0x0]	129691	1			T1	33		T2	1		T3	4
all_pins[5]	values[0x1]	224	1			T16	2		T17	2		T19	2
all_pins[5]	transitions[0x0=>0x1]	170	1			T16	2		T17	2		T19	2
all_pins[5]	transitions[0x1=>0x0]	798	1			T1	1		T8	1		T9	3
all_pins[6]	values[0x0]	129063	1			T1	32		T2	1		T3	4
all_pins[6]	values[0x1]	852	1			T1	1		T8	1		T9	3
all_pins[6]	transitions[0x0=>0x1]	774	1			T1	1		T8	1		T9	3
all_pins[6]	transitions[0x1=>0x0]	304	1			T16	1		T42	2		T17	8
all_pins[7]	values[0x0]	129533	1			T1	33		T2	1		T3	4
all_pins[7]	values[0x1]	382	1			T16	1		T42	2		T17	8
all_pins[7]	transitions[0x0=>0x1]	210	1			T42	1		T125	7		T31	7
all_pins[7]	transitions[0x1=>0x0]	25526	1			T1	32		T3	2		T5	4